2 * Copyright © 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License version 2 as
23 * published by the Free Software Foundation.
27 #include <linux/dma-mapping.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/platform_device.h>
33 #include <linux/of_device.h>
34 #include <linux/of_gpio.h>
35 #include <linux/of_mtd.h>
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/partitions.h>
40 #include <linux/dmaengine.h>
41 #include <linux/gpio.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/pinctrl/consumer.h>
48 static int use_dma
= 1;
49 module_param(use_dma
, int, 0);
51 static int on_flash_bbt
= 0;
52 module_param(on_flash_bbt
, int, 0);
54 /* Register access macros */
55 #define ecc_readl(add, reg) \
56 __raw_readl(add + ATMEL_ECC_##reg)
57 #define ecc_writel(add, reg, value) \
58 __raw_writel((value), add + ATMEL_ECC_##reg)
60 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
62 /* oob layout for large page size
63 * bad block info is on bytes 0 and 1
64 * the bytes have to be consecutives to avoid
65 * several NAND_CMD_RNDOUT during read
67 static struct nand_ecclayout atmel_oobinfo_large
= {
69 .eccpos
= {60, 61, 62, 63},
75 /* oob layout for small page size
76 * bad block info is on bytes 4 and 5
77 * the bytes have to be consecutives to avoid
78 * several NAND_CMD_RNDOUT during read
80 static struct nand_ecclayout atmel_oobinfo_small
= {
82 .eccpos
= {0, 1, 2, 3},
88 struct atmel_nand_host
{
89 struct nand_chip nand_chip
;
91 void __iomem
*io_base
;
93 struct atmel_nand_data board
;
97 struct completion comp
;
98 struct dma_chan
*dma_chan
;
102 u16 pmecc_sector_size
;
103 u32 pmecc_lookup_table_offset
;
104 u32 pmecc_lookup_table_offset_512
;
105 u32 pmecc_lookup_table_offset_1024
;
107 int pmecc_bytes_per_sector
;
108 int pmecc_sector_number
;
109 int pmecc_degree
; /* Degree of remainders */
110 int pmecc_cw_len
; /* Length of codeword */
112 void __iomem
*pmerrloc_base
;
113 void __iomem
*pmecc_rom_base
;
115 /* lookup table for alpha_to and index_of */
116 void __iomem
*pmecc_alpha_to
;
117 void __iomem
*pmecc_index_of
;
119 /* data for pmecc computation */
120 int16_t *pmecc_partial_syn
;
122 int16_t *pmecc_smu
; /* Sigma table */
123 int16_t *pmecc_lmu
; /* polynomal order */
129 static struct nand_ecclayout atmel_pmecc_oobinfo
;
131 static int cpu_has_dma(void)
133 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
139 static void atmel_nand_enable(struct atmel_nand_host
*host
)
141 if (gpio_is_valid(host
->board
.enable_pin
))
142 gpio_set_value(host
->board
.enable_pin
, 0);
148 static void atmel_nand_disable(struct atmel_nand_host
*host
)
150 if (gpio_is_valid(host
->board
.enable_pin
))
151 gpio_set_value(host
->board
.enable_pin
, 1);
155 * Hardware specific access to control-lines
157 static void atmel_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
159 struct nand_chip
*nand_chip
= mtd
->priv
;
160 struct atmel_nand_host
*host
= nand_chip
->priv
;
162 if (ctrl
& NAND_CTRL_CHANGE
) {
164 atmel_nand_enable(host
);
166 atmel_nand_disable(host
);
168 if (cmd
== NAND_CMD_NONE
)
172 writeb(cmd
, host
->io_base
+ (1 << host
->board
.cle
));
174 writeb(cmd
, host
->io_base
+ (1 << host
->board
.ale
));
178 * Read the Device Ready pin.
180 static int atmel_nand_device_ready(struct mtd_info
*mtd
)
182 struct nand_chip
*nand_chip
= mtd
->priv
;
183 struct atmel_nand_host
*host
= nand_chip
->priv
;
185 return gpio_get_value(host
->board
.rdy_pin
) ^
186 !!host
->board
.rdy_pin_active_low
;
190 * Minimal-overhead PIO for data access.
192 static void atmel_read_buf8(struct mtd_info
*mtd
, u8
*buf
, int len
)
194 struct nand_chip
*nand_chip
= mtd
->priv
;
196 __raw_readsb(nand_chip
->IO_ADDR_R
, buf
, len
);
199 static void atmel_read_buf16(struct mtd_info
*mtd
, u8
*buf
, int len
)
201 struct nand_chip
*nand_chip
= mtd
->priv
;
203 __raw_readsw(nand_chip
->IO_ADDR_R
, buf
, len
/ 2);
206 static void atmel_write_buf8(struct mtd_info
*mtd
, const u8
*buf
, int len
)
208 struct nand_chip
*nand_chip
= mtd
->priv
;
210 __raw_writesb(nand_chip
->IO_ADDR_W
, buf
, len
);
213 static void atmel_write_buf16(struct mtd_info
*mtd
, const u8
*buf
, int len
)
215 struct nand_chip
*nand_chip
= mtd
->priv
;
217 __raw_writesw(nand_chip
->IO_ADDR_W
, buf
, len
/ 2);
220 static void dma_complete_func(void *completion
)
222 complete(completion
);
225 static int atmel_nand_dma_op(struct mtd_info
*mtd
, void *buf
, int len
,
228 struct dma_device
*dma_dev
;
229 enum dma_ctrl_flags flags
;
230 dma_addr_t dma_src_addr
, dma_dst_addr
, phys_addr
;
231 struct dma_async_tx_descriptor
*tx
= NULL
;
233 struct nand_chip
*chip
= mtd
->priv
;
234 struct atmel_nand_host
*host
= chip
->priv
;
237 enum dma_data_direction dir
= is_read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
239 if (buf
>= high_memory
)
242 dma_dev
= host
->dma_chan
->device
;
244 flags
= DMA_CTRL_ACK
| DMA_PREP_INTERRUPT
| DMA_COMPL_SKIP_SRC_UNMAP
|
245 DMA_COMPL_SKIP_DEST_UNMAP
;
247 phys_addr
= dma_map_single(dma_dev
->dev
, p
, len
, dir
);
248 if (dma_mapping_error(dma_dev
->dev
, phys_addr
)) {
249 dev_err(host
->dev
, "Failed to dma_map_single\n");
254 dma_src_addr
= host
->io_phys
;
255 dma_dst_addr
= phys_addr
;
257 dma_src_addr
= phys_addr
;
258 dma_dst_addr
= host
->io_phys
;
261 tx
= dma_dev
->device_prep_dma_memcpy(host
->dma_chan
, dma_dst_addr
,
262 dma_src_addr
, len
, flags
);
264 dev_err(host
->dev
, "Failed to prepare DMA memcpy\n");
268 init_completion(&host
->comp
);
269 tx
->callback
= dma_complete_func
;
270 tx
->callback_param
= &host
->comp
;
272 cookie
= tx
->tx_submit(tx
);
273 if (dma_submit_error(cookie
)) {
274 dev_err(host
->dev
, "Failed to do DMA tx_submit\n");
278 dma_async_issue_pending(host
->dma_chan
);
279 wait_for_completion(&host
->comp
);
284 dma_unmap_single(dma_dev
->dev
, phys_addr
, len
, dir
);
287 dev_warn(host
->dev
, "Fall back to CPU I/O\n");
291 static void atmel_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
293 struct nand_chip
*chip
= mtd
->priv
;
294 struct atmel_nand_host
*host
= chip
->priv
;
296 if (use_dma
&& len
> mtd
->oobsize
)
297 /* only use DMA for bigger than oob size: better performances */
298 if (atmel_nand_dma_op(mtd
, buf
, len
, 1) == 0)
301 if (host
->board
.bus_width_16
)
302 atmel_read_buf16(mtd
, buf
, len
);
304 atmel_read_buf8(mtd
, buf
, len
);
307 static void atmel_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
309 struct nand_chip
*chip
= mtd
->priv
;
310 struct atmel_nand_host
*host
= chip
->priv
;
312 if (use_dma
&& len
> mtd
->oobsize
)
313 /* only use DMA for bigger than oob size: better performances */
314 if (atmel_nand_dma_op(mtd
, (void *)buf
, len
, 0) == 0)
317 if (host
->board
.bus_width_16
)
318 atmel_write_buf16(mtd
, buf
, len
);
320 atmel_write_buf8(mtd
, buf
, len
);
324 * Return number of ecc bytes per sector according to sector size and
325 * correction capability
327 * Following table shows what at91 PMECC supported:
328 * Correction Capability Sector_512_bytes Sector_1024_bytes
329 * ===================== ================ =================
330 * 2-bits 4-bytes 4-bytes
331 * 4-bits 7-bytes 7-bytes
332 * 8-bits 13-bytes 14-bytes
333 * 12-bits 20-bytes 21-bytes
334 * 24-bits 39-bytes 42-bytes
336 static int pmecc_get_ecc_bytes(int cap
, int sector_size
)
338 int m
= 12 + sector_size
/ 512;
339 return (m
* cap
+ 7) / 8;
342 static void pmecc_config_ecc_layout(struct nand_ecclayout
*layout
,
343 int oobsize
, int ecc_len
)
347 layout
->eccbytes
= ecc_len
;
349 /* ECC will occupy the last ecc_len bytes continuously */
350 for (i
= 0; i
< ecc_len
; i
++)
351 layout
->eccpos
[i
] = oobsize
- ecc_len
+ i
;
353 layout
->oobfree
[0].offset
= 2;
354 layout
->oobfree
[0].length
=
355 oobsize
- ecc_len
- layout
->oobfree
[0].offset
;
358 static void __iomem
*pmecc_get_alpha_to(struct atmel_nand_host
*host
)
362 table_size
= host
->pmecc_sector_size
== 512 ?
363 PMECC_LOOKUP_TABLE_SIZE_512
: PMECC_LOOKUP_TABLE_SIZE_1024
;
365 return host
->pmecc_rom_base
+ host
->pmecc_lookup_table_offset
+
366 table_size
* sizeof(int16_t);
369 static void pmecc_data_free(struct atmel_nand_host
*host
)
371 kfree(host
->pmecc_partial_syn
);
372 kfree(host
->pmecc_si
);
373 kfree(host
->pmecc_lmu
);
374 kfree(host
->pmecc_smu
);
375 kfree(host
->pmecc_mu
);
376 kfree(host
->pmecc_dmu
);
377 kfree(host
->pmecc_delta
);
380 static int pmecc_data_alloc(struct atmel_nand_host
*host
)
382 const int cap
= host
->pmecc_corr_cap
;
384 host
->pmecc_partial_syn
= kzalloc((2 * cap
+ 1) * sizeof(int16_t),
386 host
->pmecc_si
= kzalloc((2 * cap
+ 1) * sizeof(int16_t), GFP_KERNEL
);
387 host
->pmecc_lmu
= kzalloc((cap
+ 1) * sizeof(int16_t), GFP_KERNEL
);
388 host
->pmecc_smu
= kzalloc((cap
+ 2) * (2 * cap
+ 1) * sizeof(int16_t),
390 host
->pmecc_mu
= kzalloc((cap
+ 1) * sizeof(int), GFP_KERNEL
);
391 host
->pmecc_dmu
= kzalloc((cap
+ 1) * sizeof(int), GFP_KERNEL
);
392 host
->pmecc_delta
= kzalloc((cap
+ 1) * sizeof(int), GFP_KERNEL
);
394 if (host
->pmecc_partial_syn
&&
404 pmecc_data_free(host
);
408 static void pmecc_gen_syndrome(struct mtd_info
*mtd
, int sector
)
410 struct nand_chip
*nand_chip
= mtd
->priv
;
411 struct atmel_nand_host
*host
= nand_chip
->priv
;
415 /* Fill odd syndromes */
416 for (i
= 0; i
< host
->pmecc_corr_cap
; i
++) {
417 value
= pmecc_readl_rem_relaxed(host
->ecc
, sector
, i
/ 2);
421 host
->pmecc_partial_syn
[(2 * i
) + 1] = (int16_t)value
;
425 static void pmecc_substitute(struct mtd_info
*mtd
)
427 struct nand_chip
*nand_chip
= mtd
->priv
;
428 struct atmel_nand_host
*host
= nand_chip
->priv
;
429 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
430 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
431 int16_t *partial_syn
= host
->pmecc_partial_syn
;
432 const int cap
= host
->pmecc_corr_cap
;
436 /* si[] is a table that holds the current syndrome value,
437 * an element of that table belongs to the field
441 memset(&si
[1], 0, sizeof(int16_t) * (2 * cap
- 1));
443 /* Computation 2t syndromes based on S(x) */
445 for (i
= 1; i
< 2 * cap
; i
+= 2) {
446 for (j
= 0; j
< host
->pmecc_degree
; j
++) {
447 if (partial_syn
[i
] & ((unsigned short)0x1 << j
))
448 si
[i
] = readw_relaxed(alpha_to
+ i
* j
) ^ si
[i
];
451 /* Even syndrome = (Odd syndrome) ** 2 */
452 for (i
= 2, j
= 1; j
<= cap
; i
= ++j
<< 1) {
458 tmp
= readw_relaxed(index_of
+ si
[j
]);
459 tmp
= (tmp
* 2) % host
->pmecc_cw_len
;
460 si
[i
] = readw_relaxed(alpha_to
+ tmp
);
467 static void pmecc_get_sigma(struct mtd_info
*mtd
)
469 struct nand_chip
*nand_chip
= mtd
->priv
;
470 struct atmel_nand_host
*host
= nand_chip
->priv
;
472 int16_t *lmu
= host
->pmecc_lmu
;
473 int16_t *si
= host
->pmecc_si
;
474 int *mu
= host
->pmecc_mu
;
475 int *dmu
= host
->pmecc_dmu
; /* Discrepancy */
476 int *delta
= host
->pmecc_delta
; /* Delta order */
477 int cw_len
= host
->pmecc_cw_len
;
478 const int16_t cap
= host
->pmecc_corr_cap
;
479 const int num
= 2 * cap
+ 1;
480 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
481 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
483 uint32_t dmu_0_count
, tmp
;
484 int16_t *smu
= host
->pmecc_smu
;
486 /* index of largest delta */
498 memset(smu
, 0, sizeof(int16_t) * num
);
501 /* discrepancy set to 1 */
503 /* polynom order set to 0 */
505 delta
[0] = (mu
[0] * 2 - lmu
[0]) >> 1;
511 /* Sigma(x) set to 1 */
512 memset(&smu
[num
], 0, sizeof(int16_t) * num
);
515 /* discrepancy set to S1 */
518 /* polynom order set to 0 */
521 delta
[1] = (mu
[1] * 2 - lmu
[1]) >> 1;
523 /* Init the Sigma(x) last row */
524 memset(&smu
[(cap
+ 1) * num
], 0, sizeof(int16_t) * num
);
526 for (i
= 1; i
<= cap
; i
++) {
528 /* Begin Computing Sigma (Mu+1) and L(mu) */
529 /* check if discrepancy is set to 0 */
533 tmp
= ((cap
- (lmu
[i
] >> 1) - 1) / 2);
534 if ((cap
- (lmu
[i
] >> 1) - 1) & 0x1)
539 if (dmu_0_count
== tmp
) {
540 for (j
= 0; j
<= (lmu
[i
] >> 1) + 1; j
++)
541 smu
[(cap
+ 1) * num
+ j
] =
544 lmu
[cap
+ 1] = lmu
[i
];
549 for (j
= 0; j
<= lmu
[i
] >> 1; j
++)
550 smu
[(i
+ 1) * num
+ j
] = smu
[i
* num
+ j
];
552 /* copy previous polynom order to the next */
557 /* find largest delta with dmu != 0 */
558 for (j
= 0; j
< i
; j
++) {
559 if ((dmu
[j
]) && (delta
[j
] > largest
)) {
565 /* compute difference */
566 diff
= (mu
[i
] - mu
[ro
]);
568 /* Compute degree of the new smu polynomial */
569 if ((lmu
[i
] >> 1) > ((lmu
[ro
] >> 1) + diff
))
572 lmu
[i
+ 1] = ((lmu
[ro
] >> 1) + diff
) * 2;
574 /* Init smu[i+1] with 0 */
575 for (k
= 0; k
< num
; k
++)
576 smu
[(i
+ 1) * num
+ k
] = 0;
578 /* Compute smu[i+1] */
579 for (k
= 0; k
<= lmu
[ro
] >> 1; k
++) {
582 if (!(smu
[ro
* num
+ k
] && dmu
[i
]))
584 a
= readw_relaxed(index_of
+ dmu
[i
]);
585 b
= readw_relaxed(index_of
+ dmu
[ro
]);
586 c
= readw_relaxed(index_of
+ smu
[ro
* num
+ k
]);
587 tmp
= a
+ (cw_len
- b
) + c
;
588 a
= readw_relaxed(alpha_to
+ tmp
% cw_len
);
589 smu
[(i
+ 1) * num
+ (k
+ diff
)] = a
;
592 for (k
= 0; k
<= lmu
[i
] >> 1; k
++)
593 smu
[(i
+ 1) * num
+ k
] ^= smu
[i
* num
+ k
];
596 /* End Computing Sigma (Mu+1) and L(mu) */
597 /* In either case compute delta */
598 delta
[i
+ 1] = (mu
[i
+ 1] * 2 - lmu
[i
+ 1]) >> 1;
600 /* Do not compute discrepancy for the last iteration */
604 for (k
= 0; k
<= (lmu
[i
+ 1] >> 1); k
++) {
607 dmu
[i
+ 1] = si
[tmp
+ 3];
608 } else if (smu
[(i
+ 1) * num
+ k
] && si
[tmp
+ 3 - k
]) {
610 a
= readw_relaxed(index_of
+
611 smu
[(i
+ 1) * num
+ k
]);
612 b
= si
[2 * (i
- 1) + 3 - k
];
613 c
= readw_relaxed(index_of
+ b
);
616 dmu
[i
+ 1] = readw_relaxed(alpha_to
+ tmp
) ^
625 static int pmecc_err_location(struct mtd_info
*mtd
)
627 struct nand_chip
*nand_chip
= mtd
->priv
;
628 struct atmel_nand_host
*host
= nand_chip
->priv
;
629 unsigned long end_time
;
630 const int cap
= host
->pmecc_corr_cap
;
631 const int num
= 2 * cap
+ 1;
632 int sector_size
= host
->pmecc_sector_size
;
633 int err_nbr
= 0; /* number of error */
634 int roots_nbr
; /* number of roots */
637 int16_t *smu
= host
->pmecc_smu
;
639 pmerrloc_writel(host
->pmerrloc_base
, ELDIS
, PMERRLOC_DISABLE
);
641 for (i
= 0; i
<= host
->pmecc_lmu
[cap
+ 1] >> 1; i
++) {
642 pmerrloc_writel_sigma_relaxed(host
->pmerrloc_base
, i
,
643 smu
[(cap
+ 1) * num
+ i
]);
647 val
= (err_nbr
- 1) << 16;
648 if (sector_size
== 1024)
651 pmerrloc_writel(host
->pmerrloc_base
, ELCFG
, val
);
652 pmerrloc_writel(host
->pmerrloc_base
, ELEN
,
653 sector_size
* 8 + host
->pmecc_degree
* cap
);
655 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
656 while (!(pmerrloc_readl_relaxed(host
->pmerrloc_base
, ELISR
)
657 & PMERRLOC_CALC_DONE
)) {
658 if (unlikely(time_after(jiffies
, end_time
))) {
659 dev_err(host
->dev
, "PMECC: Timeout to calculate error location.\n");
665 roots_nbr
= (pmerrloc_readl_relaxed(host
->pmerrloc_base
, ELISR
)
666 & PMERRLOC_ERR_NUM_MASK
) >> 8;
667 /* Number of roots == degree of smu hence <= cap */
668 if (roots_nbr
== host
->pmecc_lmu
[cap
+ 1] >> 1)
671 /* Number of roots does not match the degree of smu
672 * unable to correct error */
676 static void pmecc_correct_data(struct mtd_info
*mtd
, uint8_t *buf
, uint8_t *ecc
,
677 int sector_num
, int extra_bytes
, int err_nbr
)
679 struct nand_chip
*nand_chip
= mtd
->priv
;
680 struct atmel_nand_host
*host
= nand_chip
->priv
;
682 int byte_pos
, bit_pos
, sector_size
, pos
;
686 sector_size
= host
->pmecc_sector_size
;
689 tmp
= pmerrloc_readl_el_relaxed(host
->pmerrloc_base
, i
) - 1;
693 if (byte_pos
>= (sector_size
+ extra_bytes
))
694 BUG(); /* should never happen */
696 if (byte_pos
< sector_size
) {
697 err_byte
= *(buf
+ byte_pos
);
698 *(buf
+ byte_pos
) ^= (1 << bit_pos
);
700 pos
= sector_num
* host
->pmecc_sector_size
+ byte_pos
;
701 dev_info(host
->dev
, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
702 pos
, bit_pos
, err_byte
, *(buf
+ byte_pos
));
704 /* Bit flip in OOB area */
705 tmp
= sector_num
* host
->pmecc_bytes_per_sector
706 + (byte_pos
- sector_size
);
708 ecc
[tmp
] ^= (1 << bit_pos
);
710 pos
= tmp
+ nand_chip
->ecc
.layout
->eccpos
[0];
711 dev_info(host
->dev
, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
712 pos
, bit_pos
, err_byte
, ecc
[tmp
]);
722 static int pmecc_correction(struct mtd_info
*mtd
, u32 pmecc_stat
, uint8_t *buf
,
725 struct nand_chip
*nand_chip
= mtd
->priv
;
726 struct atmel_nand_host
*host
= nand_chip
->priv
;
727 int i
, err_nbr
, eccbytes
;
731 eccbytes
= nand_chip
->ecc
.bytes
;
732 for (i
= 0; i
< eccbytes
; i
++)
735 /* Erased page, return OK */
739 for (i
= 0; i
< host
->pmecc_sector_number
; i
++) {
741 if (pmecc_stat
& 0x1) {
742 buf_pos
= buf
+ i
* host
->pmecc_sector_size
;
744 pmecc_gen_syndrome(mtd
, i
);
745 pmecc_substitute(mtd
);
746 pmecc_get_sigma(mtd
);
748 err_nbr
= pmecc_err_location(mtd
);
750 dev_err(host
->dev
, "PMECC: Too many errors\n");
751 mtd
->ecc_stats
.failed
++;
754 pmecc_correct_data(mtd
, buf_pos
, ecc
, i
,
755 host
->pmecc_bytes_per_sector
, err_nbr
);
756 mtd
->ecc_stats
.corrected
+= err_nbr
;
757 total_err
+= err_nbr
;
766 static int atmel_nand_pmecc_read_page(struct mtd_info
*mtd
,
767 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
769 struct atmel_nand_host
*host
= chip
->priv
;
770 int eccsize
= chip
->ecc
.size
;
771 uint8_t *oob
= chip
->oob_poi
;
772 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
774 unsigned long end_time
;
777 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
778 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
779 pmecc_writel(host
->ecc
, CFG
, (pmecc_readl_relaxed(host
->ecc
, CFG
)
780 & ~PMECC_CFG_WRITE_OP
) | PMECC_CFG_AUTO_ENABLE
);
782 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
783 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DATA
);
785 chip
->read_buf(mtd
, buf
, eccsize
);
786 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
788 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
789 while ((pmecc_readl_relaxed(host
->ecc
, SR
) & PMECC_SR_BUSY
)) {
790 if (unlikely(time_after(jiffies
, end_time
))) {
791 dev_err(host
->dev
, "PMECC: Timeout to get error status.\n");
797 stat
= pmecc_readl_relaxed(host
->ecc
, ISR
);
799 bitflips
= pmecc_correction(mtd
, stat
, buf
, &oob
[eccpos
[0]]);
801 /* uncorrectable errors */
808 static int atmel_nand_pmecc_write_page(struct mtd_info
*mtd
,
809 struct nand_chip
*chip
, const uint8_t *buf
, int oob_required
)
811 struct atmel_nand_host
*host
= chip
->priv
;
812 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
814 unsigned long end_time
;
816 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
817 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
819 pmecc_writel(host
->ecc
, CFG
, (pmecc_readl_relaxed(host
->ecc
, CFG
) |
820 PMECC_CFG_WRITE_OP
) & ~PMECC_CFG_AUTO_ENABLE
);
822 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
823 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DATA
);
825 chip
->write_buf(mtd
, (u8
*)buf
, mtd
->writesize
);
827 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
828 while ((pmecc_readl_relaxed(host
->ecc
, SR
) & PMECC_SR_BUSY
)) {
829 if (unlikely(time_after(jiffies
, end_time
))) {
830 dev_err(host
->dev
, "PMECC: Timeout to get ECC value.\n");
836 for (i
= 0; i
< host
->pmecc_sector_number
; i
++) {
837 for (j
= 0; j
< host
->pmecc_bytes_per_sector
; j
++) {
840 pos
= i
* host
->pmecc_bytes_per_sector
+ j
;
841 chip
->oob_poi
[eccpos
[pos
]] =
842 pmecc_readb_ecc_relaxed(host
->ecc
, i
, j
);
845 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
850 static void atmel_pmecc_core_init(struct mtd_info
*mtd
)
852 struct nand_chip
*nand_chip
= mtd
->priv
;
853 struct atmel_nand_host
*host
= nand_chip
->priv
;
855 struct nand_ecclayout
*ecc_layout
;
857 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
858 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
860 switch (host
->pmecc_corr_cap
) {
862 val
= PMECC_CFG_BCH_ERR2
;
865 val
= PMECC_CFG_BCH_ERR4
;
868 val
= PMECC_CFG_BCH_ERR8
;
871 val
= PMECC_CFG_BCH_ERR12
;
874 val
= PMECC_CFG_BCH_ERR24
;
878 if (host
->pmecc_sector_size
== 512)
879 val
|= PMECC_CFG_SECTOR512
;
880 else if (host
->pmecc_sector_size
== 1024)
881 val
|= PMECC_CFG_SECTOR1024
;
883 switch (host
->pmecc_sector_number
) {
885 val
|= PMECC_CFG_PAGE_1SECTOR
;
888 val
|= PMECC_CFG_PAGE_2SECTORS
;
891 val
|= PMECC_CFG_PAGE_4SECTORS
;
894 val
|= PMECC_CFG_PAGE_8SECTORS
;
898 val
|= (PMECC_CFG_READ_OP
| PMECC_CFG_SPARE_DISABLE
899 | PMECC_CFG_AUTO_DISABLE
);
900 pmecc_writel(host
->ecc
, CFG
, val
);
902 ecc_layout
= nand_chip
->ecc
.layout
;
903 pmecc_writel(host
->ecc
, SAREA
, mtd
->oobsize
- 1);
904 pmecc_writel(host
->ecc
, SADDR
, ecc_layout
->eccpos
[0]);
905 pmecc_writel(host
->ecc
, EADDR
,
906 ecc_layout
->eccpos
[ecc_layout
->eccbytes
- 1]);
907 /* See datasheet about PMECC Clock Control Register */
908 pmecc_writel(host
->ecc
, CLK
, 2);
909 pmecc_writel(host
->ecc
, IDR
, 0xff);
910 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
914 * Get ECC requirement in ONFI parameters, returns -1 if ONFI
915 * parameters is not supported.
916 * return 0 if success to get the ECC requirement.
918 static int get_onfi_ecc_param(struct nand_chip
*chip
,
919 int *ecc_bits
, int *sector_size
)
921 *ecc_bits
= *sector_size
= 0;
923 if (chip
->onfi_params
.ecc_bits
== 0xff)
924 /* TODO: the sector_size and ecc_bits need to be find in
925 * extended ecc parameter, currently we don't support it.
929 *ecc_bits
= chip
->onfi_params
.ecc_bits
;
931 /* The default sector size (ecc codeword size) is 512 */
938 * Get ecc requirement from ONFI parameters ecc requirement.
939 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
940 * will set them according to ONFI ecc requirement. Otherwise, use the
942 * return 0 if success. otherwise return error code.
944 static int pmecc_choose_ecc(struct atmel_nand_host
*host
,
945 int *cap
, int *sector_size
)
947 /* Get ECC requirement from ONFI parameters */
948 *cap
= *sector_size
= 0;
949 if (host
->nand_chip
.onfi_version
) {
950 if (!get_onfi_ecc_param(&host
->nand_chip
, cap
, sector_size
))
951 dev_info(host
->dev
, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
954 dev_info(host
->dev
, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
956 dev_info(host
->dev
, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
958 if (*cap
== 0 && *sector_size
== 0) {
963 /* If dts file doesn't specify then use the one in ONFI parameters */
964 if (host
->pmecc_corr_cap
== 0) {
965 /* use the most fitable ecc bits (the near bigger one ) */
967 host
->pmecc_corr_cap
= 2;
969 host
->pmecc_corr_cap
= 4;
971 host
->pmecc_corr_cap
= 8;
973 host
->pmecc_corr_cap
= 12;
975 host
->pmecc_corr_cap
= 24;
979 if (host
->pmecc_sector_size
== 0) {
980 /* use the most fitable sector size (the near smaller one ) */
981 if (*sector_size
>= 1024)
982 host
->pmecc_sector_size
= 1024;
983 else if (*sector_size
>= 512)
984 host
->pmecc_sector_size
= 512;
991 static int __init
atmel_pmecc_nand_init_params(struct platform_device
*pdev
,
992 struct atmel_nand_host
*host
)
994 struct mtd_info
*mtd
= &host
->mtd
;
995 struct nand_chip
*nand_chip
= &host
->nand_chip
;
996 struct resource
*regs
, *regs_pmerr
, *regs_rom
;
997 int cap
, sector_size
, err_no
;
999 err_no
= pmecc_choose_ecc(host
, &cap
, §or_size
);
1001 dev_err(host
->dev
, "The NAND flash's ECC requirement are not support!");
1005 if (cap
!= host
->pmecc_corr_cap
||
1006 sector_size
!= host
->pmecc_sector_size
)
1007 dev_info(host
->dev
, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1009 cap
= host
->pmecc_corr_cap
;
1010 sector_size
= host
->pmecc_sector_size
;
1011 host
->pmecc_lookup_table_offset
= (sector_size
== 512) ?
1012 host
->pmecc_lookup_table_offset_512
:
1013 host
->pmecc_lookup_table_offset_1024
;
1015 dev_info(host
->dev
, "Initialize PMECC params, cap: %d, sector: %d\n",
1018 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1021 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1022 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1026 host
->ecc
= ioremap(regs
->start
, resource_size(regs
));
1027 if (host
->ecc
== NULL
) {
1028 dev_err(host
->dev
, "ioremap failed\n");
1030 goto err_pmecc_ioremap
;
1033 regs_pmerr
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
1034 regs_rom
= platform_get_resource(pdev
, IORESOURCE_MEM
, 3);
1035 if (regs_pmerr
&& regs_rom
) {
1036 host
->pmerrloc_base
= ioremap(regs_pmerr
->start
,
1037 resource_size(regs_pmerr
));
1038 host
->pmecc_rom_base
= ioremap(regs_rom
->start
,
1039 resource_size(regs_rom
));
1042 if (!host
->pmerrloc_base
|| !host
->pmecc_rom_base
) {
1044 "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
1046 goto err_pmloc_ioremap
;
1049 /* ECC is calculated for the whole page (1 step) */
1050 nand_chip
->ecc
.size
= mtd
->writesize
;
1052 /* set ECC page size and oob layout */
1053 switch (mtd
->writesize
) {
1055 host
->pmecc_degree
= PMECC_GF_DIMENSION_13
;
1056 host
->pmecc_cw_len
= (1 << host
->pmecc_degree
) - 1;
1057 host
->pmecc_sector_number
= mtd
->writesize
/ sector_size
;
1058 host
->pmecc_bytes_per_sector
= pmecc_get_ecc_bytes(
1060 host
->pmecc_alpha_to
= pmecc_get_alpha_to(host
);
1061 host
->pmecc_index_of
= host
->pmecc_rom_base
+
1062 host
->pmecc_lookup_table_offset
;
1064 nand_chip
->ecc
.steps
= 1;
1065 nand_chip
->ecc
.strength
= cap
;
1066 nand_chip
->ecc
.bytes
= host
->pmecc_bytes_per_sector
*
1067 host
->pmecc_sector_number
;
1068 if (nand_chip
->ecc
.bytes
> mtd
->oobsize
- 2) {
1069 dev_err(host
->dev
, "No room for ECC bytes\n");
1071 goto err_no_ecc_room
;
1073 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo
,
1075 nand_chip
->ecc
.bytes
);
1076 nand_chip
->ecc
.layout
= &atmel_pmecc_oobinfo
;
1083 "Unsupported page size for PMECC, use Software ECC\n");
1085 /* page size not handled by HW ECC */
1086 /* switching back to soft ECC */
1087 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1091 /* Allocate data for PMECC computation */
1092 err_no
= pmecc_data_alloc(host
);
1095 "Cannot allocate memory for PMECC computation!\n");
1096 goto err_pmecc_data_alloc
;
1099 nand_chip
->ecc
.read_page
= atmel_nand_pmecc_read_page
;
1100 nand_chip
->ecc
.write_page
= atmel_nand_pmecc_write_page
;
1102 atmel_pmecc_core_init(mtd
);
1106 err_pmecc_data_alloc
:
1110 if (host
->pmerrloc_base
)
1111 iounmap(host
->pmerrloc_base
);
1112 if (host
->pmecc_rom_base
)
1113 iounmap(host
->pmecc_rom_base
);
1121 * function called after a write
1123 * mtd: MTD block structure
1124 * dat: raw data (unused)
1125 * ecc_code: buffer for ECC
1127 static int atmel_nand_calculate(struct mtd_info
*mtd
,
1128 const u_char
*dat
, unsigned char *ecc_code
)
1130 struct nand_chip
*nand_chip
= mtd
->priv
;
1131 struct atmel_nand_host
*host
= nand_chip
->priv
;
1132 unsigned int ecc_value
;
1134 /* get the first 2 ECC bytes */
1135 ecc_value
= ecc_readl(host
->ecc
, PR
);
1137 ecc_code
[0] = ecc_value
& 0xFF;
1138 ecc_code
[1] = (ecc_value
>> 8) & 0xFF;
1140 /* get the last 2 ECC bytes */
1141 ecc_value
= ecc_readl(host
->ecc
, NPR
) & ATMEL_ECC_NPARITY
;
1143 ecc_code
[2] = ecc_value
& 0xFF;
1144 ecc_code
[3] = (ecc_value
>> 8) & 0xFF;
1150 * HW ECC read page function
1152 * mtd: mtd info structure
1153 * chip: nand chip info structure
1154 * buf: buffer to store read data
1155 * oob_required: caller expects OOB data read to chip->oob_poi
1157 static int atmel_nand_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1158 uint8_t *buf
, int oob_required
, int page
)
1160 int eccsize
= chip
->ecc
.size
;
1161 int eccbytes
= chip
->ecc
.bytes
;
1162 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1164 uint8_t *oob
= chip
->oob_poi
;
1167 unsigned int max_bitflips
= 0;
1170 * Errata: ALE is incorrectly wired up to the ECC controller
1171 * on the AP7000, so it will include the address cycles in the
1174 * Workaround: Reset the parity registers before reading the
1177 if (cpu_is_at32ap7000()) {
1178 struct atmel_nand_host
*host
= chip
->priv
;
1179 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
1183 chip
->read_buf(mtd
, p
, eccsize
);
1185 /* move to ECC position if needed */
1186 if (eccpos
[0] != 0) {
1187 /* This only works on large pages
1188 * because the ECC controller waits for
1189 * NAND_CMD_RNDOUTSTART after the
1191 * anyway, for small pages, the eccpos[0] == 0
1193 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1194 mtd
->writesize
+ eccpos
[0], -1);
1197 /* the ECC controller needs to read the ECC just after the data */
1198 ecc_pos
= oob
+ eccpos
[0];
1199 chip
->read_buf(mtd
, ecc_pos
, eccbytes
);
1201 /* check if there's an error */
1202 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1205 mtd
->ecc_stats
.failed
++;
1207 mtd
->ecc_stats
.corrected
+= stat
;
1208 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1211 /* get back to oob start (end of page) */
1212 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1215 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
1217 return max_bitflips
;
1223 * function called after a read
1225 * mtd: MTD block structure
1226 * dat: raw data read from the chip
1227 * read_ecc: ECC from the chip (unused)
1230 * Detect and correct a 1 bit error for a page
1232 static int atmel_nand_correct(struct mtd_info
*mtd
, u_char
*dat
,
1233 u_char
*read_ecc
, u_char
*isnull
)
1235 struct nand_chip
*nand_chip
= mtd
->priv
;
1236 struct atmel_nand_host
*host
= nand_chip
->priv
;
1237 unsigned int ecc_status
;
1238 unsigned int ecc_word
, ecc_bit
;
1240 /* get the status from the Status Register */
1241 ecc_status
= ecc_readl(host
->ecc
, SR
);
1243 /* if there's no error */
1244 if (likely(!(ecc_status
& ATMEL_ECC_RECERR
)))
1247 /* get error bit offset (4 bits) */
1248 ecc_bit
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_BITADDR
;
1249 /* get word address (12 bits) */
1250 ecc_word
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_WORDADDR
;
1253 /* if there are multiple errors */
1254 if (ecc_status
& ATMEL_ECC_MULERR
) {
1255 /* check if it is a freshly erased block
1256 * (filled with 0xff) */
1257 if ((ecc_bit
== ATMEL_ECC_BITADDR
)
1258 && (ecc_word
== (ATMEL_ECC_WORDADDR
>> 4))) {
1259 /* the block has just been erased, return OK */
1262 /* it doesn't seems to be a freshly
1264 * We can't correct so many errors */
1265 dev_dbg(host
->dev
, "atmel_nand : multiple errors detected."
1266 " Unable to correct.\n");
1270 /* if there's a single bit error : we can correct it */
1271 if (ecc_status
& ATMEL_ECC_ECCERR
) {
1272 /* there's nothing much to do here.
1273 * the bit error is on the ECC itself.
1275 dev_dbg(host
->dev
, "atmel_nand : one bit error on ECC code."
1276 " Nothing to correct\n");
1280 dev_dbg(host
->dev
, "atmel_nand : one bit error on data."
1281 " (word offset in the page :"
1282 " 0x%x bit offset : 0x%x)\n",
1284 /* correct the error */
1285 if (nand_chip
->options
& NAND_BUSWIDTH_16
) {
1287 ((unsigned short *) dat
)[ecc_word
] ^= (1 << ecc_bit
);
1290 dat
[ecc_word
] ^= (1 << ecc_bit
);
1292 dev_dbg(host
->dev
, "atmel_nand : error corrected\n");
1297 * Enable HW ECC : unused on most chips
1299 static void atmel_nand_hwctl(struct mtd_info
*mtd
, int mode
)
1301 if (cpu_is_at32ap7000()) {
1302 struct nand_chip
*nand_chip
= mtd
->priv
;
1303 struct atmel_nand_host
*host
= nand_chip
->priv
;
1304 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
1308 #if defined(CONFIG_OF)
1309 static int atmel_of_init_port(struct atmel_nand_host
*host
,
1310 struct device_node
*np
)
1315 struct atmel_nand_data
*board
= &host
->board
;
1316 enum of_gpio_flags flags
;
1318 if (of_property_read_u32(np
, "atmel,nand-addr-offset", &val
) == 0) {
1320 dev_err(host
->dev
, "invalid addr-offset %u\n", val
);
1326 if (of_property_read_u32(np
, "atmel,nand-cmd-offset", &val
) == 0) {
1328 dev_err(host
->dev
, "invalid cmd-offset %u\n", val
);
1334 ecc_mode
= of_get_nand_ecc_mode(np
);
1336 board
->ecc_mode
= ecc_mode
< 0 ? NAND_ECC_SOFT
: ecc_mode
;
1338 board
->on_flash_bbt
= of_get_nand_on_flash_bbt(np
);
1340 if (of_get_nand_bus_width(np
) == 16)
1341 board
->bus_width_16
= 1;
1343 board
->rdy_pin
= of_get_gpio_flags(np
, 0, &flags
);
1344 board
->rdy_pin_active_low
= (flags
== OF_GPIO_ACTIVE_LOW
);
1346 board
->enable_pin
= of_get_gpio(np
, 1);
1347 board
->det_pin
= of_get_gpio(np
, 2);
1349 host
->has_pmecc
= of_property_read_bool(np
, "atmel,has-pmecc");
1351 if (!(board
->ecc_mode
== NAND_ECC_HW
) || !host
->has_pmecc
)
1352 return 0; /* Not using PMECC */
1354 /* use PMECC, get correction capability, sector size and lookup
1356 * If correction bits and sector size are not specified, then find
1357 * them from NAND ONFI parameters.
1359 if (of_property_read_u32(np
, "atmel,pmecc-cap", &val
) == 0) {
1360 if ((val
!= 2) && (val
!= 4) && (val
!= 8) && (val
!= 12) &&
1363 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1367 host
->pmecc_corr_cap
= (u8
)val
;
1370 if (of_property_read_u32(np
, "atmel,pmecc-sector-size", &val
) == 0) {
1371 if ((val
!= 512) && (val
!= 1024)) {
1373 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1377 host
->pmecc_sector_size
= (u16
)val
;
1380 if (of_property_read_u32_array(np
, "atmel,pmecc-lookup-table-offset",
1382 dev_err(host
->dev
, "Cannot get PMECC lookup table offset\n");
1385 if (!offset
[0] && !offset
[1]) {
1386 dev_err(host
->dev
, "Invalid PMECC lookup table offset\n");
1389 host
->pmecc_lookup_table_offset_512
= offset
[0];
1390 host
->pmecc_lookup_table_offset_1024
= offset
[1];
1395 static int atmel_of_init_port(struct atmel_nand_host
*host
,
1396 struct device_node
*np
)
1402 static int __init
atmel_hw_nand_init_params(struct platform_device
*pdev
,
1403 struct atmel_nand_host
*host
)
1405 struct mtd_info
*mtd
= &host
->mtd
;
1406 struct nand_chip
*nand_chip
= &host
->nand_chip
;
1407 struct resource
*regs
;
1409 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1412 "Can't get I/O resource regs, use software ECC\n");
1413 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1417 host
->ecc
= ioremap(regs
->start
, resource_size(regs
));
1418 if (host
->ecc
== NULL
) {
1419 dev_err(host
->dev
, "ioremap failed\n");
1423 /* ECC is calculated for the whole page (1 step) */
1424 nand_chip
->ecc
.size
= mtd
->writesize
;
1426 /* set ECC page size and oob layout */
1427 switch (mtd
->writesize
) {
1429 nand_chip
->ecc
.layout
= &atmel_oobinfo_small
;
1430 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_528
);
1433 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1434 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_1056
);
1437 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1438 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_2112
);
1441 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1442 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_4224
);
1445 /* page size not handled by HW ECC */
1446 /* switching back to soft ECC */
1447 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1451 /* set up for HW ECC */
1452 nand_chip
->ecc
.calculate
= atmel_nand_calculate
;
1453 nand_chip
->ecc
.correct
= atmel_nand_correct
;
1454 nand_chip
->ecc
.hwctl
= atmel_nand_hwctl
;
1455 nand_chip
->ecc
.read_page
= atmel_nand_read_page
;
1456 nand_chip
->ecc
.bytes
= 4;
1457 nand_chip
->ecc
.strength
= 1;
1463 * Probe for the NAND device.
1465 static int __init
atmel_nand_probe(struct platform_device
*pdev
)
1467 struct atmel_nand_host
*host
;
1468 struct mtd_info
*mtd
;
1469 struct nand_chip
*nand_chip
;
1470 struct resource
*mem
;
1471 struct mtd_part_parser_data ppdata
= {};
1473 struct pinctrl
*pinctrl
;
1475 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1477 printk(KERN_ERR
"atmel_nand: can't get I/O resource mem\n");
1481 /* Allocate memory for the device structure (and zero it) */
1482 host
= kzalloc(sizeof(struct atmel_nand_host
), GFP_KERNEL
);
1484 printk(KERN_ERR
"atmel_nand: failed to allocate device structure.\n");
1488 host
->io_phys
= (dma_addr_t
)mem
->start
;
1490 host
->io_base
= ioremap(mem
->start
, resource_size(mem
));
1491 if (host
->io_base
== NULL
) {
1492 printk(KERN_ERR
"atmel_nand: ioremap failed\n");
1494 goto err_nand_ioremap
;
1498 nand_chip
= &host
->nand_chip
;
1499 host
->dev
= &pdev
->dev
;
1500 if (pdev
->dev
.of_node
) {
1501 res
= atmel_of_init_port(host
, pdev
->dev
.of_node
);
1503 goto err_ecc_ioremap
;
1505 memcpy(&host
->board
, pdev
->dev
.platform_data
,
1506 sizeof(struct atmel_nand_data
));
1509 nand_chip
->priv
= host
; /* link the private data structures */
1510 mtd
->priv
= nand_chip
;
1511 mtd
->owner
= THIS_MODULE
;
1513 /* Set address of NAND IO lines */
1514 nand_chip
->IO_ADDR_R
= host
->io_base
;
1515 nand_chip
->IO_ADDR_W
= host
->io_base
;
1516 nand_chip
->cmd_ctrl
= atmel_nand_cmd_ctrl
;
1518 pinctrl
= devm_pinctrl_get_select_default(&pdev
->dev
);
1519 if (IS_ERR(pinctrl
)) {
1520 dev_err(host
->dev
, "Failed to request pinctrl\n");
1521 res
= PTR_ERR(pinctrl
);
1522 goto err_ecc_ioremap
;
1525 if (gpio_is_valid(host
->board
.rdy_pin
)) {
1526 res
= gpio_request(host
->board
.rdy_pin
, "nand_rdy");
1529 "can't request rdy gpio %d\n",
1530 host
->board
.rdy_pin
);
1531 goto err_ecc_ioremap
;
1534 res
= gpio_direction_input(host
->board
.rdy_pin
);
1537 "can't request input direction rdy gpio %d\n",
1538 host
->board
.rdy_pin
);
1539 goto err_ecc_ioremap
;
1542 nand_chip
->dev_ready
= atmel_nand_device_ready
;
1545 if (gpio_is_valid(host
->board
.enable_pin
)) {
1546 res
= gpio_request(host
->board
.enable_pin
, "nand_enable");
1549 "can't request enable gpio %d\n",
1550 host
->board
.enable_pin
);
1551 goto err_ecc_ioremap
;
1554 res
= gpio_direction_output(host
->board
.enable_pin
, 1);
1557 "can't request output direction enable gpio %d\n",
1558 host
->board
.enable_pin
);
1559 goto err_ecc_ioremap
;
1563 nand_chip
->ecc
.mode
= host
->board
.ecc_mode
;
1564 nand_chip
->chip_delay
= 20; /* 20us command delay time */
1566 if (host
->board
.bus_width_16
) /* 16-bit bus width */
1567 nand_chip
->options
|= NAND_BUSWIDTH_16
;
1569 nand_chip
->read_buf
= atmel_read_buf
;
1570 nand_chip
->write_buf
= atmel_write_buf
;
1572 platform_set_drvdata(pdev
, host
);
1573 atmel_nand_enable(host
);
1575 if (gpio_is_valid(host
->board
.det_pin
)) {
1576 res
= gpio_request(host
->board
.det_pin
, "nand_det");
1579 "can't request det gpio %d\n",
1580 host
->board
.det_pin
);
1584 res
= gpio_direction_input(host
->board
.det_pin
);
1587 "can't request input direction det gpio %d\n",
1588 host
->board
.det_pin
);
1592 if (gpio_get_value(host
->board
.det_pin
)) {
1593 printk(KERN_INFO
"No SmartMedia card inserted.\n");
1599 if (host
->board
.on_flash_bbt
|| on_flash_bbt
) {
1600 printk(KERN_INFO
"atmel_nand: Use On Flash BBT\n");
1601 nand_chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
1608 dma_cap_mask_t mask
;
1611 dma_cap_set(DMA_MEMCPY
, mask
);
1612 host
->dma_chan
= dma_request_channel(mask
, NULL
, NULL
);
1613 if (!host
->dma_chan
) {
1614 dev_err(host
->dev
, "Failed to request DMA channel\n");
1619 dev_info(host
->dev
, "Using %s for DMA transfers.\n",
1620 dma_chan_name(host
->dma_chan
));
1622 dev_info(host
->dev
, "No DMA support for NAND access.\n");
1624 /* first scan to find the device and get the page size */
1625 if (nand_scan_ident(mtd
, 1, NULL
)) {
1627 goto err_scan_ident
;
1630 if (nand_chip
->ecc
.mode
== NAND_ECC_HW
) {
1631 if (host
->has_pmecc
)
1632 res
= atmel_pmecc_nand_init_params(pdev
, host
);
1634 res
= atmel_hw_nand_init_params(pdev
, host
);
1640 /* second phase scan */
1641 if (nand_scan_tail(mtd
)) {
1646 mtd
->name
= "atmel_nand";
1647 ppdata
.of_node
= pdev
->dev
.of_node
;
1648 res
= mtd_device_parse_register(mtd
, NULL
, &ppdata
,
1649 host
->board
.parts
, host
->board
.num_parts
);
1654 if (host
->has_pmecc
&& host
->nand_chip
.ecc
.mode
== NAND_ECC_HW
) {
1655 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
1656 pmecc_data_free(host
);
1660 if (host
->pmerrloc_base
)
1661 iounmap(host
->pmerrloc_base
);
1662 if (host
->pmecc_rom_base
)
1663 iounmap(host
->pmecc_rom_base
);
1667 atmel_nand_disable(host
);
1668 platform_set_drvdata(pdev
, NULL
);
1670 dma_release_channel(host
->dma_chan
);
1672 iounmap(host
->io_base
);
1679 * Remove a NAND device.
1681 static int __exit
atmel_nand_remove(struct platform_device
*pdev
)
1683 struct atmel_nand_host
*host
= platform_get_drvdata(pdev
);
1684 struct mtd_info
*mtd
= &host
->mtd
;
1688 atmel_nand_disable(host
);
1690 if (host
->has_pmecc
&& host
->nand_chip
.ecc
.mode
== NAND_ECC_HW
) {
1691 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
1692 pmerrloc_writel(host
->pmerrloc_base
, ELDIS
,
1694 pmecc_data_free(host
);
1697 if (gpio_is_valid(host
->board
.det_pin
))
1698 gpio_free(host
->board
.det_pin
);
1700 if (gpio_is_valid(host
->board
.enable_pin
))
1701 gpio_free(host
->board
.enable_pin
);
1703 if (gpio_is_valid(host
->board
.rdy_pin
))
1704 gpio_free(host
->board
.rdy_pin
);
1708 if (host
->pmecc_rom_base
)
1709 iounmap(host
->pmecc_rom_base
);
1710 if (host
->pmerrloc_base
)
1711 iounmap(host
->pmerrloc_base
);
1714 dma_release_channel(host
->dma_chan
);
1716 iounmap(host
->io_base
);
1722 #if defined(CONFIG_OF)
1723 static const struct of_device_id atmel_nand_dt_ids
[] = {
1724 { .compatible
= "atmel,at91rm9200-nand" },
1728 MODULE_DEVICE_TABLE(of
, atmel_nand_dt_ids
);
1731 static struct platform_driver atmel_nand_driver
= {
1732 .remove
= __exit_p(atmel_nand_remove
),
1734 .name
= "atmel_nand",
1735 .owner
= THIS_MODULE
,
1736 .of_match_table
= of_match_ptr(atmel_nand_dt_ids
),
1740 module_platform_driver_probe(atmel_nand_driver
, atmel_nand_probe
);
1742 MODULE_LICENSE("GPL");
1743 MODULE_AUTHOR("Rick Bronson");
1744 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
1745 MODULE_ALIAS("platform:atmel_nand");