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mtd: nand: atmel_nand: remove unnecessary platform_set_drvdata()
[mirror_ubuntu-zesty-kernel.git] / drivers / mtd / nand / atmel_nand.c
1 /*
2 * Copyright © 2003 Rick Bronson
3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
6 *
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
9 *
10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 *
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License version 2 as
23 * published by the Free Software Foundation.
24 *
25 */
26
27 #include <linux/dma-mapping.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/platform_device.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_gpio.h>
35 #include <linux/of_mtd.h>
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/partitions.h>
39
40 #include <linux/dmaengine.h>
41 #include <linux/gpio.h>
42 #include <linux/io.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/pinctrl/consumer.h>
45
46 static int use_dma = 1;
47 module_param(use_dma, int, 0);
48
49 static int on_flash_bbt = 0;
50 module_param(on_flash_bbt, int, 0);
51
52 /* Register access macros */
53 #define ecc_readl(add, reg) \
54 __raw_readl(add + ATMEL_ECC_##reg)
55 #define ecc_writel(add, reg, value) \
56 __raw_writel((value), add + ATMEL_ECC_##reg)
57
58 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
59
60 /* oob layout for large page size
61 * bad block info is on bytes 0 and 1
62 * the bytes have to be consecutives to avoid
63 * several NAND_CMD_RNDOUT during read
64 */
65 static struct nand_ecclayout atmel_oobinfo_large = {
66 .eccbytes = 4,
67 .eccpos = {60, 61, 62, 63},
68 .oobfree = {
69 {2, 58}
70 },
71 };
72
73 /* oob layout for small page size
74 * bad block info is on bytes 4 and 5
75 * the bytes have to be consecutives to avoid
76 * several NAND_CMD_RNDOUT during read
77 */
78 static struct nand_ecclayout atmel_oobinfo_small = {
79 .eccbytes = 4,
80 .eccpos = {0, 1, 2, 3},
81 .oobfree = {
82 {6, 10}
83 },
84 };
85
86 struct atmel_nand_host {
87 struct nand_chip nand_chip;
88 struct mtd_info mtd;
89 void __iomem *io_base;
90 dma_addr_t io_phys;
91 struct atmel_nand_data board;
92 struct device *dev;
93 void __iomem *ecc;
94
95 struct completion comp;
96 struct dma_chan *dma_chan;
97
98 bool has_pmecc;
99 u8 pmecc_corr_cap;
100 u16 pmecc_sector_size;
101 u32 pmecc_lookup_table_offset;
102 u32 pmecc_lookup_table_offset_512;
103 u32 pmecc_lookup_table_offset_1024;
104
105 int pmecc_bytes_per_sector;
106 int pmecc_sector_number;
107 int pmecc_degree; /* Degree of remainders */
108 int pmecc_cw_len; /* Length of codeword */
109
110 void __iomem *pmerrloc_base;
111 void __iomem *pmecc_rom_base;
112
113 /* lookup table for alpha_to and index_of */
114 void __iomem *pmecc_alpha_to;
115 void __iomem *pmecc_index_of;
116
117 /* data for pmecc computation */
118 int16_t *pmecc_partial_syn;
119 int16_t *pmecc_si;
120 int16_t *pmecc_smu; /* Sigma table */
121 int16_t *pmecc_lmu; /* polynomal order */
122 int *pmecc_mu;
123 int *pmecc_dmu;
124 int *pmecc_delta;
125 };
126
127 static struct nand_ecclayout atmel_pmecc_oobinfo;
128
129 /*
130 * Enable NAND.
131 */
132 static void atmel_nand_enable(struct atmel_nand_host *host)
133 {
134 if (gpio_is_valid(host->board.enable_pin))
135 gpio_set_value(host->board.enable_pin, 0);
136 }
137
138 /*
139 * Disable NAND.
140 */
141 static void atmel_nand_disable(struct atmel_nand_host *host)
142 {
143 if (gpio_is_valid(host->board.enable_pin))
144 gpio_set_value(host->board.enable_pin, 1);
145 }
146
147 /*
148 * Hardware specific access to control-lines
149 */
150 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
151 {
152 struct nand_chip *nand_chip = mtd->priv;
153 struct atmel_nand_host *host = nand_chip->priv;
154
155 if (ctrl & NAND_CTRL_CHANGE) {
156 if (ctrl & NAND_NCE)
157 atmel_nand_enable(host);
158 else
159 atmel_nand_disable(host);
160 }
161 if (cmd == NAND_CMD_NONE)
162 return;
163
164 if (ctrl & NAND_CLE)
165 writeb(cmd, host->io_base + (1 << host->board.cle));
166 else
167 writeb(cmd, host->io_base + (1 << host->board.ale));
168 }
169
170 /*
171 * Read the Device Ready pin.
172 */
173 static int atmel_nand_device_ready(struct mtd_info *mtd)
174 {
175 struct nand_chip *nand_chip = mtd->priv;
176 struct atmel_nand_host *host = nand_chip->priv;
177
178 return gpio_get_value(host->board.rdy_pin) ^
179 !!host->board.rdy_pin_active_low;
180 }
181
182 /*
183 * Minimal-overhead PIO for data access.
184 */
185 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
186 {
187 struct nand_chip *nand_chip = mtd->priv;
188
189 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
190 }
191
192 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
193 {
194 struct nand_chip *nand_chip = mtd->priv;
195
196 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
197 }
198
199 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
200 {
201 struct nand_chip *nand_chip = mtd->priv;
202
203 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
204 }
205
206 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
207 {
208 struct nand_chip *nand_chip = mtd->priv;
209
210 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
211 }
212
213 static void dma_complete_func(void *completion)
214 {
215 complete(completion);
216 }
217
218 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
219 int is_read)
220 {
221 struct dma_device *dma_dev;
222 enum dma_ctrl_flags flags;
223 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
224 struct dma_async_tx_descriptor *tx = NULL;
225 dma_cookie_t cookie;
226 struct nand_chip *chip = mtd->priv;
227 struct atmel_nand_host *host = chip->priv;
228 void *p = buf;
229 int err = -EIO;
230 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
231
232 if (buf >= high_memory)
233 goto err_buf;
234
235 dma_dev = host->dma_chan->device;
236
237 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
238 DMA_COMPL_SKIP_DEST_UNMAP;
239
240 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
241 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
242 dev_err(host->dev, "Failed to dma_map_single\n");
243 goto err_buf;
244 }
245
246 if (is_read) {
247 dma_src_addr = host->io_phys;
248 dma_dst_addr = phys_addr;
249 } else {
250 dma_src_addr = phys_addr;
251 dma_dst_addr = host->io_phys;
252 }
253
254 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
255 dma_src_addr, len, flags);
256 if (!tx) {
257 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
258 goto err_dma;
259 }
260
261 init_completion(&host->comp);
262 tx->callback = dma_complete_func;
263 tx->callback_param = &host->comp;
264
265 cookie = tx->tx_submit(tx);
266 if (dma_submit_error(cookie)) {
267 dev_err(host->dev, "Failed to do DMA tx_submit\n");
268 goto err_dma;
269 }
270
271 dma_async_issue_pending(host->dma_chan);
272 wait_for_completion(&host->comp);
273
274 err = 0;
275
276 err_dma:
277 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
278 err_buf:
279 if (err != 0)
280 dev_warn(host->dev, "Fall back to CPU I/O\n");
281 return err;
282 }
283
284 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
285 {
286 struct nand_chip *chip = mtd->priv;
287 struct atmel_nand_host *host = chip->priv;
288
289 if (use_dma && len > mtd->oobsize)
290 /* only use DMA for bigger than oob size: better performances */
291 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
292 return;
293
294 if (host->board.bus_width_16)
295 atmel_read_buf16(mtd, buf, len);
296 else
297 atmel_read_buf8(mtd, buf, len);
298 }
299
300 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
301 {
302 struct nand_chip *chip = mtd->priv;
303 struct atmel_nand_host *host = chip->priv;
304
305 if (use_dma && len > mtd->oobsize)
306 /* only use DMA for bigger than oob size: better performances */
307 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
308 return;
309
310 if (host->board.bus_width_16)
311 atmel_write_buf16(mtd, buf, len);
312 else
313 atmel_write_buf8(mtd, buf, len);
314 }
315
316 /*
317 * Return number of ecc bytes per sector according to sector size and
318 * correction capability
319 *
320 * Following table shows what at91 PMECC supported:
321 * Correction Capability Sector_512_bytes Sector_1024_bytes
322 * ===================== ================ =================
323 * 2-bits 4-bytes 4-bytes
324 * 4-bits 7-bytes 7-bytes
325 * 8-bits 13-bytes 14-bytes
326 * 12-bits 20-bytes 21-bytes
327 * 24-bits 39-bytes 42-bytes
328 */
329 static int pmecc_get_ecc_bytes(int cap, int sector_size)
330 {
331 int m = 12 + sector_size / 512;
332 return (m * cap + 7) / 8;
333 }
334
335 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
336 int oobsize, int ecc_len)
337 {
338 int i;
339
340 layout->eccbytes = ecc_len;
341
342 /* ECC will occupy the last ecc_len bytes continuously */
343 for (i = 0; i < ecc_len; i++)
344 layout->eccpos[i] = oobsize - ecc_len + i;
345
346 layout->oobfree[0].offset = 2;
347 layout->oobfree[0].length =
348 oobsize - ecc_len - layout->oobfree[0].offset;
349 }
350
351 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
352 {
353 int table_size;
354
355 table_size = host->pmecc_sector_size == 512 ?
356 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
357
358 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
359 table_size * sizeof(int16_t);
360 }
361
362 static void pmecc_data_free(struct atmel_nand_host *host)
363 {
364 kfree(host->pmecc_partial_syn);
365 kfree(host->pmecc_si);
366 kfree(host->pmecc_lmu);
367 kfree(host->pmecc_smu);
368 kfree(host->pmecc_mu);
369 kfree(host->pmecc_dmu);
370 kfree(host->pmecc_delta);
371 }
372
373 static int pmecc_data_alloc(struct atmel_nand_host *host)
374 {
375 const int cap = host->pmecc_corr_cap;
376
377 host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t),
378 GFP_KERNEL);
379 host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL);
380 host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL);
381 host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t),
382 GFP_KERNEL);
383 host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
384 host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
385 host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
386
387 if (host->pmecc_partial_syn &&
388 host->pmecc_si &&
389 host->pmecc_lmu &&
390 host->pmecc_smu &&
391 host->pmecc_mu &&
392 host->pmecc_dmu &&
393 host->pmecc_delta)
394 return 0;
395
396 /* error happened */
397 pmecc_data_free(host);
398 return -ENOMEM;
399 }
400
401 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
402 {
403 struct nand_chip *nand_chip = mtd->priv;
404 struct atmel_nand_host *host = nand_chip->priv;
405 int i;
406 uint32_t value;
407
408 /* Fill odd syndromes */
409 for (i = 0; i < host->pmecc_corr_cap; i++) {
410 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
411 if (i & 1)
412 value >>= 16;
413 value &= 0xffff;
414 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
415 }
416 }
417
418 static void pmecc_substitute(struct mtd_info *mtd)
419 {
420 struct nand_chip *nand_chip = mtd->priv;
421 struct atmel_nand_host *host = nand_chip->priv;
422 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
423 int16_t __iomem *index_of = host->pmecc_index_of;
424 int16_t *partial_syn = host->pmecc_partial_syn;
425 const int cap = host->pmecc_corr_cap;
426 int16_t *si;
427 int i, j;
428
429 /* si[] is a table that holds the current syndrome value,
430 * an element of that table belongs to the field
431 */
432 si = host->pmecc_si;
433
434 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
435
436 /* Computation 2t syndromes based on S(x) */
437 /* Odd syndromes */
438 for (i = 1; i < 2 * cap; i += 2) {
439 for (j = 0; j < host->pmecc_degree; j++) {
440 if (partial_syn[i] & ((unsigned short)0x1 << j))
441 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
442 }
443 }
444 /* Even syndrome = (Odd syndrome) ** 2 */
445 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
446 if (si[j] == 0) {
447 si[i] = 0;
448 } else {
449 int16_t tmp;
450
451 tmp = readw_relaxed(index_of + si[j]);
452 tmp = (tmp * 2) % host->pmecc_cw_len;
453 si[i] = readw_relaxed(alpha_to + tmp);
454 }
455 }
456
457 return;
458 }
459
460 static void pmecc_get_sigma(struct mtd_info *mtd)
461 {
462 struct nand_chip *nand_chip = mtd->priv;
463 struct atmel_nand_host *host = nand_chip->priv;
464
465 int16_t *lmu = host->pmecc_lmu;
466 int16_t *si = host->pmecc_si;
467 int *mu = host->pmecc_mu;
468 int *dmu = host->pmecc_dmu; /* Discrepancy */
469 int *delta = host->pmecc_delta; /* Delta order */
470 int cw_len = host->pmecc_cw_len;
471 const int16_t cap = host->pmecc_corr_cap;
472 const int num = 2 * cap + 1;
473 int16_t __iomem *index_of = host->pmecc_index_of;
474 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
475 int i, j, k;
476 uint32_t dmu_0_count, tmp;
477 int16_t *smu = host->pmecc_smu;
478
479 /* index of largest delta */
480 int ro;
481 int largest;
482 int diff;
483
484 dmu_0_count = 0;
485
486 /* First Row */
487
488 /* Mu */
489 mu[0] = -1;
490
491 memset(smu, 0, sizeof(int16_t) * num);
492 smu[0] = 1;
493
494 /* discrepancy set to 1 */
495 dmu[0] = 1;
496 /* polynom order set to 0 */
497 lmu[0] = 0;
498 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
499
500 /* Second Row */
501
502 /* Mu */
503 mu[1] = 0;
504 /* Sigma(x) set to 1 */
505 memset(&smu[num], 0, sizeof(int16_t) * num);
506 smu[num] = 1;
507
508 /* discrepancy set to S1 */
509 dmu[1] = si[1];
510
511 /* polynom order set to 0 */
512 lmu[1] = 0;
513
514 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
515
516 /* Init the Sigma(x) last row */
517 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
518
519 for (i = 1; i <= cap; i++) {
520 mu[i + 1] = i << 1;
521 /* Begin Computing Sigma (Mu+1) and L(mu) */
522 /* check if discrepancy is set to 0 */
523 if (dmu[i] == 0) {
524 dmu_0_count++;
525
526 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
527 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
528 tmp += 2;
529 else
530 tmp += 1;
531
532 if (dmu_0_count == tmp) {
533 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
534 smu[(cap + 1) * num + j] =
535 smu[i * num + j];
536
537 lmu[cap + 1] = lmu[i];
538 return;
539 }
540
541 /* copy polynom */
542 for (j = 0; j <= lmu[i] >> 1; j++)
543 smu[(i + 1) * num + j] = smu[i * num + j];
544
545 /* copy previous polynom order to the next */
546 lmu[i + 1] = lmu[i];
547 } else {
548 ro = 0;
549 largest = -1;
550 /* find largest delta with dmu != 0 */
551 for (j = 0; j < i; j++) {
552 if ((dmu[j]) && (delta[j] > largest)) {
553 largest = delta[j];
554 ro = j;
555 }
556 }
557
558 /* compute difference */
559 diff = (mu[i] - mu[ro]);
560
561 /* Compute degree of the new smu polynomial */
562 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
563 lmu[i + 1] = lmu[i];
564 else
565 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
566
567 /* Init smu[i+1] with 0 */
568 for (k = 0; k < num; k++)
569 smu[(i + 1) * num + k] = 0;
570
571 /* Compute smu[i+1] */
572 for (k = 0; k <= lmu[ro] >> 1; k++) {
573 int16_t a, b, c;
574
575 if (!(smu[ro * num + k] && dmu[i]))
576 continue;
577 a = readw_relaxed(index_of + dmu[i]);
578 b = readw_relaxed(index_of + dmu[ro]);
579 c = readw_relaxed(index_of + smu[ro * num + k]);
580 tmp = a + (cw_len - b) + c;
581 a = readw_relaxed(alpha_to + tmp % cw_len);
582 smu[(i + 1) * num + (k + diff)] = a;
583 }
584
585 for (k = 0; k <= lmu[i] >> 1; k++)
586 smu[(i + 1) * num + k] ^= smu[i * num + k];
587 }
588
589 /* End Computing Sigma (Mu+1) and L(mu) */
590 /* In either case compute delta */
591 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
592
593 /* Do not compute discrepancy for the last iteration */
594 if (i >= cap)
595 continue;
596
597 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
598 tmp = 2 * (i - 1);
599 if (k == 0) {
600 dmu[i + 1] = si[tmp + 3];
601 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
602 int16_t a, b, c;
603 a = readw_relaxed(index_of +
604 smu[(i + 1) * num + k]);
605 b = si[2 * (i - 1) + 3 - k];
606 c = readw_relaxed(index_of + b);
607 tmp = a + c;
608 tmp %= cw_len;
609 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
610 dmu[i + 1];
611 }
612 }
613 }
614
615 return;
616 }
617
618 static int pmecc_err_location(struct mtd_info *mtd)
619 {
620 struct nand_chip *nand_chip = mtd->priv;
621 struct atmel_nand_host *host = nand_chip->priv;
622 unsigned long end_time;
623 const int cap = host->pmecc_corr_cap;
624 const int num = 2 * cap + 1;
625 int sector_size = host->pmecc_sector_size;
626 int err_nbr = 0; /* number of error */
627 int roots_nbr; /* number of roots */
628 int i;
629 uint32_t val;
630 int16_t *smu = host->pmecc_smu;
631
632 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
633
634 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
635 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
636 smu[(cap + 1) * num + i]);
637 err_nbr++;
638 }
639
640 val = (err_nbr - 1) << 16;
641 if (sector_size == 1024)
642 val |= 1;
643
644 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
645 pmerrloc_writel(host->pmerrloc_base, ELEN,
646 sector_size * 8 + host->pmecc_degree * cap);
647
648 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
649 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
650 & PMERRLOC_CALC_DONE)) {
651 if (unlikely(time_after(jiffies, end_time))) {
652 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
653 return -1;
654 }
655 cpu_relax();
656 }
657
658 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
659 & PMERRLOC_ERR_NUM_MASK) >> 8;
660 /* Number of roots == degree of smu hence <= cap */
661 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
662 return err_nbr - 1;
663
664 /* Number of roots does not match the degree of smu
665 * unable to correct error */
666 return -1;
667 }
668
669 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
670 int sector_num, int extra_bytes, int err_nbr)
671 {
672 struct nand_chip *nand_chip = mtd->priv;
673 struct atmel_nand_host *host = nand_chip->priv;
674 int i = 0;
675 int byte_pos, bit_pos, sector_size, pos;
676 uint32_t tmp;
677 uint8_t err_byte;
678
679 sector_size = host->pmecc_sector_size;
680
681 while (err_nbr) {
682 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
683 byte_pos = tmp / 8;
684 bit_pos = tmp % 8;
685
686 if (byte_pos >= (sector_size + extra_bytes))
687 BUG(); /* should never happen */
688
689 if (byte_pos < sector_size) {
690 err_byte = *(buf + byte_pos);
691 *(buf + byte_pos) ^= (1 << bit_pos);
692
693 pos = sector_num * host->pmecc_sector_size + byte_pos;
694 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
695 pos, bit_pos, err_byte, *(buf + byte_pos));
696 } else {
697 /* Bit flip in OOB area */
698 tmp = sector_num * host->pmecc_bytes_per_sector
699 + (byte_pos - sector_size);
700 err_byte = ecc[tmp];
701 ecc[tmp] ^= (1 << bit_pos);
702
703 pos = tmp + nand_chip->ecc.layout->eccpos[0];
704 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
705 pos, bit_pos, err_byte, ecc[tmp]);
706 }
707
708 i++;
709 err_nbr--;
710 }
711
712 return;
713 }
714
715 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
716 u8 *ecc)
717 {
718 struct nand_chip *nand_chip = mtd->priv;
719 struct atmel_nand_host *host = nand_chip->priv;
720 int i, err_nbr, eccbytes;
721 uint8_t *buf_pos;
722 int total_err = 0;
723
724 eccbytes = nand_chip->ecc.bytes;
725 for (i = 0; i < eccbytes; i++)
726 if (ecc[i] != 0xff)
727 goto normal_check;
728 /* Erased page, return OK */
729 return 0;
730
731 normal_check:
732 for (i = 0; i < host->pmecc_sector_number; i++) {
733 err_nbr = 0;
734 if (pmecc_stat & 0x1) {
735 buf_pos = buf + i * host->pmecc_sector_size;
736
737 pmecc_gen_syndrome(mtd, i);
738 pmecc_substitute(mtd);
739 pmecc_get_sigma(mtd);
740
741 err_nbr = pmecc_err_location(mtd);
742 if (err_nbr == -1) {
743 dev_err(host->dev, "PMECC: Too many errors\n");
744 mtd->ecc_stats.failed++;
745 return -EIO;
746 } else {
747 pmecc_correct_data(mtd, buf_pos, ecc, i,
748 host->pmecc_bytes_per_sector, err_nbr);
749 mtd->ecc_stats.corrected += err_nbr;
750 total_err += err_nbr;
751 }
752 }
753 pmecc_stat >>= 1;
754 }
755
756 return total_err;
757 }
758
759 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
760 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
761 {
762 struct atmel_nand_host *host = chip->priv;
763 int eccsize = chip->ecc.size;
764 uint8_t *oob = chip->oob_poi;
765 uint32_t *eccpos = chip->ecc.layout->eccpos;
766 uint32_t stat;
767 unsigned long end_time;
768 int bitflips = 0;
769
770 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
771 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
772 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
773 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
774
775 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
776 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
777
778 chip->read_buf(mtd, buf, eccsize);
779 chip->read_buf(mtd, oob, mtd->oobsize);
780
781 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
782 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
783 if (unlikely(time_after(jiffies, end_time))) {
784 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
785 return -EIO;
786 }
787 cpu_relax();
788 }
789
790 stat = pmecc_readl_relaxed(host->ecc, ISR);
791 if (stat != 0) {
792 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
793 if (bitflips < 0)
794 /* uncorrectable errors */
795 return 0;
796 }
797
798 return bitflips;
799 }
800
801 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
802 struct nand_chip *chip, const uint8_t *buf, int oob_required)
803 {
804 struct atmel_nand_host *host = chip->priv;
805 uint32_t *eccpos = chip->ecc.layout->eccpos;
806 int i, j;
807 unsigned long end_time;
808
809 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
810 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
811
812 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
813 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
814
815 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
816 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
817
818 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
819
820 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
821 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
822 if (unlikely(time_after(jiffies, end_time))) {
823 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
824 return -EIO;
825 }
826 cpu_relax();
827 }
828
829 for (i = 0; i < host->pmecc_sector_number; i++) {
830 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
831 int pos;
832
833 pos = i * host->pmecc_bytes_per_sector + j;
834 chip->oob_poi[eccpos[pos]] =
835 pmecc_readb_ecc_relaxed(host->ecc, i, j);
836 }
837 }
838 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
839
840 return 0;
841 }
842
843 static void atmel_pmecc_core_init(struct mtd_info *mtd)
844 {
845 struct nand_chip *nand_chip = mtd->priv;
846 struct atmel_nand_host *host = nand_chip->priv;
847 uint32_t val = 0;
848 struct nand_ecclayout *ecc_layout;
849
850 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
851 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
852
853 switch (host->pmecc_corr_cap) {
854 case 2:
855 val = PMECC_CFG_BCH_ERR2;
856 break;
857 case 4:
858 val = PMECC_CFG_BCH_ERR4;
859 break;
860 case 8:
861 val = PMECC_CFG_BCH_ERR8;
862 break;
863 case 12:
864 val = PMECC_CFG_BCH_ERR12;
865 break;
866 case 24:
867 val = PMECC_CFG_BCH_ERR24;
868 break;
869 }
870
871 if (host->pmecc_sector_size == 512)
872 val |= PMECC_CFG_SECTOR512;
873 else if (host->pmecc_sector_size == 1024)
874 val |= PMECC_CFG_SECTOR1024;
875
876 switch (host->pmecc_sector_number) {
877 case 1:
878 val |= PMECC_CFG_PAGE_1SECTOR;
879 break;
880 case 2:
881 val |= PMECC_CFG_PAGE_2SECTORS;
882 break;
883 case 4:
884 val |= PMECC_CFG_PAGE_4SECTORS;
885 break;
886 case 8:
887 val |= PMECC_CFG_PAGE_8SECTORS;
888 break;
889 }
890
891 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
892 | PMECC_CFG_AUTO_DISABLE);
893 pmecc_writel(host->ecc, CFG, val);
894
895 ecc_layout = nand_chip->ecc.layout;
896 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
897 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
898 pmecc_writel(host->ecc, EADDR,
899 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
900 /* See datasheet about PMECC Clock Control Register */
901 pmecc_writel(host->ecc, CLK, 2);
902 pmecc_writel(host->ecc, IDR, 0xff);
903 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
904 }
905
906 /*
907 * Get ECC requirement in ONFI parameters, returns -1 if ONFI
908 * parameters is not supported.
909 * return 0 if success to get the ECC requirement.
910 */
911 static int get_onfi_ecc_param(struct nand_chip *chip,
912 int *ecc_bits, int *sector_size)
913 {
914 *ecc_bits = *sector_size = 0;
915
916 if (chip->onfi_params.ecc_bits == 0xff)
917 /* TODO: the sector_size and ecc_bits need to be find in
918 * extended ecc parameter, currently we don't support it.
919 */
920 return -1;
921
922 *ecc_bits = chip->onfi_params.ecc_bits;
923
924 /* The default sector size (ecc codeword size) is 512 */
925 *sector_size = 512;
926
927 return 0;
928 }
929
930 /*
931 * Get ecc requirement from ONFI parameters ecc requirement.
932 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
933 * will set them according to ONFI ecc requirement. Otherwise, use the
934 * value in DTS file.
935 * return 0 if success. otherwise return error code.
936 */
937 static int pmecc_choose_ecc(struct atmel_nand_host *host,
938 int *cap, int *sector_size)
939 {
940 /* Get ECC requirement from ONFI parameters */
941 *cap = *sector_size = 0;
942 if (host->nand_chip.onfi_version) {
943 if (!get_onfi_ecc_param(&host->nand_chip, cap, sector_size))
944 dev_info(host->dev, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
945 *cap, *sector_size);
946 else
947 dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
948 } else {
949 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
950 }
951 if (*cap == 0 && *sector_size == 0) {
952 *cap = 2;
953 *sector_size = 512;
954 }
955
956 /* If dts file doesn't specify then use the one in ONFI parameters */
957 if (host->pmecc_corr_cap == 0) {
958 /* use the most fitable ecc bits (the near bigger one ) */
959 if (*cap <= 2)
960 host->pmecc_corr_cap = 2;
961 else if (*cap <= 4)
962 host->pmecc_corr_cap = 4;
963 else if (*cap < 8)
964 host->pmecc_corr_cap = 8;
965 else if (*cap < 12)
966 host->pmecc_corr_cap = 12;
967 else if (*cap < 24)
968 host->pmecc_corr_cap = 24;
969 else
970 return -EINVAL;
971 }
972 if (host->pmecc_sector_size == 0) {
973 /* use the most fitable sector size (the near smaller one ) */
974 if (*sector_size >= 1024)
975 host->pmecc_sector_size = 1024;
976 else if (*sector_size >= 512)
977 host->pmecc_sector_size = 512;
978 else
979 return -EINVAL;
980 }
981 return 0;
982 }
983
984 static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
985 struct atmel_nand_host *host)
986 {
987 struct mtd_info *mtd = &host->mtd;
988 struct nand_chip *nand_chip = &host->nand_chip;
989 struct resource *regs, *regs_pmerr, *regs_rom;
990 int cap, sector_size, err_no;
991
992 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
993 if (err_no) {
994 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
995 return err_no;
996 }
997
998 if (cap != host->pmecc_corr_cap ||
999 sector_size != host->pmecc_sector_size)
1000 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1001
1002 cap = host->pmecc_corr_cap;
1003 sector_size = host->pmecc_sector_size;
1004 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1005 host->pmecc_lookup_table_offset_512 :
1006 host->pmecc_lookup_table_offset_1024;
1007
1008 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1009 cap, sector_size);
1010
1011 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1012 if (!regs) {
1013 dev_warn(host->dev,
1014 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1015 nand_chip->ecc.mode = NAND_ECC_SOFT;
1016 return 0;
1017 }
1018
1019 host->ecc = ioremap(regs->start, resource_size(regs));
1020 if (host->ecc == NULL) {
1021 dev_err(host->dev, "ioremap failed\n");
1022 err_no = -EIO;
1023 goto err_pmecc_ioremap;
1024 }
1025
1026 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1027 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1028 if (regs_pmerr && regs_rom) {
1029 host->pmerrloc_base = ioremap(regs_pmerr->start,
1030 resource_size(regs_pmerr));
1031 host->pmecc_rom_base = ioremap(regs_rom->start,
1032 resource_size(regs_rom));
1033 }
1034
1035 if (!host->pmerrloc_base || !host->pmecc_rom_base) {
1036 dev_err(host->dev,
1037 "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
1038 err_no = -EIO;
1039 goto err_pmloc_ioremap;
1040 }
1041
1042 /* ECC is calculated for the whole page (1 step) */
1043 nand_chip->ecc.size = mtd->writesize;
1044
1045 /* set ECC page size and oob layout */
1046 switch (mtd->writesize) {
1047 case 2048:
1048 host->pmecc_degree = PMECC_GF_DIMENSION_13;
1049 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1050 host->pmecc_sector_number = mtd->writesize / sector_size;
1051 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1052 cap, sector_size);
1053 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1054 host->pmecc_index_of = host->pmecc_rom_base +
1055 host->pmecc_lookup_table_offset;
1056
1057 nand_chip->ecc.steps = 1;
1058 nand_chip->ecc.strength = cap;
1059 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
1060 host->pmecc_sector_number;
1061 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
1062 dev_err(host->dev, "No room for ECC bytes\n");
1063 err_no = -EINVAL;
1064 goto err_no_ecc_room;
1065 }
1066 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1067 mtd->oobsize,
1068 nand_chip->ecc.bytes);
1069 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1070 break;
1071 case 512:
1072 case 1024:
1073 case 4096:
1074 /* TODO */
1075 dev_warn(host->dev,
1076 "Unsupported page size for PMECC, use Software ECC\n");
1077 default:
1078 /* page size not handled by HW ECC */
1079 /* switching back to soft ECC */
1080 nand_chip->ecc.mode = NAND_ECC_SOFT;
1081 return 0;
1082 }
1083
1084 /* Allocate data for PMECC computation */
1085 err_no = pmecc_data_alloc(host);
1086 if (err_no) {
1087 dev_err(host->dev,
1088 "Cannot allocate memory for PMECC computation!\n");
1089 goto err_pmecc_data_alloc;
1090 }
1091
1092 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1093 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1094
1095 atmel_pmecc_core_init(mtd);
1096
1097 return 0;
1098
1099 err_pmecc_data_alloc:
1100 err_no_ecc_room:
1101 err_pmloc_ioremap:
1102 iounmap(host->ecc);
1103 if (host->pmerrloc_base)
1104 iounmap(host->pmerrloc_base);
1105 if (host->pmecc_rom_base)
1106 iounmap(host->pmecc_rom_base);
1107 err_pmecc_ioremap:
1108 return err_no;
1109 }
1110
1111 /*
1112 * Calculate HW ECC
1113 *
1114 * function called after a write
1115 *
1116 * mtd: MTD block structure
1117 * dat: raw data (unused)
1118 * ecc_code: buffer for ECC
1119 */
1120 static int atmel_nand_calculate(struct mtd_info *mtd,
1121 const u_char *dat, unsigned char *ecc_code)
1122 {
1123 struct nand_chip *nand_chip = mtd->priv;
1124 struct atmel_nand_host *host = nand_chip->priv;
1125 unsigned int ecc_value;
1126
1127 /* get the first 2 ECC bytes */
1128 ecc_value = ecc_readl(host->ecc, PR);
1129
1130 ecc_code[0] = ecc_value & 0xFF;
1131 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1132
1133 /* get the last 2 ECC bytes */
1134 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1135
1136 ecc_code[2] = ecc_value & 0xFF;
1137 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1138
1139 return 0;
1140 }
1141
1142 /*
1143 * HW ECC read page function
1144 *
1145 * mtd: mtd info structure
1146 * chip: nand chip info structure
1147 * buf: buffer to store read data
1148 * oob_required: caller expects OOB data read to chip->oob_poi
1149 */
1150 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1151 uint8_t *buf, int oob_required, int page)
1152 {
1153 int eccsize = chip->ecc.size;
1154 int eccbytes = chip->ecc.bytes;
1155 uint32_t *eccpos = chip->ecc.layout->eccpos;
1156 uint8_t *p = buf;
1157 uint8_t *oob = chip->oob_poi;
1158 uint8_t *ecc_pos;
1159 int stat;
1160 unsigned int max_bitflips = 0;
1161
1162 /*
1163 * Errata: ALE is incorrectly wired up to the ECC controller
1164 * on the AP7000, so it will include the address cycles in the
1165 * ECC calculation.
1166 *
1167 * Workaround: Reset the parity registers before reading the
1168 * actual data.
1169 */
1170 struct atmel_nand_host *host = chip->priv;
1171 if (host->board.need_reset_workaround)
1172 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1173
1174 /* read the page */
1175 chip->read_buf(mtd, p, eccsize);
1176
1177 /* move to ECC position if needed */
1178 if (eccpos[0] != 0) {
1179 /* This only works on large pages
1180 * because the ECC controller waits for
1181 * NAND_CMD_RNDOUTSTART after the
1182 * NAND_CMD_RNDOUT.
1183 * anyway, for small pages, the eccpos[0] == 0
1184 */
1185 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1186 mtd->writesize + eccpos[0], -1);
1187 }
1188
1189 /* the ECC controller needs to read the ECC just after the data */
1190 ecc_pos = oob + eccpos[0];
1191 chip->read_buf(mtd, ecc_pos, eccbytes);
1192
1193 /* check if there's an error */
1194 stat = chip->ecc.correct(mtd, p, oob, NULL);
1195
1196 if (stat < 0) {
1197 mtd->ecc_stats.failed++;
1198 } else {
1199 mtd->ecc_stats.corrected += stat;
1200 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1201 }
1202
1203 /* get back to oob start (end of page) */
1204 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1205
1206 /* read the oob */
1207 chip->read_buf(mtd, oob, mtd->oobsize);
1208
1209 return max_bitflips;
1210 }
1211
1212 /*
1213 * HW ECC Correction
1214 *
1215 * function called after a read
1216 *
1217 * mtd: MTD block structure
1218 * dat: raw data read from the chip
1219 * read_ecc: ECC from the chip (unused)
1220 * isnull: unused
1221 *
1222 * Detect and correct a 1 bit error for a page
1223 */
1224 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1225 u_char *read_ecc, u_char *isnull)
1226 {
1227 struct nand_chip *nand_chip = mtd->priv;
1228 struct atmel_nand_host *host = nand_chip->priv;
1229 unsigned int ecc_status;
1230 unsigned int ecc_word, ecc_bit;
1231
1232 /* get the status from the Status Register */
1233 ecc_status = ecc_readl(host->ecc, SR);
1234
1235 /* if there's no error */
1236 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1237 return 0;
1238
1239 /* get error bit offset (4 bits) */
1240 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1241 /* get word address (12 bits) */
1242 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1243 ecc_word >>= 4;
1244
1245 /* if there are multiple errors */
1246 if (ecc_status & ATMEL_ECC_MULERR) {
1247 /* check if it is a freshly erased block
1248 * (filled with 0xff) */
1249 if ((ecc_bit == ATMEL_ECC_BITADDR)
1250 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1251 /* the block has just been erased, return OK */
1252 return 0;
1253 }
1254 /* it doesn't seems to be a freshly
1255 * erased block.
1256 * We can't correct so many errors */
1257 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1258 " Unable to correct.\n");
1259 return -EIO;
1260 }
1261
1262 /* if there's a single bit error : we can correct it */
1263 if (ecc_status & ATMEL_ECC_ECCERR) {
1264 /* there's nothing much to do here.
1265 * the bit error is on the ECC itself.
1266 */
1267 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1268 " Nothing to correct\n");
1269 return 0;
1270 }
1271
1272 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1273 " (word offset in the page :"
1274 " 0x%x bit offset : 0x%x)\n",
1275 ecc_word, ecc_bit);
1276 /* correct the error */
1277 if (nand_chip->options & NAND_BUSWIDTH_16) {
1278 /* 16 bits words */
1279 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1280 } else {
1281 /* 8 bits words */
1282 dat[ecc_word] ^= (1 << ecc_bit);
1283 }
1284 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1285 return 1;
1286 }
1287
1288 /*
1289 * Enable HW ECC : unused on most chips
1290 */
1291 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1292 {
1293 struct nand_chip *nand_chip = mtd->priv;
1294 struct atmel_nand_host *host = nand_chip->priv;
1295
1296 if (host->board.need_reset_workaround)
1297 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1298 }
1299
1300 #if defined(CONFIG_OF)
1301 static int atmel_of_init_port(struct atmel_nand_host *host,
1302 struct device_node *np)
1303 {
1304 u32 val;
1305 u32 offset[2];
1306 int ecc_mode;
1307 struct atmel_nand_data *board = &host->board;
1308 enum of_gpio_flags flags;
1309
1310 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1311 if (val >= 32) {
1312 dev_err(host->dev, "invalid addr-offset %u\n", val);
1313 return -EINVAL;
1314 }
1315 board->ale = val;
1316 }
1317
1318 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1319 if (val >= 32) {
1320 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1321 return -EINVAL;
1322 }
1323 board->cle = val;
1324 }
1325
1326 ecc_mode = of_get_nand_ecc_mode(np);
1327
1328 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1329
1330 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1331
1332 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1333
1334 if (of_get_nand_bus_width(np) == 16)
1335 board->bus_width_16 = 1;
1336
1337 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1338 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1339
1340 board->enable_pin = of_get_gpio(np, 1);
1341 board->det_pin = of_get_gpio(np, 2);
1342
1343 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1344
1345 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1346 return 0; /* Not using PMECC */
1347
1348 /* use PMECC, get correction capability, sector size and lookup
1349 * table offset.
1350 * If correction bits and sector size are not specified, then find
1351 * them from NAND ONFI parameters.
1352 */
1353 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1354 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1355 (val != 24)) {
1356 dev_err(host->dev,
1357 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1358 val);
1359 return -EINVAL;
1360 }
1361 host->pmecc_corr_cap = (u8)val;
1362 }
1363
1364 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1365 if ((val != 512) && (val != 1024)) {
1366 dev_err(host->dev,
1367 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1368 val);
1369 return -EINVAL;
1370 }
1371 host->pmecc_sector_size = (u16)val;
1372 }
1373
1374 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1375 offset, 2) != 0) {
1376 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1377 return -EINVAL;
1378 }
1379 if (!offset[0] && !offset[1]) {
1380 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1381 return -EINVAL;
1382 }
1383 host->pmecc_lookup_table_offset_512 = offset[0];
1384 host->pmecc_lookup_table_offset_1024 = offset[1];
1385
1386 return 0;
1387 }
1388 #else
1389 static int atmel_of_init_port(struct atmel_nand_host *host,
1390 struct device_node *np)
1391 {
1392 return -EINVAL;
1393 }
1394 #endif
1395
1396 static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
1397 struct atmel_nand_host *host)
1398 {
1399 struct mtd_info *mtd = &host->mtd;
1400 struct nand_chip *nand_chip = &host->nand_chip;
1401 struct resource *regs;
1402
1403 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1404 if (!regs) {
1405 dev_err(host->dev,
1406 "Can't get I/O resource regs, use software ECC\n");
1407 nand_chip->ecc.mode = NAND_ECC_SOFT;
1408 return 0;
1409 }
1410
1411 host->ecc = ioremap(regs->start, resource_size(regs));
1412 if (host->ecc == NULL) {
1413 dev_err(host->dev, "ioremap failed\n");
1414 return -EIO;
1415 }
1416
1417 /* ECC is calculated for the whole page (1 step) */
1418 nand_chip->ecc.size = mtd->writesize;
1419
1420 /* set ECC page size and oob layout */
1421 switch (mtd->writesize) {
1422 case 512:
1423 nand_chip->ecc.layout = &atmel_oobinfo_small;
1424 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1425 break;
1426 case 1024:
1427 nand_chip->ecc.layout = &atmel_oobinfo_large;
1428 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1429 break;
1430 case 2048:
1431 nand_chip->ecc.layout = &atmel_oobinfo_large;
1432 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1433 break;
1434 case 4096:
1435 nand_chip->ecc.layout = &atmel_oobinfo_large;
1436 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1437 break;
1438 default:
1439 /* page size not handled by HW ECC */
1440 /* switching back to soft ECC */
1441 nand_chip->ecc.mode = NAND_ECC_SOFT;
1442 return 0;
1443 }
1444
1445 /* set up for HW ECC */
1446 nand_chip->ecc.calculate = atmel_nand_calculate;
1447 nand_chip->ecc.correct = atmel_nand_correct;
1448 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1449 nand_chip->ecc.read_page = atmel_nand_read_page;
1450 nand_chip->ecc.bytes = 4;
1451 nand_chip->ecc.strength = 1;
1452
1453 return 0;
1454 }
1455
1456 /*
1457 * Probe for the NAND device.
1458 */
1459 static int __init atmel_nand_probe(struct platform_device *pdev)
1460 {
1461 struct atmel_nand_host *host;
1462 struct mtd_info *mtd;
1463 struct nand_chip *nand_chip;
1464 struct resource *mem;
1465 struct mtd_part_parser_data ppdata = {};
1466 int res;
1467 struct pinctrl *pinctrl;
1468
1469 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1470 if (!mem) {
1471 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
1472 return -ENXIO;
1473 }
1474
1475 /* Allocate memory for the device structure (and zero it) */
1476 host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
1477 if (!host) {
1478 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
1479 return -ENOMEM;
1480 }
1481
1482 host->io_phys = (dma_addr_t)mem->start;
1483
1484 host->io_base = ioremap(mem->start, resource_size(mem));
1485 if (host->io_base == NULL) {
1486 printk(KERN_ERR "atmel_nand: ioremap failed\n");
1487 res = -EIO;
1488 goto err_nand_ioremap;
1489 }
1490
1491 mtd = &host->mtd;
1492 nand_chip = &host->nand_chip;
1493 host->dev = &pdev->dev;
1494 if (pdev->dev.of_node) {
1495 res = atmel_of_init_port(host, pdev->dev.of_node);
1496 if (res)
1497 goto err_ecc_ioremap;
1498 } else {
1499 memcpy(&host->board, pdev->dev.platform_data,
1500 sizeof(struct atmel_nand_data));
1501 }
1502
1503 nand_chip->priv = host; /* link the private data structures */
1504 mtd->priv = nand_chip;
1505 mtd->owner = THIS_MODULE;
1506
1507 /* Set address of NAND IO lines */
1508 nand_chip->IO_ADDR_R = host->io_base;
1509 nand_chip->IO_ADDR_W = host->io_base;
1510 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1511
1512 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1513 if (IS_ERR(pinctrl)) {
1514 dev_err(host->dev, "Failed to request pinctrl\n");
1515 res = PTR_ERR(pinctrl);
1516 goto err_ecc_ioremap;
1517 }
1518
1519 if (gpio_is_valid(host->board.rdy_pin)) {
1520 res = gpio_request(host->board.rdy_pin, "nand_rdy");
1521 if (res < 0) {
1522 dev_err(&pdev->dev,
1523 "can't request rdy gpio %d\n",
1524 host->board.rdy_pin);
1525 goto err_ecc_ioremap;
1526 }
1527
1528 res = gpio_direction_input(host->board.rdy_pin);
1529 if (res < 0) {
1530 dev_err(&pdev->dev,
1531 "can't request input direction rdy gpio %d\n",
1532 host->board.rdy_pin);
1533 goto err_ecc_ioremap;
1534 }
1535
1536 nand_chip->dev_ready = atmel_nand_device_ready;
1537 }
1538
1539 if (gpio_is_valid(host->board.enable_pin)) {
1540 res = gpio_request(host->board.enable_pin, "nand_enable");
1541 if (res < 0) {
1542 dev_err(&pdev->dev,
1543 "can't request enable gpio %d\n",
1544 host->board.enable_pin);
1545 goto err_ecc_ioremap;
1546 }
1547
1548 res = gpio_direction_output(host->board.enable_pin, 1);
1549 if (res < 0) {
1550 dev_err(&pdev->dev,
1551 "can't request output direction enable gpio %d\n",
1552 host->board.enable_pin);
1553 goto err_ecc_ioremap;
1554 }
1555 }
1556
1557 nand_chip->ecc.mode = host->board.ecc_mode;
1558 nand_chip->chip_delay = 20; /* 20us command delay time */
1559
1560 if (host->board.bus_width_16) /* 16-bit bus width */
1561 nand_chip->options |= NAND_BUSWIDTH_16;
1562
1563 nand_chip->read_buf = atmel_read_buf;
1564 nand_chip->write_buf = atmel_write_buf;
1565
1566 platform_set_drvdata(pdev, host);
1567 atmel_nand_enable(host);
1568
1569 if (gpio_is_valid(host->board.det_pin)) {
1570 res = gpio_request(host->board.det_pin, "nand_det");
1571 if (res < 0) {
1572 dev_err(&pdev->dev,
1573 "can't request det gpio %d\n",
1574 host->board.det_pin);
1575 goto err_no_card;
1576 }
1577
1578 res = gpio_direction_input(host->board.det_pin);
1579 if (res < 0) {
1580 dev_err(&pdev->dev,
1581 "can't request input direction det gpio %d\n",
1582 host->board.det_pin);
1583 goto err_no_card;
1584 }
1585
1586 if (gpio_get_value(host->board.det_pin)) {
1587 printk(KERN_INFO "No SmartMedia card inserted.\n");
1588 res = -ENXIO;
1589 goto err_no_card;
1590 }
1591 }
1592
1593 if (host->board.on_flash_bbt || on_flash_bbt) {
1594 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
1595 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
1596 }
1597
1598 if (!host->board.has_dma)
1599 use_dma = 0;
1600
1601 if (use_dma) {
1602 dma_cap_mask_t mask;
1603
1604 dma_cap_zero(mask);
1605 dma_cap_set(DMA_MEMCPY, mask);
1606 host->dma_chan = dma_request_channel(mask, NULL, NULL);
1607 if (!host->dma_chan) {
1608 dev_err(host->dev, "Failed to request DMA channel\n");
1609 use_dma = 0;
1610 }
1611 }
1612 if (use_dma)
1613 dev_info(host->dev, "Using %s for DMA transfers.\n",
1614 dma_chan_name(host->dma_chan));
1615 else
1616 dev_info(host->dev, "No DMA support for NAND access.\n");
1617
1618 /* first scan to find the device and get the page size */
1619 if (nand_scan_ident(mtd, 1, NULL)) {
1620 res = -ENXIO;
1621 goto err_scan_ident;
1622 }
1623
1624 if (nand_chip->ecc.mode == NAND_ECC_HW) {
1625 if (host->has_pmecc)
1626 res = atmel_pmecc_nand_init_params(pdev, host);
1627 else
1628 res = atmel_hw_nand_init_params(pdev, host);
1629
1630 if (res != 0)
1631 goto err_hw_ecc;
1632 }
1633
1634 /* second phase scan */
1635 if (nand_scan_tail(mtd)) {
1636 res = -ENXIO;
1637 goto err_scan_tail;
1638 }
1639
1640 mtd->name = "atmel_nand";
1641 ppdata.of_node = pdev->dev.of_node;
1642 res = mtd_device_parse_register(mtd, NULL, &ppdata,
1643 host->board.parts, host->board.num_parts);
1644 if (!res)
1645 return res;
1646
1647 err_scan_tail:
1648 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1649 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1650 pmecc_data_free(host);
1651 }
1652 if (host->ecc)
1653 iounmap(host->ecc);
1654 if (host->pmerrloc_base)
1655 iounmap(host->pmerrloc_base);
1656 if (host->pmecc_rom_base)
1657 iounmap(host->pmecc_rom_base);
1658 err_hw_ecc:
1659 err_scan_ident:
1660 err_no_card:
1661 atmel_nand_disable(host);
1662 if (host->dma_chan)
1663 dma_release_channel(host->dma_chan);
1664 err_ecc_ioremap:
1665 iounmap(host->io_base);
1666 err_nand_ioremap:
1667 kfree(host);
1668 return res;
1669 }
1670
1671 /*
1672 * Remove a NAND device.
1673 */
1674 static int __exit atmel_nand_remove(struct platform_device *pdev)
1675 {
1676 struct atmel_nand_host *host = platform_get_drvdata(pdev);
1677 struct mtd_info *mtd = &host->mtd;
1678
1679 nand_release(mtd);
1680
1681 atmel_nand_disable(host);
1682
1683 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1684 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1685 pmerrloc_writel(host->pmerrloc_base, ELDIS,
1686 PMERRLOC_DISABLE);
1687 pmecc_data_free(host);
1688 }
1689
1690 if (gpio_is_valid(host->board.det_pin))
1691 gpio_free(host->board.det_pin);
1692
1693 if (gpio_is_valid(host->board.enable_pin))
1694 gpio_free(host->board.enable_pin);
1695
1696 if (gpio_is_valid(host->board.rdy_pin))
1697 gpio_free(host->board.rdy_pin);
1698
1699 if (host->ecc)
1700 iounmap(host->ecc);
1701 if (host->pmecc_rom_base)
1702 iounmap(host->pmecc_rom_base);
1703 if (host->pmerrloc_base)
1704 iounmap(host->pmerrloc_base);
1705
1706 if (host->dma_chan)
1707 dma_release_channel(host->dma_chan);
1708
1709 iounmap(host->io_base);
1710 kfree(host);
1711
1712 return 0;
1713 }
1714
1715 #if defined(CONFIG_OF)
1716 static const struct of_device_id atmel_nand_dt_ids[] = {
1717 { .compatible = "atmel,at91rm9200-nand" },
1718 { /* sentinel */ }
1719 };
1720
1721 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
1722 #endif
1723
1724 static struct platform_driver atmel_nand_driver = {
1725 .remove = __exit_p(atmel_nand_remove),
1726 .driver = {
1727 .name = "atmel_nand",
1728 .owner = THIS_MODULE,
1729 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
1730 },
1731 };
1732
1733 module_platform_driver_probe(atmel_nand_driver, atmel_nand_probe);
1734
1735 MODULE_LICENSE("GPL");
1736 MODULE_AUTHOR("Rick Bronson");
1737 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
1738 MODULE_ALIAS("platform:atmel_nand");
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