2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/wait.h>
23 #include <linux/mutex.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/module.h>
29 MODULE_LICENSE("GPL");
32 * We define a module parameter that allows the user to override
33 * the hardware and decide what timing mode should be used.
35 #define NAND_DEFAULT_TIMINGS -1
37 static int onfi_timing_mode
= NAND_DEFAULT_TIMINGS
;
38 module_param(onfi_timing_mode
, int, S_IRUGO
);
39 MODULE_PARM_DESC(onfi_timing_mode
,
40 "Overrides default ONFI setting. -1 indicates use default timings");
42 #define DENALI_NAND_NAME "denali-nand"
45 * We define a macro here that combines all interrupts this driver uses into
46 * a single constant value, for convenience.
48 #define DENALI_IRQ_ALL (INTR__DMA_CMD_COMP | \
49 INTR__ECC_TRANSACTION_DONE | \
51 INTR__PROGRAM_FAIL | \
53 INTR__PROGRAM_COMP | \
60 * indicates whether or not the internal value for the flash bank is
63 #define CHIP_SELECT_INVALID -1
66 * This macro divides two integers and rounds fractional values up
67 * to the nearest integer value.
69 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
72 * this macro allows us to convert from an MTD structure to our own
73 * device context (denali) structure.
75 static inline struct denali_nand_info
*mtd_to_denali(struct mtd_info
*mtd
)
77 return container_of(mtd_to_nand(mtd
), struct denali_nand_info
, nand
);
81 * These constants are defined by the driver to enable common driver
82 * configuration options.
84 #define SPARE_ACCESS 0x41
85 #define MAIN_ACCESS 0x42
86 #define MAIN_SPARE_ACCESS 0x43
89 #define DENALI_WRITE 0x100
92 * this is a helper macro that allows us to
93 * format the bank into the proper bits for the controller
95 #define BANK(x) ((x) << 24)
97 /* forward declarations */
98 static void clear_interrupts(struct denali_nand_info
*denali
);
99 static uint32_t wait_for_irq(struct denali_nand_info
*denali
,
101 static void denali_irq_enable(struct denali_nand_info
*denali
,
103 static uint32_t read_interrupt_status(struct denali_nand_info
*denali
);
106 * Certain operations for the denali NAND controller use an indexed mode to
107 * read/write data. The operation is performed by writing the address value
108 * of the command to the device memory followed by the data. This function
109 * abstracts this common operation.
111 static void index_addr(struct denali_nand_info
*denali
,
112 uint32_t address
, uint32_t data
)
114 iowrite32(address
, denali
->flash_mem
);
115 iowrite32(data
, denali
->flash_mem
+ 0x10);
118 /* Perform an indexed read of the device */
119 static void index_addr_read_data(struct denali_nand_info
*denali
,
120 uint32_t address
, uint32_t *pdata
)
122 iowrite32(address
, denali
->flash_mem
);
123 *pdata
= ioread32(denali
->flash_mem
+ 0x10);
127 * We need to buffer some data for some of the NAND core routines.
128 * The operations manage buffering that data.
130 static void reset_buf(struct denali_nand_info
*denali
)
132 denali
->buf
.head
= denali
->buf
.tail
= 0;
135 static void write_byte_to_buf(struct denali_nand_info
*denali
, uint8_t byte
)
137 denali
->buf
.buf
[denali
->buf
.tail
++] = byte
;
140 /* reads the status of the device */
141 static void read_status(struct denali_nand_info
*denali
)
145 /* initialize the data buffer to store status */
148 cmd
= ioread32(denali
->flash_reg
+ WRITE_PROTECT
);
150 write_byte_to_buf(denali
, NAND_STATUS_WP
);
152 write_byte_to_buf(denali
, 0);
155 /* resets a specific device connected to the core */
156 static void reset_bank(struct denali_nand_info
*denali
)
159 uint32_t irq_mask
= INTR__RST_COMP
| INTR__TIME_OUT
;
161 clear_interrupts(denali
);
163 iowrite32(1 << denali
->flash_bank
, denali
->flash_reg
+ DEVICE_RESET
);
165 irq_status
= wait_for_irq(denali
, irq_mask
);
167 if (irq_status
& INTR__TIME_OUT
)
168 dev_err(denali
->dev
, "reset bank failed.\n");
171 /* Reset the flash controller */
172 static uint16_t denali_nand_reset(struct denali_nand_info
*denali
)
176 for (i
= 0; i
< denali
->max_banks
; i
++)
177 iowrite32(INTR__RST_COMP
| INTR__TIME_OUT
,
178 denali
->flash_reg
+ INTR_STATUS(i
));
180 for (i
= 0; i
< denali
->max_banks
; i
++) {
181 iowrite32(1 << i
, denali
->flash_reg
+ DEVICE_RESET
);
182 while (!(ioread32(denali
->flash_reg
+ INTR_STATUS(i
)) &
183 (INTR__RST_COMP
| INTR__TIME_OUT
)))
185 if (ioread32(denali
->flash_reg
+ INTR_STATUS(i
)) &
188 "NAND Reset operation timed out on bank %d\n", i
);
191 for (i
= 0; i
< denali
->max_banks
; i
++)
192 iowrite32(INTR__RST_COMP
| INTR__TIME_OUT
,
193 denali
->flash_reg
+ INTR_STATUS(i
));
199 * this routine calculates the ONFI timing values for a given mode and
200 * programs the clocking register accordingly. The mode is determined by
201 * the get_onfi_nand_para routine.
203 static void nand_onfi_timing_set(struct denali_nand_info
*denali
,
206 uint16_t Trea
[6] = {40, 30, 25, 20, 20, 16};
207 uint16_t Trp
[6] = {50, 25, 17, 15, 12, 10};
208 uint16_t Treh
[6] = {30, 15, 15, 10, 10, 7};
209 uint16_t Trc
[6] = {100, 50, 35, 30, 25, 20};
210 uint16_t Trhoh
[6] = {0, 15, 15, 15, 15, 15};
211 uint16_t Trloh
[6] = {0, 0, 0, 0, 5, 5};
212 uint16_t Tcea
[6] = {100, 45, 30, 25, 25, 25};
213 uint16_t Tadl
[6] = {200, 100, 100, 100, 70, 70};
214 uint16_t Trhw
[6] = {200, 100, 100, 100, 100, 100};
215 uint16_t Trhz
[6] = {200, 100, 100, 100, 100, 100};
216 uint16_t Twhr
[6] = {120, 80, 80, 60, 60, 60};
217 uint16_t Tcs
[6] = {70, 35, 25, 25, 20, 15};
219 uint16_t data_invalid_rhoh
, data_invalid_rloh
, data_invalid
;
220 uint16_t dv_window
= 0;
221 uint16_t en_lo
, en_hi
;
223 uint16_t addr_2_data
, re_2_we
, re_2_re
, we_2_re
, cs_cnt
;
225 en_lo
= CEIL_DIV(Trp
[mode
], CLK_X
);
226 en_hi
= CEIL_DIV(Treh
[mode
], CLK_X
);
228 if ((en_hi
* CLK_X
) < (Treh
[mode
] + 2))
232 if ((en_lo
+ en_hi
) * CLK_X
< Trc
[mode
])
233 en_lo
+= CEIL_DIV((Trc
[mode
] - (en_lo
+ en_hi
) * CLK_X
), CLK_X
);
235 if ((en_lo
+ en_hi
) < CLK_MULTI
)
236 en_lo
+= CLK_MULTI
- en_lo
- en_hi
;
238 while (dv_window
< 8) {
239 data_invalid_rhoh
= en_lo
* CLK_X
+ Trhoh
[mode
];
241 data_invalid_rloh
= (en_lo
+ en_hi
) * CLK_X
+ Trloh
[mode
];
243 data_invalid
= data_invalid_rhoh
< data_invalid_rloh
?
244 data_invalid_rhoh
: data_invalid_rloh
;
246 dv_window
= data_invalid
- Trea
[mode
];
252 acc_clks
= CEIL_DIV(Trea
[mode
], CLK_X
);
254 while (acc_clks
* CLK_X
- Trea
[mode
] < 3)
257 if (data_invalid
- acc_clks
* CLK_X
< 2)
258 dev_warn(denali
->dev
, "%s, Line %d: Warning!\n",
261 addr_2_data
= CEIL_DIV(Tadl
[mode
], CLK_X
);
262 re_2_we
= CEIL_DIV(Trhw
[mode
], CLK_X
);
263 re_2_re
= CEIL_DIV(Trhz
[mode
], CLK_X
);
264 we_2_re
= CEIL_DIV(Twhr
[mode
], CLK_X
);
265 cs_cnt
= CEIL_DIV((Tcs
[mode
] - Trp
[mode
]), CLK_X
);
270 while (cs_cnt
* CLK_X
+ Trea
[mode
] < Tcea
[mode
])
279 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
280 if (ioread32(denali
->flash_reg
+ MANUFACTURER_ID
) == 0 &&
281 ioread32(denali
->flash_reg
+ DEVICE_ID
) == 0x88)
284 iowrite32(acc_clks
, denali
->flash_reg
+ ACC_CLKS
);
285 iowrite32(re_2_we
, denali
->flash_reg
+ RE_2_WE
);
286 iowrite32(re_2_re
, denali
->flash_reg
+ RE_2_RE
);
287 iowrite32(we_2_re
, denali
->flash_reg
+ WE_2_RE
);
288 iowrite32(addr_2_data
, denali
->flash_reg
+ ADDR_2_DATA
);
289 iowrite32(en_lo
, denali
->flash_reg
+ RDWR_EN_LO_CNT
);
290 iowrite32(en_hi
, denali
->flash_reg
+ RDWR_EN_HI_CNT
);
291 iowrite32(cs_cnt
, denali
->flash_reg
+ CS_SETUP_CNT
);
294 /* queries the NAND device to see what ONFI modes it supports. */
295 static uint16_t get_onfi_nand_para(struct denali_nand_info
*denali
)
300 * we needn't to do a reset here because driver has already
301 * reset all the banks before
303 if (!(ioread32(denali
->flash_reg
+ ONFI_TIMING_MODE
) &
304 ONFI_TIMING_MODE__VALUE
))
307 for (i
= 5; i
> 0; i
--) {
308 if (ioread32(denali
->flash_reg
+ ONFI_TIMING_MODE
) &
313 nand_onfi_timing_set(denali
, i
);
316 * By now, all the ONFI devices we know support the page cache
317 * rw feature. So here we enable the pipeline_rw_ahead feature
319 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
320 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
325 static void get_samsung_nand_para(struct denali_nand_info
*denali
,
328 if (device_id
== 0xd3) { /* Samsung K9WAG08U1A */
329 /* Set timing register values according to datasheet */
330 iowrite32(5, denali
->flash_reg
+ ACC_CLKS
);
331 iowrite32(20, denali
->flash_reg
+ RE_2_WE
);
332 iowrite32(12, denali
->flash_reg
+ WE_2_RE
);
333 iowrite32(14, denali
->flash_reg
+ ADDR_2_DATA
);
334 iowrite32(3, denali
->flash_reg
+ RDWR_EN_LO_CNT
);
335 iowrite32(2, denali
->flash_reg
+ RDWR_EN_HI_CNT
);
336 iowrite32(2, denali
->flash_reg
+ CS_SETUP_CNT
);
340 static void get_toshiba_nand_para(struct denali_nand_info
*denali
)
343 * Workaround to fix a controller bug which reports a wrong
344 * spare area size for some kind of Toshiba NAND device
346 if ((ioread32(denali
->flash_reg
+ DEVICE_MAIN_AREA_SIZE
) == 4096) &&
347 (ioread32(denali
->flash_reg
+ DEVICE_SPARE_AREA_SIZE
) == 64))
348 iowrite32(216, denali
->flash_reg
+ DEVICE_SPARE_AREA_SIZE
);
351 static void get_hynix_nand_para(struct denali_nand_info
*denali
,
355 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
356 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
357 iowrite32(128, denali
->flash_reg
+ PAGES_PER_BLOCK
);
358 iowrite32(4096, denali
->flash_reg
+ DEVICE_MAIN_AREA_SIZE
);
359 iowrite32(224, denali
->flash_reg
+ DEVICE_SPARE_AREA_SIZE
);
360 iowrite32(0, denali
->flash_reg
+ DEVICE_WIDTH
);
363 dev_warn(denali
->dev
,
364 "Unknown Hynix NAND (Device ID: 0x%x).\n"
365 "Will use default parameter values instead.\n",
371 * determines how many NAND chips are connected to the controller. Note for
372 * Intel CE4100 devices we don't support more than one device.
374 static void find_valid_banks(struct denali_nand_info
*denali
)
376 uint32_t id
[denali
->max_banks
];
379 denali
->total_used_banks
= 1;
380 for (i
= 0; i
< denali
->max_banks
; i
++) {
381 index_addr(denali
, MODE_11
| (i
<< 24) | 0, 0x90);
382 index_addr(denali
, MODE_11
| (i
<< 24) | 1, 0);
383 index_addr_read_data(denali
, MODE_11
| (i
<< 24) | 2, &id
[i
]);
386 "Return 1st ID for bank[%d]: %x\n", i
, id
[i
]);
389 if (!(id
[i
] & 0x0ff))
392 if ((id
[i
] & 0x0ff) == (id
[0] & 0x0ff))
393 denali
->total_used_banks
++;
399 if (denali
->platform
== INTEL_CE4100
) {
401 * Platform limitations of the CE4100 device limit
402 * users to a single chip solution for NAND.
403 * Multichip support is not enabled.
405 if (denali
->total_used_banks
!= 1) {
407 "Sorry, Intel CE4100 only supports a single NAND device.\n");
412 "denali->total_used_banks: %d\n", denali
->total_used_banks
);
416 * Use the configuration feature register to determine the maximum number of
417 * banks that the hardware supports.
419 static void detect_max_banks(struct denali_nand_info
*denali
)
421 uint32_t features
= ioread32(denali
->flash_reg
+ FEATURES
);
423 denali
->max_banks
= 1 << (features
& FEATURES__N_BANKS
);
425 /* the encoding changed from rev 5.0 to 5.1 */
426 if (denali
->revision
< 0x0501)
427 denali
->max_banks
<<= 1;
430 static uint16_t denali_nand_timing_set(struct denali_nand_info
*denali
)
432 uint16_t status
= PASS
;
433 uint32_t id_bytes
[8], addr
;
434 uint8_t maf_id
, device_id
;
438 * Use read id method to get device ID and other params.
439 * For some NAND chips, controller can't report the correct
440 * device ID by reading from DEVICE_ID register
442 addr
= MODE_11
| BANK(denali
->flash_bank
);
443 index_addr(denali
, addr
| 0, 0x90);
444 index_addr(denali
, addr
| 1, 0);
445 for (i
= 0; i
< 8; i
++)
446 index_addr_read_data(denali
, addr
| 2, &id_bytes
[i
]);
447 maf_id
= id_bytes
[0];
448 device_id
= id_bytes
[1];
450 if (ioread32(denali
->flash_reg
+ ONFI_DEVICE_NO_OF_LUNS
) &
451 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE
) { /* ONFI 1.0 NAND */
452 if (FAIL
== get_onfi_nand_para(denali
))
454 } else if (maf_id
== 0xEC) { /* Samsung NAND */
455 get_samsung_nand_para(denali
, device_id
);
456 } else if (maf_id
== 0x98) { /* Toshiba NAND */
457 get_toshiba_nand_para(denali
);
458 } else if (maf_id
== 0xAD) { /* Hynix NAND */
459 get_hynix_nand_para(denali
, device_id
);
462 dev_info(denali
->dev
,
463 "Dump timing register values:\n"
464 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
465 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
466 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
467 ioread32(denali
->flash_reg
+ ACC_CLKS
),
468 ioread32(denali
->flash_reg
+ RE_2_WE
),
469 ioread32(denali
->flash_reg
+ RE_2_RE
),
470 ioread32(denali
->flash_reg
+ WE_2_RE
),
471 ioread32(denali
->flash_reg
+ ADDR_2_DATA
),
472 ioread32(denali
->flash_reg
+ RDWR_EN_LO_CNT
),
473 ioread32(denali
->flash_reg
+ RDWR_EN_HI_CNT
),
474 ioread32(denali
->flash_reg
+ CS_SETUP_CNT
));
476 find_valid_banks(denali
);
479 * If the user specified to override the default timings
480 * with a specific ONFI mode, we apply those changes here.
482 if (onfi_timing_mode
!= NAND_DEFAULT_TIMINGS
)
483 nand_onfi_timing_set(denali
, onfi_timing_mode
);
488 static void denali_set_intr_modes(struct denali_nand_info
*denali
,
492 iowrite32(1, denali
->flash_reg
+ GLOBAL_INT_ENABLE
);
494 iowrite32(0, denali
->flash_reg
+ GLOBAL_INT_ENABLE
);
498 * validation function to verify that the controlling software is making
501 static inline bool is_flash_bank_valid(int flash_bank
)
503 return flash_bank
>= 0 && flash_bank
< 4;
506 static void denali_irq_init(struct denali_nand_info
*denali
)
511 /* Disable global interrupts */
512 denali_set_intr_modes(denali
, false);
514 int_mask
= DENALI_IRQ_ALL
;
516 /* Clear all status bits */
517 for (i
= 0; i
< denali
->max_banks
; ++i
)
518 iowrite32(0xFFFF, denali
->flash_reg
+ INTR_STATUS(i
));
520 denali_irq_enable(denali
, int_mask
);
523 static void denali_irq_cleanup(int irqnum
, struct denali_nand_info
*denali
)
525 denali_set_intr_modes(denali
, false);
528 static void denali_irq_enable(struct denali_nand_info
*denali
,
533 for (i
= 0; i
< denali
->max_banks
; ++i
)
534 iowrite32(int_mask
, denali
->flash_reg
+ INTR_EN(i
));
538 * This function only returns when an interrupt that this driver cares about
539 * occurs. This is to reduce the overhead of servicing interrupts
541 static inline uint32_t denali_irq_detected(struct denali_nand_info
*denali
)
543 return read_interrupt_status(denali
) & DENALI_IRQ_ALL
;
546 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
547 static inline void clear_interrupt(struct denali_nand_info
*denali
,
550 uint32_t intr_status_reg
;
552 intr_status_reg
= INTR_STATUS(denali
->flash_bank
);
554 iowrite32(irq_mask
, denali
->flash_reg
+ intr_status_reg
);
557 static void clear_interrupts(struct denali_nand_info
*denali
)
561 spin_lock_irq(&denali
->irq_lock
);
563 status
= read_interrupt_status(denali
);
564 clear_interrupt(denali
, status
);
566 denali
->irq_status
= 0x0;
567 spin_unlock_irq(&denali
->irq_lock
);
570 static uint32_t read_interrupt_status(struct denali_nand_info
*denali
)
572 uint32_t intr_status_reg
;
574 intr_status_reg
= INTR_STATUS(denali
->flash_bank
);
576 return ioread32(denali
->flash_reg
+ intr_status_reg
);
580 * This is the interrupt service routine. It handles all interrupts
581 * sent to this device. Note that on CE4100, this is a shared interrupt.
583 static irqreturn_t
denali_isr(int irq
, void *dev_id
)
585 struct denali_nand_info
*denali
= dev_id
;
587 irqreturn_t result
= IRQ_NONE
;
589 spin_lock(&denali
->irq_lock
);
591 /* check to see if a valid NAND chip has been selected. */
592 if (is_flash_bank_valid(denali
->flash_bank
)) {
594 * check to see if controller generated the interrupt,
595 * since this is a shared interrupt
597 irq_status
= denali_irq_detected(denali
);
598 if (irq_status
!= 0) {
599 /* handle interrupt */
600 /* first acknowledge it */
601 clear_interrupt(denali
, irq_status
);
603 * store the status in the device context for someone
606 denali
->irq_status
|= irq_status
;
607 /* notify anyone who cares that it happened */
608 complete(&denali
->complete
);
609 /* tell the OS that we've handled this */
610 result
= IRQ_HANDLED
;
613 spin_unlock(&denali
->irq_lock
);
617 static uint32_t wait_for_irq(struct denali_nand_info
*denali
, uint32_t irq_mask
)
619 unsigned long comp_res
;
620 uint32_t intr_status
;
621 unsigned long timeout
= msecs_to_jiffies(1000);
625 wait_for_completion_timeout(&denali
->complete
, timeout
);
626 spin_lock_irq(&denali
->irq_lock
);
627 intr_status
= denali
->irq_status
;
629 if (intr_status
& irq_mask
) {
630 denali
->irq_status
&= ~irq_mask
;
631 spin_unlock_irq(&denali
->irq_lock
);
632 /* our interrupt was detected */
637 * these are not the interrupts you are looking for -
640 spin_unlock_irq(&denali
->irq_lock
);
641 } while (comp_res
!= 0);
645 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
646 intr_status
, irq_mask
);
654 * This helper function setups the registers for ECC and whether or not
655 * the spare area will be transferred.
657 static void setup_ecc_for_xfer(struct denali_nand_info
*denali
, bool ecc_en
,
660 int ecc_en_flag
, transfer_spare_flag
;
662 /* set ECC, transfer spare bits if needed */
663 ecc_en_flag
= ecc_en
? ECC_ENABLE__FLAG
: 0;
664 transfer_spare_flag
= transfer_spare
? TRANSFER_SPARE_REG__FLAG
: 0;
666 /* Enable spare area/ECC per user's request. */
667 iowrite32(ecc_en_flag
, denali
->flash_reg
+ ECC_ENABLE
);
668 iowrite32(transfer_spare_flag
, denali
->flash_reg
+ TRANSFER_SPARE_REG
);
672 * sends a pipeline command operation to the controller. See the Denali NAND
673 * controller's user guide for more information (section 4.2.3.6).
675 static int denali_send_pipeline_cmd(struct denali_nand_info
*denali
,
676 bool ecc_en
, bool transfer_spare
,
677 int access_type
, int op
)
682 setup_ecc_for_xfer(denali
, ecc_en
, transfer_spare
);
684 clear_interrupts(denali
);
686 addr
= BANK(denali
->flash_bank
) | denali
->page
;
688 if (op
== DENALI_WRITE
&& access_type
!= SPARE_ACCESS
) {
689 cmd
= MODE_01
| addr
;
690 iowrite32(cmd
, denali
->flash_mem
);
691 } else if (op
== DENALI_WRITE
&& access_type
== SPARE_ACCESS
) {
692 /* read spare area */
693 cmd
= MODE_10
| addr
;
694 index_addr(denali
, cmd
, access_type
);
696 cmd
= MODE_01
| addr
;
697 iowrite32(cmd
, denali
->flash_mem
);
698 } else if (op
== DENALI_READ
) {
699 /* setup page read request for access type */
700 cmd
= MODE_10
| addr
;
701 index_addr(denali
, cmd
, access_type
);
703 cmd
= MODE_01
| addr
;
704 iowrite32(cmd
, denali
->flash_mem
);
709 /* helper function that simply writes a buffer to the flash */
710 static int write_data_to_flash_mem(struct denali_nand_info
*denali
,
711 const uint8_t *buf
, int len
)
717 * verify that the len is a multiple of 4.
718 * see comment in read_data_from_flash_mem()
720 BUG_ON((len
% 4) != 0);
722 /* write the data to the flash memory */
723 buf32
= (uint32_t *)buf
;
724 for (i
= 0; i
< len
/ 4; i
++)
725 iowrite32(*buf32
++, denali
->flash_mem
+ 0x10);
726 return i
* 4; /* intent is to return the number of bytes read */
729 /* helper function that simply reads a buffer from the flash */
730 static int read_data_from_flash_mem(struct denali_nand_info
*denali
,
731 uint8_t *buf
, int len
)
737 * we assume that len will be a multiple of 4, if not it would be nice
738 * to know about it ASAP rather than have random failures...
739 * This assumption is based on the fact that this function is designed
740 * to be used to read flash pages, which are typically multiples of 4.
742 BUG_ON((len
% 4) != 0);
744 /* transfer the data from the flash */
745 buf32
= (uint32_t *)buf
;
746 for (i
= 0; i
< len
/ 4; i
++)
747 *buf32
++ = ioread32(denali
->flash_mem
+ 0x10);
748 return i
* 4; /* intent is to return the number of bytes read */
751 /* writes OOB data to the device */
752 static int write_oob_data(struct mtd_info
*mtd
, uint8_t *buf
, int page
)
754 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
756 uint32_t irq_mask
= INTR__PROGRAM_COMP
| INTR__PROGRAM_FAIL
;
761 if (denali_send_pipeline_cmd(denali
, false, false, SPARE_ACCESS
,
762 DENALI_WRITE
) == PASS
) {
763 write_data_to_flash_mem(denali
, buf
, mtd
->oobsize
);
765 /* wait for operation to complete */
766 irq_status
= wait_for_irq(denali
, irq_mask
);
768 if (irq_status
== 0) {
769 dev_err(denali
->dev
, "OOB write failed\n");
773 dev_err(denali
->dev
, "unable to send pipeline command\n");
779 /* reads OOB data from the device */
780 static void read_oob_data(struct mtd_info
*mtd
, uint8_t *buf
, int page
)
782 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
783 uint32_t irq_mask
= INTR__LOAD_COMP
;
784 uint32_t irq_status
, addr
, cmd
;
788 if (denali_send_pipeline_cmd(denali
, false, true, SPARE_ACCESS
,
789 DENALI_READ
) == PASS
) {
790 read_data_from_flash_mem(denali
, buf
, mtd
->oobsize
);
793 * wait for command to be accepted
794 * can always use status0 bit as the
795 * mask is identical for each bank.
797 irq_status
= wait_for_irq(denali
, irq_mask
);
800 dev_err(denali
->dev
, "page on OOB timeout %d\n",
804 * We set the device back to MAIN_ACCESS here as I observed
805 * instability with the controller if you do a block erase
806 * and the last transaction was a SPARE_ACCESS. Block erase
807 * is reliable (according to the MTD test infrastructure)
808 * if you are in MAIN_ACCESS.
810 addr
= BANK(denali
->flash_bank
) | denali
->page
;
811 cmd
= MODE_10
| addr
;
812 index_addr(denali
, cmd
, MAIN_ACCESS
);
816 static int denali_check_erased_page(struct mtd_info
*mtd
,
817 struct nand_chip
*chip
, uint8_t *buf
,
818 unsigned long uncor_ecc_flags
,
819 unsigned int max_bitflips
)
821 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
822 int ecc_steps
= chip
->ecc
.steps
;
823 int ecc_size
= chip
->ecc
.size
;
824 int ecc_bytes
= chip
->ecc
.bytes
;
827 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
832 for (i
= 0; i
< ecc_steps
; i
++) {
833 if (!(uncor_ecc_flags
& BIT(i
)))
836 stat
= nand_check_erased_ecc_chunk(buf
, ecc_size
,
841 mtd
->ecc_stats
.failed
++;
843 mtd
->ecc_stats
.corrected
+= stat
;
844 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
848 ecc_code
+= ecc_bytes
;
854 static int denali_hw_ecc_fixup(struct mtd_info
*mtd
,
855 struct denali_nand_info
*denali
,
856 unsigned long *uncor_ecc_flags
)
858 struct nand_chip
*chip
= mtd_to_nand(mtd
);
859 int bank
= denali
->flash_bank
;
861 unsigned int max_bitflips
;
863 ecc_cor
= ioread32(denali
->flash_reg
+ ECC_COR_INFO(bank
));
864 ecc_cor
>>= ECC_COR_INFO__SHIFT(bank
);
866 if (ecc_cor
& ECC_COR_INFO__UNCOR_ERR
) {
868 * This flag is set when uncorrectable error occurs at least in
869 * one ECC sector. We can not know "how many sectors", or
870 * "which sector(s)". We need erase-page check for all sectors.
872 *uncor_ecc_flags
= GENMASK(chip
->ecc
.steps
- 1, 0);
876 max_bitflips
= ecc_cor
& ECC_COR_INFO__MAX_ERRORS
;
879 * The register holds the maximum of per-sector corrected bitflips.
880 * This is suitable for the return value of the ->read_page() callback.
881 * Unfortunately, we can not know the total number of corrected bits in
882 * the page. Increase the stats by max_bitflips. (compromised solution)
884 mtd
->ecc_stats
.corrected
+= max_bitflips
;
889 #define ECC_SECTOR_SIZE 512
891 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
892 #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
893 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
894 #define ECC_ERROR_UNCORRECTABLE(x) ((x) & ERR_CORRECTION_INFO__ERROR_TYPE)
895 #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
896 #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
898 static int denali_sw_ecc_fixup(struct mtd_info
*mtd
,
899 struct denali_nand_info
*denali
,
900 unsigned long *uncor_ecc_flags
, uint8_t *buf
)
902 unsigned int bitflips
= 0;
903 unsigned int max_bitflips
= 0;
904 uint32_t err_addr
, err_cor_info
;
905 unsigned int err_byte
, err_sector
, err_device
;
906 uint8_t err_cor_value
;
907 unsigned int prev_sector
= 0;
909 /* read the ECC errors. we'll ignore them for now */
910 denali_set_intr_modes(denali
, false);
913 err_addr
= ioread32(denali
->flash_reg
+ ECC_ERROR_ADDRESS
);
914 err_sector
= ECC_SECTOR(err_addr
);
915 err_byte
= ECC_BYTE(err_addr
);
917 err_cor_info
= ioread32(denali
->flash_reg
+ ERR_CORRECTION_INFO
);
918 err_cor_value
= ECC_CORRECTION_VALUE(err_cor_info
);
919 err_device
= ECC_ERR_DEVICE(err_cor_info
);
921 /* reset the bitflip counter when crossing ECC sector */
922 if (err_sector
!= prev_sector
)
925 if (ECC_ERROR_UNCORRECTABLE(err_cor_info
)) {
927 * Check later if this is a real ECC error, or
930 *uncor_ecc_flags
|= BIT(err_sector
);
931 } else if (err_byte
< ECC_SECTOR_SIZE
) {
933 * If err_byte is larger than ECC_SECTOR_SIZE, means error
934 * happened in OOB, so we ignore it. It's no need for
935 * us to correct it err_device is represented the NAND
936 * error bits are happened in if there are more than
937 * one NAND connected.
940 unsigned int flips_in_byte
;
942 offset
= (err_sector
* ECC_SECTOR_SIZE
+ err_byte
) *
943 denali
->devnum
+ err_device
;
945 /* correct the ECC error */
946 flips_in_byte
= hweight8(buf
[offset
] ^ err_cor_value
);
947 buf
[offset
] ^= err_cor_value
;
948 mtd
->ecc_stats
.corrected
+= flips_in_byte
;
949 bitflips
+= flips_in_byte
;
951 max_bitflips
= max(max_bitflips
, bitflips
);
954 prev_sector
= err_sector
;
955 } while (!ECC_LAST_ERR(err_cor_info
));
958 * Once handle all ecc errors, controller will trigger a
959 * ECC_TRANSACTION_DONE interrupt, so here just wait for
960 * a while for this interrupt
962 while (!(read_interrupt_status(denali
) & INTR__ECC_TRANSACTION_DONE
))
964 clear_interrupts(denali
);
965 denali_set_intr_modes(denali
, true);
970 /* programs the controller to either enable/disable DMA transfers */
971 static void denali_enable_dma(struct denali_nand_info
*denali
, bool en
)
973 iowrite32(en
? DMA_ENABLE__FLAG
: 0, denali
->flash_reg
+ DMA_ENABLE
);
974 ioread32(denali
->flash_reg
+ DMA_ENABLE
);
977 static void denali_setup_dma64(struct denali_nand_info
*denali
, int op
)
980 const int page_count
= 1;
981 uint64_t addr
= denali
->buf
.dma_buf
;
983 mode
= MODE_10
| BANK(denali
->flash_bank
) | denali
->page
;
985 /* DMA is a three step process */
988 * 1. setup transfer type, interrupt when complete,
989 * burst len = 64 bytes, the number of pages
991 index_addr(denali
, mode
, 0x01002000 | (64 << 16) | op
| page_count
);
993 /* 2. set memory low address */
994 index_addr(denali
, mode
, addr
);
996 /* 3. set memory high address */
997 index_addr(denali
, mode
, addr
>> 32);
1000 static void denali_setup_dma32(struct denali_nand_info
*denali
, int op
)
1003 const int page_count
= 1;
1004 uint32_t addr
= denali
->buf
.dma_buf
;
1006 mode
= MODE_10
| BANK(denali
->flash_bank
);
1008 /* DMA is a four step process */
1010 /* 1. setup transfer type and # of pages */
1011 index_addr(denali
, mode
| denali
->page
, 0x2000 | op
| page_count
);
1013 /* 2. set memory high address bits 23:8 */
1014 index_addr(denali
, mode
| ((addr
>> 16) << 8), 0x2200);
1016 /* 3. set memory low address bits 23:8 */
1017 index_addr(denali
, mode
| ((addr
& 0xffff) << 8), 0x2300);
1019 /* 4. interrupt when complete, burst len = 64 bytes */
1020 index_addr(denali
, mode
| 0x14000, 0x2400);
1023 static void denali_setup_dma(struct denali_nand_info
*denali
, int op
)
1025 if (denali
->caps
& DENALI_CAP_DMA_64BIT
)
1026 denali_setup_dma64(denali
, op
);
1028 denali_setup_dma32(denali
, op
);
1032 * writes a page. user specifies type, and this function handles the
1033 * configuration details.
1035 static int write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1036 const uint8_t *buf
, bool raw_xfer
)
1038 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1039 dma_addr_t addr
= denali
->buf
.dma_buf
;
1040 size_t size
= mtd
->writesize
+ mtd
->oobsize
;
1041 uint32_t irq_status
;
1042 uint32_t irq_mask
= INTR__DMA_CMD_COMP
| INTR__PROGRAM_FAIL
;
1045 * if it is a raw xfer, we want to disable ecc and send the spare area.
1046 * !raw_xfer - enable ecc
1047 * raw_xfer - transfer spare
1049 setup_ecc_for_xfer(denali
, !raw_xfer
, raw_xfer
);
1051 /* copy buffer into DMA buffer */
1052 memcpy(denali
->buf
.buf
, buf
, mtd
->writesize
);
1055 /* transfer the data to the spare area */
1056 memcpy(denali
->buf
.buf
+ mtd
->writesize
,
1061 dma_sync_single_for_device(denali
->dev
, addr
, size
, DMA_TO_DEVICE
);
1063 clear_interrupts(denali
);
1064 denali_enable_dma(denali
, true);
1066 denali_setup_dma(denali
, DENALI_WRITE
);
1068 /* wait for operation to complete */
1069 irq_status
= wait_for_irq(denali
, irq_mask
);
1071 if (irq_status
== 0) {
1072 dev_err(denali
->dev
, "timeout on write_page (type = %d)\n",
1074 denali
->status
= NAND_STATUS_FAIL
;
1077 denali_enable_dma(denali
, false);
1078 dma_sync_single_for_cpu(denali
->dev
, addr
, size
, DMA_TO_DEVICE
);
1083 /* NAND core entry points */
1086 * this is the callback that the NAND core calls to write a page. Since
1087 * writing a page with ECC or without is similar, all the work is done
1088 * by write_page above.
1090 static int denali_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1091 const uint8_t *buf
, int oob_required
, int page
)
1094 * for regular page writes, we let HW handle all the ECC
1095 * data written to the device.
1097 return write_page(mtd
, chip
, buf
, false);
1101 * This is the callback that the NAND core calls to write a page without ECC.
1102 * raw access is similar to ECC page writes, so all the work is done in the
1103 * write_page() function above.
1105 static int denali_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1106 const uint8_t *buf
, int oob_required
,
1110 * for raw page writes, we want to disable ECC and simply write
1111 * whatever data is in the buffer.
1113 return write_page(mtd
, chip
, buf
, true);
1116 static int denali_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1119 return write_oob_data(mtd
, chip
->oob_poi
, page
);
1122 static int denali_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1125 read_oob_data(mtd
, chip
->oob_poi
, page
);
1130 static int denali_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1131 uint8_t *buf
, int oob_required
, int page
)
1133 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1134 dma_addr_t addr
= denali
->buf
.dma_buf
;
1135 size_t size
= mtd
->writesize
+ mtd
->oobsize
;
1136 uint32_t irq_status
;
1137 uint32_t irq_mask
= denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
?
1138 INTR__DMA_CMD_COMP
| INTR__ECC_UNCOR_ERR
:
1139 INTR__ECC_TRANSACTION_DONE
| INTR__ECC_ERR
;
1140 unsigned long uncor_ecc_flags
= 0;
1143 if (page
!= denali
->page
) {
1144 dev_err(denali
->dev
,
1145 "IN %s: page %d is not equal to denali->page %d",
1146 __func__
, page
, denali
->page
);
1150 setup_ecc_for_xfer(denali
, true, false);
1152 denali_enable_dma(denali
, true);
1153 dma_sync_single_for_device(denali
->dev
, addr
, size
, DMA_FROM_DEVICE
);
1155 clear_interrupts(denali
);
1156 denali_setup_dma(denali
, DENALI_READ
);
1158 /* wait for operation to complete */
1159 irq_status
= wait_for_irq(denali
, irq_mask
);
1161 dma_sync_single_for_cpu(denali
->dev
, addr
, size
, DMA_FROM_DEVICE
);
1163 memcpy(buf
, denali
->buf
.buf
, mtd
->writesize
);
1165 if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
)
1166 stat
= denali_hw_ecc_fixup(mtd
, denali
, &uncor_ecc_flags
);
1167 else if (irq_status
& INTR__ECC_ERR
)
1168 stat
= denali_sw_ecc_fixup(mtd
, denali
, &uncor_ecc_flags
, buf
);
1169 denali_enable_dma(denali
, false);
1174 if (uncor_ecc_flags
) {
1175 read_oob_data(mtd
, chip
->oob_poi
, denali
->page
);
1177 stat
= denali_check_erased_page(mtd
, chip
, buf
,
1178 uncor_ecc_flags
, stat
);
1184 static int denali_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1185 uint8_t *buf
, int oob_required
, int page
)
1187 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1188 dma_addr_t addr
= denali
->buf
.dma_buf
;
1189 size_t size
= mtd
->writesize
+ mtd
->oobsize
;
1190 uint32_t irq_mask
= INTR__DMA_CMD_COMP
;
1192 if (page
!= denali
->page
) {
1193 dev_err(denali
->dev
,
1194 "IN %s: page %d is not equal to denali->page %d",
1195 __func__
, page
, denali
->page
);
1199 setup_ecc_for_xfer(denali
, false, true);
1200 denali_enable_dma(denali
, true);
1202 dma_sync_single_for_device(denali
->dev
, addr
, size
, DMA_FROM_DEVICE
);
1204 clear_interrupts(denali
);
1205 denali_setup_dma(denali
, DENALI_READ
);
1207 /* wait for operation to complete */
1208 wait_for_irq(denali
, irq_mask
);
1210 dma_sync_single_for_cpu(denali
->dev
, addr
, size
, DMA_FROM_DEVICE
);
1212 denali_enable_dma(denali
, false);
1214 memcpy(buf
, denali
->buf
.buf
, mtd
->writesize
);
1215 memcpy(chip
->oob_poi
, denali
->buf
.buf
+ mtd
->writesize
, mtd
->oobsize
);
1220 static uint8_t denali_read_byte(struct mtd_info
*mtd
)
1222 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1223 uint8_t result
= 0xff;
1225 if (denali
->buf
.head
< denali
->buf
.tail
)
1226 result
= denali
->buf
.buf
[denali
->buf
.head
++];
1231 static void denali_select_chip(struct mtd_info
*mtd
, int chip
)
1233 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1235 spin_lock_irq(&denali
->irq_lock
);
1236 denali
->flash_bank
= chip
;
1237 spin_unlock_irq(&denali
->irq_lock
);
1240 static int denali_waitfunc(struct mtd_info
*mtd
, struct nand_chip
*chip
)
1242 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1243 int status
= denali
->status
;
1250 static int denali_erase(struct mtd_info
*mtd
, int page
)
1252 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1254 uint32_t cmd
, irq_status
;
1256 clear_interrupts(denali
);
1258 /* setup page read request for access type */
1259 cmd
= MODE_10
| BANK(denali
->flash_bank
) | page
;
1260 index_addr(denali
, cmd
, 0x1);
1262 /* wait for erase to complete or failure to occur */
1263 irq_status
= wait_for_irq(denali
, INTR__ERASE_COMP
| INTR__ERASE_FAIL
);
1265 return irq_status
& INTR__ERASE_FAIL
? NAND_STATUS_FAIL
: PASS
;
1268 static void denali_cmdfunc(struct mtd_info
*mtd
, unsigned int cmd
, int col
,
1271 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1276 case NAND_CMD_PAGEPROG
:
1278 case NAND_CMD_STATUS
:
1279 read_status(denali
);
1281 case NAND_CMD_READID
:
1282 case NAND_CMD_PARAM
:
1285 * sometimes ManufactureId read from register is not right
1286 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1287 * So here we send READID cmd to NAND insteand
1289 addr
= MODE_11
| BANK(denali
->flash_bank
);
1290 index_addr(denali
, addr
| 0, 0x90);
1291 index_addr(denali
, addr
| 1, col
);
1292 for (i
= 0; i
< 8; i
++) {
1293 index_addr_read_data(denali
, addr
| 2, &id
);
1294 write_byte_to_buf(denali
, id
);
1297 case NAND_CMD_READ0
:
1298 case NAND_CMD_SEQIN
:
1299 denali
->page
= page
;
1301 case NAND_CMD_RESET
:
1304 case NAND_CMD_READOOB
:
1305 /* TODO: Read OOB data */
1308 pr_err(": unsupported command received 0x%x\n", cmd
);
1312 /* end NAND core entry points */
1314 /* Initialization code to bring the device up to a known good state */
1315 static void denali_hw_init(struct denali_nand_info
*denali
)
1318 * The REVISION register may not be reliable. Platforms are allowed to
1321 if (!denali
->revision
)
1323 swab16(ioread32(denali
->flash_reg
+ REVISION
));
1326 * tell driver how many bit controller will skip before
1327 * writing ECC code in OOB, this register may be already
1328 * set by firmware. So we read this value out.
1329 * if this value is 0, just let it be.
1331 denali
->bbtskipbytes
= ioread32(denali
->flash_reg
+
1332 SPARE_AREA_SKIP_BYTES
);
1333 detect_max_banks(denali
);
1334 denali_nand_reset(denali
);
1335 iowrite32(0x0F, denali
->flash_reg
+ RB_PIN_ENABLED
);
1336 iowrite32(CHIP_EN_DONT_CARE__FLAG
,
1337 denali
->flash_reg
+ CHIP_ENABLE_DONT_CARE
);
1339 iowrite32(0xffff, denali
->flash_reg
+ SPARE_AREA_MARKER
);
1341 /* Should set value for these registers when init */
1342 iowrite32(0, denali
->flash_reg
+ TWO_ROW_ADDR_CYCLES
);
1343 iowrite32(1, denali
->flash_reg
+ ECC_ENABLE
);
1344 denali_nand_timing_set(denali
);
1345 denali_irq_init(denali
);
1349 * Althogh controller spec said SLC ECC is forceb to be 4bit,
1350 * but denali controller in MRST only support 15bit and 8bit ECC
1353 #define ECC_8BITS 14
1354 #define ECC_15BITS 26
1356 static int denali_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1357 struct mtd_oob_region
*oobregion
)
1359 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1360 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1365 oobregion
->offset
= denali
->bbtskipbytes
;
1366 oobregion
->length
= chip
->ecc
.total
;
1371 static int denali_ooblayout_free(struct mtd_info
*mtd
, int section
,
1372 struct mtd_oob_region
*oobregion
)
1374 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1375 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1380 oobregion
->offset
= chip
->ecc
.total
+ denali
->bbtskipbytes
;
1381 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
1386 static const struct mtd_ooblayout_ops denali_ooblayout_ops
= {
1387 .ecc
= denali_ooblayout_ecc
,
1388 .free
= denali_ooblayout_free
,
1391 static uint8_t bbt_pattern
[] = {'B', 'b', 't', '0' };
1392 static uint8_t mirror_pattern
[] = {'1', 't', 'b', 'B' };
1394 static struct nand_bbt_descr bbt_main_descr
= {
1395 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
1396 | NAND_BBT_2BIT
| NAND_BBT_VERSION
| NAND_BBT_PERCHIP
,
1401 .pattern
= bbt_pattern
,
1404 static struct nand_bbt_descr bbt_mirror_descr
= {
1405 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
1406 | NAND_BBT_2BIT
| NAND_BBT_VERSION
| NAND_BBT_PERCHIP
,
1411 .pattern
= mirror_pattern
,
1414 /* initialize driver data structures */
1415 static void denali_drv_init(struct denali_nand_info
*denali
)
1418 * the completion object will be used to notify
1419 * the callee that the interrupt is done
1421 init_completion(&denali
->complete
);
1424 * the spinlock will be used to synchronize the ISR with any
1425 * element that might be access shared data (interrupt status)
1427 spin_lock_init(&denali
->irq_lock
);
1429 /* indicate that MTD has not selected a valid bank yet */
1430 denali
->flash_bank
= CHIP_SELECT_INVALID
;
1432 /* initialize our irq_status variable to indicate no interrupts */
1433 denali
->irq_status
= 0;
1436 static int denali_multidev_fixup(struct denali_nand_info
*denali
)
1438 struct nand_chip
*chip
= &denali
->nand
;
1439 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1442 * Support for multi device:
1443 * When the IP configuration is x16 capable and two x8 chips are
1444 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1445 * In this case, the core framework knows nothing about this fact,
1446 * so we should tell it the _logical_ pagesize and anything necessary.
1448 denali
->devnum
= ioread32(denali
->flash_reg
+ DEVICES_CONNECTED
);
1451 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1452 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1454 if (denali
->devnum
== 0) {
1456 iowrite32(1, denali
->flash_reg
+ DEVICES_CONNECTED
);
1459 if (denali
->devnum
== 1)
1462 if (denali
->devnum
!= 2) {
1463 dev_err(denali
->dev
, "unsupported number of devices %d\n",
1468 /* 2 chips in parallel */
1470 mtd
->erasesize
<<= 1;
1471 mtd
->writesize
<<= 1;
1473 chip
->chipsize
<<= 1;
1474 chip
->page_shift
+= 1;
1475 chip
->phys_erase_shift
+= 1;
1476 chip
->bbt_erase_shift
+= 1;
1477 chip
->chip_shift
+= 1;
1478 chip
->pagemask
<<= 1;
1479 chip
->ecc
.size
<<= 1;
1480 chip
->ecc
.bytes
<<= 1;
1481 chip
->ecc
.strength
<<= 1;
1482 denali
->bbtskipbytes
<<= 1;
1487 int denali_init(struct denali_nand_info
*denali
)
1489 struct nand_chip
*chip
= &denali
->nand
;
1490 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1493 if (denali
->platform
== INTEL_CE4100
) {
1495 * Due to a silicon limitation, we can only support
1496 * ONFI timing mode 1 and below.
1498 if (onfi_timing_mode
< -1 || onfi_timing_mode
> 1) {
1499 pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1504 /* allocate a temporary buffer for nand_scan_ident() */
1505 denali
->buf
.buf
= devm_kzalloc(denali
->dev
, PAGE_SIZE
,
1506 GFP_DMA
| GFP_KERNEL
);
1507 if (!denali
->buf
.buf
)
1510 mtd
->dev
.parent
= denali
->dev
;
1511 denali_hw_init(denali
);
1512 denali_drv_init(denali
);
1514 /* Request IRQ after all the hardware initialization is finished */
1515 ret
= devm_request_irq(denali
->dev
, denali
->irq
, denali_isr
,
1516 IRQF_SHARED
, DENALI_NAND_NAME
, denali
);
1518 dev_err(denali
->dev
, "Unable to request IRQ\n");
1522 /* now that our ISR is registered, we can enable interrupts */
1523 denali_set_intr_modes(denali
, true);
1524 nand_set_flash_node(chip
, denali
->dev
->of_node
);
1525 /* Fallback to the default name if DT did not give "label" property */
1527 mtd
->name
= "denali-nand";
1529 /* register the driver with the NAND core subsystem */
1530 chip
->select_chip
= denali_select_chip
;
1531 chip
->cmdfunc
= denali_cmdfunc
;
1532 chip
->read_byte
= denali_read_byte
;
1533 chip
->waitfunc
= denali_waitfunc
;
1536 * scan for NAND devices attached to the controller
1537 * this is the first stage in a two step process to register
1538 * with the nand subsystem
1540 ret
= nand_scan_ident(mtd
, denali
->max_banks
, NULL
);
1542 goto failed_req_irq
;
1544 /* allocate the right size buffer now */
1545 devm_kfree(denali
->dev
, denali
->buf
.buf
);
1546 denali
->buf
.buf
= devm_kzalloc(denali
->dev
,
1547 mtd
->writesize
+ mtd
->oobsize
,
1549 if (!denali
->buf
.buf
) {
1551 goto failed_req_irq
;
1554 ret
= dma_set_mask(denali
->dev
,
1555 DMA_BIT_MASK(denali
->caps
& DENALI_CAP_DMA_64BIT
?
1558 dev_err(denali
->dev
, "No usable DMA configuration\n");
1559 goto failed_req_irq
;
1562 denali
->buf
.dma_buf
= dma_map_single(denali
->dev
, denali
->buf
.buf
,
1563 mtd
->writesize
+ mtd
->oobsize
,
1565 if (dma_mapping_error(denali
->dev
, denali
->buf
.dma_buf
)) {
1566 dev_err(denali
->dev
, "Failed to map DMA buffer\n");
1568 goto failed_req_irq
;
1572 * second stage of the NAND scan
1573 * this stage requires information regarding ECC and
1574 * bad block management.
1577 /* Bad block management */
1578 chip
->bbt_td
= &bbt_main_descr
;
1579 chip
->bbt_md
= &bbt_mirror_descr
;
1581 /* skip the scan for now until we have OOB read and write support */
1582 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
1583 chip
->options
|= NAND_SKIP_BBTSCAN
;
1584 chip
->ecc
.mode
= NAND_ECC_HW_SYNDROME
;
1586 /* no subpage writes on denali */
1587 chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
1590 * Denali Controller only support 15bit and 8bit ECC in MRST,
1591 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1594 if (!nand_is_slc(chip
) &&
1595 (mtd
->oobsize
> (denali
->bbtskipbytes
+
1596 ECC_15BITS
* (mtd
->writesize
/
1597 ECC_SECTOR_SIZE
)))) {
1598 /* if MLC OOB size is large enough, use 15bit ECC*/
1599 chip
->ecc
.strength
= 15;
1600 chip
->ecc
.bytes
= ECC_15BITS
;
1601 iowrite32(15, denali
->flash_reg
+ ECC_CORRECTION
);
1602 } else if (mtd
->oobsize
< (denali
->bbtskipbytes
+
1603 ECC_8BITS
* (mtd
->writesize
/
1604 ECC_SECTOR_SIZE
))) {
1605 pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
1606 goto failed_req_irq
;
1608 chip
->ecc
.strength
= 8;
1609 chip
->ecc
.bytes
= ECC_8BITS
;
1610 iowrite32(8, denali
->flash_reg
+ ECC_CORRECTION
);
1613 mtd_set_ooblayout(mtd
, &denali_ooblayout_ops
);
1615 /* override the default read operations */
1616 chip
->ecc
.size
= ECC_SECTOR_SIZE
;
1617 chip
->ecc
.read_page
= denali_read_page
;
1618 chip
->ecc
.read_page_raw
= denali_read_page_raw
;
1619 chip
->ecc
.write_page
= denali_write_page
;
1620 chip
->ecc
.write_page_raw
= denali_write_page_raw
;
1621 chip
->ecc
.read_oob
= denali_read_oob
;
1622 chip
->ecc
.write_oob
= denali_write_oob
;
1623 chip
->erase
= denali_erase
;
1625 ret
= denali_multidev_fixup(denali
);
1627 goto failed_req_irq
;
1629 ret
= nand_scan_tail(mtd
);
1631 goto failed_req_irq
;
1633 ret
= mtd_device_register(mtd
, NULL
, 0);
1635 dev_err(denali
->dev
, "Failed to register MTD: %d\n", ret
);
1636 goto failed_req_irq
;
1641 denali_irq_cleanup(denali
->irq
, denali
);
1645 EXPORT_SYMBOL(denali_init
);
1647 /* driver exit point */
1648 void denali_remove(struct denali_nand_info
*denali
)
1650 struct mtd_info
*mtd
= nand_to_mtd(&denali
->nand
);
1652 * Pre-compute DMA buffer size to avoid any problems in case
1653 * nand_release() ever changes in a way that mtd->writesize and
1654 * mtd->oobsize are not reliable after this call.
1656 int bufsize
= mtd
->writesize
+ mtd
->oobsize
;
1659 denali_irq_cleanup(denali
->irq
, denali
);
1660 dma_unmap_single(denali
->dev
, denali
->buf
.dma_buf
, bufsize
,
1663 EXPORT_SYMBOL(denali_remove
);