2 * drivers/mtd/nand/fsmc_nand.c
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
12 * Based on drivers/mtd/nand/nomadik_nand.c
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
35 #include <linux/mtd/partitions.h>
37 #include <linux/slab.h>
38 #include <linux/amba/bus.h>
39 #include <mtd/mtd-abi.h>
41 /* fsmc controller registers for NOR flash */
43 /* ctrl register definitions */
44 #define BANK_ENABLE (1 << 0)
45 #define MUXED (1 << 1)
46 #define NOR_DEV (2 << 2)
47 #define WIDTH_8 (0 << 4)
48 #define WIDTH_16 (1 << 4)
49 #define RSTPWRDWN (1 << 6)
50 #define WPROT (1 << 7)
51 #define WRT_ENABLE (1 << 12)
52 #define WAIT_ENB (1 << 13)
55 /* ctrl_tim register definitions */
57 #define FSMC_NOR_BANK_SZ 0x8
58 #define FSMC_NOR_REG_SIZE 0x40
60 #define FSMC_NOR_REG(base, bank, reg) (base + \
61 FSMC_NOR_BANK_SZ * (bank) + \
64 /* fsmc controller registers for NAND flash */
66 /* pc register definitions */
67 #define FSMC_RESET (1 << 0)
68 #define FSMC_WAITON (1 << 1)
69 #define FSMC_ENABLE (1 << 2)
70 #define FSMC_DEVTYPE_NAND (1 << 3)
71 #define FSMC_DEVWID_8 (0 << 4)
72 #define FSMC_DEVWID_16 (1 << 4)
73 #define FSMC_ECCEN (1 << 6)
74 #define FSMC_ECCPLEN_512 (0 << 7)
75 #define FSMC_ECCPLEN_256 (1 << 7)
76 #define FSMC_TCLR_1 (1)
77 #define FSMC_TCLR_SHIFT (9)
78 #define FSMC_TCLR_MASK (0xF)
79 #define FSMC_TAR_1 (1)
80 #define FSMC_TAR_SHIFT (13)
81 #define FSMC_TAR_MASK (0xF)
83 /* sts register definitions */
84 #define FSMC_CODE_RDY (1 << 15)
86 /* comm register definitions */
88 #define FSMC_TSET_SHIFT 0
89 #define FSMC_TSET_MASK 0xFF
90 #define FSMC_TWAIT_6 6
91 #define FSMC_TWAIT_SHIFT 8
92 #define FSMC_TWAIT_MASK 0xFF
93 #define FSMC_THOLD_4 4
94 #define FSMC_THOLD_SHIFT 16
95 #define FSMC_THOLD_MASK 0xFF
97 #define FSMC_THIZ_SHIFT 24
98 #define FSMC_THIZ_MASK 0xFF
104 #define FSMC_NAND_BANK_SZ 0x20
106 #define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
107 (FSMC_NAND_BANK_SZ * (bank)) + \
110 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
112 struct fsmc_nand_timings
{
127 * struct fsmc_nand_data - structure for FSMC NAND device state
129 * @pid: Part ID on the AMBA PrimeCell format
130 * @mtd: MTD info for a NAND flash.
131 * @nand: Chip related info for a NAND flash.
132 * @partitions: Partition info for a NAND Flash.
133 * @nr_partitions: Total number of partition of a NAND flash.
135 * @bank: Bank number for probed device.
136 * @clk: Clock structure for FSMC.
138 * @read_dma_chan: DMA channel for read access
139 * @write_dma_chan: DMA channel for write access to NAND
140 * @dma_access_complete: Completion structure
142 * @data_pa: NAND Physical port for Data.
143 * @data_va: NAND port for Data.
144 * @cmd_va: NAND port for Command.
145 * @addr_va: NAND port for Address.
146 * @regs_va: FSMC regs base address.
148 struct fsmc_nand_data
{
150 struct nand_chip nand
;
154 enum access_mode mode
;
157 /* DMA related objects */
158 struct dma_chan
*read_dma_chan
;
159 struct dma_chan
*write_dma_chan
;
160 struct completion dma_access_complete
;
162 struct fsmc_nand_timings
*dev_timings
;
165 void __iomem
*data_va
;
166 void __iomem
*cmd_va
;
167 void __iomem
*addr_va
;
168 void __iomem
*regs_va
;
171 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
172 struct mtd_oob_region
*oobregion
)
174 struct nand_chip
*chip
= mtd_to_nand(mtd
);
176 if (section
>= chip
->ecc
.steps
)
179 oobregion
->offset
= (section
* 16) + 2;
180 oobregion
->length
= 3;
185 static int fsmc_ecc1_ooblayout_free(struct mtd_info
*mtd
, int section
,
186 struct mtd_oob_region
*oobregion
)
188 struct nand_chip
*chip
= mtd_to_nand(mtd
);
190 if (section
>= chip
->ecc
.steps
)
193 oobregion
->offset
= (section
* 16) + 8;
195 if (section
< chip
->ecc
.steps
- 1)
196 oobregion
->length
= 8;
198 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
203 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops
= {
204 .ecc
= fsmc_ecc1_ooblayout_ecc
,
205 .free
= fsmc_ecc1_ooblayout_free
,
209 * ECC placement definitions in oobfree type format.
210 * There are 13 bytes of ecc for every 512 byte block and it has to be read
211 * consecutively and immediately after the 512 byte data block for hardware to
212 * generate the error bit offsets in 512 byte data.
214 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
215 struct mtd_oob_region
*oobregion
)
217 struct nand_chip
*chip
= mtd_to_nand(mtd
);
219 if (section
>= chip
->ecc
.steps
)
222 oobregion
->length
= chip
->ecc
.bytes
;
224 if (!section
&& mtd
->writesize
<= 512)
225 oobregion
->offset
= 0;
227 oobregion
->offset
= (section
* 16) + 2;
232 static int fsmc_ecc4_ooblayout_free(struct mtd_info
*mtd
, int section
,
233 struct mtd_oob_region
*oobregion
)
235 struct nand_chip
*chip
= mtd_to_nand(mtd
);
237 if (section
>= chip
->ecc
.steps
)
240 oobregion
->offset
= (section
* 16) + 15;
242 if (section
< chip
->ecc
.steps
- 1)
243 oobregion
->length
= 3;
245 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
250 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops
= {
251 .ecc
= fsmc_ecc4_ooblayout_ecc
,
252 .free
= fsmc_ecc4_ooblayout_free
,
255 static inline struct fsmc_nand_data
*mtd_to_fsmc(struct mtd_info
*mtd
)
257 return container_of(mtd_to_nand(mtd
), struct fsmc_nand_data
, nand
);
261 * fsmc_cmd_ctrl - For facilitaing Hardware access
262 * This routine allows hardware specific access to control-lines(ALE,CLE)
264 static void fsmc_cmd_ctrl(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
266 struct nand_chip
*this = mtd_to_nand(mtd
);
267 struct fsmc_nand_data
*host
= mtd_to_fsmc(mtd
);
268 void __iomem
*regs
= host
->regs_va
;
269 unsigned int bank
= host
->bank
;
271 if (ctrl
& NAND_CTRL_CHANGE
) {
274 if (ctrl
& NAND_CLE
) {
275 this->IO_ADDR_R
= host
->cmd_va
;
276 this->IO_ADDR_W
= host
->cmd_va
;
277 } else if (ctrl
& NAND_ALE
) {
278 this->IO_ADDR_R
= host
->addr_va
;
279 this->IO_ADDR_W
= host
->addr_va
;
281 this->IO_ADDR_R
= host
->data_va
;
282 this->IO_ADDR_W
= host
->data_va
;
285 pc
= readl(FSMC_NAND_REG(regs
, bank
, PC
));
290 writel_relaxed(pc
, FSMC_NAND_REG(regs
, bank
, PC
));
295 if (cmd
!= NAND_CMD_NONE
)
296 writeb_relaxed(cmd
, this->IO_ADDR_W
);
300 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
302 * This routine initializes timing parameters related to NAND memory access in
305 static void fsmc_nand_setup(void __iomem
*regs
, uint32_t bank
,
306 uint32_t busw
, struct fsmc_nand_timings
*timings
)
308 uint32_t value
= FSMC_DEVTYPE_NAND
| FSMC_ENABLE
| FSMC_WAITON
;
309 uint32_t tclr
, tar
, thiz
, thold
, twait
, tset
;
310 struct fsmc_nand_timings
*tims
;
311 struct fsmc_nand_timings default_timings
= {
315 .thold
= FSMC_THOLD_4
,
316 .twait
= FSMC_TWAIT_6
,
323 tims
= &default_timings
;
325 tclr
= (tims
->tclr
& FSMC_TCLR_MASK
) << FSMC_TCLR_SHIFT
;
326 tar
= (tims
->tar
& FSMC_TAR_MASK
) << FSMC_TAR_SHIFT
;
327 thiz
= (tims
->thiz
& FSMC_THIZ_MASK
) << FSMC_THIZ_SHIFT
;
328 thold
= (tims
->thold
& FSMC_THOLD_MASK
) << FSMC_THOLD_SHIFT
;
329 twait
= (tims
->twait
& FSMC_TWAIT_MASK
) << FSMC_TWAIT_SHIFT
;
330 tset
= (tims
->tset
& FSMC_TSET_MASK
) << FSMC_TSET_SHIFT
;
333 writel_relaxed(value
| FSMC_DEVWID_16
,
334 FSMC_NAND_REG(regs
, bank
, PC
));
336 writel_relaxed(value
| FSMC_DEVWID_8
,
337 FSMC_NAND_REG(regs
, bank
, PC
));
339 writel_relaxed(readl(FSMC_NAND_REG(regs
, bank
, PC
)) | tclr
| tar
,
340 FSMC_NAND_REG(regs
, bank
, PC
));
341 writel_relaxed(thiz
| thold
| twait
| tset
,
342 FSMC_NAND_REG(regs
, bank
, COMM
));
343 writel_relaxed(thiz
| thold
| twait
| tset
,
344 FSMC_NAND_REG(regs
, bank
, ATTRIB
));
348 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
350 static void fsmc_enable_hwecc(struct mtd_info
*mtd
, int mode
)
352 struct fsmc_nand_data
*host
= mtd_to_fsmc(mtd
);
353 void __iomem
*regs
= host
->regs_va
;
354 uint32_t bank
= host
->bank
;
356 writel_relaxed(readl(FSMC_NAND_REG(regs
, bank
, PC
)) & ~FSMC_ECCPLEN_256
,
357 FSMC_NAND_REG(regs
, bank
, PC
));
358 writel_relaxed(readl(FSMC_NAND_REG(regs
, bank
, PC
)) & ~FSMC_ECCEN
,
359 FSMC_NAND_REG(regs
, bank
, PC
));
360 writel_relaxed(readl(FSMC_NAND_REG(regs
, bank
, PC
)) | FSMC_ECCEN
,
361 FSMC_NAND_REG(regs
, bank
, PC
));
365 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
366 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
369 static int fsmc_read_hwecc_ecc4(struct mtd_info
*mtd
, const uint8_t *data
,
372 struct fsmc_nand_data
*host
= mtd_to_fsmc(mtd
);
373 void __iomem
*regs
= host
->regs_va
;
374 uint32_t bank
= host
->bank
;
376 unsigned long deadline
= jiffies
+ FSMC_BUSY_WAIT_TIMEOUT
;
379 if (readl_relaxed(FSMC_NAND_REG(regs
, bank
, STS
)) & FSMC_CODE_RDY
)
383 } while (!time_after_eq(jiffies
, deadline
));
385 if (time_after_eq(jiffies
, deadline
)) {
386 dev_err(host
->dev
, "calculate ecc timed out\n");
390 ecc_tmp
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, ECC1
));
391 ecc
[0] = (uint8_t) (ecc_tmp
>> 0);
392 ecc
[1] = (uint8_t) (ecc_tmp
>> 8);
393 ecc
[2] = (uint8_t) (ecc_tmp
>> 16);
394 ecc
[3] = (uint8_t) (ecc_tmp
>> 24);
396 ecc_tmp
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, ECC2
));
397 ecc
[4] = (uint8_t) (ecc_tmp
>> 0);
398 ecc
[5] = (uint8_t) (ecc_tmp
>> 8);
399 ecc
[6] = (uint8_t) (ecc_tmp
>> 16);
400 ecc
[7] = (uint8_t) (ecc_tmp
>> 24);
402 ecc_tmp
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, ECC3
));
403 ecc
[8] = (uint8_t) (ecc_tmp
>> 0);
404 ecc
[9] = (uint8_t) (ecc_tmp
>> 8);
405 ecc
[10] = (uint8_t) (ecc_tmp
>> 16);
406 ecc
[11] = (uint8_t) (ecc_tmp
>> 24);
408 ecc_tmp
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, STS
));
409 ecc
[12] = (uint8_t) (ecc_tmp
>> 16);
415 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
416 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
419 static int fsmc_read_hwecc_ecc1(struct mtd_info
*mtd
, const uint8_t *data
,
422 struct fsmc_nand_data
*host
= mtd_to_fsmc(mtd
);
423 void __iomem
*regs
= host
->regs_va
;
424 uint32_t bank
= host
->bank
;
427 ecc_tmp
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, ECC1
));
428 ecc
[0] = (uint8_t) (ecc_tmp
>> 0);
429 ecc
[1] = (uint8_t) (ecc_tmp
>> 8);
430 ecc
[2] = (uint8_t) (ecc_tmp
>> 16);
435 /* Count the number of 0's in buff upto a max of max_bits */
436 static int count_written_bits(uint8_t *buff
, int size
, int max_bits
)
438 int k
, written_bits
= 0;
440 for (k
= 0; k
< size
; k
++) {
441 written_bits
+= hweight8(~buff
[k
]);
442 if (written_bits
> max_bits
)
449 static void dma_complete(void *param
)
451 struct fsmc_nand_data
*host
= param
;
453 complete(&host
->dma_access_complete
);
456 static int dma_xfer(struct fsmc_nand_data
*host
, void *buffer
, int len
,
457 enum dma_data_direction direction
)
459 struct dma_chan
*chan
;
460 struct dma_device
*dma_dev
;
461 struct dma_async_tx_descriptor
*tx
;
462 dma_addr_t dma_dst
, dma_src
, dma_addr
;
464 unsigned long flags
= DMA_CTRL_ACK
| DMA_PREP_INTERRUPT
;
466 unsigned long time_left
;
468 if (direction
== DMA_TO_DEVICE
)
469 chan
= host
->write_dma_chan
;
470 else if (direction
== DMA_FROM_DEVICE
)
471 chan
= host
->read_dma_chan
;
475 dma_dev
= chan
->device
;
476 dma_addr
= dma_map_single(dma_dev
->dev
, buffer
, len
, direction
);
478 if (direction
== DMA_TO_DEVICE
) {
480 dma_dst
= host
->data_pa
;
482 dma_src
= host
->data_pa
;
486 tx
= dma_dev
->device_prep_dma_memcpy(chan
, dma_dst
, dma_src
,
489 dev_err(host
->dev
, "device_prep_dma_memcpy error\n");
494 tx
->callback
= dma_complete
;
495 tx
->callback_param
= host
;
496 cookie
= tx
->tx_submit(tx
);
498 ret
= dma_submit_error(cookie
);
500 dev_err(host
->dev
, "dma_submit_error %d\n", cookie
);
504 dma_async_issue_pending(chan
);
507 wait_for_completion_timeout(&host
->dma_access_complete
,
508 msecs_to_jiffies(3000));
509 if (time_left
== 0) {
510 dmaengine_terminate_all(chan
);
511 dev_err(host
->dev
, "wait_for_completion_timeout\n");
519 dma_unmap_single(dma_dev
->dev
, dma_addr
, len
, direction
);
525 * fsmc_write_buf - write buffer to chip
526 * @mtd: MTD device structure
528 * @len: number of bytes to write
530 static void fsmc_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
533 struct nand_chip
*chip
= mtd_to_nand(mtd
);
535 if (IS_ALIGNED((uint32_t)buf
, sizeof(uint32_t)) &&
536 IS_ALIGNED(len
, sizeof(uint32_t))) {
537 uint32_t *p
= (uint32_t *)buf
;
539 for (i
= 0; i
< len
; i
++)
540 writel_relaxed(p
[i
], chip
->IO_ADDR_W
);
542 for (i
= 0; i
< len
; i
++)
543 writeb_relaxed(buf
[i
], chip
->IO_ADDR_W
);
548 * fsmc_read_buf - read chip data into buffer
549 * @mtd: MTD device structure
550 * @buf: buffer to store date
551 * @len: number of bytes to read
553 static void fsmc_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
556 struct nand_chip
*chip
= mtd_to_nand(mtd
);
558 if (IS_ALIGNED((uint32_t)buf
, sizeof(uint32_t)) &&
559 IS_ALIGNED(len
, sizeof(uint32_t))) {
560 uint32_t *p
= (uint32_t *)buf
;
562 for (i
= 0; i
< len
; i
++)
563 p
[i
] = readl_relaxed(chip
->IO_ADDR_R
);
565 for (i
= 0; i
< len
; i
++)
566 buf
[i
] = readb_relaxed(chip
->IO_ADDR_R
);
571 * fsmc_read_buf_dma - read chip data into buffer
572 * @mtd: MTD device structure
573 * @buf: buffer to store date
574 * @len: number of bytes to read
576 static void fsmc_read_buf_dma(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
578 struct fsmc_nand_data
*host
= mtd_to_fsmc(mtd
);
580 dma_xfer(host
, buf
, len
, DMA_FROM_DEVICE
);
584 * fsmc_write_buf_dma - write buffer to chip
585 * @mtd: MTD device structure
587 * @len: number of bytes to write
589 static void fsmc_write_buf_dma(struct mtd_info
*mtd
, const uint8_t *buf
,
592 struct fsmc_nand_data
*host
= mtd_to_fsmc(mtd
);
594 dma_xfer(host
, (void *)buf
, len
, DMA_TO_DEVICE
);
598 * fsmc_read_page_hwecc
599 * @mtd: mtd info structure
600 * @chip: nand chip info structure
601 * @buf: buffer to store read data
602 * @oob_required: caller expects OOB data read to chip->oob_poi
603 * @page: page number to read
605 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
606 * performed in a strict sequence as follows:
607 * data(512 byte) -> ecc(13 byte)
608 * After this read, fsmc hardware generates and reports error data bits(up to a
611 static int fsmc_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
612 uint8_t *buf
, int oob_required
, int page
)
614 int i
, j
, s
, stat
, eccsize
= chip
->ecc
.size
;
615 int eccbytes
= chip
->ecc
.bytes
;
616 int eccsteps
= chip
->ecc
.steps
;
618 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
619 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
620 int off
, len
, group
= 0;
622 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
623 * end up reading 14 bytes (7 words) from oob. The local array is
624 * to maintain word alignment
627 uint8_t *oob
= (uint8_t *)&ecc_oob
[0];
628 unsigned int max_bitflips
= 0;
630 for (i
= 0, s
= 0; s
< eccsteps
; s
++, i
+= eccbytes
, p
+= eccsize
) {
631 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, s
* eccsize
, page
);
632 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
633 chip
->read_buf(mtd
, p
, eccsize
);
635 for (j
= 0; j
< eccbytes
;) {
636 struct mtd_oob_region oobregion
;
639 ret
= mtd_ooblayout_ecc(mtd
, group
++, &oobregion
);
643 off
= oobregion
.offset
;
644 len
= oobregion
.length
;
647 * length is intentionally kept a higher multiple of 2
648 * to read at least 13 bytes even in case of 16 bit NAND
651 if (chip
->options
& NAND_BUSWIDTH_16
)
652 len
= roundup(len
, 2);
654 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, off
, page
);
655 chip
->read_buf(mtd
, oob
+ j
, len
);
659 memcpy(&ecc_code
[i
], oob
, chip
->ecc
.bytes
);
660 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
662 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
664 mtd
->ecc_stats
.failed
++;
666 mtd
->ecc_stats
.corrected
+= stat
;
667 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
675 * fsmc_bch8_correct_data
676 * @mtd: mtd info structure
677 * @dat: buffer of read data
678 * @read_ecc: ecc read from device spare area
679 * @calc_ecc: ecc calculated from read data
681 * calc_ecc is a 104 bit information containing maximum of 8 error
682 * offset informations of 13 bits each in 512 bytes of read data.
684 static int fsmc_bch8_correct_data(struct mtd_info
*mtd
, uint8_t *dat
,
685 uint8_t *read_ecc
, uint8_t *calc_ecc
)
687 struct nand_chip
*chip
= mtd_to_nand(mtd
);
688 struct fsmc_nand_data
*host
= mtd_to_fsmc(mtd
);
689 void __iomem
*regs
= host
->regs_va
;
690 unsigned int bank
= host
->bank
;
693 uint32_t ecc1
, ecc2
, ecc3
, ecc4
;
695 num_err
= (readl_relaxed(FSMC_NAND_REG(regs
, bank
, STS
)) >> 10) & 0xF;
697 /* no bit flipping */
698 if (likely(num_err
== 0))
701 /* too many errors */
702 if (unlikely(num_err
> 8)) {
704 * This is a temporary erase check. A newly erased page read
705 * would result in an ecc error because the oob data is also
706 * erased to FF and the calculated ecc for an FF data is not
708 * This is a workaround to skip performing correction in case
712 * For every page, each bit written as 0 is counted until these
713 * number of bits are greater than 8 (the maximum correction
714 * capability of FSMC for each 512 + 13 bytes)
717 int bits_ecc
= count_written_bits(read_ecc
, chip
->ecc
.bytes
, 8);
718 int bits_data
= count_written_bits(dat
, chip
->ecc
.size
, 8);
720 if ((bits_ecc
+ bits_data
) <= 8) {
722 memset(dat
, 0xff, chip
->ecc
.size
);
730 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
731 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
733 * calc_ecc is a 104 bit information containing maximum of 8 error
734 * offset informations of 13 bits each. calc_ecc is copied into a
735 * uint64_t array and error offset indexes are populated in err_idx
738 ecc1
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, ECC1
));
739 ecc2
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, ECC2
));
740 ecc3
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, ECC3
));
741 ecc4
= readl_relaxed(FSMC_NAND_REG(regs
, bank
, STS
));
743 err_idx
[0] = (ecc1
>> 0) & 0x1FFF;
744 err_idx
[1] = (ecc1
>> 13) & 0x1FFF;
745 err_idx
[2] = (((ecc2
>> 0) & 0x7F) << 6) | ((ecc1
>> 26) & 0x3F);
746 err_idx
[3] = (ecc2
>> 7) & 0x1FFF;
747 err_idx
[4] = (((ecc3
>> 0) & 0x1) << 12) | ((ecc2
>> 20) & 0xFFF);
748 err_idx
[5] = (ecc3
>> 1) & 0x1FFF;
749 err_idx
[6] = (ecc3
>> 14) & 0x1FFF;
750 err_idx
[7] = (((ecc4
>> 16) & 0xFF) << 5) | ((ecc3
>> 27) & 0x1F);
754 change_bit(0, (unsigned long *)&err_idx
[i
]);
755 change_bit(1, (unsigned long *)&err_idx
[i
]);
757 if (err_idx
[i
] < chip
->ecc
.size
* 8) {
758 change_bit(err_idx
[i
], (unsigned long *)dat
);
765 static bool filter(struct dma_chan
*chan
, void *slave
)
767 chan
->private = slave
;
771 static int fsmc_nand_probe_config_dt(struct platform_device
*pdev
,
772 struct fsmc_nand_data
*host
,
773 struct nand_chip
*nand
)
775 struct device_node
*np
= pdev
->dev
.of_node
;
781 if (!of_property_read_u32(np
, "bank-width", &val
)) {
783 nand
->options
|= NAND_BUSWIDTH_16
;
784 } else if (val
!= 1) {
785 dev_err(&pdev
->dev
, "invalid bank-width %u\n", val
);
790 if (of_get_property(np
, "nand-skip-bbtscan", NULL
))
791 nand
->options
|= NAND_SKIP_BBTSCAN
;
793 host
->dev_timings
= devm_kzalloc(&pdev
->dev
,
794 sizeof(*host
->dev_timings
), GFP_KERNEL
);
795 if (!host
->dev_timings
)
797 ret
= of_property_read_u8_array(np
, "timings", (u8
*)host
->dev_timings
,
798 sizeof(*host
->dev_timings
));
800 dev_info(&pdev
->dev
, "No timings in dts specified, using default timings!\n");
801 host
->dev_timings
= NULL
;
804 /* Set default NAND bank to 0 */
806 if (!of_property_read_u32(np
, "bank", &val
)) {
808 dev_err(&pdev
->dev
, "invalid bank %u\n", val
);
817 * fsmc_nand_probe - Probe function
818 * @pdev: platform device structure
820 static int __init
fsmc_nand_probe(struct platform_device
*pdev
)
822 struct fsmc_nand_data
*host
;
823 struct mtd_info
*mtd
;
824 struct nand_chip
*nand
;
825 struct resource
*res
;
831 /* Allocate memory for the device structure (and zero it) */
832 host
= devm_kzalloc(&pdev
->dev
, sizeof(*host
), GFP_KERNEL
);
838 ret
= fsmc_nand_probe_config_dt(pdev
, host
, nand
);
842 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "nand_data");
843 host
->data_va
= devm_ioremap_resource(&pdev
->dev
, res
);
844 if (IS_ERR(host
->data_va
))
845 return PTR_ERR(host
->data_va
);
847 host
->data_pa
= (dma_addr_t
)res
->start
;
849 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "nand_addr");
850 host
->addr_va
= devm_ioremap_resource(&pdev
->dev
, res
);
851 if (IS_ERR(host
->addr_va
))
852 return PTR_ERR(host
->addr_va
);
854 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "nand_cmd");
855 host
->cmd_va
= devm_ioremap_resource(&pdev
->dev
, res
);
856 if (IS_ERR(host
->cmd_va
))
857 return PTR_ERR(host
->cmd_va
);
859 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "fsmc_regs");
860 host
->regs_va
= devm_ioremap_resource(&pdev
->dev
, res
);
861 if (IS_ERR(host
->regs_va
))
862 return PTR_ERR(host
->regs_va
);
864 host
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
865 if (IS_ERR(host
->clk
)) {
866 dev_err(&pdev
->dev
, "failed to fetch block clock\n");
867 return PTR_ERR(host
->clk
);
870 ret
= clk_prepare_enable(host
->clk
);
875 * This device ID is actually a common AMBA ID as used on the
876 * AMBA PrimeCell bus. However it is not a PrimeCell.
878 for (pid
= 0, i
= 0; i
< 4; i
++)
879 pid
|= (readl(host
->regs_va
+ resource_size(res
) - 0x20 + 4 * i
) & 255) << (i
* 8);
881 dev_info(&pdev
->dev
, "FSMC device partno %03x, manufacturer %02x, "
882 "revision %02x, config %02x\n",
883 AMBA_PART_BITS(pid
), AMBA_MANF_BITS(pid
),
884 AMBA_REV_BITS(pid
), AMBA_CONFIG_BITS(pid
));
886 host
->dev
= &pdev
->dev
;
888 if (host
->mode
== USE_DMA_ACCESS
)
889 init_completion(&host
->dma_access_complete
);
891 /* Link all private pointers */
892 mtd
= nand_to_mtd(&host
->nand
);
893 nand_set_controller_data(nand
, host
);
894 nand_set_flash_node(nand
, pdev
->dev
.of_node
);
896 mtd
->dev
.parent
= &pdev
->dev
;
897 nand
->IO_ADDR_R
= host
->data_va
;
898 nand
->IO_ADDR_W
= host
->data_va
;
899 nand
->cmd_ctrl
= fsmc_cmd_ctrl
;
900 nand
->chip_delay
= 30;
903 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
904 * can overwrite this value if the DT provides a different value.
906 nand
->ecc
.mode
= NAND_ECC_HW
;
907 nand
->ecc
.hwctl
= fsmc_enable_hwecc
;
908 nand
->ecc
.size
= 512;
909 nand
->badblockbits
= 7;
911 switch (host
->mode
) {
914 dma_cap_set(DMA_MEMCPY
, mask
);
915 host
->read_dma_chan
= dma_request_channel(mask
, filter
, NULL
);
916 if (!host
->read_dma_chan
) {
917 dev_err(&pdev
->dev
, "Unable to get read dma channel\n");
918 goto err_req_read_chnl
;
920 host
->write_dma_chan
= dma_request_channel(mask
, filter
, NULL
);
921 if (!host
->write_dma_chan
) {
922 dev_err(&pdev
->dev
, "Unable to get write dma channel\n");
923 goto err_req_write_chnl
;
925 nand
->read_buf
= fsmc_read_buf_dma
;
926 nand
->write_buf
= fsmc_write_buf_dma
;
930 case USE_WORD_ACCESS
:
931 nand
->read_buf
= fsmc_read_buf
;
932 nand
->write_buf
= fsmc_write_buf
;
936 fsmc_nand_setup(host
->regs_va
, host
->bank
,
937 nand
->options
& NAND_BUSWIDTH_16
,
940 if (AMBA_REV_BITS(host
->pid
) >= 8) {
941 nand
->ecc
.read_page
= fsmc_read_page_hwecc
;
942 nand
->ecc
.calculate
= fsmc_read_hwecc_ecc4
;
943 nand
->ecc
.correct
= fsmc_bch8_correct_data
;
944 nand
->ecc
.bytes
= 13;
945 nand
->ecc
.strength
= 8;
949 * Scan to find existence of the device
951 ret
= nand_scan_ident(mtd
, 1, NULL
);
953 dev_err(&pdev
->dev
, "No NAND Device found!\n");
957 if (AMBA_REV_BITS(host
->pid
) >= 8) {
958 switch (mtd
->oobsize
) {
966 dev_warn(&pdev
->dev
, "No oob scheme defined for oobsize %d\n",
972 mtd_set_ooblayout(mtd
, &fsmc_ecc4_ooblayout_ops
);
974 switch (nand
->ecc
.mode
) {
976 dev_info(&pdev
->dev
, "Using 1-bit HW ECC scheme\n");
977 nand
->ecc
.calculate
= fsmc_read_hwecc_ecc1
;
978 nand
->ecc
.correct
= nand_correct_data
;
980 nand
->ecc
.strength
= 1;
984 if (nand
->ecc
.algo
== NAND_ECC_BCH
) {
985 dev_info(&pdev
->dev
, "Using 4-bit SW BCH ECC scheme\n");
990 dev_err(&pdev
->dev
, "Unsupported ECC mode!\n");
995 * Don't set layout for BCH4 SW ECC. This will be
996 * generated later in nand_bch_init() later.
998 if (nand
->ecc
.mode
== NAND_ECC_HW
) {
999 switch (mtd
->oobsize
) {
1003 mtd_set_ooblayout(mtd
,
1004 &fsmc_ecc1_ooblayout_ops
);
1007 dev_warn(&pdev
->dev
,
1008 "No oob scheme defined for oobsize %d\n",
1016 /* Second stage of scan to fill MTD data-structures */
1017 ret
= nand_scan_tail(mtd
);
1022 ret
= mtd_device_register(mtd
, NULL
, 0);
1026 platform_set_drvdata(pdev
, host
);
1027 dev_info(&pdev
->dev
, "FSMC NAND driver registration successful\n");
1032 if (host
->mode
== USE_DMA_ACCESS
)
1033 dma_release_channel(host
->write_dma_chan
);
1035 if (host
->mode
== USE_DMA_ACCESS
)
1036 dma_release_channel(host
->read_dma_chan
);
1038 clk_disable_unprepare(host
->clk
);
1045 static int fsmc_nand_remove(struct platform_device
*pdev
)
1047 struct fsmc_nand_data
*host
= platform_get_drvdata(pdev
);
1050 nand_release(nand_to_mtd(&host
->nand
));
1052 if (host
->mode
== USE_DMA_ACCESS
) {
1053 dma_release_channel(host
->write_dma_chan
);
1054 dma_release_channel(host
->read_dma_chan
);
1056 clk_disable_unprepare(host
->clk
);
1062 #ifdef CONFIG_PM_SLEEP
1063 static int fsmc_nand_suspend(struct device
*dev
)
1065 struct fsmc_nand_data
*host
= dev_get_drvdata(dev
);
1067 clk_disable_unprepare(host
->clk
);
1071 static int fsmc_nand_resume(struct device
*dev
)
1073 struct fsmc_nand_data
*host
= dev_get_drvdata(dev
);
1075 clk_prepare_enable(host
->clk
);
1076 fsmc_nand_setup(host
->regs_va
, host
->bank
,
1077 host
->nand
.options
& NAND_BUSWIDTH_16
,
1084 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops
, fsmc_nand_suspend
, fsmc_nand_resume
);
1086 static const struct of_device_id fsmc_nand_id_table
[] = {
1087 { .compatible
= "st,spear600-fsmc-nand" },
1088 { .compatible
= "stericsson,fsmc-nand" },
1091 MODULE_DEVICE_TABLE(of
, fsmc_nand_id_table
);
1093 static struct platform_driver fsmc_nand_driver
= {
1094 .remove
= fsmc_nand_remove
,
1096 .name
= "fsmc-nand",
1097 .of_match_table
= fsmc_nand_id_table
,
1098 .pm
= &fsmc_nand_pm_ops
,
1102 module_platform_driver_probe(fsmc_nand_driver
, fsmc_nand_probe
);
1104 MODULE_LICENSE("GPL");
1105 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1106 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");