2 * Freescale GPMI NAND Flash Driver
4 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
5 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include <linux/mtd/gpmi-nand.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
26 #include "gpmi-nand.h"
27 #include "gpmi-regs.h"
30 struct timing_threshod timing_default_threshold
= {
31 .max_data_setup_cycles
= (BM_GPMI_TIMING0_DATA_SETUP
>>
32 BP_GPMI_TIMING0_DATA_SETUP
),
33 .internal_data_setup_in_ns
= 0,
34 .max_sample_delay_factor
= (BM_GPMI_CTRL1_RDN_DELAY
>>
35 BP_GPMI_CTRL1_RDN_DELAY
),
36 .max_dll_clock_period_in_ns
= 32,
37 .max_dll_delay_in_ns
= 16,
41 * Clear the bit and poll it cleared. This is usually called with
42 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
45 static int clear_poll_bit(void __iomem
*addr
, u32 mask
)
50 __mxs_clrl(mask
, addr
);
53 * SFTRST needs 3 GPMI clocks to settle, the reference manual
54 * recommends to wait 1us.
58 /* poll the bit becoming clear */
59 while ((readl(addr
) & mask
) && --timeout
)
65 #define MODULE_CLKGATE (1 << 30)
66 #define MODULE_SFTRST (1 << 31)
68 * The current mxs_reset_block() will do two things:
69 * [1] enable the module.
70 * [2] reset the module.
72 * In most of the cases, it's ok. But there is a hardware bug in the BCH block.
73 * If you try to soft reset the BCH block, it becomes unusable until
74 * the next hard reset. This case occurs in the NAND boot mode. When the board
75 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
76 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
77 * You will see a DMA timeout in this case.
79 * To avoid this bug, just add a new parameter `just_enable` for
80 * the mxs_reset_block(), and rewrite it here.
82 int gpmi_reset_block(void __iomem
*reset_addr
, bool just_enable
)
87 /* clear and poll SFTRST */
88 ret
= clear_poll_bit(reset_addr
, MODULE_SFTRST
);
93 __mxs_clrl(MODULE_CLKGATE
, reset_addr
);
96 /* set SFTRST to reset the block */
97 __mxs_setl(MODULE_SFTRST
, reset_addr
);
100 /* poll CLKGATE becoming set */
101 while ((!(readl(reset_addr
) & MODULE_CLKGATE
)) && --timeout
)
103 if (unlikely(!timeout
))
107 /* clear and poll SFTRST */
108 ret
= clear_poll_bit(reset_addr
, MODULE_SFTRST
);
112 /* clear and poll CLKGATE */
113 ret
= clear_poll_bit(reset_addr
, MODULE_CLKGATE
);
120 pr_err("%s(%p): module reset timeout\n", __func__
, reset_addr
);
124 int gpmi_init(struct gpmi_nand_data
*this)
126 struct resources
*r
= &this->resources
;
129 ret
= clk_prepare_enable(r
->clock
);
132 ret
= gpmi_reset_block(r
->gpmi_regs
, false);
136 /* Choose NAND mode. */
137 writel(BM_GPMI_CTRL1_GPMI_MODE
, r
->gpmi_regs
+ HW_GPMI_CTRL1_CLR
);
139 /* Set the IRQ polarity. */
140 writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY
,
141 r
->gpmi_regs
+ HW_GPMI_CTRL1_SET
);
143 /* Disable Write-Protection. */
144 writel(BM_GPMI_CTRL1_DEV_RESET
, r
->gpmi_regs
+ HW_GPMI_CTRL1_SET
);
146 /* Select BCH ECC. */
147 writel(BM_GPMI_CTRL1_BCH_MODE
, r
->gpmi_regs
+ HW_GPMI_CTRL1_SET
);
149 clk_disable_unprepare(r
->clock
);
155 /* This function is very useful. It is called only when the bug occur. */
156 void gpmi_dump_info(struct gpmi_nand_data
*this)
158 struct resources
*r
= &this->resources
;
159 struct bch_geometry
*geo
= &this->bch_geometry
;
163 pr_err("Show GPMI registers :\n");
164 for (i
= 0; i
<= HW_GPMI_DEBUG
/ 0x10 + 1; i
++) {
165 reg
= readl(r
->gpmi_regs
+ i
* 0x10);
166 pr_err("offset 0x%.3x : 0x%.8x\n", i
* 0x10, reg
);
169 /* start to print out the BCH info */
170 pr_err("BCH Geometry :\n");
171 pr_err("GF length : %u\n", geo
->gf_len
);
172 pr_err("ECC Strength : %u\n", geo
->ecc_strength
);
173 pr_err("Page Size in Bytes : %u\n", geo
->page_size
);
174 pr_err("Metadata Size in Bytes : %u\n", geo
->metadata_size
);
175 pr_err("ECC Chunk Size in Bytes: %u\n", geo
->ecc_chunk_size
);
176 pr_err("ECC Chunk Count : %u\n", geo
->ecc_chunk_count
);
177 pr_err("Payload Size in Bytes : %u\n", geo
->payload_size
);
178 pr_err("Auxiliary Size in Bytes: %u\n", geo
->auxiliary_size
);
179 pr_err("Auxiliary Status Offset: %u\n", geo
->auxiliary_status_offset
);
180 pr_err("Block Mark Byte Offset : %u\n", geo
->block_mark_byte_offset
);
181 pr_err("Block Mark Bit Offset : %u\n", geo
->block_mark_bit_offset
);
184 /* Configures the geometry for BCH. */
185 int bch_set_geometry(struct gpmi_nand_data
*this)
187 struct resources
*r
= &this->resources
;
188 struct bch_geometry
*bch_geo
= &this->bch_geometry
;
189 unsigned int block_count
;
190 unsigned int block_size
;
191 unsigned int metadata_size
;
192 unsigned int ecc_strength
;
193 unsigned int page_size
;
196 if (common_nfc_set_geometry(this))
199 block_count
= bch_geo
->ecc_chunk_count
- 1;
200 block_size
= bch_geo
->ecc_chunk_size
;
201 metadata_size
= bch_geo
->metadata_size
;
202 ecc_strength
= bch_geo
->ecc_strength
>> 1;
203 page_size
= bch_geo
->page_size
;
205 ret
= clk_prepare_enable(r
->clock
);
209 ret
= gpmi_reset_block(r
->bch_regs
, true);
213 /* Configure layout 0. */
214 writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count
)
215 | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size
)
216 | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength
)
217 | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size
),
218 r
->bch_regs
+ HW_BCH_FLASH0LAYOUT0
);
220 writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size
)
221 | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength
)
222 | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size
),
223 r
->bch_regs
+ HW_BCH_FLASH0LAYOUT1
);
225 /* Set *all* chip selects to use layout 0. */
226 writel(0, r
->bch_regs
+ HW_BCH_LAYOUTSELECT
);
228 /* Enable interrupts. */
229 writel(BM_BCH_CTRL_COMPLETE_IRQ_EN
,
230 r
->bch_regs
+ HW_BCH_CTRL_SET
);
232 clk_disable_unprepare(r
->clock
);
238 /* Converts time in nanoseconds to cycles. */
239 static unsigned int ns_to_cycles(unsigned int time
,
240 unsigned int period
, unsigned int min
)
244 k
= (time
+ period
- 1) / period
;
248 /* Apply timing to current hardware conditions. */
249 static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data
*this,
250 struct gpmi_nfc_hardware_timing
*hw
)
252 struct gpmi_nand_platform_data
*pdata
= this->pdata
;
253 struct timing_threshod
*nfc
= &timing_default_threshold
;
254 struct nand_chip
*nand
= &this->nand
;
255 struct nand_timing target
= this->timing
;
256 bool improved_timing_is_available
;
257 unsigned long clock_frequency_in_hz
;
258 unsigned int clock_period_in_ns
;
259 bool dll_use_half_periods
;
260 unsigned int dll_delay_shift
;
261 unsigned int max_sample_delay_in_ns
;
262 unsigned int address_setup_in_cycles
;
263 unsigned int data_setup_in_ns
;
264 unsigned int data_setup_in_cycles
;
265 unsigned int data_hold_in_cycles
;
266 int ideal_sample_delay_in_ns
;
267 unsigned int sample_delay_factor
;
269 unsigned int min_prop_delay_in_ns
= pdata
->min_prop_delay_in_ns
;
270 unsigned int max_prop_delay_in_ns
= pdata
->max_prop_delay_in_ns
;
273 * If there are multiple chips, we need to relax the timings to allow
274 * for signal distortion due to higher capacitance.
276 if (nand
->numchips
> 2) {
277 target
.data_setup_in_ns
+= 10;
278 target
.data_hold_in_ns
+= 10;
279 target
.address_setup_in_ns
+= 10;
280 } else if (nand
->numchips
> 1) {
281 target
.data_setup_in_ns
+= 5;
282 target
.data_hold_in_ns
+= 5;
283 target
.address_setup_in_ns
+= 5;
286 /* Check if improved timing information is available. */
287 improved_timing_is_available
=
288 (target
.tREA_in_ns
>= 0) &&
289 (target
.tRLOH_in_ns
>= 0) &&
290 (target
.tRHOH_in_ns
>= 0) ;
292 /* Inspect the clock. */
293 clock_frequency_in_hz
= nfc
->clock_frequency_in_hz
;
294 clock_period_in_ns
= 1000000000 / clock_frequency_in_hz
;
297 * The NFC quantizes setup and hold parameters in terms of clock cycles.
298 * Here, we quantize the setup and hold timing parameters to the
299 * next-highest clock period to make sure we apply at least the
302 * For data setup and data hold, the hardware interprets a value of zero
303 * as the largest possible delay. This is not what's intended by a zero
304 * in the input parameter, so we impose a minimum of one cycle.
306 data_setup_in_cycles
= ns_to_cycles(target
.data_setup_in_ns
,
307 clock_period_in_ns
, 1);
308 data_hold_in_cycles
= ns_to_cycles(target
.data_hold_in_ns
,
309 clock_period_in_ns
, 1);
310 address_setup_in_cycles
= ns_to_cycles(target
.address_setup_in_ns
,
311 clock_period_in_ns
, 0);
314 * The clock's period affects the sample delay in a number of ways:
316 * (1) The NFC HAL tells us the maximum clock period the sample delay
317 * DLL can tolerate. If the clock period is greater than half that
318 * maximum, we must configure the DLL to be driven by half periods.
320 * (2) We need to convert from an ideal sample delay, in ns, to a
321 * "sample delay factor," which the NFC uses. This factor depends on
322 * whether we're driving the DLL with full or half periods.
323 * Paraphrasing the reference manual:
325 * AD = SDF x 0.125 x RP
329 * AD is the applied delay, in ns.
330 * SDF is the sample delay factor, which is dimensionless.
331 * RP is the reference period, in ns, which is a full clock period
332 * if the DLL is being driven by full periods, or half that if
333 * the DLL is being driven by half periods.
335 * Let's re-arrange this in a way that's more useful to us:
341 * The reference period is either the clock period or half that, so this
345 * SDF = AD x ----- = --------
350 * f is 1 or 1/2, depending on how we're driving the DLL.
351 * P is the clock period.
352 * DDF is the DLL Delay Factor, a dimensionless value that
353 * incorporates all the constants in the conversion.
355 * DDF will be either 8 or 16, both of which are powers of two. We can
356 * reduce the cost of this conversion by using bit shifts instead of
357 * multiplication or division. Thus:
365 * AD = (SDF >> DDS) x P
369 * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
371 if (clock_period_in_ns
> (nfc
->max_dll_clock_period_in_ns
>> 1)) {
372 dll_use_half_periods
= true;
373 dll_delay_shift
= 3 + 1;
375 dll_use_half_periods
= false;
380 * Compute the maximum sample delay the NFC allows, under current
381 * conditions. If the clock is running too slowly, no sample delay is
384 if (clock_period_in_ns
> nfc
->max_dll_clock_period_in_ns
)
385 max_sample_delay_in_ns
= 0;
388 * Compute the delay implied by the largest sample delay factor
391 max_sample_delay_in_ns
=
392 (nfc
->max_sample_delay_factor
* clock_period_in_ns
) >>
396 * Check if the implied sample delay larger than the NFC
399 if (max_sample_delay_in_ns
> nfc
->max_dll_delay_in_ns
)
400 max_sample_delay_in_ns
= nfc
->max_dll_delay_in_ns
;
404 * Check if improved timing information is available. If not, we have to
405 * use a less-sophisticated algorithm.
407 if (!improved_timing_is_available
) {
409 * Fold the read setup time required by the NFC into the ideal
412 ideal_sample_delay_in_ns
= target
.gpmi_sample_delay_in_ns
+
413 nfc
->internal_data_setup_in_ns
;
416 * The ideal sample delay may be greater than the maximum
417 * allowed by the NFC. If so, we can trade off sample delay time
418 * for more data setup time.
420 * In each iteration of the following loop, we add a cycle to
421 * the data setup time and subtract a corresponding amount from
422 * the sample delay until we've satisified the constraints or
423 * can't do any better.
425 while ((ideal_sample_delay_in_ns
> max_sample_delay_in_ns
) &&
426 (data_setup_in_cycles
< nfc
->max_data_setup_cycles
)) {
428 data_setup_in_cycles
++;
429 ideal_sample_delay_in_ns
-= clock_period_in_ns
;
431 if (ideal_sample_delay_in_ns
< 0)
432 ideal_sample_delay_in_ns
= 0;
437 * Compute the sample delay factor that corresponds most closely
438 * to the ideal sample delay. If the result is too large for the
439 * NFC, use the maximum value.
441 * Notice that we use the ns_to_cycles function to compute the
442 * sample delay factor. We do this because the form of the
443 * computation is the same as that for calculating cycles.
445 sample_delay_factor
=
447 ideal_sample_delay_in_ns
<< dll_delay_shift
,
448 clock_period_in_ns
, 0);
450 if (sample_delay_factor
> nfc
->max_sample_delay_factor
)
451 sample_delay_factor
= nfc
->max_sample_delay_factor
;
453 /* Skip to the part where we return our results. */
458 * If control arrives here, we have more detailed timing information,
459 * so we can use a better algorithm.
463 * Fold the read setup time required by the NFC into the maximum
466 max_prop_delay_in_ns
+= nfc
->internal_data_setup_in_ns
;
469 * Earlier, we computed the number of clock cycles required to satisfy
470 * the data setup time. Now, we need to know the actual nanoseconds.
472 data_setup_in_ns
= clock_period_in_ns
* data_setup_in_cycles
;
475 * Compute tEYE, the width of the data eye when reading from the NAND
476 * Flash. The eye width is fundamentally determined by the data setup
477 * time, perturbed by propagation delays and some characteristics of the
480 * start of the eye = max_prop_delay + tREA
481 * end of the eye = min_prop_delay + tRHOH + data_setup
483 tEYE
= (int)min_prop_delay_in_ns
+ (int)target
.tRHOH_in_ns
+
484 (int)data_setup_in_ns
;
486 tEYE
-= (int)max_prop_delay_in_ns
+ (int)target
.tREA_in_ns
;
489 * The eye must be open. If it's not, we can try to open it by
490 * increasing its main forcer, the data setup time.
492 * In each iteration of the following loop, we increase the data setup
493 * time by a single clock cycle. We do this until either the eye is
494 * open or we run into NFC limits.
496 while ((tEYE
<= 0) &&
497 (data_setup_in_cycles
< nfc
->max_data_setup_cycles
)) {
498 /* Give a cycle to data setup. */
499 data_setup_in_cycles
++;
500 /* Synchronize the data setup time with the cycles. */
501 data_setup_in_ns
+= clock_period_in_ns
;
502 /* Adjust tEYE accordingly. */
503 tEYE
+= clock_period_in_ns
;
507 * When control arrives here, the eye is open. The ideal time to sample
508 * the data is in the center of the eye:
510 * end of the eye + start of the eye
511 * --------------------------------- - data_setup
514 * After some algebra, this simplifies to the code immediately below.
516 ideal_sample_delay_in_ns
=
517 ((int)max_prop_delay_in_ns
+
518 (int)target
.tREA_in_ns
+
519 (int)min_prop_delay_in_ns
+
520 (int)target
.tRHOH_in_ns
-
521 (int)data_setup_in_ns
) >> 1;
524 * The following figure illustrates some aspects of a NAND Flash read:
527 * __ _____________________________________
528 * RDN \_________________/
531 * /-----------------\
532 * Read Data ----------------------------< >---------
533 * \-----------------/
536 * |<--Data Setup -->|<--Delay Time -->| |
539 * | |<-- Quantized Delay Time -->|
543 * We have some issues we must now address:
545 * (1) The *ideal* sample delay time must not be negative. If it is, we
548 * (2) The *ideal* sample delay time must not be greater than that
549 * allowed by the NFC. If it is, we can increase the data setup
550 * time, which will reduce the delay between the end of the data
551 * setup and the center of the eye. It will also make the eye
552 * larger, which might help with the next issue...
554 * (3) The *quantized* sample delay time must not fall either before the
555 * eye opens or after it closes (the latter is the problem
556 * illustrated in the above figure).
559 /* Jam a negative ideal sample delay to zero. */
560 if (ideal_sample_delay_in_ns
< 0)
561 ideal_sample_delay_in_ns
= 0;
564 * Extend the data setup as needed to reduce the ideal sample delay
565 * below the maximum permitted by the NFC.
567 while ((ideal_sample_delay_in_ns
> max_sample_delay_in_ns
) &&
568 (data_setup_in_cycles
< nfc
->max_data_setup_cycles
)) {
570 /* Give a cycle to data setup. */
571 data_setup_in_cycles
++;
572 /* Synchronize the data setup time with the cycles. */
573 data_setup_in_ns
+= clock_period_in_ns
;
574 /* Adjust tEYE accordingly. */
575 tEYE
+= clock_period_in_ns
;
578 * Decrease the ideal sample delay by one half cycle, to keep it
579 * in the middle of the eye.
581 ideal_sample_delay_in_ns
-= (clock_period_in_ns
>> 1);
583 /* Jam a negative ideal sample delay to zero. */
584 if (ideal_sample_delay_in_ns
< 0)
585 ideal_sample_delay_in_ns
= 0;
589 * Compute the sample delay factor that corresponds to the ideal sample
590 * delay. If the result is too large, then use the maximum allowed
593 * Notice that we use the ns_to_cycles function to compute the sample
594 * delay factor. We do this because the form of the computation is the
595 * same as that for calculating cycles.
597 sample_delay_factor
=
598 ns_to_cycles(ideal_sample_delay_in_ns
<< dll_delay_shift
,
599 clock_period_in_ns
, 0);
601 if (sample_delay_factor
> nfc
->max_sample_delay_factor
)
602 sample_delay_factor
= nfc
->max_sample_delay_factor
;
605 * These macros conveniently encapsulate a computation we'll use to
606 * continuously evaluate whether or not the data sample delay is inside
609 #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
611 #define QUANTIZED_DELAY \
612 ((int) ((sample_delay_factor * clock_period_in_ns) >> \
615 #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
617 #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
620 * While the quantized sample time falls outside the eye, reduce the
621 * sample delay or extend the data setup to move the sampling point back
622 * toward the eye. Do not allow the number of data setup cycles to
623 * exceed the maximum allowed by the NFC.
625 while (SAMPLE_IS_NOT_WITHIN_THE_EYE
&&
626 (data_setup_in_cycles
< nfc
->max_data_setup_cycles
)) {
628 * If control arrives here, the quantized sample delay falls
629 * outside the eye. Check if it's before the eye opens, or after
632 if (QUANTIZED_DELAY
> IDEAL_DELAY
) {
634 * If control arrives here, the quantized sample delay
635 * falls after the eye closes. Decrease the quantized
636 * delay time and then go back to re-evaluate.
638 if (sample_delay_factor
!= 0)
639 sample_delay_factor
--;
644 * If control arrives here, the quantized sample delay falls
645 * before the eye opens. Shift the sample point by increasing
646 * data setup time. This will also make the eye larger.
649 /* Give a cycle to data setup. */
650 data_setup_in_cycles
++;
651 /* Synchronize the data setup time with the cycles. */
652 data_setup_in_ns
+= clock_period_in_ns
;
653 /* Adjust tEYE accordingly. */
654 tEYE
+= clock_period_in_ns
;
657 * Decrease the ideal sample delay by one half cycle, to keep it
658 * in the middle of the eye.
660 ideal_sample_delay_in_ns
-= (clock_period_in_ns
>> 1);
662 /* ...and one less period for the delay time. */
663 ideal_sample_delay_in_ns
-= clock_period_in_ns
;
665 /* Jam a negative ideal sample delay to zero. */
666 if (ideal_sample_delay_in_ns
< 0)
667 ideal_sample_delay_in_ns
= 0;
670 * We have a new ideal sample delay, so re-compute the quantized
673 sample_delay_factor
=
675 ideal_sample_delay_in_ns
<< dll_delay_shift
,
676 clock_period_in_ns
, 0);
678 if (sample_delay_factor
> nfc
->max_sample_delay_factor
)
679 sample_delay_factor
= nfc
->max_sample_delay_factor
;
682 /* Control arrives here when we're ready to return our results. */
684 hw
->data_setup_in_cycles
= data_setup_in_cycles
;
685 hw
->data_hold_in_cycles
= data_hold_in_cycles
;
686 hw
->address_setup_in_cycles
= address_setup_in_cycles
;
687 hw
->use_half_periods
= dll_use_half_periods
;
688 hw
->sample_delay_factor
= sample_delay_factor
;
690 /* Return success. */
695 void gpmi_begin(struct gpmi_nand_data
*this)
697 struct resources
*r
= &this->resources
;
698 struct timing_threshod
*nfc
= &timing_default_threshold
;
699 unsigned char *gpmi_regs
= r
->gpmi_regs
;
700 unsigned int clock_period_in_ns
;
702 unsigned int dll_wait_time_in_us
;
703 struct gpmi_nfc_hardware_timing hw
;
706 /* Enable the clock. */
707 ret
= clk_prepare_enable(r
->clock
);
709 pr_err("We failed in enable the clk\n");
713 /* set ready/busy timeout */
714 writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT
,
715 gpmi_regs
+ HW_GPMI_TIMING1
);
717 /* Get the timing information we need. */
718 nfc
->clock_frequency_in_hz
= clk_get_rate(r
->clock
);
719 clock_period_in_ns
= 1000000000 / nfc
->clock_frequency_in_hz
;
721 gpmi_nfc_compute_hardware_timing(this, &hw
);
723 /* Set up all the simple timing parameters. */
724 reg
= BF_GPMI_TIMING0_ADDRESS_SETUP(hw
.address_setup_in_cycles
) |
725 BF_GPMI_TIMING0_DATA_HOLD(hw
.data_hold_in_cycles
) |
726 BF_GPMI_TIMING0_DATA_SETUP(hw
.data_setup_in_cycles
) ;
728 writel(reg
, gpmi_regs
+ HW_GPMI_TIMING0
);
731 * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
733 writel(BM_GPMI_CTRL1_DLL_ENABLE
, gpmi_regs
+ HW_GPMI_CTRL1_CLR
);
735 /* Clear out the DLL control fields. */
736 writel(BM_GPMI_CTRL1_RDN_DELAY
, gpmi_regs
+ HW_GPMI_CTRL1_CLR
);
737 writel(BM_GPMI_CTRL1_HALF_PERIOD
, gpmi_regs
+ HW_GPMI_CTRL1_CLR
);
739 /* If no sample delay is called for, return immediately. */
740 if (!hw
.sample_delay_factor
)
743 /* Configure the HALF_PERIOD flag. */
744 if (hw
.use_half_periods
)
745 writel(BM_GPMI_CTRL1_HALF_PERIOD
,
746 gpmi_regs
+ HW_GPMI_CTRL1_SET
);
748 /* Set the delay factor. */
749 writel(BF_GPMI_CTRL1_RDN_DELAY(hw
.sample_delay_factor
),
750 gpmi_regs
+ HW_GPMI_CTRL1_SET
);
752 /* Enable the DLL. */
753 writel(BM_GPMI_CTRL1_DLL_ENABLE
, gpmi_regs
+ HW_GPMI_CTRL1_SET
);
756 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
757 * we can use the GPMI.
759 * Calculate the amount of time we need to wait, in microseconds.
761 dll_wait_time_in_us
= (clock_period_in_ns
* 64) / 1000;
763 if (!dll_wait_time_in_us
)
764 dll_wait_time_in_us
= 1;
766 /* Wait for the DLL to settle. */
767 udelay(dll_wait_time_in_us
);
773 void gpmi_end(struct gpmi_nand_data
*this)
775 struct resources
*r
= &this->resources
;
776 clk_disable_unprepare(r
->clock
);
779 /* Clears a BCH interrupt. */
780 void gpmi_clear_bch(struct gpmi_nand_data
*this)
782 struct resources
*r
= &this->resources
;
783 writel(BM_BCH_CTRL_COMPLETE_IRQ
, r
->bch_regs
+ HW_BCH_CTRL_CLR
);
786 /* Returns the Ready/Busy status of the given chip. */
787 int gpmi_is_ready(struct gpmi_nand_data
*this, unsigned chip
)
789 struct resources
*r
= &this->resources
;
793 if (GPMI_IS_MX23(this)) {
794 mask
= MX23_BM_GPMI_DEBUG_READY0
<< chip
;
795 reg
= readl(r
->gpmi_regs
+ HW_GPMI_DEBUG
);
796 } else if (GPMI_IS_MX28(this)) {
797 mask
= MX28_BF_GPMI_STAT_READY_BUSY(1 << chip
);
798 reg
= readl(r
->gpmi_regs
+ HW_GPMI_STAT
);
800 pr_err("unknow arch.\n");
804 static inline void set_dma_type(struct gpmi_nand_data
*this,
805 enum dma_ops_type type
)
807 this->last_dma_type
= this->dma_type
;
808 this->dma_type
= type
;
811 int gpmi_send_command(struct gpmi_nand_data
*this)
813 struct dma_chan
*channel
= get_dma_chan(this);
814 struct dma_async_tx_descriptor
*desc
;
815 struct scatterlist
*sgl
;
816 int chip
= this->current_chip
;
819 /* [1] send out the PIO words */
820 pio
[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE
)
821 | BM_GPMI_CTRL0_WORD_LENGTH
822 | BF_GPMI_CTRL0_CS(chip
, this)
823 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE
, this)
824 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE
)
825 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
826 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length
);
828 desc
= channel
->device
->device_prep_slave_sg(channel
,
829 (struct scatterlist
*)pio
,
830 ARRAY_SIZE(pio
), DMA_TRANS_NONE
, 0);
832 pr_err("step 1 error\n");
836 /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
837 sgl
= &this->cmd_sgl
;
839 sg_init_one(sgl
, this->cmd_buffer
, this->command_length
);
840 dma_map_sg(this->dev
, sgl
, 1, DMA_TO_DEVICE
);
841 desc
= channel
->device
->device_prep_slave_sg(channel
,
842 sgl
, 1, DMA_MEM_TO_DEV
, 1);
844 pr_err("step 2 error\n");
848 /* [3] submit the DMA */
849 set_dma_type(this, DMA_FOR_COMMAND
);
850 return start_dma_without_bch_irq(this, desc
);
853 int gpmi_send_data(struct gpmi_nand_data
*this)
855 struct dma_async_tx_descriptor
*desc
;
856 struct dma_chan
*channel
= get_dma_chan(this);
857 int chip
= this->current_chip
;
858 uint32_t command_mode
;
863 command_mode
= BV_GPMI_CTRL0_COMMAND_MODE__WRITE
;
864 address
= BV_GPMI_CTRL0_ADDRESS__NAND_DATA
;
866 pio
[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode
)
867 | BM_GPMI_CTRL0_WORD_LENGTH
868 | BF_GPMI_CTRL0_CS(chip
, this)
869 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE
, this)
870 | BF_GPMI_CTRL0_ADDRESS(address
)
871 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len
);
873 desc
= channel
->device
->device_prep_slave_sg(channel
,
874 (struct scatterlist
*)pio
,
875 ARRAY_SIZE(pio
), DMA_TRANS_NONE
, 0);
877 pr_err("step 1 error\n");
881 /* [2] send DMA request */
882 prepare_data_dma(this, DMA_TO_DEVICE
);
883 desc
= channel
->device
->device_prep_slave_sg(channel
, &this->data_sgl
,
884 1, DMA_MEM_TO_DEV
, 1);
886 pr_err("step 2 error\n");
889 /* [3] submit the DMA */
890 set_dma_type(this, DMA_FOR_WRITE_DATA
);
891 return start_dma_without_bch_irq(this, desc
);
894 int gpmi_read_data(struct gpmi_nand_data
*this)
896 struct dma_async_tx_descriptor
*desc
;
897 struct dma_chan
*channel
= get_dma_chan(this);
898 int chip
= this->current_chip
;
902 pio
[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ
)
903 | BM_GPMI_CTRL0_WORD_LENGTH
904 | BF_GPMI_CTRL0_CS(chip
, this)
905 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE
, this)
906 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA
)
907 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len
);
909 desc
= channel
->device
->device_prep_slave_sg(channel
,
910 (struct scatterlist
*)pio
,
911 ARRAY_SIZE(pio
), DMA_TRANS_NONE
, 0);
913 pr_err("step 1 error\n");
917 /* [2] : send DMA request */
918 prepare_data_dma(this, DMA_FROM_DEVICE
);
919 desc
= channel
->device
->device_prep_slave_sg(channel
, &this->data_sgl
,
920 1, DMA_DEV_TO_MEM
, 1);
922 pr_err("step 2 error\n");
926 /* [3] : submit the DMA */
927 set_dma_type(this, DMA_FOR_READ_DATA
);
928 return start_dma_without_bch_irq(this, desc
);
931 int gpmi_send_page(struct gpmi_nand_data
*this,
932 dma_addr_t payload
, dma_addr_t auxiliary
)
934 struct bch_geometry
*geo
= &this->bch_geometry
;
935 uint32_t command_mode
;
937 uint32_t ecc_command
;
938 uint32_t buffer_mask
;
939 struct dma_async_tx_descriptor
*desc
;
940 struct dma_chan
*channel
= get_dma_chan(this);
941 int chip
= this->current_chip
;
944 /* A DMA descriptor that does an ECC page read. */
945 command_mode
= BV_GPMI_CTRL0_COMMAND_MODE__WRITE
;
946 address
= BV_GPMI_CTRL0_ADDRESS__NAND_DATA
;
947 ecc_command
= BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE
;
948 buffer_mask
= BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
|
949 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY
;
951 pio
[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode
)
952 | BM_GPMI_CTRL0_WORD_LENGTH
953 | BF_GPMI_CTRL0_CS(chip
, this)
954 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE
, this)
955 | BF_GPMI_CTRL0_ADDRESS(address
)
956 | BF_GPMI_CTRL0_XFER_COUNT(0);
958 pio
[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
959 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command
)
960 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask
);
961 pio
[3] = geo
->page_size
;
965 desc
= channel
->device
->device_prep_slave_sg(channel
,
966 (struct scatterlist
*)pio
,
967 ARRAY_SIZE(pio
), DMA_TRANS_NONE
, 0);
969 pr_err("step 2 error\n");
972 set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE
);
973 return start_dma_with_bch_irq(this, desc
);
976 int gpmi_read_page(struct gpmi_nand_data
*this,
977 dma_addr_t payload
, dma_addr_t auxiliary
)
979 struct bch_geometry
*geo
= &this->bch_geometry
;
980 uint32_t command_mode
;
982 uint32_t ecc_command
;
983 uint32_t buffer_mask
;
984 struct dma_async_tx_descriptor
*desc
;
985 struct dma_chan
*channel
= get_dma_chan(this);
986 int chip
= this->current_chip
;
989 /* [1] Wait for the chip to report ready. */
990 command_mode
= BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY
;
991 address
= BV_GPMI_CTRL0_ADDRESS__NAND_DATA
;
993 pio
[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode
)
994 | BM_GPMI_CTRL0_WORD_LENGTH
995 | BF_GPMI_CTRL0_CS(chip
, this)
996 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE
, this)
997 | BF_GPMI_CTRL0_ADDRESS(address
)
998 | BF_GPMI_CTRL0_XFER_COUNT(0);
1000 desc
= channel
->device
->device_prep_slave_sg(channel
,
1001 (struct scatterlist
*)pio
, 2,
1004 pr_err("step 1 error\n");
1008 /* [2] Enable the BCH block and read. */
1009 command_mode
= BV_GPMI_CTRL0_COMMAND_MODE__READ
;
1010 address
= BV_GPMI_CTRL0_ADDRESS__NAND_DATA
;
1011 ecc_command
= BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE
;
1012 buffer_mask
= BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
1013 | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY
;
1015 pio
[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode
)
1016 | BM_GPMI_CTRL0_WORD_LENGTH
1017 | BF_GPMI_CTRL0_CS(chip
, this)
1018 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE
, this)
1019 | BF_GPMI_CTRL0_ADDRESS(address
)
1020 | BF_GPMI_CTRL0_XFER_COUNT(geo
->page_size
);
1023 pio
[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
1024 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command
)
1025 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask
);
1026 pio
[3] = geo
->page_size
;
1029 desc
= channel
->device
->device_prep_slave_sg(channel
,
1030 (struct scatterlist
*)pio
,
1031 ARRAY_SIZE(pio
), DMA_TRANS_NONE
, 1);
1033 pr_err("step 2 error\n");
1037 /* [3] Disable the BCH block */
1038 command_mode
= BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY
;
1039 address
= BV_GPMI_CTRL0_ADDRESS__NAND_DATA
;
1041 pio
[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode
)
1042 | BM_GPMI_CTRL0_WORD_LENGTH
1043 | BF_GPMI_CTRL0_CS(chip
, this)
1044 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE
, this)
1045 | BF_GPMI_CTRL0_ADDRESS(address
)
1046 | BF_GPMI_CTRL0_XFER_COUNT(geo
->page_size
);
1048 desc
= channel
->device
->device_prep_slave_sg(channel
,
1049 (struct scatterlist
*)pio
, 2,
1052 pr_err("step 3 error\n");
1056 /* [4] submit the DMA */
1057 set_dma_type(this, DMA_FOR_READ_ECC_PAGE
);
1058 return start_dma_with_bch_irq(this, desc
);