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[mirror_ubuntu-artful-kernel.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/of_mtd.h>
38
39 #include <asm/mach/flash.h>
40 #include <linux/platform_data/mtd-mxc_nand.h>
41
42 #define DRIVER_NAME "mxc_nand"
43
44 /* Addresses for NFC registers */
45 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
46 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
47 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
48 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
49 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
50 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
51 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
52 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
53 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
54 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
55 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
56 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
57 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
58 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
59 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
60 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
61 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
62 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
63 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
64 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
65 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
66 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67
68 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
69 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
70 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
71 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
72 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
73 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
74 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
75 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
76 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
77 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
78
79 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
80
81 /*
82 * Operation modes for the NFC. Valid for v1, v2 and v3
83 * type controllers.
84 */
85 #define NFC_CMD (1 << 0)
86 #define NFC_ADDR (1 << 1)
87 #define NFC_INPUT (1 << 2)
88 #define NFC_OUTPUT (1 << 3)
89 #define NFC_ID (1 << 4)
90 #define NFC_STATUS (1 << 5)
91
92 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
93 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94
95 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
96 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
97 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98
99 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100
101 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102
103 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
104 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
105 #define NFC_V3_WRPROT_LOCK (1 << 1)
106 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
107 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108
109 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110
111 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
112 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
113 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
114 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
115 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
116 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
117 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
118 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
119 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
120 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
122 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
123 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
124 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125
126 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
127 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
128 #define NFC_V3_CONFIG3_FW8 (1 << 3)
129 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
130 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
131 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
132 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133
134 #define NFC_V3_IPC (host->regs_ip + 0x2C)
135 #define NFC_V3_IPC_CREQ (1 << 0)
136 #define NFC_V3_IPC_INT (1 << 31)
137
138 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
139
140 struct mxc_nand_host;
141
142 struct mxc_nand_devtype_data {
143 void (*preset)(struct mtd_info *);
144 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
146 void (*send_page)(struct mtd_info *, unsigned int);
147 void (*send_read_id)(struct mxc_nand_host *);
148 uint16_t (*get_dev_status)(struct mxc_nand_host *);
149 int (*check_int)(struct mxc_nand_host *);
150 void (*irq_control)(struct mxc_nand_host *, int);
151 u32 (*get_ecc_status)(struct mxc_nand_host *);
152 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
153 void (*select_chip)(struct mtd_info *mtd, int chip);
154 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
155 u_char *read_ecc, u_char *calc_ecc);
156
157 /*
158 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
159 * (CONFIG1:INT_MSK is set). To handle this the driver uses
160 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
161 */
162 int irqpending_quirk;
163 int needs_ip;
164
165 size_t regs_offset;
166 size_t spare0_offset;
167 size_t axi_offset;
168
169 int spare_len;
170 int eccbytes;
171 int eccsize;
172 int ppb_shift;
173 };
174
175 struct mxc_nand_host {
176 struct nand_chip nand;
177 struct device *dev;
178
179 void __iomem *spare0;
180 void __iomem *main_area0;
181
182 void __iomem *base;
183 void __iomem *regs;
184 void __iomem *regs_axi;
185 void __iomem *regs_ip;
186 int status_request;
187 struct clk *clk;
188 int clk_act;
189 int irq;
190 int eccsize;
191 int used_oobsize;
192 int active_cs;
193
194 struct completion op_completion;
195
196 uint8_t *data_buf;
197 unsigned int buf_start;
198
199 const struct mxc_nand_devtype_data *devtype_data;
200 struct mxc_nand_platform_data pdata;
201 };
202
203 /* OOB placement block for use with hardware ecc generation */
204 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
205 .eccbytes = 5,
206 .eccpos = {6, 7, 8, 9, 10},
207 .oobfree = {{0, 5}, {12, 4}, }
208 };
209
210 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
211 .eccbytes = 20,
212 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
213 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
214 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
215 };
216
217 /* OOB description for 512 byte pages with 16 byte OOB */
218 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
219 .eccbytes = 1 * 9,
220 .eccpos = {
221 7, 8, 9, 10, 11, 12, 13, 14, 15
222 },
223 .oobfree = {
224 {.offset = 0, .length = 5}
225 }
226 };
227
228 /* OOB description for 2048 byte pages with 64 byte OOB */
229 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
230 .eccbytes = 4 * 9,
231 .eccpos = {
232 7, 8, 9, 10, 11, 12, 13, 14, 15,
233 23, 24, 25, 26, 27, 28, 29, 30, 31,
234 39, 40, 41, 42, 43, 44, 45, 46, 47,
235 55, 56, 57, 58, 59, 60, 61, 62, 63
236 },
237 .oobfree = {
238 {.offset = 2, .length = 4},
239 {.offset = 16, .length = 7},
240 {.offset = 32, .length = 7},
241 {.offset = 48, .length = 7}
242 }
243 };
244
245 /* OOB description for 4096 byte pages with 128 byte OOB */
246 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
247 .eccbytes = 8 * 9,
248 .eccpos = {
249 7, 8, 9, 10, 11, 12, 13, 14, 15,
250 23, 24, 25, 26, 27, 28, 29, 30, 31,
251 39, 40, 41, 42, 43, 44, 45, 46, 47,
252 55, 56, 57, 58, 59, 60, 61, 62, 63,
253 71, 72, 73, 74, 75, 76, 77, 78, 79,
254 87, 88, 89, 90, 91, 92, 93, 94, 95,
255 103, 104, 105, 106, 107, 108, 109, 110, 111,
256 119, 120, 121, 122, 123, 124, 125, 126, 127,
257 },
258 .oobfree = {
259 {.offset = 2, .length = 4},
260 {.offset = 16, .length = 7},
261 {.offset = 32, .length = 7},
262 {.offset = 48, .length = 7},
263 {.offset = 64, .length = 7},
264 {.offset = 80, .length = 7},
265 {.offset = 96, .length = 7},
266 {.offset = 112, .length = 7},
267 }
268 };
269
270 static const char * const part_probes[] = {
271 "cmdlinepart", "RedBoot", "ofpart", NULL };
272
273 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
274 {
275 int i;
276 u32 *t = trg;
277 const __iomem u32 *s = src;
278
279 for (i = 0; i < (size >> 2); i++)
280 *t++ = __raw_readl(s++);
281 }
282
283 static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size)
284 {
285 int i;
286 u16 *t = trg;
287 const __iomem u16 *s = src;
288
289 /* We assume that src (IO) is always 32bit aligned */
290 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
291 memcpy32_fromio(trg, src, size);
292 return;
293 }
294
295 for (i = 0; i < (size >> 1); i++)
296 *t++ = __raw_readw(s++);
297 }
298
299 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
300 {
301 /* __iowrite32_copy use 32bit size values so divide by 4 */
302 __iowrite32_copy(trg, src, size / 4);
303 }
304
305 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
306 {
307 int i;
308 __iomem u16 *t = trg;
309 const u16 *s = src;
310
311 /* We assume that trg (IO) is always 32bit aligned */
312 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
313 memcpy32_toio(trg, src, size);
314 return;
315 }
316
317 for (i = 0; i < (size >> 1); i++)
318 __raw_writew(*s++, t++);
319 }
320
321 static int check_int_v3(struct mxc_nand_host *host)
322 {
323 uint32_t tmp;
324
325 tmp = readl(NFC_V3_IPC);
326 if (!(tmp & NFC_V3_IPC_INT))
327 return 0;
328
329 tmp &= ~NFC_V3_IPC_INT;
330 writel(tmp, NFC_V3_IPC);
331
332 return 1;
333 }
334
335 static int check_int_v1_v2(struct mxc_nand_host *host)
336 {
337 uint32_t tmp;
338
339 tmp = readw(NFC_V1_V2_CONFIG2);
340 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
341 return 0;
342
343 if (!host->devtype_data->irqpending_quirk)
344 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
345
346 return 1;
347 }
348
349 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
350 {
351 uint16_t tmp;
352
353 tmp = readw(NFC_V1_V2_CONFIG1);
354
355 if (activate)
356 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
357 else
358 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
359
360 writew(tmp, NFC_V1_V2_CONFIG1);
361 }
362
363 static void irq_control_v3(struct mxc_nand_host *host, int activate)
364 {
365 uint32_t tmp;
366
367 tmp = readl(NFC_V3_CONFIG2);
368
369 if (activate)
370 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
371 else
372 tmp |= NFC_V3_CONFIG2_INT_MSK;
373
374 writel(tmp, NFC_V3_CONFIG2);
375 }
376
377 static void irq_control(struct mxc_nand_host *host, int activate)
378 {
379 if (host->devtype_data->irqpending_quirk) {
380 if (activate)
381 enable_irq(host->irq);
382 else
383 disable_irq_nosync(host->irq);
384 } else {
385 host->devtype_data->irq_control(host, activate);
386 }
387 }
388
389 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
390 {
391 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
392 }
393
394 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
395 {
396 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
397 }
398
399 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
400 {
401 return readl(NFC_V3_ECC_STATUS_RESULT);
402 }
403
404 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
405 {
406 struct mxc_nand_host *host = dev_id;
407
408 if (!host->devtype_data->check_int(host))
409 return IRQ_NONE;
410
411 irq_control(host, 0);
412
413 complete(&host->op_completion);
414
415 return IRQ_HANDLED;
416 }
417
418 /* This function polls the NANDFC to wait for the basic operation to
419 * complete by checking the INT bit of config2 register.
420 */
421 static int wait_op_done(struct mxc_nand_host *host, int useirq)
422 {
423 int ret = 0;
424
425 /*
426 * If operation is already complete, don't bother to setup an irq or a
427 * loop.
428 */
429 if (host->devtype_data->check_int(host))
430 return 0;
431
432 if (useirq) {
433 unsigned long timeout;
434
435 reinit_completion(&host->op_completion);
436
437 irq_control(host, 1);
438
439 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
440 if (!timeout && !host->devtype_data->check_int(host)) {
441 dev_dbg(host->dev, "timeout waiting for irq\n");
442 ret = -ETIMEDOUT;
443 }
444 } else {
445 int max_retries = 8000;
446 int done;
447
448 do {
449 udelay(1);
450
451 done = host->devtype_data->check_int(host);
452 if (done)
453 break;
454
455 } while (--max_retries);
456
457 if (!done) {
458 dev_dbg(host->dev, "timeout polling for completion\n");
459 ret = -ETIMEDOUT;
460 }
461 }
462
463 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
464
465 return ret;
466 }
467
468 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
469 {
470 /* fill command */
471 writel(cmd, NFC_V3_FLASH_CMD);
472
473 /* send out command */
474 writel(NFC_CMD, NFC_V3_LAUNCH);
475
476 /* Wait for operation to complete */
477 wait_op_done(host, useirq);
478 }
479
480 /* This function issues the specified command to the NAND device and
481 * waits for completion. */
482 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
483 {
484 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
485
486 writew(cmd, NFC_V1_V2_FLASH_CMD);
487 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
488
489 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
490 int max_retries = 100;
491 /* Reset completion is indicated by NFC_CONFIG2 */
492 /* being set to 0 */
493 while (max_retries-- > 0) {
494 if (readw(NFC_V1_V2_CONFIG2) == 0) {
495 break;
496 }
497 udelay(1);
498 }
499 if (max_retries < 0)
500 pr_debug("%s: RESET failed\n", __func__);
501 } else {
502 /* Wait for operation to complete */
503 wait_op_done(host, useirq);
504 }
505 }
506
507 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
508 {
509 /* fill address */
510 writel(addr, NFC_V3_FLASH_ADDR0);
511
512 /* send out address */
513 writel(NFC_ADDR, NFC_V3_LAUNCH);
514
515 wait_op_done(host, 0);
516 }
517
518 /* This function sends an address (or partial address) to the
519 * NAND device. The address is used to select the source/destination for
520 * a NAND command. */
521 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
522 {
523 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
524
525 writew(addr, NFC_V1_V2_FLASH_ADDR);
526 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
527
528 /* Wait for operation to complete */
529 wait_op_done(host, islast);
530 }
531
532 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
533 {
534 struct nand_chip *nand_chip = mtd_to_nand(mtd);
535 struct mxc_nand_host *host = nand_chip->priv;
536 uint32_t tmp;
537
538 tmp = readl(NFC_V3_CONFIG1);
539 tmp &= ~(7 << 4);
540 writel(tmp, NFC_V3_CONFIG1);
541
542 /* transfer data from NFC ram to nand */
543 writel(ops, NFC_V3_LAUNCH);
544
545 wait_op_done(host, false);
546 }
547
548 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
549 {
550 struct nand_chip *nand_chip = mtd_to_nand(mtd);
551 struct mxc_nand_host *host = nand_chip->priv;
552
553 /* NANDFC buffer 0 is used for page read/write */
554 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
555
556 writew(ops, NFC_V1_V2_CONFIG2);
557
558 /* Wait for operation to complete */
559 wait_op_done(host, true);
560 }
561
562 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
563 {
564 struct nand_chip *nand_chip = mtd_to_nand(mtd);
565 struct mxc_nand_host *host = nand_chip->priv;
566 int bufs, i;
567
568 if (mtd->writesize > 512)
569 bufs = 4;
570 else
571 bufs = 1;
572
573 for (i = 0; i < bufs; i++) {
574
575 /* NANDFC buffer 0 is used for page read/write */
576 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
577
578 writew(ops, NFC_V1_V2_CONFIG2);
579
580 /* Wait for operation to complete */
581 wait_op_done(host, true);
582 }
583 }
584
585 static void send_read_id_v3(struct mxc_nand_host *host)
586 {
587 /* Read ID into main buffer */
588 writel(NFC_ID, NFC_V3_LAUNCH);
589
590 wait_op_done(host, true);
591
592 memcpy32_fromio(host->data_buf, host->main_area0, 16);
593 }
594
595 /* Request the NANDFC to perform a read of the NAND device ID. */
596 static void send_read_id_v1_v2(struct mxc_nand_host *host)
597 {
598 /* NANDFC buffer 0 is used for device ID output */
599 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
600
601 writew(NFC_ID, NFC_V1_V2_CONFIG2);
602
603 /* Wait for operation to complete */
604 wait_op_done(host, true);
605
606 memcpy32_fromio(host->data_buf, host->main_area0, 16);
607 }
608
609 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
610 {
611 writew(NFC_STATUS, NFC_V3_LAUNCH);
612 wait_op_done(host, true);
613
614 return readl(NFC_V3_CONFIG1) >> 16;
615 }
616
617 /* This function requests the NANDFC to perform a read of the
618 * NAND device status and returns the current status. */
619 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
620 {
621 void __iomem *main_buf = host->main_area0;
622 uint32_t store;
623 uint16_t ret;
624
625 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
626
627 /*
628 * The device status is stored in main_area0. To
629 * prevent corruption of the buffer save the value
630 * and restore it afterwards.
631 */
632 store = readl(main_buf);
633
634 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
635 wait_op_done(host, true);
636
637 ret = readw(main_buf);
638
639 writel(store, main_buf);
640
641 return ret;
642 }
643
644 /* This functions is used by upper layer to checks if device is ready */
645 static int mxc_nand_dev_ready(struct mtd_info *mtd)
646 {
647 /*
648 * NFC handles R/B internally. Therefore, this function
649 * always returns status as ready.
650 */
651 return 1;
652 }
653
654 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
655 {
656 /*
657 * If HW ECC is enabled, we turn it on during init. There is
658 * no need to enable again here.
659 */
660 }
661
662 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
663 u_char *read_ecc, u_char *calc_ecc)
664 {
665 struct nand_chip *nand_chip = mtd_to_nand(mtd);
666 struct mxc_nand_host *host = nand_chip->priv;
667
668 /*
669 * 1-Bit errors are automatically corrected in HW. No need for
670 * additional correction. 2-Bit errors cannot be corrected by
671 * HW ECC, so we need to return failure
672 */
673 uint16_t ecc_status = get_ecc_status_v1(host);
674
675 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
676 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
677 return -1;
678 }
679
680 return 0;
681 }
682
683 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
684 u_char *read_ecc, u_char *calc_ecc)
685 {
686 struct nand_chip *nand_chip = mtd_to_nand(mtd);
687 struct mxc_nand_host *host = nand_chip->priv;
688 u32 ecc_stat, err;
689 int no_subpages = 1;
690 int ret = 0;
691 u8 ecc_bit_mask, err_limit;
692
693 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
694 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
695
696 no_subpages = mtd->writesize >> 9;
697
698 ecc_stat = host->devtype_data->get_ecc_status(host);
699
700 do {
701 err = ecc_stat & ecc_bit_mask;
702 if (err > err_limit) {
703 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
704 return -1;
705 } else {
706 ret += err;
707 }
708 ecc_stat >>= 4;
709 } while (--no_subpages);
710
711 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
712
713 return ret;
714 }
715
716 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
717 u_char *ecc_code)
718 {
719 return 0;
720 }
721
722 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
723 {
724 struct nand_chip *nand_chip = mtd_to_nand(mtd);
725 struct mxc_nand_host *host = nand_chip->priv;
726 uint8_t ret;
727
728 /* Check for status request */
729 if (host->status_request)
730 return host->devtype_data->get_dev_status(host) & 0xFF;
731
732 if (nand_chip->options & NAND_BUSWIDTH_16) {
733 /* only take the lower byte of each word */
734 ret = *(uint16_t *)(host->data_buf + host->buf_start);
735
736 host->buf_start += 2;
737 } else {
738 ret = *(uint8_t *)(host->data_buf + host->buf_start);
739 host->buf_start++;
740 }
741
742 pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
743 return ret;
744 }
745
746 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
747 {
748 struct nand_chip *nand_chip = mtd_to_nand(mtd);
749 struct mxc_nand_host *host = nand_chip->priv;
750 uint16_t ret;
751
752 ret = *(uint16_t *)(host->data_buf + host->buf_start);
753 host->buf_start += 2;
754
755 return ret;
756 }
757
758 /* Write data of length len to buffer buf. The data to be
759 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
760 * Operation by the NFC, the data is written to NAND Flash */
761 static void mxc_nand_write_buf(struct mtd_info *mtd,
762 const u_char *buf, int len)
763 {
764 struct nand_chip *nand_chip = mtd_to_nand(mtd);
765 struct mxc_nand_host *host = nand_chip->priv;
766 u16 col = host->buf_start;
767 int n = mtd->oobsize + mtd->writesize - col;
768
769 n = min(n, len);
770
771 memcpy(host->data_buf + col, buf, n);
772
773 host->buf_start += n;
774 }
775
776 /* Read the data buffer from the NAND Flash. To read the data from NAND
777 * Flash first the data output cycle is initiated by the NFC, which copies
778 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
779 */
780 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
781 {
782 struct nand_chip *nand_chip = mtd_to_nand(mtd);
783 struct mxc_nand_host *host = nand_chip->priv;
784 u16 col = host->buf_start;
785 int n = mtd->oobsize + mtd->writesize - col;
786
787 n = min(n, len);
788
789 memcpy(buf, host->data_buf + col, n);
790
791 host->buf_start += n;
792 }
793
794 /* This function is used by upper layer for select and
795 * deselect of the NAND chip */
796 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
797 {
798 struct nand_chip *nand_chip = mtd_to_nand(mtd);
799 struct mxc_nand_host *host = nand_chip->priv;
800
801 if (chip == -1) {
802 /* Disable the NFC clock */
803 if (host->clk_act) {
804 clk_disable_unprepare(host->clk);
805 host->clk_act = 0;
806 }
807 return;
808 }
809
810 if (!host->clk_act) {
811 /* Enable the NFC clock */
812 clk_prepare_enable(host->clk);
813 host->clk_act = 1;
814 }
815 }
816
817 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
818 {
819 struct nand_chip *nand_chip = mtd_to_nand(mtd);
820 struct mxc_nand_host *host = nand_chip->priv;
821
822 if (chip == -1) {
823 /* Disable the NFC clock */
824 if (host->clk_act) {
825 clk_disable_unprepare(host->clk);
826 host->clk_act = 0;
827 }
828 return;
829 }
830
831 if (!host->clk_act) {
832 /* Enable the NFC clock */
833 clk_prepare_enable(host->clk);
834 host->clk_act = 1;
835 }
836
837 host->active_cs = chip;
838 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
839 }
840
841 /*
842 * The controller splits a page into data chunks of 512 bytes + partial oob.
843 * There are writesize / 512 such chunks, the size of the partial oob parts is
844 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
845 * contains additionally the byte lost by rounding (if any).
846 * This function handles the needed shuffling between host->data_buf (which
847 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
848 * spare) and the NFC buffer.
849 */
850 static void copy_spare(struct mtd_info *mtd, bool bfrom)
851 {
852 struct nand_chip *this = mtd_to_nand(mtd);
853 struct mxc_nand_host *host = this->priv;
854 u16 i, oob_chunk_size;
855 u16 num_chunks = mtd->writesize / 512;
856
857 u8 *d = host->data_buf + mtd->writesize;
858 u8 __iomem *s = host->spare0;
859 u16 sparebuf_size = host->devtype_data->spare_len;
860
861 /* size of oob chunk for all but possibly the last one */
862 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
863
864 if (bfrom) {
865 for (i = 0; i < num_chunks - 1; i++)
866 memcpy16_fromio(d + i * oob_chunk_size,
867 s + i * sparebuf_size,
868 oob_chunk_size);
869
870 /* the last chunk */
871 memcpy16_fromio(d + i * oob_chunk_size,
872 s + i * sparebuf_size,
873 host->used_oobsize - i * oob_chunk_size);
874 } else {
875 for (i = 0; i < num_chunks - 1; i++)
876 memcpy16_toio(&s[i * sparebuf_size],
877 &d[i * oob_chunk_size],
878 oob_chunk_size);
879
880 /* the last chunk */
881 memcpy16_toio(&s[i * sparebuf_size],
882 &d[i * oob_chunk_size],
883 host->used_oobsize - i * oob_chunk_size);
884 }
885 }
886
887 /*
888 * MXC NANDFC can only perform full page+spare or spare-only read/write. When
889 * the upper layers perform a read/write buf operation, the saved column address
890 * is used to index into the full page. So usually this function is called with
891 * column == 0 (unless no column cycle is needed indicated by column == -1)
892 */
893 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
894 {
895 struct nand_chip *nand_chip = mtd_to_nand(mtd);
896 struct mxc_nand_host *host = nand_chip->priv;
897
898 /* Write out column address, if necessary */
899 if (column != -1) {
900 host->devtype_data->send_addr(host, column & 0xff,
901 page_addr == -1);
902 if (mtd->writesize > 512)
903 /* another col addr cycle for 2k page */
904 host->devtype_data->send_addr(host,
905 (column >> 8) & 0xff,
906 false);
907 }
908
909 /* Write out page address, if necessary */
910 if (page_addr != -1) {
911 /* paddr_0 - p_addr_7 */
912 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
913
914 if (mtd->writesize > 512) {
915 if (mtd->size >= 0x10000000) {
916 /* paddr_8 - paddr_15 */
917 host->devtype_data->send_addr(host,
918 (page_addr >> 8) & 0xff,
919 false);
920 host->devtype_data->send_addr(host,
921 (page_addr >> 16) & 0xff,
922 true);
923 } else
924 /* paddr_8 - paddr_15 */
925 host->devtype_data->send_addr(host,
926 (page_addr >> 8) & 0xff, true);
927 } else {
928 /* One more address cycle for higher density devices */
929 if (mtd->size >= 0x4000000) {
930 /* paddr_8 - paddr_15 */
931 host->devtype_data->send_addr(host,
932 (page_addr >> 8) & 0xff,
933 false);
934 host->devtype_data->send_addr(host,
935 (page_addr >> 16) & 0xff,
936 true);
937 } else
938 /* paddr_8 - paddr_15 */
939 host->devtype_data->send_addr(host,
940 (page_addr >> 8) & 0xff, true);
941 }
942 }
943 }
944
945 /*
946 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
947 * on how much oob the nand chip has. For 8bit ecc we need at least
948 * 26 bytes of oob data per 512 byte block.
949 */
950 static int get_eccsize(struct mtd_info *mtd)
951 {
952 int oobbytes_per_512 = 0;
953
954 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
955
956 if (oobbytes_per_512 < 26)
957 return 4;
958 else
959 return 8;
960 }
961
962 static void ecc_8bit_layout_4k(struct nand_ecclayout *layout)
963 {
964 int i, j;
965
966 layout->eccbytes = 8*18;
967 for (i = 0; i < 8; i++)
968 for (j = 0; j < 18; j++)
969 layout->eccpos[i*18 + j] = i*26 + j + 7;
970
971 layout->oobfree[0].offset = 2;
972 layout->oobfree[0].length = 4;
973 for (i = 1; i < 8; i++) {
974 layout->oobfree[i].offset = i*26;
975 layout->oobfree[i].length = 7;
976 }
977 }
978
979 static void preset_v1(struct mtd_info *mtd)
980 {
981 struct nand_chip *nand_chip = mtd_to_nand(mtd);
982 struct mxc_nand_host *host = nand_chip->priv;
983 uint16_t config1 = 0;
984
985 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
986 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
987
988 if (!host->devtype_data->irqpending_quirk)
989 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
990
991 host->eccsize = 1;
992
993 writew(config1, NFC_V1_V2_CONFIG1);
994 /* preset operation */
995
996 /* Unlock the internal RAM Buffer */
997 writew(0x2, NFC_V1_V2_CONFIG);
998
999 /* Blocks to be unlocked */
1000 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1001 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1002
1003 /* Unlock Block Command for given address range */
1004 writew(0x4, NFC_V1_V2_WRPROT);
1005 }
1006
1007 static void preset_v2(struct mtd_info *mtd)
1008 {
1009 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1010 struct mxc_nand_host *host = nand_chip->priv;
1011 uint16_t config1 = 0;
1012
1013 config1 |= NFC_V2_CONFIG1_FP_INT;
1014
1015 if (!host->devtype_data->irqpending_quirk)
1016 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1017
1018 if (mtd->writesize) {
1019 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1020
1021 if (nand_chip->ecc.mode == NAND_ECC_HW)
1022 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1023
1024 host->eccsize = get_eccsize(mtd);
1025 if (host->eccsize == 4)
1026 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1027
1028 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1029 } else {
1030 host->eccsize = 1;
1031 }
1032
1033 writew(config1, NFC_V1_V2_CONFIG1);
1034 /* preset operation */
1035
1036 /* Unlock the internal RAM Buffer */
1037 writew(0x2, NFC_V1_V2_CONFIG);
1038
1039 /* Blocks to be unlocked */
1040 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1041 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1042 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1043 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1044 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1045 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1046 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1047 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1048
1049 /* Unlock Block Command for given address range */
1050 writew(0x4, NFC_V1_V2_WRPROT);
1051 }
1052
1053 static void preset_v3(struct mtd_info *mtd)
1054 {
1055 struct nand_chip *chip = mtd_to_nand(mtd);
1056 struct mxc_nand_host *host = chip->priv;
1057 uint32_t config2, config3;
1058 int i, addr_phases;
1059
1060 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1061 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1062
1063 /* Unlock the internal RAM Buffer */
1064 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1065 NFC_V3_WRPROT);
1066
1067 /* Blocks to be unlocked */
1068 for (i = 0; i < NAND_MAX_CHIPS; i++)
1069 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1070
1071 writel(0, NFC_V3_IPC);
1072
1073 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1074 NFC_V3_CONFIG2_2CMD_PHASES |
1075 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1076 NFC_V3_CONFIG2_ST_CMD(0x70) |
1077 NFC_V3_CONFIG2_INT_MSK |
1078 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1079
1080 addr_phases = fls(chip->pagemask) >> 3;
1081
1082 if (mtd->writesize == 2048) {
1083 config2 |= NFC_V3_CONFIG2_PS_2048;
1084 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1085 } else if (mtd->writesize == 4096) {
1086 config2 |= NFC_V3_CONFIG2_PS_4096;
1087 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1088 } else {
1089 config2 |= NFC_V3_CONFIG2_PS_512;
1090 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1091 }
1092
1093 if (mtd->writesize) {
1094 if (chip->ecc.mode == NAND_ECC_HW)
1095 config2 |= NFC_V3_CONFIG2_ECC_EN;
1096
1097 config2 |= NFC_V3_CONFIG2_PPB(
1098 ffs(mtd->erasesize / mtd->writesize) - 6,
1099 host->devtype_data->ppb_shift);
1100 host->eccsize = get_eccsize(mtd);
1101 if (host->eccsize == 8)
1102 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1103 }
1104
1105 writel(config2, NFC_V3_CONFIG2);
1106
1107 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1108 NFC_V3_CONFIG3_NO_SDMA |
1109 NFC_V3_CONFIG3_RBB_MODE |
1110 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1111 NFC_V3_CONFIG3_ADD_OP(0);
1112
1113 if (!(chip->options & NAND_BUSWIDTH_16))
1114 config3 |= NFC_V3_CONFIG3_FW8;
1115
1116 writel(config3, NFC_V3_CONFIG3);
1117
1118 writel(0, NFC_V3_DELAY_LINE);
1119 }
1120
1121 /* Used by the upper layer to write command to NAND Flash for
1122 * different operations to be carried out on NAND Flash */
1123 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1124 int column, int page_addr)
1125 {
1126 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1127 struct mxc_nand_host *host = nand_chip->priv;
1128
1129 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1130 command, column, page_addr);
1131
1132 /* Reset command state information */
1133 host->status_request = false;
1134
1135 /* Command pre-processing step */
1136 switch (command) {
1137 case NAND_CMD_RESET:
1138 host->devtype_data->preset(mtd);
1139 host->devtype_data->send_cmd(host, command, false);
1140 break;
1141
1142 case NAND_CMD_STATUS:
1143 host->buf_start = 0;
1144 host->status_request = true;
1145
1146 host->devtype_data->send_cmd(host, command, true);
1147 WARN_ONCE(column != -1 || page_addr != -1,
1148 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1149 command, column, page_addr);
1150 mxc_do_addr_cycle(mtd, column, page_addr);
1151 break;
1152
1153 case NAND_CMD_READ0:
1154 case NAND_CMD_READOOB:
1155 if (command == NAND_CMD_READ0)
1156 host->buf_start = column;
1157 else
1158 host->buf_start = column + mtd->writesize;
1159
1160 command = NAND_CMD_READ0; /* only READ0 is valid */
1161
1162 host->devtype_data->send_cmd(host, command, false);
1163 WARN_ONCE(column < 0,
1164 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1165 command, column, page_addr);
1166 mxc_do_addr_cycle(mtd, 0, page_addr);
1167
1168 if (mtd->writesize > 512)
1169 host->devtype_data->send_cmd(host,
1170 NAND_CMD_READSTART, true);
1171
1172 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1173
1174 memcpy32_fromio(host->data_buf, host->main_area0,
1175 mtd->writesize);
1176 copy_spare(mtd, true);
1177 break;
1178
1179 case NAND_CMD_SEQIN:
1180 if (column >= mtd->writesize)
1181 /* call ourself to read a page */
1182 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1183
1184 host->buf_start = column;
1185
1186 host->devtype_data->send_cmd(host, command, false);
1187 WARN_ONCE(column < -1,
1188 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1189 command, column, page_addr);
1190 mxc_do_addr_cycle(mtd, 0, page_addr);
1191 break;
1192
1193 case NAND_CMD_PAGEPROG:
1194 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1195 copy_spare(mtd, false);
1196 host->devtype_data->send_page(mtd, NFC_INPUT);
1197 host->devtype_data->send_cmd(host, command, true);
1198 WARN_ONCE(column != -1 || page_addr != -1,
1199 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1200 command, column, page_addr);
1201 mxc_do_addr_cycle(mtd, column, page_addr);
1202 break;
1203
1204 case NAND_CMD_READID:
1205 host->devtype_data->send_cmd(host, command, true);
1206 mxc_do_addr_cycle(mtd, column, page_addr);
1207 host->devtype_data->send_read_id(host);
1208 host->buf_start = 0;
1209 break;
1210
1211 case NAND_CMD_ERASE1:
1212 case NAND_CMD_ERASE2:
1213 host->devtype_data->send_cmd(host, command, false);
1214 WARN_ONCE(column != -1,
1215 "Unexpected column value (cmd=%u, col=%d)\n",
1216 command, column);
1217 mxc_do_addr_cycle(mtd, column, page_addr);
1218
1219 break;
1220 case NAND_CMD_PARAM:
1221 host->devtype_data->send_cmd(host, command, false);
1222 mxc_do_addr_cycle(mtd, column, page_addr);
1223 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1224 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1225 host->buf_start = 0;
1226 break;
1227 default:
1228 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1229 command);
1230 break;
1231 }
1232 }
1233
1234 /*
1235 * The generic flash bbt decriptors overlap with our ecc
1236 * hardware, so define some i.MX specific ones.
1237 */
1238 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1239 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1240
1241 static struct nand_bbt_descr bbt_main_descr = {
1242 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1243 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1244 .offs = 0,
1245 .len = 4,
1246 .veroffs = 4,
1247 .maxblocks = 4,
1248 .pattern = bbt_pattern,
1249 };
1250
1251 static struct nand_bbt_descr bbt_mirror_descr = {
1252 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1253 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1254 .offs = 0,
1255 .len = 4,
1256 .veroffs = 4,
1257 .maxblocks = 4,
1258 .pattern = mirror_pattern,
1259 };
1260
1261 /* v1 + irqpending_quirk: i.MX21 */
1262 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1263 .preset = preset_v1,
1264 .send_cmd = send_cmd_v1_v2,
1265 .send_addr = send_addr_v1_v2,
1266 .send_page = send_page_v1,
1267 .send_read_id = send_read_id_v1_v2,
1268 .get_dev_status = get_dev_status_v1_v2,
1269 .check_int = check_int_v1_v2,
1270 .irq_control = irq_control_v1_v2,
1271 .get_ecc_status = get_ecc_status_v1,
1272 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1273 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1274 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1275 .select_chip = mxc_nand_select_chip_v1_v3,
1276 .correct_data = mxc_nand_correct_data_v1,
1277 .irqpending_quirk = 1,
1278 .needs_ip = 0,
1279 .regs_offset = 0xe00,
1280 .spare0_offset = 0x800,
1281 .spare_len = 16,
1282 .eccbytes = 3,
1283 .eccsize = 1,
1284 };
1285
1286 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1287 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1288 .preset = preset_v1,
1289 .send_cmd = send_cmd_v1_v2,
1290 .send_addr = send_addr_v1_v2,
1291 .send_page = send_page_v1,
1292 .send_read_id = send_read_id_v1_v2,
1293 .get_dev_status = get_dev_status_v1_v2,
1294 .check_int = check_int_v1_v2,
1295 .irq_control = irq_control_v1_v2,
1296 .get_ecc_status = get_ecc_status_v1,
1297 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1298 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1299 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1300 .select_chip = mxc_nand_select_chip_v1_v3,
1301 .correct_data = mxc_nand_correct_data_v1,
1302 .irqpending_quirk = 0,
1303 .needs_ip = 0,
1304 .regs_offset = 0xe00,
1305 .spare0_offset = 0x800,
1306 .axi_offset = 0,
1307 .spare_len = 16,
1308 .eccbytes = 3,
1309 .eccsize = 1,
1310 };
1311
1312 /* v21: i.MX25, i.MX35 */
1313 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1314 .preset = preset_v2,
1315 .send_cmd = send_cmd_v1_v2,
1316 .send_addr = send_addr_v1_v2,
1317 .send_page = send_page_v2,
1318 .send_read_id = send_read_id_v1_v2,
1319 .get_dev_status = get_dev_status_v1_v2,
1320 .check_int = check_int_v1_v2,
1321 .irq_control = irq_control_v1_v2,
1322 .get_ecc_status = get_ecc_status_v2,
1323 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1324 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1325 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1326 .select_chip = mxc_nand_select_chip_v2,
1327 .correct_data = mxc_nand_correct_data_v2_v3,
1328 .irqpending_quirk = 0,
1329 .needs_ip = 0,
1330 .regs_offset = 0x1e00,
1331 .spare0_offset = 0x1000,
1332 .axi_offset = 0,
1333 .spare_len = 64,
1334 .eccbytes = 9,
1335 .eccsize = 0,
1336 };
1337
1338 /* v3.2a: i.MX51 */
1339 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1340 .preset = preset_v3,
1341 .send_cmd = send_cmd_v3,
1342 .send_addr = send_addr_v3,
1343 .send_page = send_page_v3,
1344 .send_read_id = send_read_id_v3,
1345 .get_dev_status = get_dev_status_v3,
1346 .check_int = check_int_v3,
1347 .irq_control = irq_control_v3,
1348 .get_ecc_status = get_ecc_status_v3,
1349 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1350 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1351 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1352 .select_chip = mxc_nand_select_chip_v1_v3,
1353 .correct_data = mxc_nand_correct_data_v2_v3,
1354 .irqpending_quirk = 0,
1355 .needs_ip = 1,
1356 .regs_offset = 0,
1357 .spare0_offset = 0x1000,
1358 .axi_offset = 0x1e00,
1359 .spare_len = 64,
1360 .eccbytes = 0,
1361 .eccsize = 0,
1362 .ppb_shift = 7,
1363 };
1364
1365 /* v3.2b: i.MX53 */
1366 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1367 .preset = preset_v3,
1368 .send_cmd = send_cmd_v3,
1369 .send_addr = send_addr_v3,
1370 .send_page = send_page_v3,
1371 .send_read_id = send_read_id_v3,
1372 .get_dev_status = get_dev_status_v3,
1373 .check_int = check_int_v3,
1374 .irq_control = irq_control_v3,
1375 .get_ecc_status = get_ecc_status_v3,
1376 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1377 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1378 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1379 .select_chip = mxc_nand_select_chip_v1_v3,
1380 .correct_data = mxc_nand_correct_data_v2_v3,
1381 .irqpending_quirk = 0,
1382 .needs_ip = 1,
1383 .regs_offset = 0,
1384 .spare0_offset = 0x1000,
1385 .axi_offset = 0x1e00,
1386 .spare_len = 64,
1387 .eccbytes = 0,
1388 .eccsize = 0,
1389 .ppb_shift = 8,
1390 };
1391
1392 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1393 {
1394 return host->devtype_data == &imx21_nand_devtype_data;
1395 }
1396
1397 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1398 {
1399 return host->devtype_data == &imx27_nand_devtype_data;
1400 }
1401
1402 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1403 {
1404 return host->devtype_data == &imx25_nand_devtype_data;
1405 }
1406
1407 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1408 {
1409 return host->devtype_data == &imx51_nand_devtype_data;
1410 }
1411
1412 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1413 {
1414 return host->devtype_data == &imx53_nand_devtype_data;
1415 }
1416
1417 static const struct platform_device_id mxcnd_devtype[] = {
1418 {
1419 .name = "imx21-nand",
1420 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1421 }, {
1422 .name = "imx27-nand",
1423 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1424 }, {
1425 .name = "imx25-nand",
1426 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1427 }, {
1428 .name = "imx51-nand",
1429 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1430 }, {
1431 .name = "imx53-nand",
1432 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1433 }, {
1434 /* sentinel */
1435 }
1436 };
1437 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1438
1439 #ifdef CONFIG_OF_MTD
1440 static const struct of_device_id mxcnd_dt_ids[] = {
1441 {
1442 .compatible = "fsl,imx21-nand",
1443 .data = &imx21_nand_devtype_data,
1444 }, {
1445 .compatible = "fsl,imx27-nand",
1446 .data = &imx27_nand_devtype_data,
1447 }, {
1448 .compatible = "fsl,imx25-nand",
1449 .data = &imx25_nand_devtype_data,
1450 }, {
1451 .compatible = "fsl,imx51-nand",
1452 .data = &imx51_nand_devtype_data,
1453 }, {
1454 .compatible = "fsl,imx53-nand",
1455 .data = &imx53_nand_devtype_data,
1456 },
1457 { /* sentinel */ }
1458 };
1459 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1460
1461 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1462 {
1463 struct device_node *np = host->dev->of_node;
1464 struct mxc_nand_platform_data *pdata = &host->pdata;
1465 const struct of_device_id *of_id =
1466 of_match_device(mxcnd_dt_ids, host->dev);
1467 int buswidth;
1468
1469 if (!np)
1470 return 1;
1471
1472 if (of_get_nand_ecc_mode(np) >= 0)
1473 pdata->hw_ecc = 1;
1474
1475 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1476
1477 buswidth = of_get_nand_bus_width(np);
1478 if (buswidth < 0)
1479 return buswidth;
1480
1481 pdata->width = buswidth / 8;
1482
1483 host->devtype_data = of_id->data;
1484
1485 return 0;
1486 }
1487 #else
1488 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1489 {
1490 return 1;
1491 }
1492 #endif
1493
1494 static int mxcnd_probe(struct platform_device *pdev)
1495 {
1496 struct nand_chip *this;
1497 struct mtd_info *mtd;
1498 struct mxc_nand_host *host;
1499 struct resource *res;
1500 int err = 0;
1501
1502 /* Allocate memory for MTD device structure and private data */
1503 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1504 GFP_KERNEL);
1505 if (!host)
1506 return -ENOMEM;
1507
1508 /* allocate a temporary buffer for the nand_scan_ident() */
1509 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1510 if (!host->data_buf)
1511 return -ENOMEM;
1512
1513 host->dev = &pdev->dev;
1514 /* structures must be linked */
1515 this = &host->nand;
1516 mtd = nand_to_mtd(this);
1517 mtd->priv = this;
1518 mtd->dev.parent = &pdev->dev;
1519 mtd->name = DRIVER_NAME;
1520
1521 /* 50 us command delay time */
1522 this->chip_delay = 5;
1523
1524 this->priv = host;
1525 nand_set_flash_node(this, pdev->dev.of_node),
1526 this->dev_ready = mxc_nand_dev_ready;
1527 this->cmdfunc = mxc_nand_command;
1528 this->read_byte = mxc_nand_read_byte;
1529 this->read_word = mxc_nand_read_word;
1530 this->write_buf = mxc_nand_write_buf;
1531 this->read_buf = mxc_nand_read_buf;
1532
1533 host->clk = devm_clk_get(&pdev->dev, NULL);
1534 if (IS_ERR(host->clk))
1535 return PTR_ERR(host->clk);
1536
1537 err = mxcnd_probe_dt(host);
1538 if (err > 0) {
1539 struct mxc_nand_platform_data *pdata =
1540 dev_get_platdata(&pdev->dev);
1541 if (pdata) {
1542 host->pdata = *pdata;
1543 host->devtype_data = (struct mxc_nand_devtype_data *)
1544 pdev->id_entry->driver_data;
1545 } else {
1546 err = -ENODEV;
1547 }
1548 }
1549 if (err < 0)
1550 return err;
1551
1552 if (host->devtype_data->needs_ip) {
1553 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1554 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1555 if (IS_ERR(host->regs_ip))
1556 return PTR_ERR(host->regs_ip);
1557
1558 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1559 } else {
1560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1561 }
1562
1563 host->base = devm_ioremap_resource(&pdev->dev, res);
1564 if (IS_ERR(host->base))
1565 return PTR_ERR(host->base);
1566
1567 host->main_area0 = host->base;
1568
1569 if (host->devtype_data->regs_offset)
1570 host->regs = host->base + host->devtype_data->regs_offset;
1571 host->spare0 = host->base + host->devtype_data->spare0_offset;
1572 if (host->devtype_data->axi_offset)
1573 host->regs_axi = host->base + host->devtype_data->axi_offset;
1574
1575 this->ecc.bytes = host->devtype_data->eccbytes;
1576 host->eccsize = host->devtype_data->eccsize;
1577
1578 this->select_chip = host->devtype_data->select_chip;
1579 this->ecc.size = 512;
1580 this->ecc.layout = host->devtype_data->ecclayout_512;
1581
1582 if (host->pdata.hw_ecc) {
1583 this->ecc.calculate = mxc_nand_calculate_ecc;
1584 this->ecc.hwctl = mxc_nand_enable_hwecc;
1585 this->ecc.correct = host->devtype_data->correct_data;
1586 this->ecc.mode = NAND_ECC_HW;
1587 } else {
1588 this->ecc.mode = NAND_ECC_SOFT;
1589 }
1590
1591 /* NAND bus width determines access functions used by upper layer */
1592 if (host->pdata.width == 2)
1593 this->options |= NAND_BUSWIDTH_16;
1594
1595 if (host->pdata.flash_bbt) {
1596 this->bbt_td = &bbt_main_descr;
1597 this->bbt_md = &bbt_mirror_descr;
1598 /* update flash based bbt */
1599 this->bbt_options |= NAND_BBT_USE_FLASH;
1600 }
1601
1602 init_completion(&host->op_completion);
1603
1604 host->irq = platform_get_irq(pdev, 0);
1605 if (host->irq < 0)
1606 return host->irq;
1607
1608 /*
1609 * Use host->devtype_data->irq_control() here instead of irq_control()
1610 * because we must not disable_irq_nosync without having requested the
1611 * irq.
1612 */
1613 host->devtype_data->irq_control(host, 0);
1614
1615 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1616 0, DRIVER_NAME, host);
1617 if (err)
1618 return err;
1619
1620 err = clk_prepare_enable(host->clk);
1621 if (err)
1622 return err;
1623 host->clk_act = 1;
1624
1625 /*
1626 * Now that we "own" the interrupt make sure the interrupt mask bit is
1627 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1628 * on this machine.
1629 */
1630 if (host->devtype_data->irqpending_quirk) {
1631 disable_irq_nosync(host->irq);
1632 host->devtype_data->irq_control(host, 1);
1633 }
1634
1635 /* first scan to find the device and get the page size */
1636 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1637 err = -ENXIO;
1638 goto escan;
1639 }
1640
1641 /* allocate the right size buffer now */
1642 devm_kfree(&pdev->dev, (void *)host->data_buf);
1643 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1644 GFP_KERNEL);
1645 if (!host->data_buf) {
1646 err = -ENOMEM;
1647 goto escan;
1648 }
1649
1650 /* Call preset again, with correct writesize this time */
1651 host->devtype_data->preset(mtd);
1652
1653 if (mtd->writesize == 2048)
1654 this->ecc.layout = host->devtype_data->ecclayout_2k;
1655 else if (mtd->writesize == 4096) {
1656 this->ecc.layout = host->devtype_data->ecclayout_4k;
1657 if (get_eccsize(mtd) == 8)
1658 ecc_8bit_layout_4k(this->ecc.layout);
1659 }
1660
1661 /*
1662 * Experimentation shows that i.MX NFC can only handle up to 218 oob
1663 * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1664 * into copying invalid data to/from the spare IO buffer, as this
1665 * might cause ECC data corruption when doing sub-page write to a
1666 * partially written page.
1667 */
1668 host->used_oobsize = min(mtd->oobsize, 218U);
1669
1670 if (this->ecc.mode == NAND_ECC_HW) {
1671 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1672 this->ecc.strength = 1;
1673 else
1674 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1675 }
1676
1677 /* second phase scan */
1678 if (nand_scan_tail(mtd)) {
1679 err = -ENXIO;
1680 goto escan;
1681 }
1682
1683 /* Register the partitions */
1684 mtd_device_parse_register(mtd, part_probes,
1685 NULL,
1686 host->pdata.parts,
1687 host->pdata.nr_parts);
1688
1689 platform_set_drvdata(pdev, host);
1690
1691 return 0;
1692
1693 escan:
1694 if (host->clk_act)
1695 clk_disable_unprepare(host->clk);
1696
1697 return err;
1698 }
1699
1700 static int mxcnd_remove(struct platform_device *pdev)
1701 {
1702 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1703
1704 nand_release(nand_to_mtd(&host->nand));
1705 if (host->clk_act)
1706 clk_disable_unprepare(host->clk);
1707
1708 return 0;
1709 }
1710
1711 static struct platform_driver mxcnd_driver = {
1712 .driver = {
1713 .name = DRIVER_NAME,
1714 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1715 },
1716 .id_table = mxcnd_devtype,
1717 .probe = mxcnd_probe,
1718 .remove = mxcnd_remove,
1719 };
1720 module_platform_driver(mxcnd_driver);
1721
1722 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1723 MODULE_DESCRIPTION("MXC NAND MTD driver");
1724 MODULE_LICENSE("GPL");
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