3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
47 #include <linux/mtd/partitions.h>
50 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
52 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
53 struct mtd_oob_ops
*ops
);
55 /* Define default oob placement schemes for large and small page devices */
56 static int nand_ooblayout_ecc_sp(struct mtd_info
*mtd
, int section
,
57 struct mtd_oob_region
*oobregion
)
59 struct nand_chip
*chip
= mtd_to_nand(mtd
);
60 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
66 oobregion
->offset
= 0;
67 oobregion
->length
= 4;
69 oobregion
->offset
= 6;
70 oobregion
->length
= ecc
->total
- 4;
76 static int nand_ooblayout_free_sp(struct mtd_info
*mtd
, int section
,
77 struct mtd_oob_region
*oobregion
)
82 if (mtd
->oobsize
== 16) {
86 oobregion
->length
= 8;
87 oobregion
->offset
= 8;
89 oobregion
->length
= 2;
91 oobregion
->offset
= 3;
93 oobregion
->offset
= 6;
99 const struct mtd_ooblayout_ops nand_ooblayout_sp_ops
= {
100 .ecc
= nand_ooblayout_ecc_sp
,
101 .free
= nand_ooblayout_free_sp
,
103 EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops
);
105 static int nand_ooblayout_ecc_lp(struct mtd_info
*mtd
, int section
,
106 struct mtd_oob_region
*oobregion
)
108 struct nand_chip
*chip
= mtd_to_nand(mtd
);
109 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
114 oobregion
->length
= ecc
->total
;
115 oobregion
->offset
= mtd
->oobsize
- oobregion
->length
;
120 static int nand_ooblayout_free_lp(struct mtd_info
*mtd
, int section
,
121 struct mtd_oob_region
*oobregion
)
123 struct nand_chip
*chip
= mtd_to_nand(mtd
);
124 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
129 oobregion
->length
= mtd
->oobsize
- ecc
->total
- 2;
130 oobregion
->offset
= 2;
135 const struct mtd_ooblayout_ops nand_ooblayout_lp_ops
= {
136 .ecc
= nand_ooblayout_ecc_lp
,
137 .free
= nand_ooblayout_free_lp
,
139 EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops
);
141 static int check_offs_len(struct mtd_info
*mtd
,
142 loff_t ofs
, uint64_t len
)
144 struct nand_chip
*chip
= mtd_to_nand(mtd
);
147 /* Start address must align on block boundary */
148 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
149 pr_debug("%s: unaligned address\n", __func__
);
153 /* Length must align on block boundary */
154 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
155 pr_debug("%s: length not block aligned\n", __func__
);
163 * nand_release_device - [GENERIC] release chip
164 * @mtd: MTD device structure
166 * Release chip lock and wake up anyone waiting on the device.
168 static void nand_release_device(struct mtd_info
*mtd
)
170 struct nand_chip
*chip
= mtd_to_nand(mtd
);
172 /* Release the controller and the chip */
173 spin_lock(&chip
->controller
->lock
);
174 chip
->controller
->active
= NULL
;
175 chip
->state
= FL_READY
;
176 wake_up(&chip
->controller
->wq
);
177 spin_unlock(&chip
->controller
->lock
);
181 * nand_read_byte - [DEFAULT] read one byte from the chip
182 * @mtd: MTD device structure
184 * Default read function for 8bit buswidth
186 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
188 struct nand_chip
*chip
= mtd_to_nand(mtd
);
189 return readb(chip
->IO_ADDR_R
);
193 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
194 * @mtd: MTD device structure
196 * Default read function for 16bit buswidth with endianness conversion.
199 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
201 struct nand_chip
*chip
= mtd_to_nand(mtd
);
202 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
206 * nand_read_word - [DEFAULT] read one word from the chip
207 * @mtd: MTD device structure
209 * Default read function for 16bit buswidth without endianness conversion.
211 static u16
nand_read_word(struct mtd_info
*mtd
)
213 struct nand_chip
*chip
= mtd_to_nand(mtd
);
214 return readw(chip
->IO_ADDR_R
);
218 * nand_select_chip - [DEFAULT] control CE line
219 * @mtd: MTD device structure
220 * @chipnr: chipnumber to select, -1 for deselect
222 * Default select function for 1 chip devices.
224 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
226 struct nand_chip
*chip
= mtd_to_nand(mtd
);
230 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
241 * nand_write_byte - [DEFAULT] write single byte to chip
242 * @mtd: MTD device structure
243 * @byte: value to write
245 * Default function to write a byte to I/O[7:0]
247 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
249 struct nand_chip
*chip
= mtd_to_nand(mtd
);
251 chip
->write_buf(mtd
, &byte
, 1);
255 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
256 * @mtd: MTD device structure
257 * @byte: value to write
259 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
261 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
263 struct nand_chip
*chip
= mtd_to_nand(mtd
);
264 uint16_t word
= byte
;
267 * It's not entirely clear what should happen to I/O[15:8] when writing
268 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
270 * When the host supports a 16-bit bus width, only data is
271 * transferred at the 16-bit width. All address and command line
272 * transfers shall use only the lower 8-bits of the data bus. During
273 * command transfers, the host may place any value on the upper
274 * 8-bits of the data bus. During address transfers, the host shall
275 * set the upper 8-bits of the data bus to 00h.
277 * One user of the write_byte callback is nand_onfi_set_features. The
278 * four parameters are specified to be written to I/O[7:0], but this is
279 * neither an address nor a command transfer. Let's assume a 0 on the
280 * upper I/O lines is OK.
282 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
286 * nand_write_buf - [DEFAULT] write buffer to chip
287 * @mtd: MTD device structure
289 * @len: number of bytes to write
291 * Default write function for 8bit buswidth.
293 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
295 struct nand_chip
*chip
= mtd_to_nand(mtd
);
297 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
301 * nand_read_buf - [DEFAULT] read chip data into buffer
302 * @mtd: MTD device structure
303 * @buf: buffer to store date
304 * @len: number of bytes to read
306 * Default read function for 8bit buswidth.
308 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
310 struct nand_chip
*chip
= mtd_to_nand(mtd
);
312 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
316 * nand_write_buf16 - [DEFAULT] write buffer to chip
317 * @mtd: MTD device structure
319 * @len: number of bytes to write
321 * Default write function for 16bit buswidth.
323 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
325 struct nand_chip
*chip
= mtd_to_nand(mtd
);
326 u16
*p
= (u16
*) buf
;
328 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
332 * nand_read_buf16 - [DEFAULT] read chip data into buffer
333 * @mtd: MTD device structure
334 * @buf: buffer to store date
335 * @len: number of bytes to read
337 * Default read function for 16bit buswidth.
339 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
341 struct nand_chip
*chip
= mtd_to_nand(mtd
);
342 u16
*p
= (u16
*) buf
;
344 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
348 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
349 * @mtd: MTD device structure
350 * @ofs: offset from device start
352 * Check, if the block is bad.
354 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
356 int page
, res
= 0, i
= 0;
357 struct nand_chip
*chip
= mtd_to_nand(mtd
);
360 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
361 ofs
+= mtd
->erasesize
- mtd
->writesize
;
363 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
366 if (chip
->options
& NAND_BUSWIDTH_16
) {
367 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
368 chip
->badblockpos
& 0xFE, page
);
369 bad
= cpu_to_le16(chip
->read_word(mtd
));
370 if (chip
->badblockpos
& 0x1)
375 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
377 bad
= chip
->read_byte(mtd
);
380 if (likely(chip
->badblockbits
== 8))
383 res
= hweight8(bad
) < chip
->badblockbits
;
384 ofs
+= mtd
->writesize
;
385 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
387 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
393 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
394 * @mtd: MTD device structure
395 * @ofs: offset from device start
397 * This is the default implementation, which can be overridden by a hardware
398 * specific driver. It provides the details for writing a bad block marker to a
401 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
403 struct nand_chip
*chip
= mtd_to_nand(mtd
);
404 struct mtd_oob_ops ops
;
405 uint8_t buf
[2] = { 0, 0 };
406 int ret
= 0, res
, i
= 0;
408 memset(&ops
, 0, sizeof(ops
));
410 ops
.ooboffs
= chip
->badblockpos
;
411 if (chip
->options
& NAND_BUSWIDTH_16
) {
412 ops
.ooboffs
&= ~0x01;
413 ops
.len
= ops
.ooblen
= 2;
415 ops
.len
= ops
.ooblen
= 1;
417 ops
.mode
= MTD_OPS_PLACE_OOB
;
419 /* Write to first/last page(s) if necessary */
420 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
421 ofs
+= mtd
->erasesize
- mtd
->writesize
;
423 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
428 ofs
+= mtd
->writesize
;
429 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
435 * nand_block_markbad_lowlevel - mark a block bad
436 * @mtd: MTD device structure
437 * @ofs: offset from device start
439 * This function performs the generic NAND bad block marking steps (i.e., bad
440 * block table(s) and/or marker(s)). We only allow the hardware driver to
441 * specify how to write bad block markers to OOB (chip->block_markbad).
443 * We try operations in the following order:
444 * (1) erase the affected block, to allow OOB marker to be written cleanly
445 * (2) write bad block marker to OOB area of affected block (unless flag
446 * NAND_BBT_NO_OOB_BBM is present)
448 * Note that we retain the first error encountered in (2) or (3), finish the
449 * procedures, and dump the error in the end.
451 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
453 struct nand_chip
*chip
= mtd_to_nand(mtd
);
456 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
457 struct erase_info einfo
;
459 /* Attempt erase before marking OOB */
460 memset(&einfo
, 0, sizeof(einfo
));
463 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
464 nand_erase_nand(mtd
, &einfo
, 0);
466 /* Write bad block marker to OOB */
467 nand_get_device(mtd
, FL_WRITING
);
468 ret
= chip
->block_markbad(mtd
, ofs
);
469 nand_release_device(mtd
);
472 /* Mark block bad in BBT */
474 res
= nand_markbad_bbt(mtd
, ofs
);
480 mtd
->ecc_stats
.badblocks
++;
486 * nand_check_wp - [GENERIC] check if the chip is write protected
487 * @mtd: MTD device structure
489 * Check, if the device is write protected. The function expects, that the
490 * device is already selected.
492 static int nand_check_wp(struct mtd_info
*mtd
)
494 struct nand_chip
*chip
= mtd_to_nand(mtd
);
496 /* Broken xD cards report WP despite being writable */
497 if (chip
->options
& NAND_BROKEN_XD
)
500 /* Check the WP bit */
501 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
502 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
506 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
507 * @mtd: MTD device structure
508 * @ofs: offset from device start
510 * Check if the block is marked as reserved.
512 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
514 struct nand_chip
*chip
= mtd_to_nand(mtd
);
518 /* Return info from the table */
519 return nand_isreserved_bbt(mtd
, ofs
);
523 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
524 * @mtd: MTD device structure
525 * @ofs: offset from device start
526 * @allowbbt: 1, if its allowed to access the bbt area
528 * Check, if the block is bad. Either by reading the bad block table or
529 * calling of the scan function.
531 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
533 struct nand_chip
*chip
= mtd_to_nand(mtd
);
536 return chip
->block_bad(mtd
, ofs
);
538 /* Return info from the table */
539 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
543 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
544 * @mtd: MTD device structure
547 * Helper function for nand_wait_ready used when needing to wait in interrupt
550 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
552 struct nand_chip
*chip
= mtd_to_nand(mtd
);
555 /* Wait for the device to get ready */
556 for (i
= 0; i
< timeo
; i
++) {
557 if (chip
->dev_ready(mtd
))
559 touch_softlockup_watchdog();
565 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
566 * @mtd: MTD device structure
568 * Wait for the ready pin after a command, and warn if a timeout occurs.
570 void nand_wait_ready(struct mtd_info
*mtd
)
572 struct nand_chip
*chip
= mtd_to_nand(mtd
);
573 unsigned long timeo
= 400;
575 if (in_interrupt() || oops_in_progress
)
576 return panic_nand_wait_ready(mtd
, timeo
);
578 /* Wait until command is processed or timeout occurs */
579 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
581 if (chip
->dev_ready(mtd
))
584 } while (time_before(jiffies
, timeo
));
586 if (!chip
->dev_ready(mtd
))
587 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
589 EXPORT_SYMBOL_GPL(nand_wait_ready
);
592 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
593 * @mtd: MTD device structure
594 * @timeo: Timeout in ms
596 * Wait for status ready (i.e. command done) or timeout.
598 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
600 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
602 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
604 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
606 touch_softlockup_watchdog();
607 } while (time_before(jiffies
, timeo
));
611 * nand_command - [DEFAULT] Send command to NAND device
612 * @mtd: MTD device structure
613 * @command: the command to be sent
614 * @column: the column address for this command, -1 if none
615 * @page_addr: the page address for this command, -1 if none
617 * Send command to NAND device. This function is used for small page devices
618 * (512 Bytes per page).
620 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
621 int column
, int page_addr
)
623 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
624 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
626 /* Write out the command to the device */
627 if (command
== NAND_CMD_SEQIN
) {
630 if (column
>= mtd
->writesize
) {
632 column
-= mtd
->writesize
;
633 readcmd
= NAND_CMD_READOOB
;
634 } else if (column
< 256) {
635 /* First 256 bytes --> READ0 */
636 readcmd
= NAND_CMD_READ0
;
639 readcmd
= NAND_CMD_READ1
;
641 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
642 ctrl
&= ~NAND_CTRL_CHANGE
;
644 chip
->cmd_ctrl(mtd
, command
, ctrl
);
646 /* Address cycle, when necessary */
647 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
648 /* Serially input address */
650 /* Adjust columns for 16 bit buswidth */
651 if (chip
->options
& NAND_BUSWIDTH_16
&&
652 !nand_opcode_8bits(command
))
654 chip
->cmd_ctrl(mtd
, column
, ctrl
);
655 ctrl
&= ~NAND_CTRL_CHANGE
;
657 if (page_addr
!= -1) {
658 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
659 ctrl
&= ~NAND_CTRL_CHANGE
;
660 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
661 /* One more address cycle for devices > 32MiB */
662 if (chip
->chipsize
> (32 << 20))
663 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
665 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
668 * Program and erase have their own busy handlers status and sequential
673 case NAND_CMD_PAGEPROG
:
674 case NAND_CMD_ERASE1
:
675 case NAND_CMD_ERASE2
:
677 case NAND_CMD_STATUS
:
683 udelay(chip
->chip_delay
);
684 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
685 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
687 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
688 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
689 nand_wait_status_ready(mtd
, 250);
692 /* This applies to read commands */
695 * If we don't have access to the busy pin, we apply the given
698 if (!chip
->dev_ready
) {
699 udelay(chip
->chip_delay
);
704 * Apply this short delay always to ensure that we do wait tWB in
705 * any case on any machine.
709 nand_wait_ready(mtd
);
712 static void nand_ccs_delay(struct nand_chip
*chip
)
715 * The controller already takes care of waiting for tCCS when the RNDIN
716 * or RNDOUT command is sent, return directly.
718 if (!(chip
->options
& NAND_WAIT_TCCS
))
722 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
723 * (which should be safe for all NANDs).
725 if (chip
->data_interface
&& chip
->data_interface
->timings
.sdr
.tCCS_min
)
726 ndelay(chip
->data_interface
->timings
.sdr
.tCCS_min
/ 1000);
732 * nand_command_lp - [DEFAULT] Send command to NAND large page device
733 * @mtd: MTD device structure
734 * @command: the command to be sent
735 * @column: the column address for this command, -1 if none
736 * @page_addr: the page address for this command, -1 if none
738 * Send command to NAND device. This is the version for the new large page
739 * devices. We don't have the separate regions as we have in the small page
740 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
742 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
743 int column
, int page_addr
)
745 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
747 /* Emulate NAND_CMD_READOOB */
748 if (command
== NAND_CMD_READOOB
) {
749 column
+= mtd
->writesize
;
750 command
= NAND_CMD_READ0
;
753 /* Command latch cycle */
754 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
756 if (column
!= -1 || page_addr
!= -1) {
757 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
759 /* Serially input address */
761 /* Adjust columns for 16 bit buswidth */
762 if (chip
->options
& NAND_BUSWIDTH_16
&&
763 !nand_opcode_8bits(command
))
765 chip
->cmd_ctrl(mtd
, column
, ctrl
);
766 ctrl
&= ~NAND_CTRL_CHANGE
;
768 /* Only output a single addr cycle for 8bits opcodes. */
769 if (!nand_opcode_8bits(command
))
770 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
772 if (page_addr
!= -1) {
773 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
774 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
775 NAND_NCE
| NAND_ALE
);
776 /* One more address cycle for devices > 128MiB */
777 if (chip
->chipsize
> (128 << 20))
778 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
779 NAND_NCE
| NAND_ALE
);
782 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
785 * Program and erase have their own busy handlers status, sequential
786 * in and status need no delay.
790 case NAND_CMD_CACHEDPROG
:
791 case NAND_CMD_PAGEPROG
:
792 case NAND_CMD_ERASE1
:
793 case NAND_CMD_ERASE2
:
795 case NAND_CMD_STATUS
:
799 nand_ccs_delay(chip
);
805 udelay(chip
->chip_delay
);
806 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
807 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
808 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
809 NAND_NCE
| NAND_CTRL_CHANGE
);
810 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
811 nand_wait_status_ready(mtd
, 250);
814 case NAND_CMD_RNDOUT
:
815 /* No ready / busy check necessary */
816 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
817 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
818 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
819 NAND_NCE
| NAND_CTRL_CHANGE
);
821 nand_ccs_delay(chip
);
825 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
826 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
827 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
828 NAND_NCE
| NAND_CTRL_CHANGE
);
830 /* This applies to read commands */
833 * If we don't have access to the busy pin, we apply the given
836 if (!chip
->dev_ready
) {
837 udelay(chip
->chip_delay
);
843 * Apply this short delay always to ensure that we do wait tWB in
844 * any case on any machine.
848 nand_wait_ready(mtd
);
852 * panic_nand_get_device - [GENERIC] Get chip for selected access
853 * @chip: the nand chip descriptor
854 * @mtd: MTD device structure
855 * @new_state: the state which is requested
857 * Used when in panic, no locks are taken.
859 static void panic_nand_get_device(struct nand_chip
*chip
,
860 struct mtd_info
*mtd
, int new_state
)
862 /* Hardware controller shared among independent devices */
863 chip
->controller
->active
= chip
;
864 chip
->state
= new_state
;
868 * nand_get_device - [GENERIC] Get chip for selected access
869 * @mtd: MTD device structure
870 * @new_state: the state which is requested
872 * Get the device and lock it for exclusive access
875 nand_get_device(struct mtd_info
*mtd
, int new_state
)
877 struct nand_chip
*chip
= mtd_to_nand(mtd
);
878 spinlock_t
*lock
= &chip
->controller
->lock
;
879 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
880 DECLARE_WAITQUEUE(wait
, current
);
884 /* Hardware controller shared among independent devices */
885 if (!chip
->controller
->active
)
886 chip
->controller
->active
= chip
;
888 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
889 chip
->state
= new_state
;
893 if (new_state
== FL_PM_SUSPENDED
) {
894 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
895 chip
->state
= FL_PM_SUSPENDED
;
900 set_current_state(TASK_UNINTERRUPTIBLE
);
901 add_wait_queue(wq
, &wait
);
904 remove_wait_queue(wq
, &wait
);
909 * panic_nand_wait - [GENERIC] wait until the command is done
910 * @mtd: MTD device structure
911 * @chip: NAND chip structure
914 * Wait for command done. This is a helper function for nand_wait used when
915 * we are in interrupt context. May happen when in panic and trying to write
916 * an oops through mtdoops.
918 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
922 for (i
= 0; i
< timeo
; i
++) {
923 if (chip
->dev_ready
) {
924 if (chip
->dev_ready(mtd
))
927 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
935 * nand_wait - [DEFAULT] wait until the command is done
936 * @mtd: MTD device structure
937 * @chip: NAND chip structure
939 * Wait for command done. This applies to erase and program only.
941 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
945 unsigned long timeo
= 400;
948 * Apply this short delay always to ensure that we do wait tWB in any
949 * case on any machine.
953 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
955 if (in_interrupt() || oops_in_progress
)
956 panic_nand_wait(mtd
, chip
, timeo
);
958 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
960 if (chip
->dev_ready
) {
961 if (chip
->dev_ready(mtd
))
964 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
968 } while (time_before(jiffies
, timeo
));
971 status
= (int)chip
->read_byte(mtd
);
972 /* This can happen if in case of timeout or buggy dev_ready */
973 WARN_ON(!(status
& NAND_STATUS_READY
));
978 * nand_reset_data_interface - Reset data interface and timings
979 * @chip: The NAND chip
981 * Reset the Data interface and timings to ONFI mode 0.
983 * Returns 0 for success or negative error code otherwise.
985 static int nand_reset_data_interface(struct nand_chip
*chip
)
987 struct mtd_info
*mtd
= nand_to_mtd(chip
);
988 const struct nand_data_interface
*conf
;
991 if (!chip
->setup_data_interface
)
995 * The ONFI specification says:
997 * To transition from NV-DDR or NV-DDR2 to the SDR data
998 * interface, the host shall use the Reset (FFh) command
999 * using SDR timing mode 0. A device in any timing mode is
1000 * required to recognize Reset (FFh) command issued in SDR
1004 * Configure the data interface in SDR mode and set the
1005 * timings to timing mode 0.
1008 conf
= nand_get_default_data_interface();
1009 ret
= chip
->setup_data_interface(mtd
, conf
, false);
1011 pr_err("Failed to configure data interface to SDR timing mode 0\n");
1017 * nand_setup_data_interface - Setup the best data interface and timings
1018 * @chip: The NAND chip
1020 * Find and configure the best data interface and NAND timings supported by
1021 * the chip and the driver.
1022 * First tries to retrieve supported timing modes from ONFI information,
1023 * and if the NAND chip does not support ONFI, relies on the
1024 * ->onfi_timing_mode_default specified in the nand_ids table.
1026 * Returns 0 for success or negative error code otherwise.
1028 static int nand_setup_data_interface(struct nand_chip
*chip
)
1030 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1033 if (!chip
->setup_data_interface
|| !chip
->data_interface
)
1037 * Ensure the timing mode has been changed on the chip side
1038 * before changing timings on the controller side.
1040 if (chip
->onfi_version
) {
1041 u8 tmode_param
[ONFI_SUBFEATURE_PARAM_LEN
] = {
1042 chip
->onfi_timing_mode_default
,
1045 ret
= chip
->onfi_set_features(mtd
, chip
,
1046 ONFI_FEATURE_ADDR_TIMING_MODE
,
1052 ret
= chip
->setup_data_interface(mtd
, chip
->data_interface
, false);
1058 * nand_init_data_interface - find the best data interface and timings
1059 * @chip: The NAND chip
1061 * Find the best data interface and NAND timings supported by the chip
1063 * First tries to retrieve supported timing modes from ONFI information,
1064 * and if the NAND chip does not support ONFI, relies on the
1065 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1066 * function nand_chip->data_interface is initialized with the best timing mode
1069 * Returns 0 for success or negative error code otherwise.
1071 static int nand_init_data_interface(struct nand_chip
*chip
)
1073 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1074 int modes
, mode
, ret
;
1076 if (!chip
->setup_data_interface
)
1080 * First try to identify the best timings from ONFI parameters and
1081 * if the NAND does not support ONFI, fallback to the default ONFI
1084 modes
= onfi_get_async_timing_mode(chip
);
1085 if (modes
== ONFI_TIMING_MODE_UNKNOWN
) {
1086 if (!chip
->onfi_timing_mode_default
)
1089 modes
= GENMASK(chip
->onfi_timing_mode_default
, 0);
1092 chip
->data_interface
= kzalloc(sizeof(*chip
->data_interface
),
1094 if (!chip
->data_interface
)
1097 for (mode
= fls(modes
) - 1; mode
>= 0; mode
--) {
1098 ret
= onfi_init_data_interface(chip
, chip
->data_interface
,
1099 NAND_SDR_IFACE
, mode
);
1103 ret
= chip
->setup_data_interface(mtd
, chip
->data_interface
,
1106 chip
->onfi_timing_mode_default
= mode
;
1114 static void nand_release_data_interface(struct nand_chip
*chip
)
1116 kfree(chip
->data_interface
);
1120 * nand_reset - Reset and initialize a NAND device
1121 * @chip: The NAND chip
1123 * Returns 0 for success or negative error code otherwise
1125 int nand_reset(struct nand_chip
*chip
)
1127 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1130 ret
= nand_reset_data_interface(chip
);
1134 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1136 ret
= nand_setup_data_interface(chip
);
1144 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1146 * @ofs: offset to start unlock from
1147 * @len: length to unlock
1148 * @invert: when = 0, unlock the range of blocks within the lower and
1149 * upper boundary address
1150 * when = 1, unlock the range of blocks outside the boundaries
1151 * of the lower and upper boundary address
1153 * Returs unlock status.
1155 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
1156 uint64_t len
, int invert
)
1160 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1162 /* Submit address of first page to unlock */
1163 page
= ofs
>> chip
->page_shift
;
1164 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
1166 /* Submit address of last page to unlock */
1167 page
= (ofs
+ len
) >> chip
->page_shift
;
1168 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
1169 (page
| invert
) & chip
->pagemask
);
1171 /* Call wait ready function */
1172 status
= chip
->waitfunc(mtd
, chip
);
1173 /* See if device thinks it succeeded */
1174 if (status
& NAND_STATUS_FAIL
) {
1175 pr_debug("%s: error status = 0x%08x\n",
1184 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1186 * @ofs: offset to start unlock from
1187 * @len: length to unlock
1189 * Returns unlock status.
1191 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1195 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1197 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1198 __func__
, (unsigned long long)ofs
, len
);
1200 if (check_offs_len(mtd
, ofs
, len
))
1203 /* Align to last block address if size addresses end of the device */
1204 if (ofs
+ len
== mtd
->size
)
1205 len
-= mtd
->erasesize
;
1207 nand_get_device(mtd
, FL_UNLOCKING
);
1209 /* Shift to get chip number */
1210 chipnr
= ofs
>> chip
->chip_shift
;
1212 chip
->select_chip(mtd
, chipnr
);
1216 * If we want to check the WP through READ STATUS and check the bit 7
1217 * we must reset the chip
1218 * some operation can also clear the bit 7 of status register
1219 * eg. erase/program a locked block
1223 /* Check, if it is write protected */
1224 if (nand_check_wp(mtd
)) {
1225 pr_debug("%s: device is write protected!\n",
1231 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
1234 chip
->select_chip(mtd
, -1);
1235 nand_release_device(mtd
);
1239 EXPORT_SYMBOL(nand_unlock
);
1242 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1244 * @ofs: offset to start unlock from
1245 * @len: length to unlock
1247 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1248 * have this feature, but it allows only to lock all blocks, not for specified
1249 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1252 * Returns lock status.
1254 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1257 int chipnr
, status
, page
;
1258 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1260 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1261 __func__
, (unsigned long long)ofs
, len
);
1263 if (check_offs_len(mtd
, ofs
, len
))
1266 nand_get_device(mtd
, FL_LOCKING
);
1268 /* Shift to get chip number */
1269 chipnr
= ofs
>> chip
->chip_shift
;
1271 chip
->select_chip(mtd
, chipnr
);
1275 * If we want to check the WP through READ STATUS and check the bit 7
1276 * we must reset the chip
1277 * some operation can also clear the bit 7 of status register
1278 * eg. erase/program a locked block
1282 /* Check, if it is write protected */
1283 if (nand_check_wp(mtd
)) {
1284 pr_debug("%s: device is write protected!\n",
1286 status
= MTD_ERASE_FAILED
;
1291 /* Submit address of first page to lock */
1292 page
= ofs
>> chip
->page_shift
;
1293 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1295 /* Call wait ready function */
1296 status
= chip
->waitfunc(mtd
, chip
);
1297 /* See if device thinks it succeeded */
1298 if (status
& NAND_STATUS_FAIL
) {
1299 pr_debug("%s: error status = 0x%08x\n",
1305 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1308 chip
->select_chip(mtd
, -1);
1309 nand_release_device(mtd
);
1313 EXPORT_SYMBOL(nand_lock
);
1316 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1317 * @buf: buffer to test
1318 * @len: buffer length
1319 * @bitflips_threshold: maximum number of bitflips
1321 * Check if a buffer contains only 0xff, which means the underlying region
1322 * has been erased and is ready to be programmed.
1323 * The bitflips_threshold specify the maximum number of bitflips before
1324 * considering the region is not erased.
1325 * Note: The logic of this function has been extracted from the memweight
1326 * implementation, except that nand_check_erased_buf function exit before
1327 * testing the whole buffer if the number of bitflips exceed the
1328 * bitflips_threshold value.
1330 * Returns a positive number of bitflips less than or equal to
1331 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1334 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1336 const unsigned char *bitmap
= buf
;
1340 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1342 weight
= hweight8(*bitmap
);
1343 bitflips
+= BITS_PER_BYTE
- weight
;
1344 if (unlikely(bitflips
> bitflips_threshold
))
1348 for (; len
>= sizeof(long);
1349 len
-= sizeof(long), bitmap
+= sizeof(long)) {
1350 weight
= hweight_long(*((unsigned long *)bitmap
));
1351 bitflips
+= BITS_PER_LONG
- weight
;
1352 if (unlikely(bitflips
> bitflips_threshold
))
1356 for (; len
> 0; len
--, bitmap
++) {
1357 weight
= hweight8(*bitmap
);
1358 bitflips
+= BITS_PER_BYTE
- weight
;
1359 if (unlikely(bitflips
> bitflips_threshold
))
1367 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1369 * @data: data buffer to test
1370 * @datalen: data length
1372 * @ecclen: ECC length
1373 * @extraoob: extra OOB buffer
1374 * @extraooblen: extra OOB length
1375 * @bitflips_threshold: maximum number of bitflips
1377 * Check if a data buffer and its associated ECC and OOB data contains only
1378 * 0xff pattern, which means the underlying region has been erased and is
1379 * ready to be programmed.
1380 * The bitflips_threshold specify the maximum number of bitflips before
1381 * considering the region as not erased.
1384 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1385 * different from the NAND page size. When fixing bitflips, ECC engines will
1386 * report the number of errors per chunk, and the NAND core infrastructure
1387 * expect you to return the maximum number of bitflips for the whole page.
1388 * This is why you should always use this function on a single chunk and
1389 * not on the whole page. After checking each chunk you should update your
1390 * max_bitflips value accordingly.
1391 * 2/ When checking for bitflips in erased pages you should not only check
1392 * the payload data but also their associated ECC data, because a user might
1393 * have programmed almost all bits to 1 but a few. In this case, we
1394 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1396 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1397 * data are protected by the ECC engine.
1398 * It could also be used if you support subpages and want to attach some
1399 * extra OOB data to an ECC chunk.
1401 * Returns a positive number of bitflips less than or equal to
1402 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1403 * threshold. In case of success, the passed buffers are filled with 0xff.
1405 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1406 void *ecc
, int ecclen
,
1407 void *extraoob
, int extraooblen
,
1408 int bitflips_threshold
)
1410 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1412 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1413 bitflips_threshold
);
1414 if (data_bitflips
< 0)
1415 return data_bitflips
;
1417 bitflips_threshold
-= data_bitflips
;
1419 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1420 if (ecc_bitflips
< 0)
1421 return ecc_bitflips
;
1423 bitflips_threshold
-= ecc_bitflips
;
1425 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1426 bitflips_threshold
);
1427 if (extraoob_bitflips
< 0)
1428 return extraoob_bitflips
;
1431 memset(data
, 0xff, datalen
);
1434 memset(ecc
, 0xff, ecclen
);
1436 if (extraoob_bitflips
)
1437 memset(extraoob
, 0xff, extraooblen
);
1439 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1441 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1444 * nand_read_page_raw - [INTERN] read raw page data without ecc
1445 * @mtd: mtd info structure
1446 * @chip: nand chip info structure
1447 * @buf: buffer to store read data
1448 * @oob_required: caller requires OOB data read to chip->oob_poi
1449 * @page: page number to read
1451 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1453 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1454 uint8_t *buf
, int oob_required
, int page
)
1456 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1458 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1463 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1464 * @mtd: mtd info structure
1465 * @chip: nand chip info structure
1466 * @buf: buffer to store read data
1467 * @oob_required: caller requires OOB data read to chip->oob_poi
1468 * @page: page number to read
1470 * We need a special oob layout and handling even when OOB isn't used.
1472 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1473 struct nand_chip
*chip
, uint8_t *buf
,
1474 int oob_required
, int page
)
1476 int eccsize
= chip
->ecc
.size
;
1477 int eccbytes
= chip
->ecc
.bytes
;
1478 uint8_t *oob
= chip
->oob_poi
;
1481 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1482 chip
->read_buf(mtd
, buf
, eccsize
);
1485 if (chip
->ecc
.prepad
) {
1486 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1487 oob
+= chip
->ecc
.prepad
;
1490 chip
->read_buf(mtd
, oob
, eccbytes
);
1493 if (chip
->ecc
.postpad
) {
1494 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1495 oob
+= chip
->ecc
.postpad
;
1499 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1501 chip
->read_buf(mtd
, oob
, size
);
1507 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1508 * @mtd: mtd info structure
1509 * @chip: nand chip info structure
1510 * @buf: buffer to store read data
1511 * @oob_required: caller requires OOB data read to chip->oob_poi
1512 * @page: page number to read
1514 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1515 uint8_t *buf
, int oob_required
, int page
)
1517 int i
, eccsize
= chip
->ecc
.size
, ret
;
1518 int eccbytes
= chip
->ecc
.bytes
;
1519 int eccsteps
= chip
->ecc
.steps
;
1521 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1522 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1523 unsigned int max_bitflips
= 0;
1525 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1527 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1528 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1530 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1535 eccsteps
= chip
->ecc
.steps
;
1538 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1541 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1543 mtd
->ecc_stats
.failed
++;
1545 mtd
->ecc_stats
.corrected
+= stat
;
1546 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1549 return max_bitflips
;
1553 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1554 * @mtd: mtd info structure
1555 * @chip: nand chip info structure
1556 * @data_offs: offset of requested data within the page
1557 * @readlen: data length
1558 * @bufpoi: buffer to store read data
1559 * @page: page number to read
1561 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1562 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1565 int start_step
, end_step
, num_steps
, ret
;
1567 int data_col_addr
, i
, gaps
= 0;
1568 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1569 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1570 int index
, section
= 0;
1571 unsigned int max_bitflips
= 0;
1572 struct mtd_oob_region oobregion
= { };
1574 /* Column address within the page aligned to ECC size (256bytes) */
1575 start_step
= data_offs
/ chip
->ecc
.size
;
1576 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1577 num_steps
= end_step
- start_step
+ 1;
1578 index
= start_step
* chip
->ecc
.bytes
;
1580 /* Data size aligned to ECC ecc.size */
1581 datafrag_len
= num_steps
* chip
->ecc
.size
;
1582 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1584 data_col_addr
= start_step
* chip
->ecc
.size
;
1585 /* If we read not a page aligned data */
1586 if (data_col_addr
!= 0)
1587 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1589 p
= bufpoi
+ data_col_addr
;
1590 chip
->read_buf(mtd
, p
, datafrag_len
);
1593 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1594 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1597 * The performance is faster if we position offsets according to
1598 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1600 ret
= mtd_ooblayout_find_eccregion(mtd
, index
, §ion
, &oobregion
);
1604 if (oobregion
.length
< eccfrag_len
)
1608 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1609 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1612 * Send the command to read the particular ECC bytes take care
1613 * about buswidth alignment in read_buf.
1615 aligned_pos
= oobregion
.offset
& ~(busw
- 1);
1616 aligned_len
= eccfrag_len
;
1617 if (oobregion
.offset
& (busw
- 1))
1619 if ((oobregion
.offset
+ (num_steps
* chip
->ecc
.bytes
)) &
1623 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1624 mtd
->writesize
+ aligned_pos
, -1);
1625 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1628 ret
= mtd_ooblayout_get_eccbytes(mtd
, chip
->buffers
->ecccode
,
1629 chip
->oob_poi
, index
, eccfrag_len
);
1633 p
= bufpoi
+ data_col_addr
;
1634 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1637 stat
= chip
->ecc
.correct(mtd
, p
,
1638 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1639 if (stat
== -EBADMSG
&&
1640 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1641 /* check for empty pages with bitflips */
1642 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1643 &chip
->buffers
->ecccode
[i
],
1646 chip
->ecc
.strength
);
1650 mtd
->ecc_stats
.failed
++;
1652 mtd
->ecc_stats
.corrected
+= stat
;
1653 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1656 return max_bitflips
;
1660 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1661 * @mtd: mtd info structure
1662 * @chip: nand chip info structure
1663 * @buf: buffer to store read data
1664 * @oob_required: caller requires OOB data read to chip->oob_poi
1665 * @page: page number to read
1667 * Not for syndrome calculating ECC controllers which need a special oob layout.
1669 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1670 uint8_t *buf
, int oob_required
, int page
)
1672 int i
, eccsize
= chip
->ecc
.size
, ret
;
1673 int eccbytes
= chip
->ecc
.bytes
;
1674 int eccsteps
= chip
->ecc
.steps
;
1676 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1677 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1678 unsigned int max_bitflips
= 0;
1680 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1681 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1682 chip
->read_buf(mtd
, p
, eccsize
);
1683 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1685 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1687 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1692 eccsteps
= chip
->ecc
.steps
;
1695 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1698 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1699 if (stat
== -EBADMSG
&&
1700 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1701 /* check for empty pages with bitflips */
1702 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1703 &ecc_code
[i
], eccbytes
,
1705 chip
->ecc
.strength
);
1709 mtd
->ecc_stats
.failed
++;
1711 mtd
->ecc_stats
.corrected
+= stat
;
1712 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1715 return max_bitflips
;
1719 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1720 * @mtd: mtd info structure
1721 * @chip: nand chip info structure
1722 * @buf: buffer to store read data
1723 * @oob_required: caller requires OOB data read to chip->oob_poi
1724 * @page: page number to read
1726 * Hardware ECC for large page chips, require OOB to be read first. For this
1727 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1728 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1729 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1730 * the data area, by overwriting the NAND manufacturer bad block markings.
1732 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1733 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1735 int i
, eccsize
= chip
->ecc
.size
, ret
;
1736 int eccbytes
= chip
->ecc
.bytes
;
1737 int eccsteps
= chip
->ecc
.steps
;
1739 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1740 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1741 unsigned int max_bitflips
= 0;
1743 /* Read the OOB area first */
1744 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1745 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1746 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1748 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1753 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1756 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1757 chip
->read_buf(mtd
, p
, eccsize
);
1758 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1760 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1761 if (stat
== -EBADMSG
&&
1762 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1763 /* check for empty pages with bitflips */
1764 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1765 &ecc_code
[i
], eccbytes
,
1767 chip
->ecc
.strength
);
1771 mtd
->ecc_stats
.failed
++;
1773 mtd
->ecc_stats
.corrected
+= stat
;
1774 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1777 return max_bitflips
;
1781 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1782 * @mtd: mtd info structure
1783 * @chip: nand chip info structure
1784 * @buf: buffer to store read data
1785 * @oob_required: caller requires OOB data read to chip->oob_poi
1786 * @page: page number to read
1788 * The hw generator calculates the error syndrome automatically. Therefore we
1789 * need a special oob layout and handling.
1791 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1792 uint8_t *buf
, int oob_required
, int page
)
1794 int i
, eccsize
= chip
->ecc
.size
;
1795 int eccbytes
= chip
->ecc
.bytes
;
1796 int eccsteps
= chip
->ecc
.steps
;
1797 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1799 uint8_t *oob
= chip
->oob_poi
;
1800 unsigned int max_bitflips
= 0;
1802 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1805 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1806 chip
->read_buf(mtd
, p
, eccsize
);
1808 if (chip
->ecc
.prepad
) {
1809 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1810 oob
+= chip
->ecc
.prepad
;
1813 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1814 chip
->read_buf(mtd
, oob
, eccbytes
);
1815 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1819 if (chip
->ecc
.postpad
) {
1820 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1821 oob
+= chip
->ecc
.postpad
;
1824 if (stat
== -EBADMSG
&&
1825 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1826 /* check for empty pages with bitflips */
1827 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1831 chip
->ecc
.strength
);
1835 mtd
->ecc_stats
.failed
++;
1837 mtd
->ecc_stats
.corrected
+= stat
;
1838 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1842 /* Calculate remaining oob bytes */
1843 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1845 chip
->read_buf(mtd
, oob
, i
);
1847 return max_bitflips
;
1851 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1852 * @mtd: mtd info structure
1853 * @oob: oob destination address
1854 * @ops: oob ops structure
1855 * @len: size of oob to transfer
1857 static uint8_t *nand_transfer_oob(struct mtd_info
*mtd
, uint8_t *oob
,
1858 struct mtd_oob_ops
*ops
, size_t len
)
1860 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1863 switch (ops
->mode
) {
1865 case MTD_OPS_PLACE_OOB
:
1867 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1870 case MTD_OPS_AUTO_OOB
:
1871 ret
= mtd_ooblayout_get_databytes(mtd
, oob
, chip
->oob_poi
,
1883 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1884 * @mtd: MTD device structure
1885 * @retry_mode: the retry mode to use
1887 * Some vendors supply a special command to shift the Vt threshold, to be used
1888 * when there are too many bitflips in a page (i.e., ECC error). After setting
1889 * a new threshold, the host should retry reading the page.
1891 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1893 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1895 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1897 if (retry_mode
>= chip
->read_retries
)
1900 if (!chip
->setup_read_retry
)
1903 return chip
->setup_read_retry(mtd
, retry_mode
);
1907 * nand_do_read_ops - [INTERN] Read data with ECC
1908 * @mtd: MTD device structure
1909 * @from: offset to read from
1910 * @ops: oob ops structure
1912 * Internal function. Called with chip held.
1914 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1915 struct mtd_oob_ops
*ops
)
1917 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1918 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1920 uint32_t readlen
= ops
->len
;
1921 uint32_t oobreadlen
= ops
->ooblen
;
1922 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1924 uint8_t *bufpoi
, *oob
, *buf
;
1926 unsigned int max_bitflips
= 0;
1928 bool ecc_fail
= false;
1930 chipnr
= (int)(from
>> chip
->chip_shift
);
1931 chip
->select_chip(mtd
, chipnr
);
1933 realpage
= (int)(from
>> chip
->page_shift
);
1934 page
= realpage
& chip
->pagemask
;
1936 col
= (int)(from
& (mtd
->writesize
- 1));
1940 oob_required
= oob
? 1 : 0;
1943 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1945 bytes
= min(mtd
->writesize
- col
, readlen
);
1946 aligned
= (bytes
== mtd
->writesize
);
1950 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
1951 use_bufpoi
= !virt_addr_valid(buf
);
1955 /* Is the current page in the buffer? */
1956 if (realpage
!= chip
->pagebuf
|| oob
) {
1957 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1959 if (use_bufpoi
&& aligned
)
1960 pr_debug("%s: using read bounce buffer for buf@%p\n",
1964 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1967 * Now read the page into the buffer. Absent an error,
1968 * the read methods return max bitflips per ecc step.
1970 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1971 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1974 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1976 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1980 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1981 oob_required
, page
);
1984 /* Invalidate page cache */
1989 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1991 /* Transfer not aligned data */
1993 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1994 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1995 (ops
->mode
!= MTD_OPS_RAW
)) {
1996 chip
->pagebuf
= realpage
;
1997 chip
->pagebuf_bitflips
= ret
;
1999 /* Invalidate page cache */
2002 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
2005 if (unlikely(oob
)) {
2006 int toread
= min(oobreadlen
, max_oobsize
);
2009 oob
= nand_transfer_oob(mtd
,
2011 oobreadlen
-= toread
;
2015 if (chip
->options
& NAND_NEED_READRDY
) {
2016 /* Apply delay or wait for ready/busy pin */
2017 if (!chip
->dev_ready
)
2018 udelay(chip
->chip_delay
);
2020 nand_wait_ready(mtd
);
2023 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
2024 if (retry_mode
+ 1 < chip
->read_retries
) {
2026 ret
= nand_setup_read_retry(mtd
,
2031 /* Reset failures; retry */
2032 mtd
->ecc_stats
.failed
= ecc_failures
;
2035 /* No more retry modes; real failure */
2042 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
2044 max_bitflips
= max_t(unsigned int, max_bitflips
,
2045 chip
->pagebuf_bitflips
);
2050 /* Reset to retry mode 0 */
2052 ret
= nand_setup_read_retry(mtd
, 0);
2061 /* For subsequent reads align to page boundary */
2063 /* Increment page address */
2066 page
= realpage
& chip
->pagemask
;
2067 /* Check, if we cross a chip boundary */
2070 chip
->select_chip(mtd
, -1);
2071 chip
->select_chip(mtd
, chipnr
);
2074 chip
->select_chip(mtd
, -1);
2076 ops
->retlen
= ops
->len
- (size_t) readlen
;
2078 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
2086 return max_bitflips
;
2090 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
2091 * @mtd: MTD device structure
2092 * @from: offset to read from
2093 * @len: number of bytes to read
2094 * @retlen: pointer to variable to store the number of read bytes
2095 * @buf: the databuffer to put data
2097 * Get hold of the chip and call nand_do_read.
2099 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
2100 size_t *retlen
, uint8_t *buf
)
2102 struct mtd_oob_ops ops
;
2105 nand_get_device(mtd
, FL_READING
);
2106 memset(&ops
, 0, sizeof(ops
));
2109 ops
.mode
= MTD_OPS_PLACE_OOB
;
2110 ret
= nand_do_read_ops(mtd
, from
, &ops
);
2111 *retlen
= ops
.retlen
;
2112 nand_release_device(mtd
);
2117 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
2118 * @mtd: mtd info structure
2119 * @chip: nand chip info structure
2120 * @page: page number to read
2122 int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
2124 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
2125 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2128 EXPORT_SYMBOL(nand_read_oob_std
);
2131 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
2133 * @mtd: mtd info structure
2134 * @chip: nand chip info structure
2135 * @page: page number to read
2137 int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2140 int length
= mtd
->oobsize
;
2141 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2142 int eccsize
= chip
->ecc
.size
;
2143 uint8_t *bufpoi
= chip
->oob_poi
;
2144 int i
, toread
, sndrnd
= 0, pos
;
2146 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
2147 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
2149 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2150 if (mtd
->writesize
> 512)
2151 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
2153 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
2156 toread
= min_t(int, length
, chunk
);
2157 chip
->read_buf(mtd
, bufpoi
, toread
);
2162 chip
->read_buf(mtd
, bufpoi
, length
);
2166 EXPORT_SYMBOL(nand_read_oob_syndrome
);
2169 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
2170 * @mtd: mtd info structure
2171 * @chip: nand chip info structure
2172 * @page: page number to write
2174 int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
2177 const uint8_t *buf
= chip
->oob_poi
;
2178 int length
= mtd
->oobsize
;
2180 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
2181 chip
->write_buf(mtd
, buf
, length
);
2182 /* Send command to program the OOB data */
2183 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2185 status
= chip
->waitfunc(mtd
, chip
);
2187 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2189 EXPORT_SYMBOL(nand_write_oob_std
);
2192 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
2193 * with syndrome - only for large page flash
2194 * @mtd: mtd info structure
2195 * @chip: nand chip info structure
2196 * @page: page number to write
2198 int nand_write_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2201 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2202 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
2203 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
2204 const uint8_t *bufpoi
= chip
->oob_poi
;
2207 * data-ecc-data-ecc ... ecc-oob
2209 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2211 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
2212 pos
= steps
* (eccsize
+ chunk
);
2217 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
2218 for (i
= 0; i
< steps
; i
++) {
2220 if (mtd
->writesize
<= 512) {
2221 uint32_t fill
= 0xFFFFFFFF;
2225 int num
= min_t(int, len
, 4);
2226 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2231 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2232 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2236 len
= min_t(int, length
, chunk
);
2237 chip
->write_buf(mtd
, bufpoi
, len
);
2242 chip
->write_buf(mtd
, bufpoi
, length
);
2244 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2245 status
= chip
->waitfunc(mtd
, chip
);
2247 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2249 EXPORT_SYMBOL(nand_write_oob_syndrome
);
2252 * nand_do_read_oob - [INTERN] NAND read out-of-band
2253 * @mtd: MTD device structure
2254 * @from: offset to read from
2255 * @ops: oob operations description structure
2257 * NAND read out-of-band data from the spare area.
2259 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2260 struct mtd_oob_ops
*ops
)
2262 int page
, realpage
, chipnr
;
2263 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2264 struct mtd_ecc_stats stats
;
2265 int readlen
= ops
->ooblen
;
2267 uint8_t *buf
= ops
->oobbuf
;
2270 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2271 __func__
, (unsigned long long)from
, readlen
);
2273 stats
= mtd
->ecc_stats
;
2275 len
= mtd_oobavail(mtd
, ops
);
2277 if (unlikely(ops
->ooboffs
>= len
)) {
2278 pr_debug("%s: attempt to start read outside oob\n",
2283 /* Do not allow reads past end of device */
2284 if (unlikely(from
>= mtd
->size
||
2285 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2286 (from
>> chip
->page_shift
)) * len
)) {
2287 pr_debug("%s: attempt to read beyond end of device\n",
2292 chipnr
= (int)(from
>> chip
->chip_shift
);
2293 chip
->select_chip(mtd
, chipnr
);
2295 /* Shift to get page */
2296 realpage
= (int)(from
>> chip
->page_shift
);
2297 page
= realpage
& chip
->pagemask
;
2300 if (ops
->mode
== MTD_OPS_RAW
)
2301 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2303 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2308 len
= min(len
, readlen
);
2309 buf
= nand_transfer_oob(mtd
, buf
, ops
, len
);
2311 if (chip
->options
& NAND_NEED_READRDY
) {
2312 /* Apply delay or wait for ready/busy pin */
2313 if (!chip
->dev_ready
)
2314 udelay(chip
->chip_delay
);
2316 nand_wait_ready(mtd
);
2323 /* Increment page address */
2326 page
= realpage
& chip
->pagemask
;
2327 /* Check, if we cross a chip boundary */
2330 chip
->select_chip(mtd
, -1);
2331 chip
->select_chip(mtd
, chipnr
);
2334 chip
->select_chip(mtd
, -1);
2336 ops
->oobretlen
= ops
->ooblen
- readlen
;
2341 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2344 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2348 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2349 * @mtd: MTD device structure
2350 * @from: offset to read from
2351 * @ops: oob operation description structure
2353 * NAND read data and/or out-of-band data.
2355 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2356 struct mtd_oob_ops
*ops
)
2362 /* Do not allow reads past end of device */
2363 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2364 pr_debug("%s: attempt to read beyond end of device\n",
2369 if (ops
->mode
!= MTD_OPS_PLACE_OOB
&&
2370 ops
->mode
!= MTD_OPS_AUTO_OOB
&&
2371 ops
->mode
!= MTD_OPS_RAW
)
2374 nand_get_device(mtd
, FL_READING
);
2377 ret
= nand_do_read_oob(mtd
, from
, ops
);
2379 ret
= nand_do_read_ops(mtd
, from
, ops
);
2381 nand_release_device(mtd
);
2387 * nand_write_page_raw - [INTERN] raw page write function
2388 * @mtd: mtd info structure
2389 * @chip: nand chip info structure
2391 * @oob_required: must write chip->oob_poi to OOB
2392 * @page: page number to write
2394 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2396 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2397 const uint8_t *buf
, int oob_required
, int page
)
2399 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2401 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2407 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2408 * @mtd: mtd info structure
2409 * @chip: nand chip info structure
2411 * @oob_required: must write chip->oob_poi to OOB
2412 * @page: page number to write
2414 * We need a special oob layout and handling even when ECC isn't checked.
2416 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2417 struct nand_chip
*chip
,
2418 const uint8_t *buf
, int oob_required
,
2421 int eccsize
= chip
->ecc
.size
;
2422 int eccbytes
= chip
->ecc
.bytes
;
2423 uint8_t *oob
= chip
->oob_poi
;
2426 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2427 chip
->write_buf(mtd
, buf
, eccsize
);
2430 if (chip
->ecc
.prepad
) {
2431 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2432 oob
+= chip
->ecc
.prepad
;
2435 chip
->write_buf(mtd
, oob
, eccbytes
);
2438 if (chip
->ecc
.postpad
) {
2439 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2440 oob
+= chip
->ecc
.postpad
;
2444 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2446 chip
->write_buf(mtd
, oob
, size
);
2451 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2452 * @mtd: mtd info structure
2453 * @chip: nand chip info structure
2455 * @oob_required: must write chip->oob_poi to OOB
2456 * @page: page number to write
2458 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2459 const uint8_t *buf
, int oob_required
,
2462 int i
, eccsize
= chip
->ecc
.size
, ret
;
2463 int eccbytes
= chip
->ecc
.bytes
;
2464 int eccsteps
= chip
->ecc
.steps
;
2465 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2466 const uint8_t *p
= buf
;
2468 /* Software ECC calculation */
2469 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2470 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2472 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2477 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2481 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2482 * @mtd: mtd info structure
2483 * @chip: nand chip info structure
2485 * @oob_required: must write chip->oob_poi to OOB
2486 * @page: page number to write
2488 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2489 const uint8_t *buf
, int oob_required
,
2492 int i
, eccsize
= chip
->ecc
.size
, ret
;
2493 int eccbytes
= chip
->ecc
.bytes
;
2494 int eccsteps
= chip
->ecc
.steps
;
2495 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2496 const uint8_t *p
= buf
;
2498 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2499 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2500 chip
->write_buf(mtd
, p
, eccsize
);
2501 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2504 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2509 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2516 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2517 * @mtd: mtd info structure
2518 * @chip: nand chip info structure
2519 * @offset: column address of subpage within the page
2520 * @data_len: data length
2522 * @oob_required: must write chip->oob_poi to OOB
2523 * @page: page number to write
2525 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2526 struct nand_chip
*chip
, uint32_t offset
,
2527 uint32_t data_len
, const uint8_t *buf
,
2528 int oob_required
, int page
)
2530 uint8_t *oob_buf
= chip
->oob_poi
;
2531 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2532 int ecc_size
= chip
->ecc
.size
;
2533 int ecc_bytes
= chip
->ecc
.bytes
;
2534 int ecc_steps
= chip
->ecc
.steps
;
2535 uint32_t start_step
= offset
/ ecc_size
;
2536 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2537 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2540 for (step
= 0; step
< ecc_steps
; step
++) {
2541 /* configure controller for WRITE access */
2542 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2544 /* write data (untouched subpages already masked by 0xFF) */
2545 chip
->write_buf(mtd
, buf
, ecc_size
);
2547 /* mask ECC of un-touched subpages by padding 0xFF */
2548 if ((step
< start_step
) || (step
> end_step
))
2549 memset(ecc_calc
, 0xff, ecc_bytes
);
2551 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2553 /* mask OOB of un-touched subpages by padding 0xFF */
2554 /* if oob_required, preserve OOB metadata of written subpage */
2555 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2556 memset(oob_buf
, 0xff, oob_bytes
);
2559 ecc_calc
+= ecc_bytes
;
2560 oob_buf
+= oob_bytes
;
2563 /* copy calculated ECC for whole page to chip->buffer->oob */
2564 /* this include masked-value(0xFF) for unwritten subpages */
2565 ecc_calc
= chip
->buffers
->ecccalc
;
2566 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2571 /* write OOB buffer to NAND device */
2572 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2579 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2580 * @mtd: mtd info structure
2581 * @chip: nand chip info structure
2583 * @oob_required: must write chip->oob_poi to OOB
2584 * @page: page number to write
2586 * The hw generator calculates the error syndrome automatically. Therefore we
2587 * need a special oob layout and handling.
2589 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2590 struct nand_chip
*chip
,
2591 const uint8_t *buf
, int oob_required
,
2594 int i
, eccsize
= chip
->ecc
.size
;
2595 int eccbytes
= chip
->ecc
.bytes
;
2596 int eccsteps
= chip
->ecc
.steps
;
2597 const uint8_t *p
= buf
;
2598 uint8_t *oob
= chip
->oob_poi
;
2600 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2602 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2603 chip
->write_buf(mtd
, p
, eccsize
);
2605 if (chip
->ecc
.prepad
) {
2606 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2607 oob
+= chip
->ecc
.prepad
;
2610 chip
->ecc
.calculate(mtd
, p
, oob
);
2611 chip
->write_buf(mtd
, oob
, eccbytes
);
2614 if (chip
->ecc
.postpad
) {
2615 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2616 oob
+= chip
->ecc
.postpad
;
2620 /* Calculate remaining oob bytes */
2621 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2623 chip
->write_buf(mtd
, oob
, i
);
2629 * nand_write_page - [REPLACEABLE] write one page
2630 * @mtd: MTD device structure
2631 * @chip: NAND chip descriptor
2632 * @offset: address offset within the page
2633 * @data_len: length of actual data to be written
2634 * @buf: the data to write
2635 * @oob_required: must write chip->oob_poi to OOB
2636 * @page: page number to write
2637 * @cached: cached programming
2638 * @raw: use _raw version of write_page
2640 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2641 uint32_t offset
, int data_len
, const uint8_t *buf
,
2642 int oob_required
, int page
, int cached
, int raw
)
2644 int status
, subpage
;
2646 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2647 chip
->ecc
.write_subpage
)
2648 subpage
= offset
|| (data_len
< mtd
->writesize
);
2652 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2655 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2656 oob_required
, page
);
2658 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2659 buf
, oob_required
, page
);
2661 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2668 * Cached progamming disabled for now. Not sure if it's worth the
2669 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2673 if (!cached
|| !NAND_HAS_CACHEPROG(chip
)) {
2675 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2676 status
= chip
->waitfunc(mtd
, chip
);
2678 * See if operation failed and additional status checks are
2681 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2682 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2685 if (status
& NAND_STATUS_FAIL
)
2688 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2689 status
= chip
->waitfunc(mtd
, chip
);
2696 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2697 * @mtd: MTD device structure
2698 * @oob: oob data buffer
2699 * @len: oob data write length
2700 * @ops: oob ops structure
2702 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2703 struct mtd_oob_ops
*ops
)
2705 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2709 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2710 * data from a previous OOB read.
2712 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2714 switch (ops
->mode
) {
2716 case MTD_OPS_PLACE_OOB
:
2718 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2721 case MTD_OPS_AUTO_OOB
:
2722 ret
= mtd_ooblayout_set_databytes(mtd
, oob
, chip
->oob_poi
,
2733 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2736 * nand_do_write_ops - [INTERN] NAND write with ECC
2737 * @mtd: MTD device structure
2738 * @to: offset to write to
2739 * @ops: oob operations description structure
2741 * NAND write with ECC.
2743 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2744 struct mtd_oob_ops
*ops
)
2746 int chipnr
, realpage
, page
, blockmask
, column
;
2747 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2748 uint32_t writelen
= ops
->len
;
2750 uint32_t oobwritelen
= ops
->ooblen
;
2751 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2753 uint8_t *oob
= ops
->oobbuf
;
2754 uint8_t *buf
= ops
->datbuf
;
2756 int oob_required
= oob
? 1 : 0;
2762 /* Reject writes, which are not page aligned */
2763 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2764 pr_notice("%s: attempt to write non page aligned data\n",
2769 column
= to
& (mtd
->writesize
- 1);
2771 chipnr
= (int)(to
>> chip
->chip_shift
);
2772 chip
->select_chip(mtd
, chipnr
);
2774 /* Check, if it is write protected */
2775 if (nand_check_wp(mtd
)) {
2780 realpage
= (int)(to
>> chip
->page_shift
);
2781 page
= realpage
& chip
->pagemask
;
2782 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2784 /* Invalidate the page cache, when we write to the cached page */
2785 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2786 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2789 /* Don't allow multipage oob writes with offset */
2790 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2796 int bytes
= mtd
->writesize
;
2797 int cached
= writelen
> bytes
&& page
!= blockmask
;
2798 uint8_t *wbuf
= buf
;
2800 int part_pagewr
= (column
|| writelen
< mtd
->writesize
);
2804 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2805 use_bufpoi
= !virt_addr_valid(buf
);
2809 /* Partial page write?, or need to use bounce buffer */
2811 pr_debug("%s: using write bounce buffer for buf@%p\n",
2815 bytes
= min_t(int, bytes
- column
, writelen
);
2817 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2818 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2819 wbuf
= chip
->buffers
->databuf
;
2822 if (unlikely(oob
)) {
2823 size_t len
= min(oobwritelen
, oobmaxlen
);
2824 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2827 /* We still need to erase leftover OOB data */
2828 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2830 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2831 oob_required
, page
, cached
,
2832 (ops
->mode
== MTD_OPS_RAW
));
2844 page
= realpage
& chip
->pagemask
;
2845 /* Check, if we cross a chip boundary */
2848 chip
->select_chip(mtd
, -1);
2849 chip
->select_chip(mtd
, chipnr
);
2853 ops
->retlen
= ops
->len
- writelen
;
2855 ops
->oobretlen
= ops
->ooblen
;
2858 chip
->select_chip(mtd
, -1);
2863 * panic_nand_write - [MTD Interface] NAND write with ECC
2864 * @mtd: MTD device structure
2865 * @to: offset to write to
2866 * @len: number of bytes to write
2867 * @retlen: pointer to variable to store the number of written bytes
2868 * @buf: the data to write
2870 * NAND write with ECC. Used when performing writes in interrupt context, this
2871 * may for example be called by mtdoops when writing an oops while in panic.
2873 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2874 size_t *retlen
, const uint8_t *buf
)
2876 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2877 struct mtd_oob_ops ops
;
2880 /* Wait for the device to get ready */
2881 panic_nand_wait(mtd
, chip
, 400);
2883 /* Grab the device */
2884 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2886 memset(&ops
, 0, sizeof(ops
));
2888 ops
.datbuf
= (uint8_t *)buf
;
2889 ops
.mode
= MTD_OPS_PLACE_OOB
;
2891 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2893 *retlen
= ops
.retlen
;
2898 * nand_write - [MTD Interface] NAND write with ECC
2899 * @mtd: MTD device structure
2900 * @to: offset to write to
2901 * @len: number of bytes to write
2902 * @retlen: pointer to variable to store the number of written bytes
2903 * @buf: the data to write
2905 * NAND write with ECC.
2907 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2908 size_t *retlen
, const uint8_t *buf
)
2910 struct mtd_oob_ops ops
;
2913 nand_get_device(mtd
, FL_WRITING
);
2914 memset(&ops
, 0, sizeof(ops
));
2916 ops
.datbuf
= (uint8_t *)buf
;
2917 ops
.mode
= MTD_OPS_PLACE_OOB
;
2918 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2919 *retlen
= ops
.retlen
;
2920 nand_release_device(mtd
);
2925 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2926 * @mtd: MTD device structure
2927 * @to: offset to write to
2928 * @ops: oob operation description structure
2930 * NAND write out-of-band.
2932 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2933 struct mtd_oob_ops
*ops
)
2935 int chipnr
, page
, status
, len
;
2936 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2938 pr_debug("%s: to = 0x%08x, len = %i\n",
2939 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2941 len
= mtd_oobavail(mtd
, ops
);
2943 /* Do not allow write past end of page */
2944 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2945 pr_debug("%s: attempt to write past end of page\n",
2950 if (unlikely(ops
->ooboffs
>= len
)) {
2951 pr_debug("%s: attempt to start write outside oob\n",
2956 /* Do not allow write past end of device */
2957 if (unlikely(to
>= mtd
->size
||
2958 ops
->ooboffs
+ ops
->ooblen
>
2959 ((mtd
->size
>> chip
->page_shift
) -
2960 (to
>> chip
->page_shift
)) * len
)) {
2961 pr_debug("%s: attempt to write beyond end of device\n",
2966 chipnr
= (int)(to
>> chip
->chip_shift
);
2967 chip
->select_chip(mtd
, chipnr
);
2969 /* Shift to get page */
2970 page
= (int)(to
>> chip
->page_shift
);
2973 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2974 * of my DiskOnChip 2000 test units) will clear the whole data page too
2975 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2976 * it in the doc2000 driver in August 1999. dwmw2.
2980 /* Check, if it is write protected */
2981 if (nand_check_wp(mtd
)) {
2982 chip
->select_chip(mtd
, -1);
2986 /* Invalidate the page cache, if we write to the cached page */
2987 if (page
== chip
->pagebuf
)
2990 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2992 if (ops
->mode
== MTD_OPS_RAW
)
2993 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2995 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2997 chip
->select_chip(mtd
, -1);
3002 ops
->oobretlen
= ops
->ooblen
;
3008 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
3009 * @mtd: MTD device structure
3010 * @to: offset to write to
3011 * @ops: oob operation description structure
3013 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
3014 struct mtd_oob_ops
*ops
)
3016 int ret
= -ENOTSUPP
;
3020 /* Do not allow writes past end of device */
3021 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
3022 pr_debug("%s: attempt to write beyond end of device\n",
3027 nand_get_device(mtd
, FL_WRITING
);
3029 switch (ops
->mode
) {
3030 case MTD_OPS_PLACE_OOB
:
3031 case MTD_OPS_AUTO_OOB
:
3040 ret
= nand_do_write_oob(mtd
, to
, ops
);
3042 ret
= nand_do_write_ops(mtd
, to
, ops
);
3045 nand_release_device(mtd
);
3050 * single_erase - [GENERIC] NAND standard block erase command function
3051 * @mtd: MTD device structure
3052 * @page: the page address of the block which will be erased
3054 * Standard erase command for NAND chips. Returns NAND status.
3056 static int single_erase(struct mtd_info
*mtd
, int page
)
3058 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3059 /* Send commands to erase a block */
3060 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
3061 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
3063 return chip
->waitfunc(mtd
, chip
);
3067 * nand_erase - [MTD Interface] erase block(s)
3068 * @mtd: MTD device structure
3069 * @instr: erase instruction
3071 * Erase one ore more blocks.
3073 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
3075 return nand_erase_nand(mtd
, instr
, 0);
3079 * nand_erase_nand - [INTERN] erase block(s)
3080 * @mtd: MTD device structure
3081 * @instr: erase instruction
3082 * @allowbbt: allow erasing the bbt area
3084 * Erase one ore more blocks.
3086 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
3089 int page
, status
, pages_per_block
, ret
, chipnr
;
3090 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3093 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3094 __func__
, (unsigned long long)instr
->addr
,
3095 (unsigned long long)instr
->len
);
3097 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
3100 /* Grab the lock and see if the device is available */
3101 nand_get_device(mtd
, FL_ERASING
);
3103 /* Shift to get first page */
3104 page
= (int)(instr
->addr
>> chip
->page_shift
);
3105 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
3107 /* Calculate pages in each block */
3108 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
3110 /* Select the NAND device */
3111 chip
->select_chip(mtd
, chipnr
);
3113 /* Check, if it is write protected */
3114 if (nand_check_wp(mtd
)) {
3115 pr_debug("%s: device is write protected!\n",
3117 instr
->state
= MTD_ERASE_FAILED
;
3121 /* Loop through the pages */
3124 instr
->state
= MTD_ERASING
;
3127 /* Check if we have a bad block, we do not erase bad blocks! */
3128 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
3129 chip
->page_shift
, allowbbt
)) {
3130 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3132 instr
->state
= MTD_ERASE_FAILED
;
3137 * Invalidate the page cache, if we erase the block which
3138 * contains the current cached page.
3140 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
3141 (page
+ pages_per_block
))
3144 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
3147 * See if operation failed and additional status checks are
3150 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
3151 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
3154 /* See if block erase succeeded */
3155 if (status
& NAND_STATUS_FAIL
) {
3156 pr_debug("%s: failed erase, page 0x%08x\n",
3158 instr
->state
= MTD_ERASE_FAILED
;
3160 ((loff_t
)page
<< chip
->page_shift
);
3164 /* Increment page address and decrement length */
3165 len
-= (1ULL << chip
->phys_erase_shift
);
3166 page
+= pages_per_block
;
3168 /* Check, if we cross a chip boundary */
3169 if (len
&& !(page
& chip
->pagemask
)) {
3171 chip
->select_chip(mtd
, -1);
3172 chip
->select_chip(mtd
, chipnr
);
3175 instr
->state
= MTD_ERASE_DONE
;
3179 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
3181 /* Deselect and wake up anyone waiting on the device */
3182 chip
->select_chip(mtd
, -1);
3183 nand_release_device(mtd
);
3185 /* Do call back function */
3187 mtd_erase_callback(instr
);
3189 /* Return more or less happy */
3194 * nand_sync - [MTD Interface] sync
3195 * @mtd: MTD device structure
3197 * Sync is actually a wait for chip ready function.
3199 static void nand_sync(struct mtd_info
*mtd
)
3201 pr_debug("%s: called\n", __func__
);
3203 /* Grab the lock and see if the device is available */
3204 nand_get_device(mtd
, FL_SYNCING
);
3205 /* Release it and go back */
3206 nand_release_device(mtd
);
3210 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3211 * @mtd: MTD device structure
3212 * @offs: offset relative to mtd start
3214 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
3216 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3217 int chipnr
= (int)(offs
>> chip
->chip_shift
);
3220 /* Select the NAND device */
3221 nand_get_device(mtd
, FL_READING
);
3222 chip
->select_chip(mtd
, chipnr
);
3224 ret
= nand_block_checkbad(mtd
, offs
, 0);
3226 chip
->select_chip(mtd
, -1);
3227 nand_release_device(mtd
);
3233 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3234 * @mtd: MTD device structure
3235 * @ofs: offset relative to mtd start
3237 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3241 ret
= nand_block_isbad(mtd
, ofs
);
3243 /* If it was bad already, return success and do nothing */
3249 return nand_block_markbad_lowlevel(mtd
, ofs
);
3253 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3254 * @mtd: MTD device structure
3255 * @chip: nand chip info structure
3256 * @addr: feature address.
3257 * @subfeature_param: the subfeature parameters, a four bytes array.
3259 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3260 int addr
, uint8_t *subfeature_param
)
3265 if (!chip
->onfi_version
||
3266 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3267 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3270 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3271 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3272 chip
->write_byte(mtd
, subfeature_param
[i
]);
3274 status
= chip
->waitfunc(mtd
, chip
);
3275 if (status
& NAND_STATUS_FAIL
)
3281 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3282 * @mtd: MTD device structure
3283 * @chip: nand chip info structure
3284 * @addr: feature address.
3285 * @subfeature_param: the subfeature parameters, a four bytes array.
3287 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3288 int addr
, uint8_t *subfeature_param
)
3292 if (!chip
->onfi_version
||
3293 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3294 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3297 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3298 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3299 *subfeature_param
++ = chip
->read_byte(mtd
);
3304 * nand_suspend - [MTD Interface] Suspend the NAND flash
3305 * @mtd: MTD device structure
3307 static int nand_suspend(struct mtd_info
*mtd
)
3309 return nand_get_device(mtd
, FL_PM_SUSPENDED
);
3313 * nand_resume - [MTD Interface] Resume the NAND flash
3314 * @mtd: MTD device structure
3316 static void nand_resume(struct mtd_info
*mtd
)
3318 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3320 if (chip
->state
== FL_PM_SUSPENDED
)
3321 nand_release_device(mtd
);
3323 pr_err("%s called for a chip which is not in suspended state\n",
3328 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3329 * prevent further operations
3330 * @mtd: MTD device structure
3332 static void nand_shutdown(struct mtd_info
*mtd
)
3334 nand_get_device(mtd
, FL_PM_SUSPENDED
);
3337 /* Set default functions */
3338 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
3340 /* check for proper chip_delay setup, set 20us if not */
3341 if (!chip
->chip_delay
)
3342 chip
->chip_delay
= 20;
3344 /* check, if a user supplied command function given */
3345 if (chip
->cmdfunc
== NULL
)
3346 chip
->cmdfunc
= nand_command
;
3348 /* check, if a user supplied wait function given */
3349 if (chip
->waitfunc
== NULL
)
3350 chip
->waitfunc
= nand_wait
;
3352 if (!chip
->select_chip
)
3353 chip
->select_chip
= nand_select_chip
;
3355 /* set for ONFI nand */
3356 if (!chip
->onfi_set_features
)
3357 chip
->onfi_set_features
= nand_onfi_set_features
;
3358 if (!chip
->onfi_get_features
)
3359 chip
->onfi_get_features
= nand_onfi_get_features
;
3361 /* If called twice, pointers that depend on busw may need to be reset */
3362 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3363 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3364 if (!chip
->read_word
)
3365 chip
->read_word
= nand_read_word
;
3366 if (!chip
->block_bad
)
3367 chip
->block_bad
= nand_block_bad
;
3368 if (!chip
->block_markbad
)
3369 chip
->block_markbad
= nand_default_block_markbad
;
3370 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3371 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3372 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3373 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3374 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3375 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3376 if (!chip
->scan_bbt
)
3377 chip
->scan_bbt
= nand_default_bbt
;
3379 if (!chip
->controller
) {
3380 chip
->controller
= &chip
->hwcontrol
;
3381 nand_hw_control_init(chip
->controller
);
3386 /* Sanitize ONFI strings so we can safely print them */
3387 static void sanitize_string(uint8_t *s
, size_t len
)
3391 /* Null terminate */
3394 /* Remove non printable chars */
3395 for (i
= 0; i
< len
- 1; i
++) {
3396 if (s
[i
] < ' ' || s
[i
] > 127)
3400 /* Remove trailing spaces */
3404 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3409 for (i
= 0; i
< 8; i
++)
3410 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3416 /* Parse the Extended Parameter Page. */
3417 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3418 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3420 struct onfi_ext_param_page
*ep
;
3421 struct onfi_ext_section
*s
;
3422 struct onfi_ext_ecc_info
*ecc
;
3428 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3429 ep
= kmalloc(len
, GFP_KERNEL
);
3433 /* Send our own NAND_CMD_PARAM. */
3434 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3436 /* Use the Change Read Column command to skip the ONFI param pages. */
3437 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3438 sizeof(*p
) * p
->num_of_param_pages
, -1);
3440 /* Read out the Extended Parameter Page. */
3441 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3442 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3443 != le16_to_cpu(ep
->crc
))) {
3444 pr_debug("fail in the CRC.\n");
3449 * Check the signature.
3450 * Do not strictly follow the ONFI spec, maybe changed in future.
3452 if (strncmp(ep
->sig
, "EPPS", 4)) {
3453 pr_debug("The signature is invalid.\n");
3457 /* find the ECC section. */
3458 cursor
= (uint8_t *)(ep
+ 1);
3459 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3460 s
= ep
->sections
+ i
;
3461 if (s
->type
== ONFI_SECTION_TYPE_2
)
3463 cursor
+= s
->length
* 16;
3465 if (i
== ONFI_EXT_SECTION_MAX
) {
3466 pr_debug("We can not find the ECC section.\n");
3470 /* get the info we want. */
3471 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3473 if (!ecc
->codeword_size
) {
3474 pr_debug("Invalid codeword size\n");
3478 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3479 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3487 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3489 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3490 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3492 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3497 * Configure chip properties from Micron vendor-specific ONFI table
3499 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3500 struct nand_onfi_params
*p
)
3502 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3504 if (le16_to_cpu(p
->vendor_revision
) < 1)
3507 chip
->read_retries
= micron
->read_retry_options
;
3508 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3512 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3514 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3517 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3521 /* Try ONFI for unknown chip or LP */
3522 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3523 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3524 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3527 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3528 for (i
= 0; i
< 3; i
++) {
3529 for (j
= 0; j
< sizeof(*p
); j
++)
3530 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3531 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3532 le16_to_cpu(p
->crc
)) {
3538 pr_err("Could not find valid ONFI parameter page; aborting\n");
3543 val
= le16_to_cpu(p
->revision
);
3545 chip
->onfi_version
= 23;
3546 else if (val
& (1 << 4))
3547 chip
->onfi_version
= 22;
3548 else if (val
& (1 << 3))
3549 chip
->onfi_version
= 21;
3550 else if (val
& (1 << 2))
3551 chip
->onfi_version
= 20;
3552 else if (val
& (1 << 1))
3553 chip
->onfi_version
= 10;
3555 if (!chip
->onfi_version
) {
3556 pr_info("unsupported ONFI version: %d\n", val
);
3560 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3561 sanitize_string(p
->model
, sizeof(p
->model
));
3563 mtd
->name
= p
->model
;
3565 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3568 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3569 * (don't ask me who thought of this...). MTD assumes that these
3570 * dimensions will be power-of-2, so just truncate the remaining area.
3572 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3573 mtd
->erasesize
*= mtd
->writesize
;
3575 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3577 /* See erasesize comment */
3578 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3579 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3580 chip
->bits_per_cell
= p
->bits_per_cell
;
3582 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3583 *busw
= NAND_BUSWIDTH_16
;
3587 if (p
->ecc_bits
!= 0xff) {
3588 chip
->ecc_strength_ds
= p
->ecc_bits
;
3589 chip
->ecc_step_ds
= 512;
3590 } else if (chip
->onfi_version
>= 21 &&
3591 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3594 * The nand_flash_detect_ext_param_page() uses the
3595 * Change Read Column command which maybe not supported
3596 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3597 * now. We do not replace user supplied command function.
3599 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3600 chip
->cmdfunc
= nand_command_lp
;
3602 /* The Extended Parameter Page is supported since ONFI 2.1. */
3603 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3604 pr_warn("Failed to detect ONFI extended param page\n");
3606 pr_warn("Could not retrieve ONFI ECC requirements\n");
3609 if (p
->jedec_id
== NAND_MFR_MICRON
)
3610 nand_onfi_detect_micron(chip
, p
);
3616 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3618 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3621 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3622 struct jedec_ecc_info
*ecc
;
3626 /* Try JEDEC for unknown chip or LP */
3627 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3628 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3629 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3630 chip
->read_byte(mtd
) != 'C')
3633 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3634 for (i
= 0; i
< 3; i
++) {
3635 for (j
= 0; j
< sizeof(*p
); j
++)
3636 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3638 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3639 le16_to_cpu(p
->crc
))
3644 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3649 val
= le16_to_cpu(p
->revision
);
3651 chip
->jedec_version
= 10;
3652 else if (val
& (1 << 1))
3653 chip
->jedec_version
= 1; /* vendor specific version */
3655 if (!chip
->jedec_version
) {
3656 pr_info("unsupported JEDEC version: %d\n", val
);
3660 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3661 sanitize_string(p
->model
, sizeof(p
->model
));
3663 mtd
->name
= p
->model
;
3665 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3667 /* Please reference to the comment for nand_flash_detect_onfi. */
3668 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3669 mtd
->erasesize
*= mtd
->writesize
;
3671 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3673 /* Please reference to the comment for nand_flash_detect_onfi. */
3674 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3675 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3676 chip
->bits_per_cell
= p
->bits_per_cell
;
3678 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3679 *busw
= NAND_BUSWIDTH_16
;
3684 ecc
= &p
->ecc_info
[0];
3686 if (ecc
->codeword_size
>= 9) {
3687 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3688 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3690 pr_warn("Invalid codeword size\n");
3697 * nand_id_has_period - Check if an ID string has a given wraparound period
3698 * @id_data: the ID string
3699 * @arrlen: the length of the @id_data array
3700 * @period: the period of repitition
3702 * Check if an ID string is repeated within a given sequence of bytes at
3703 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3704 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3705 * if the repetition has a period of @period; otherwise, returns zero.
3707 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3710 for (i
= 0; i
< period
; i
++)
3711 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3712 if (id_data
[i
] != id_data
[j
])
3718 * nand_id_len - Get the length of an ID string returned by CMD_READID
3719 * @id_data: the ID string
3720 * @arrlen: the length of the @id_data array
3722 * Returns the length of the ID string, according to known wraparound/trailing
3723 * zero patterns. If no pattern exists, returns the length of the array.
3725 static int nand_id_len(u8
*id_data
, int arrlen
)
3727 int last_nonzero
, period
;
3729 /* Find last non-zero byte */
3730 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3731 if (id_data
[last_nonzero
])
3735 if (last_nonzero
< 0)
3738 /* Calculate wraparound period */
3739 for (period
= 1; period
< arrlen
; period
++)
3740 if (nand_id_has_period(id_data
, arrlen
, period
))
3743 /* There's a repeated pattern */
3744 if (period
< arrlen
)
3747 /* There are trailing zeros */
3748 if (last_nonzero
< arrlen
- 1)
3749 return last_nonzero
+ 1;
3751 /* No pattern detected */
3755 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3756 static int nand_get_bits_per_cell(u8 cellinfo
)
3760 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3761 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3766 * Many new NAND share similar device ID codes, which represent the size of the
3767 * chip. The rest of the parameters must be decoded according to generic or
3768 * manufacturer-specific "extended ID" decoding patterns.
3770 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3771 u8 id_data
[8], int *busw
)
3774 /* The 3rd id byte holds MLC / multichip data */
3775 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3776 /* The 4th id byte is the important one */
3779 id_len
= nand_id_len(id_data
, 8);
3782 * Field definitions are in the following datasheets:
3783 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3784 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3785 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3787 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3788 * ID to decide what to do.
3790 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3791 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3793 mtd
->writesize
= 2048 << (extid
& 0x03);
3796 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3816 default: /* Other cases are "reserved" (unknown) */
3817 mtd
->oobsize
= 1024;
3821 /* Calc blocksize */
3822 mtd
->erasesize
= (128 * 1024) <<
3823 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3825 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3826 !nand_is_slc(chip
)) {
3830 mtd
->writesize
= 2048 << (extid
& 0x03);
3833 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3857 /* Calc blocksize */
3858 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3860 mtd
->erasesize
= (128 * 1024) << tmp
;
3861 else if (tmp
== 0x03)
3862 mtd
->erasesize
= 768 * 1024;
3864 mtd
->erasesize
= (64 * 1024) << tmp
;
3868 mtd
->writesize
= 1024 << (extid
& 0x03);
3871 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3872 (mtd
->writesize
>> 9);
3874 /* Calc blocksize. Blocksize is multiples of 64KiB */
3875 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3877 /* Get buswidth information */
3878 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3881 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3882 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3884 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3886 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3888 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3889 nand_is_slc(chip
) &&
3890 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3891 !(id_data
[4] & 0x80) /* !BENAND */) {
3892 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3899 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3900 * decodes a matching ID table entry and assigns the MTD size parameters for
3903 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3904 struct nand_flash_dev
*type
, u8 id_data
[8],
3907 int maf_id
= id_data
[0];
3909 mtd
->erasesize
= type
->erasesize
;
3910 mtd
->writesize
= type
->pagesize
;
3911 mtd
->oobsize
= mtd
->writesize
/ 32;
3912 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3914 /* All legacy ID NAND are small-page, SLC */
3915 chip
->bits_per_cell
= 1;
3918 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3919 * some Spansion chips have erasesize that conflicts with size
3920 * listed in nand_ids table.
3921 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3923 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3924 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3925 && mtd
->writesize
== 512) {
3926 mtd
->erasesize
= 128 * 1024;
3927 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3932 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3933 * heuristic patterns using various detected parameters (e.g., manufacturer,
3934 * page size, cell-type information).
3936 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3937 struct nand_chip
*chip
, u8 id_data
[8])
3939 int maf_id
= id_data
[0];
3941 /* Set the bad block position */
3942 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3943 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3945 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3948 * Bad block marker is stored in the last page of each block on Samsung
3949 * and Hynix MLC devices; stored in first two pages of each block on
3950 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3951 * AMD/Spansion, and Macronix. All others scan only the first page.
3953 if (!nand_is_slc(chip
) &&
3954 (maf_id
== NAND_MFR_SAMSUNG
||
3955 maf_id
== NAND_MFR_HYNIX
))
3956 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3957 else if ((nand_is_slc(chip
) &&
3958 (maf_id
== NAND_MFR_SAMSUNG
||
3959 maf_id
== NAND_MFR_HYNIX
||
3960 maf_id
== NAND_MFR_TOSHIBA
||
3961 maf_id
== NAND_MFR_AMD
||
3962 maf_id
== NAND_MFR_MACRONIX
)) ||
3963 (mtd
->writesize
== 2048 &&
3964 maf_id
== NAND_MFR_MICRON
))
3965 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3968 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3970 return type
->id_len
;
3973 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3974 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3976 if (!strncmp(type
->id
, id_data
, type
->id_len
)) {
3977 mtd
->writesize
= type
->pagesize
;
3978 mtd
->erasesize
= type
->erasesize
;
3979 mtd
->oobsize
= type
->oobsize
;
3981 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3982 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3983 chip
->options
|= type
->options
;
3984 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3985 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3986 chip
->onfi_timing_mode_default
=
3987 type
->onfi_timing_mode_default
;
3989 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3992 mtd
->name
= type
->name
;
4000 * Get the flash and manufacturer id and lookup if the type is supported.
4002 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
4003 struct nand_chip
*chip
,
4004 int *maf_id
, int *dev_id
,
4005 struct nand_flash_dev
*type
)
4011 /* Select the device */
4012 chip
->select_chip(mtd
, 0);
4015 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
4020 /* Send the command for reading device ID */
4021 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4023 /* Read manufacturer and device IDs */
4024 *maf_id
= chip
->read_byte(mtd
);
4025 *dev_id
= chip
->read_byte(mtd
);
4028 * Try again to make sure, as some systems the bus-hold or other
4029 * interface concerns can cause random data which looks like a
4030 * possibly credible NAND flash to appear. If the two results do
4031 * not match, ignore the device completely.
4034 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4036 /* Read entire ID string */
4037 for (i
= 0; i
< 8; i
++)
4038 id_data
[i
] = chip
->read_byte(mtd
);
4040 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
4041 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4042 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
4043 return ERR_PTR(-ENODEV
);
4047 type
= nand_flash_ids
;
4049 for (; type
->name
!= NULL
; type
++) {
4050 if (is_full_id_nand(type
)) {
4051 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
4053 } else if (*dev_id
== type
->dev_id
) {
4058 chip
->onfi_version
= 0;
4059 if (!type
->name
|| !type
->pagesize
) {
4060 /* Check if the chip is ONFI compliant */
4061 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
4064 /* Check if the chip is JEDEC compliant */
4065 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
4070 return ERR_PTR(-ENODEV
);
4073 mtd
->name
= type
->name
;
4075 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
4077 if (!type
->pagesize
) {
4078 /* Decode parameters from extended ID */
4079 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
4081 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
4083 /* Get chip options */
4084 chip
->options
|= type
->options
;
4087 * Check if chip is not a Samsung device. Do not clear the
4088 * options for chips which do not have an extended id.
4090 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
4091 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
4094 /* Try to identify manufacturer */
4095 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
4096 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
4100 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
4101 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
4102 chip
->options
|= busw
;
4103 nand_set_defaults(chip
, busw
);
4104 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
4106 * Check, if buswidth is correct. Hardware drivers should set
4109 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4111 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
4112 pr_warn("bus width %d instead %d bit\n",
4113 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
4115 return ERR_PTR(-EINVAL
);
4118 nand_decode_bbm_options(mtd
, chip
, id_data
);
4120 /* Calculate the address shift from the page size */
4121 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
4122 /* Convert chipsize to number of pages per chip -1 */
4123 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
4125 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
4126 ffs(mtd
->erasesize
) - 1;
4127 if (chip
->chipsize
& 0xffffffff)
4128 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
4130 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
4131 chip
->chip_shift
+= 32 - 1;
4134 chip
->badblockbits
= 8;
4135 chip
->erase
= single_erase
;
4137 /* Do not replace user supplied command function! */
4138 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
4139 chip
->cmdfunc
= nand_command_lp
;
4141 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4144 if (chip
->onfi_version
)
4145 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
4146 chip
->onfi_params
.model
);
4147 else if (chip
->jedec_version
)
4148 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
4149 chip
->jedec_params
.model
);
4151 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
4154 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4155 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
4156 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
4160 static const char * const nand_ecc_modes
[] = {
4161 [NAND_ECC_NONE
] = "none",
4162 [NAND_ECC_SOFT
] = "soft",
4163 [NAND_ECC_HW
] = "hw",
4164 [NAND_ECC_HW_SYNDROME
] = "hw_syndrome",
4165 [NAND_ECC_HW_OOB_FIRST
] = "hw_oob_first",
4168 static int of_get_nand_ecc_mode(struct device_node
*np
)
4173 err
= of_property_read_string(np
, "nand-ecc-mode", &pm
);
4177 for (i
= 0; i
< ARRAY_SIZE(nand_ecc_modes
); i
++)
4178 if (!strcasecmp(pm
, nand_ecc_modes
[i
]))
4182 * For backward compatibility we support few obsoleted values that don't
4183 * have their mappings into nand_ecc_modes_t anymore (they were merged
4184 * with other enums).
4186 if (!strcasecmp(pm
, "soft_bch"))
4187 return NAND_ECC_SOFT
;
4192 static const char * const nand_ecc_algos
[] = {
4193 [NAND_ECC_HAMMING
] = "hamming",
4194 [NAND_ECC_BCH
] = "bch",
4197 static int of_get_nand_ecc_algo(struct device_node
*np
)
4202 err
= of_property_read_string(np
, "nand-ecc-algo", &pm
);
4204 for (i
= NAND_ECC_HAMMING
; i
< ARRAY_SIZE(nand_ecc_algos
); i
++)
4205 if (!strcasecmp(pm
, nand_ecc_algos
[i
]))
4211 * For backward compatibility we also read "nand-ecc-mode" checking
4212 * for some obsoleted values that were specifying ECC algorithm.
4214 err
= of_property_read_string(np
, "nand-ecc-mode", &pm
);
4218 if (!strcasecmp(pm
, "soft"))
4219 return NAND_ECC_HAMMING
;
4220 else if (!strcasecmp(pm
, "soft_bch"))
4221 return NAND_ECC_BCH
;
4226 static int of_get_nand_ecc_step_size(struct device_node
*np
)
4231 ret
= of_property_read_u32(np
, "nand-ecc-step-size", &val
);
4232 return ret
? ret
: val
;
4235 static int of_get_nand_ecc_strength(struct device_node
*np
)
4240 ret
= of_property_read_u32(np
, "nand-ecc-strength", &val
);
4241 return ret
? ret
: val
;
4244 static int of_get_nand_bus_width(struct device_node
*np
)
4248 if (of_property_read_u32(np
, "nand-bus-width", &val
))
4260 static bool of_get_nand_on_flash_bbt(struct device_node
*np
)
4262 return of_property_read_bool(np
, "nand-on-flash-bbt");
4265 static int nand_dt_init(struct nand_chip
*chip
)
4267 struct device_node
*dn
= nand_get_flash_node(chip
);
4268 int ecc_mode
, ecc_algo
, ecc_strength
, ecc_step
;
4273 if (of_get_nand_bus_width(dn
) == 16)
4274 chip
->options
|= NAND_BUSWIDTH_16
;
4276 if (of_get_nand_on_flash_bbt(dn
))
4277 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
4279 ecc_mode
= of_get_nand_ecc_mode(dn
);
4280 ecc_algo
= of_get_nand_ecc_algo(dn
);
4281 ecc_strength
= of_get_nand_ecc_strength(dn
);
4282 ecc_step
= of_get_nand_ecc_step_size(dn
);
4284 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
4285 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
4286 pr_err("must set both strength and step size in DT\n");
4291 chip
->ecc
.mode
= ecc_mode
;
4294 chip
->ecc
.algo
= ecc_algo
;
4296 if (ecc_strength
>= 0)
4297 chip
->ecc
.strength
= ecc_strength
;
4300 chip
->ecc
.size
= ecc_step
;
4302 if (of_property_read_bool(dn
, "nand-ecc-maximize"))
4303 chip
->ecc
.options
|= NAND_ECC_MAXIMIZE
;
4309 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4310 * @mtd: MTD device structure
4311 * @maxchips: number of chips to scan for
4312 * @table: alternative NAND ID table
4314 * This is the first phase of the normal nand_scan() function. It reads the
4315 * flash ID and sets up MTD fields accordingly.
4318 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4319 struct nand_flash_dev
*table
)
4321 int i
, nand_maf_id
, nand_dev_id
;
4322 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4323 struct nand_flash_dev
*type
;
4326 ret
= nand_dt_init(chip
);
4330 if (!mtd
->name
&& mtd
->dev
.parent
)
4331 mtd
->name
= dev_name(mtd
->dev
.parent
);
4333 if ((!chip
->cmdfunc
|| !chip
->select_chip
) && !chip
->cmd_ctrl
) {
4335 * Default functions assigned for chip_select() and
4336 * cmdfunc() both expect cmd_ctrl() to be populated,
4337 * so we need to check that that's the case
4339 pr_err("chip.cmd_ctrl() callback is not provided");
4342 /* Set the default functions */
4343 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
4345 /* Read the flash type */
4346 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
4347 &nand_dev_id
, table
);
4350 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4351 pr_warn("No NAND device found\n");
4352 chip
->select_chip(mtd
, -1);
4353 return PTR_ERR(type
);
4356 ret
= nand_init_data_interface(chip
);
4360 chip
->select_chip(mtd
, -1);
4362 /* Check for a chip array */
4363 for (i
= 1; i
< maxchips
; i
++) {
4364 chip
->select_chip(mtd
, i
);
4365 /* See comment in nand_get_flash_type for reset */
4367 /* Send the command for reading device ID */
4368 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4369 /* Read manufacturer and device IDs */
4370 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4371 nand_dev_id
!= chip
->read_byte(mtd
)) {
4372 chip
->select_chip(mtd
, -1);
4375 chip
->select_chip(mtd
, -1);
4378 pr_info("%d chips detected\n", i
);
4380 /* Store the number of chips and calc total size for mtd */
4382 mtd
->size
= i
* chip
->chipsize
;
4386 EXPORT_SYMBOL(nand_scan_ident
);
4388 static int nand_set_ecc_soft_ops(struct mtd_info
*mtd
)
4390 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4391 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4393 if (WARN_ON(ecc
->mode
!= NAND_ECC_SOFT
))
4396 switch (ecc
->algo
) {
4397 case NAND_ECC_HAMMING
:
4398 ecc
->calculate
= nand_calculate_ecc
;
4399 ecc
->correct
= nand_correct_data
;
4400 ecc
->read_page
= nand_read_page_swecc
;
4401 ecc
->read_subpage
= nand_read_subpage
;
4402 ecc
->write_page
= nand_write_page_swecc
;
4403 ecc
->read_page_raw
= nand_read_page_raw
;
4404 ecc
->write_page_raw
= nand_write_page_raw
;
4405 ecc
->read_oob
= nand_read_oob_std
;
4406 ecc
->write_oob
= nand_write_oob_std
;
4413 if (!mtd_nand_has_bch()) {
4414 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4417 ecc
->calculate
= nand_bch_calculate_ecc
;
4418 ecc
->correct
= nand_bch_correct_data
;
4419 ecc
->read_page
= nand_read_page_swecc
;
4420 ecc
->read_subpage
= nand_read_subpage
;
4421 ecc
->write_page
= nand_write_page_swecc
;
4422 ecc
->read_page_raw
= nand_read_page_raw
;
4423 ecc
->write_page_raw
= nand_write_page_raw
;
4424 ecc
->read_oob
= nand_read_oob_std
;
4425 ecc
->write_oob
= nand_write_oob_std
;
4428 * Board driver should supply ecc.size and ecc.strength
4429 * values to select how many bits are correctable.
4430 * Otherwise, default to 4 bits for large page devices.
4432 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4438 * if no ecc placement scheme was provided pickup the default
4441 if (!mtd
->ooblayout
) {
4442 /* handle large page devices only */
4443 if (mtd
->oobsize
< 64) {
4444 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4448 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
4453 * We can only maximize ECC config when the default layout is
4454 * used, otherwise we don't know how many bytes can really be
4457 if (mtd
->ooblayout
== &nand_ooblayout_lp_ops
&&
4458 ecc
->options
& NAND_ECC_MAXIMIZE
) {
4461 /* Always prefer 1k blocks over 512bytes ones */
4463 steps
= mtd
->writesize
/ ecc
->size
;
4465 /* Reserve 2 bytes for the BBM */
4466 bytes
= (mtd
->oobsize
- 2) / steps
;
4467 ecc
->strength
= bytes
* 8 / fls(8 * ecc
->size
);
4470 /* See nand_bch_init() for details. */
4472 ecc
->priv
= nand_bch_init(mtd
);
4474 WARN(1, "BCH ECC initialization failed!\n");
4479 WARN(1, "Unsupported ECC algorithm!\n");
4485 * Check if the chip configuration meet the datasheet requirements.
4487 * If our configuration corrects A bits per B bytes and the minimum
4488 * required correction level is X bits per Y bytes, then we must ensure
4489 * both of the following are true:
4491 * (1) A / B >= X / Y
4494 * Requirement (1) ensures we can correct for the required bitflip density.
4495 * Requirement (2) ensures we can correct even when all bitflips are clumped
4496 * in the same sector.
4498 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4500 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4501 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4504 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4505 /* Not enough information */
4509 * We get the number of corrected bits per page to compare
4510 * the correction density.
4512 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4513 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4515 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4519 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4520 * @mtd: MTD device structure
4522 * This is the second phase of the normal nand_scan() function. It fills out
4523 * all the uninitialized function pointers with the defaults and scans for a
4524 * bad block table if appropriate.
4526 int nand_scan_tail(struct mtd_info
*mtd
)
4528 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4529 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4530 struct nand_buffers
*nbuf
;
4533 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4534 if (WARN_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4535 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
)))
4538 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4539 nbuf
= kzalloc(sizeof(*nbuf
) + mtd
->writesize
4540 + mtd
->oobsize
* 3, GFP_KERNEL
);
4543 nbuf
->ecccalc
= (uint8_t *)(nbuf
+ 1);
4544 nbuf
->ecccode
= nbuf
->ecccalc
+ mtd
->oobsize
;
4545 nbuf
->databuf
= nbuf
->ecccode
+ mtd
->oobsize
;
4547 chip
->buffers
= nbuf
;
4553 /* Set the internal oob buffer location, just after the page data */
4554 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4557 * If no default placement scheme is given, select an appropriate one.
4559 if (!mtd
->ooblayout
&&
4560 !(ecc
->mode
== NAND_ECC_SOFT
&& ecc
->algo
== NAND_ECC_BCH
)) {
4561 switch (mtd
->oobsize
) {
4564 mtd_set_ooblayout(mtd
, &nand_ooblayout_sp_ops
);
4568 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
4571 WARN(1, "No oob scheme defined for oobsize %d\n",
4578 if (!chip
->write_page
)
4579 chip
->write_page
= nand_write_page
;
4582 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4583 * selected and we have 256 byte pagesize fallback to software ECC
4586 switch (ecc
->mode
) {
4587 case NAND_ECC_HW_OOB_FIRST
:
4588 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4589 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4590 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4594 if (!ecc
->read_page
)
4595 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4598 /* Use standard hwecc read page function? */
4599 if (!ecc
->read_page
)
4600 ecc
->read_page
= nand_read_page_hwecc
;
4601 if (!ecc
->write_page
)
4602 ecc
->write_page
= nand_write_page_hwecc
;
4603 if (!ecc
->read_page_raw
)
4604 ecc
->read_page_raw
= nand_read_page_raw
;
4605 if (!ecc
->write_page_raw
)
4606 ecc
->write_page_raw
= nand_write_page_raw
;
4608 ecc
->read_oob
= nand_read_oob_std
;
4609 if (!ecc
->write_oob
)
4610 ecc
->write_oob
= nand_write_oob_std
;
4611 if (!ecc
->read_subpage
)
4612 ecc
->read_subpage
= nand_read_subpage
;
4613 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4614 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4616 case NAND_ECC_HW_SYNDROME
:
4617 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4619 ecc
->read_page
== nand_read_page_hwecc
||
4621 ecc
->write_page
== nand_write_page_hwecc
)) {
4622 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4626 /* Use standard syndrome read/write page function? */
4627 if (!ecc
->read_page
)
4628 ecc
->read_page
= nand_read_page_syndrome
;
4629 if (!ecc
->write_page
)
4630 ecc
->write_page
= nand_write_page_syndrome
;
4631 if (!ecc
->read_page_raw
)
4632 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4633 if (!ecc
->write_page_raw
)
4634 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4636 ecc
->read_oob
= nand_read_oob_syndrome
;
4637 if (!ecc
->write_oob
)
4638 ecc
->write_oob
= nand_write_oob_syndrome
;
4640 if (mtd
->writesize
>= ecc
->size
) {
4641 if (!ecc
->strength
) {
4642 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4648 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4649 ecc
->size
, mtd
->writesize
);
4650 ecc
->mode
= NAND_ECC_SOFT
;
4651 ecc
->algo
= NAND_ECC_HAMMING
;
4654 ret
= nand_set_ecc_soft_ops(mtd
);
4662 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4663 ecc
->read_page
= nand_read_page_raw
;
4664 ecc
->write_page
= nand_write_page_raw
;
4665 ecc
->read_oob
= nand_read_oob_std
;
4666 ecc
->read_page_raw
= nand_read_page_raw
;
4667 ecc
->write_page_raw
= nand_write_page_raw
;
4668 ecc
->write_oob
= nand_write_oob_std
;
4669 ecc
->size
= mtd
->writesize
;
4675 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4680 /* For many systems, the standard OOB write also works for raw */
4681 if (!ecc
->read_oob_raw
)
4682 ecc
->read_oob_raw
= ecc
->read_oob
;
4683 if (!ecc
->write_oob_raw
)
4684 ecc
->write_oob_raw
= ecc
->write_oob
;
4686 /* propagate ecc info to mtd_info */
4687 mtd
->ecc_strength
= ecc
->strength
;
4688 mtd
->ecc_step_size
= ecc
->size
;
4691 * Set the number of read / write steps for one page depending on ECC
4694 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4695 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4696 WARN(1, "Invalid ECC parameters\n");
4700 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4703 * The number of bytes available for a client to place data into
4704 * the out of band area.
4706 ret
= mtd_ooblayout_count_freebytes(mtd
);
4710 mtd
->oobavail
= ret
;
4712 /* ECC sanity check: warn if it's too weak */
4713 if (!nand_ecc_strength_good(mtd
))
4714 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4717 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4718 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4719 switch (ecc
->steps
) {
4721 mtd
->subpage_sft
= 1;
4726 mtd
->subpage_sft
= 2;
4730 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4732 /* Initialize state */
4733 chip
->state
= FL_READY
;
4735 /* Invalidate the pagebuffer reference */
4738 /* Large page NAND with SOFT_ECC should support subpage reads */
4739 switch (ecc
->mode
) {
4741 if (chip
->page_shift
> 9)
4742 chip
->options
|= NAND_SUBPAGE_READ
;
4749 /* Fill in remaining MTD driver data */
4750 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4751 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4753 mtd
->_erase
= nand_erase
;
4755 mtd
->_unpoint
= NULL
;
4756 mtd
->_read
= nand_read
;
4757 mtd
->_write
= nand_write
;
4758 mtd
->_panic_write
= panic_nand_write
;
4759 mtd
->_read_oob
= nand_read_oob
;
4760 mtd
->_write_oob
= nand_write_oob
;
4761 mtd
->_sync
= nand_sync
;
4763 mtd
->_unlock
= NULL
;
4764 mtd
->_suspend
= nand_suspend
;
4765 mtd
->_resume
= nand_resume
;
4766 mtd
->_reboot
= nand_shutdown
;
4767 mtd
->_block_isreserved
= nand_block_isreserved
;
4768 mtd
->_block_isbad
= nand_block_isbad
;
4769 mtd
->_block_markbad
= nand_block_markbad
;
4770 mtd
->writebufsize
= mtd
->writesize
;
4773 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4774 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4777 if (!mtd
->bitflip_threshold
)
4778 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4780 /* Check, if we should skip the bad block table scan */
4781 if (chip
->options
& NAND_SKIP_BBTSCAN
)
4784 /* Build bad block table */
4785 return chip
->scan_bbt(mtd
);
4787 if (!(chip
->options
& NAND_OWN_BUFFERS
))
4788 kfree(chip
->buffers
);
4791 EXPORT_SYMBOL(nand_scan_tail
);
4794 * is_module_text_address() isn't exported, and it's mostly a pointless
4795 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4796 * to call us from in-kernel code if the core NAND support is modular.
4799 #define caller_is_module() (1)
4801 #define caller_is_module() \
4802 is_module_text_address((unsigned long)__builtin_return_address(0))
4806 * nand_scan - [NAND Interface] Scan for the NAND device
4807 * @mtd: MTD device structure
4808 * @maxchips: number of chips to scan for
4810 * This fills out all the uninitialized function pointers with the defaults.
4811 * The flash ID is read and the mtd/chip structures are filled with the
4812 * appropriate values.
4814 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4818 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4820 ret
= nand_scan_tail(mtd
);
4823 EXPORT_SYMBOL(nand_scan
);
4826 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
4827 * @chip: NAND chip object
4829 void nand_cleanup(struct nand_chip
*chip
)
4831 if (chip
->ecc
.mode
== NAND_ECC_SOFT
&&
4832 chip
->ecc
.algo
== NAND_ECC_BCH
)
4833 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
4835 nand_release_data_interface(chip
);
4837 /* Free bad block table memory */
4839 if (!(chip
->options
& NAND_OWN_BUFFERS
))
4840 kfree(chip
->buffers
);
4842 /* Free bad block descriptor memory */
4843 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
4844 & NAND_BBT_DYNAMICSTRUCT
)
4845 kfree(chip
->badblock_pattern
);
4847 EXPORT_SYMBOL_GPL(nand_cleanup
);
4850 * nand_release - [NAND Interface] Unregister the MTD device and free resources
4851 * held by the NAND device
4852 * @mtd: MTD device structure
4854 void nand_release(struct mtd_info
*mtd
)
4856 mtd_device_unregister(mtd
);
4857 nand_cleanup(mtd_to_nand(mtd
));
4859 EXPORT_SYMBOL_GPL(nand_release
);
4861 MODULE_LICENSE("GPL");
4862 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4863 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4864 MODULE_DESCRIPTION("Generic NAND flash driver code");