3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/nmi.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/rawnand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/nand_bch.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
48 #include <linux/mtd/partitions.h>
51 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
53 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
54 struct mtd_oob_ops
*ops
);
56 /* Define default oob placement schemes for large and small page devices */
57 static int nand_ooblayout_ecc_sp(struct mtd_info
*mtd
, int section
,
58 struct mtd_oob_region
*oobregion
)
60 struct nand_chip
*chip
= mtd_to_nand(mtd
);
61 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
67 oobregion
->offset
= 0;
68 if (mtd
->oobsize
== 16)
69 oobregion
->length
= 4;
71 oobregion
->length
= 3;
73 if (mtd
->oobsize
== 8)
76 oobregion
->offset
= 6;
77 oobregion
->length
= ecc
->total
- 4;
83 static int nand_ooblayout_free_sp(struct mtd_info
*mtd
, int section
,
84 struct mtd_oob_region
*oobregion
)
89 if (mtd
->oobsize
== 16) {
93 oobregion
->length
= 8;
94 oobregion
->offset
= 8;
96 oobregion
->length
= 2;
98 oobregion
->offset
= 3;
100 oobregion
->offset
= 6;
106 const struct mtd_ooblayout_ops nand_ooblayout_sp_ops
= {
107 .ecc
= nand_ooblayout_ecc_sp
,
108 .free
= nand_ooblayout_free_sp
,
110 EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops
);
112 static int nand_ooblayout_ecc_lp(struct mtd_info
*mtd
, int section
,
113 struct mtd_oob_region
*oobregion
)
115 struct nand_chip
*chip
= mtd_to_nand(mtd
);
116 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
121 oobregion
->length
= ecc
->total
;
122 oobregion
->offset
= mtd
->oobsize
- oobregion
->length
;
127 static int nand_ooblayout_free_lp(struct mtd_info
*mtd
, int section
,
128 struct mtd_oob_region
*oobregion
)
130 struct nand_chip
*chip
= mtd_to_nand(mtd
);
131 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
136 oobregion
->length
= mtd
->oobsize
- ecc
->total
- 2;
137 oobregion
->offset
= 2;
142 const struct mtd_ooblayout_ops nand_ooblayout_lp_ops
= {
143 .ecc
= nand_ooblayout_ecc_lp
,
144 .free
= nand_ooblayout_free_lp
,
146 EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops
);
149 * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
150 * are placed at a fixed offset.
152 static int nand_ooblayout_ecc_lp_hamming(struct mtd_info
*mtd
, int section
,
153 struct mtd_oob_region
*oobregion
)
155 struct nand_chip
*chip
= mtd_to_nand(mtd
);
156 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
161 switch (mtd
->oobsize
) {
163 oobregion
->offset
= 40;
166 oobregion
->offset
= 80;
172 oobregion
->length
= ecc
->total
;
173 if (oobregion
->offset
+ oobregion
->length
> mtd
->oobsize
)
179 static int nand_ooblayout_free_lp_hamming(struct mtd_info
*mtd
, int section
,
180 struct mtd_oob_region
*oobregion
)
182 struct nand_chip
*chip
= mtd_to_nand(mtd
);
183 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
186 if (section
< 0 || section
> 1)
189 switch (mtd
->oobsize
) {
201 oobregion
->offset
= 2;
202 oobregion
->length
= ecc_offset
- 2;
204 oobregion
->offset
= ecc_offset
+ ecc
->total
;
205 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
211 static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops
= {
212 .ecc
= nand_ooblayout_ecc_lp_hamming
,
213 .free
= nand_ooblayout_free_lp_hamming
,
216 static int check_offs_len(struct mtd_info
*mtd
,
217 loff_t ofs
, uint64_t len
)
219 struct nand_chip
*chip
= mtd_to_nand(mtd
);
222 /* Start address must align on block boundary */
223 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
224 pr_debug("%s: unaligned address\n", __func__
);
228 /* Length must align on block boundary */
229 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
230 pr_debug("%s: length not block aligned\n", __func__
);
238 * nand_release_device - [GENERIC] release chip
239 * @mtd: MTD device structure
241 * Release chip lock and wake up anyone waiting on the device.
243 static void nand_release_device(struct mtd_info
*mtd
)
245 struct nand_chip
*chip
= mtd_to_nand(mtd
);
247 /* Release the controller and the chip */
248 spin_lock(&chip
->controller
->lock
);
249 chip
->controller
->active
= NULL
;
250 chip
->state
= FL_READY
;
251 wake_up(&chip
->controller
->wq
);
252 spin_unlock(&chip
->controller
->lock
);
256 * nand_read_byte - [DEFAULT] read one byte from the chip
257 * @mtd: MTD device structure
259 * Default read function for 8bit buswidth
261 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
263 struct nand_chip
*chip
= mtd_to_nand(mtd
);
264 return readb(chip
->IO_ADDR_R
);
268 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
269 * @mtd: MTD device structure
271 * Default read function for 16bit buswidth with endianness conversion.
274 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
276 struct nand_chip
*chip
= mtd_to_nand(mtd
);
277 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
281 * nand_read_word - [DEFAULT] read one word from the chip
282 * @mtd: MTD device structure
284 * Default read function for 16bit buswidth without endianness conversion.
286 static u16
nand_read_word(struct mtd_info
*mtd
)
288 struct nand_chip
*chip
= mtd_to_nand(mtd
);
289 return readw(chip
->IO_ADDR_R
);
293 * nand_select_chip - [DEFAULT] control CE line
294 * @mtd: MTD device structure
295 * @chipnr: chipnumber to select, -1 for deselect
297 * Default select function for 1 chip devices.
299 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
301 struct nand_chip
*chip
= mtd_to_nand(mtd
);
305 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
316 * nand_write_byte - [DEFAULT] write single byte to chip
317 * @mtd: MTD device structure
318 * @byte: value to write
320 * Default function to write a byte to I/O[7:0]
322 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
324 struct nand_chip
*chip
= mtd_to_nand(mtd
);
326 chip
->write_buf(mtd
, &byte
, 1);
330 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
331 * @mtd: MTD device structure
332 * @byte: value to write
334 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
336 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
338 struct nand_chip
*chip
= mtd_to_nand(mtd
);
339 uint16_t word
= byte
;
342 * It's not entirely clear what should happen to I/O[15:8] when writing
343 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
345 * When the host supports a 16-bit bus width, only data is
346 * transferred at the 16-bit width. All address and command line
347 * transfers shall use only the lower 8-bits of the data bus. During
348 * command transfers, the host may place any value on the upper
349 * 8-bits of the data bus. During address transfers, the host shall
350 * set the upper 8-bits of the data bus to 00h.
352 * One user of the write_byte callback is nand_onfi_set_features. The
353 * four parameters are specified to be written to I/O[7:0], but this is
354 * neither an address nor a command transfer. Let's assume a 0 on the
355 * upper I/O lines is OK.
357 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
361 * nand_write_buf - [DEFAULT] write buffer to chip
362 * @mtd: MTD device structure
364 * @len: number of bytes to write
366 * Default write function for 8bit buswidth.
368 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
370 struct nand_chip
*chip
= mtd_to_nand(mtd
);
372 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
376 * nand_read_buf - [DEFAULT] read chip data into buffer
377 * @mtd: MTD device structure
378 * @buf: buffer to store date
379 * @len: number of bytes to read
381 * Default read function for 8bit buswidth.
383 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
385 struct nand_chip
*chip
= mtd_to_nand(mtd
);
387 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
391 * nand_write_buf16 - [DEFAULT] write buffer to chip
392 * @mtd: MTD device structure
394 * @len: number of bytes to write
396 * Default write function for 16bit buswidth.
398 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
400 struct nand_chip
*chip
= mtd_to_nand(mtd
);
401 u16
*p
= (u16
*) buf
;
403 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
407 * nand_read_buf16 - [DEFAULT] read chip data into buffer
408 * @mtd: MTD device structure
409 * @buf: buffer to store date
410 * @len: number of bytes to read
412 * Default read function for 16bit buswidth.
414 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
416 struct nand_chip
*chip
= mtd_to_nand(mtd
);
417 u16
*p
= (u16
*) buf
;
419 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
423 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
424 * @mtd: MTD device structure
425 * @ofs: offset from device start
427 * Check, if the block is bad.
429 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
431 int page
, page_end
, res
;
432 struct nand_chip
*chip
= mtd_to_nand(mtd
);
435 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
436 ofs
+= mtd
->erasesize
- mtd
->writesize
;
438 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
439 page_end
= page
+ (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
? 2 : 1);
441 for (; page
< page_end
; page
++) {
442 res
= chip
->ecc
.read_oob(mtd
, chip
, page
);
446 bad
= chip
->oob_poi
[chip
->badblockpos
];
448 if (likely(chip
->badblockbits
== 8))
451 res
= hweight8(bad
) < chip
->badblockbits
;
460 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
461 * @mtd: MTD device structure
462 * @ofs: offset from device start
464 * This is the default implementation, which can be overridden by a hardware
465 * specific driver. It provides the details for writing a bad block marker to a
468 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
470 struct nand_chip
*chip
= mtd_to_nand(mtd
);
471 struct mtd_oob_ops ops
;
472 uint8_t buf
[2] = { 0, 0 };
473 int ret
= 0, res
, i
= 0;
475 memset(&ops
, 0, sizeof(ops
));
477 ops
.ooboffs
= chip
->badblockpos
;
478 if (chip
->options
& NAND_BUSWIDTH_16
) {
479 ops
.ooboffs
&= ~0x01;
480 ops
.len
= ops
.ooblen
= 2;
482 ops
.len
= ops
.ooblen
= 1;
484 ops
.mode
= MTD_OPS_PLACE_OOB
;
486 /* Write to first/last page(s) if necessary */
487 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
488 ofs
+= mtd
->erasesize
- mtd
->writesize
;
490 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
495 ofs
+= mtd
->writesize
;
496 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
502 * nand_block_markbad_lowlevel - mark a block bad
503 * @mtd: MTD device structure
504 * @ofs: offset from device start
506 * This function performs the generic NAND bad block marking steps (i.e., bad
507 * block table(s) and/or marker(s)). We only allow the hardware driver to
508 * specify how to write bad block markers to OOB (chip->block_markbad).
510 * We try operations in the following order:
512 * (1) erase the affected block, to allow OOB marker to be written cleanly
513 * (2) write bad block marker to OOB area of affected block (unless flag
514 * NAND_BBT_NO_OOB_BBM is present)
517 * Note that we retain the first error encountered in (2) or (3), finish the
518 * procedures, and dump the error in the end.
520 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
522 struct nand_chip
*chip
= mtd_to_nand(mtd
);
525 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
526 struct erase_info einfo
;
528 /* Attempt erase before marking OOB */
529 memset(&einfo
, 0, sizeof(einfo
));
532 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
533 nand_erase_nand(mtd
, &einfo
, 0);
535 /* Write bad block marker to OOB */
536 nand_get_device(mtd
, FL_WRITING
);
537 ret
= chip
->block_markbad(mtd
, ofs
);
538 nand_release_device(mtd
);
541 /* Mark block bad in BBT */
543 res
= nand_markbad_bbt(mtd
, ofs
);
549 mtd
->ecc_stats
.badblocks
++;
555 * nand_check_wp - [GENERIC] check if the chip is write protected
556 * @mtd: MTD device structure
558 * Check, if the device is write protected. The function expects, that the
559 * device is already selected.
561 static int nand_check_wp(struct mtd_info
*mtd
)
563 struct nand_chip
*chip
= mtd_to_nand(mtd
);
565 /* Broken xD cards report WP despite being writable */
566 if (chip
->options
& NAND_BROKEN_XD
)
569 /* Check the WP bit */
570 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
571 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
575 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
576 * @mtd: MTD device structure
577 * @ofs: offset from device start
579 * Check if the block is marked as reserved.
581 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
583 struct nand_chip
*chip
= mtd_to_nand(mtd
);
587 /* Return info from the table */
588 return nand_isreserved_bbt(mtd
, ofs
);
592 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
593 * @mtd: MTD device structure
594 * @ofs: offset from device start
595 * @allowbbt: 1, if its allowed to access the bbt area
597 * Check, if the block is bad. Either by reading the bad block table or
598 * calling of the scan function.
600 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
602 struct nand_chip
*chip
= mtd_to_nand(mtd
);
605 return chip
->block_bad(mtd
, ofs
);
607 /* Return info from the table */
608 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
612 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
613 * @mtd: MTD device structure
616 * Helper function for nand_wait_ready used when needing to wait in interrupt
619 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
621 struct nand_chip
*chip
= mtd_to_nand(mtd
);
624 /* Wait for the device to get ready */
625 for (i
= 0; i
< timeo
; i
++) {
626 if (chip
->dev_ready(mtd
))
628 touch_softlockup_watchdog();
634 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
635 * @mtd: MTD device structure
637 * Wait for the ready pin after a command, and warn if a timeout occurs.
639 void nand_wait_ready(struct mtd_info
*mtd
)
641 struct nand_chip
*chip
= mtd_to_nand(mtd
);
642 unsigned long timeo
= 400;
644 if (in_interrupt() || oops_in_progress
)
645 return panic_nand_wait_ready(mtd
, timeo
);
647 /* Wait until command is processed or timeout occurs */
648 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
650 if (chip
->dev_ready(mtd
))
653 } while (time_before(jiffies
, timeo
));
655 if (!chip
->dev_ready(mtd
))
656 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
658 EXPORT_SYMBOL_GPL(nand_wait_ready
);
661 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
662 * @mtd: MTD device structure
663 * @timeo: Timeout in ms
665 * Wait for status ready (i.e. command done) or timeout.
667 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
669 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
671 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
673 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
675 touch_softlockup_watchdog();
676 } while (time_before(jiffies
, timeo
));
680 * nand_command - [DEFAULT] Send command to NAND device
681 * @mtd: MTD device structure
682 * @command: the command to be sent
683 * @column: the column address for this command, -1 if none
684 * @page_addr: the page address for this command, -1 if none
686 * Send command to NAND device. This function is used for small page devices
687 * (512 Bytes per page).
689 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
690 int column
, int page_addr
)
692 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
693 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
695 /* Write out the command to the device */
696 if (command
== NAND_CMD_SEQIN
) {
699 if (column
>= mtd
->writesize
) {
701 column
-= mtd
->writesize
;
702 readcmd
= NAND_CMD_READOOB
;
703 } else if (column
< 256) {
704 /* First 256 bytes --> READ0 */
705 readcmd
= NAND_CMD_READ0
;
708 readcmd
= NAND_CMD_READ1
;
710 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
711 ctrl
&= ~NAND_CTRL_CHANGE
;
713 chip
->cmd_ctrl(mtd
, command
, ctrl
);
715 /* Address cycle, when necessary */
716 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
717 /* Serially input address */
719 /* Adjust columns for 16 bit buswidth */
720 if (chip
->options
& NAND_BUSWIDTH_16
&&
721 !nand_opcode_8bits(command
))
723 chip
->cmd_ctrl(mtd
, column
, ctrl
);
724 ctrl
&= ~NAND_CTRL_CHANGE
;
726 if (page_addr
!= -1) {
727 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
728 ctrl
&= ~NAND_CTRL_CHANGE
;
729 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
730 /* One more address cycle for devices > 32MiB */
731 if (chip
->chipsize
> (32 << 20))
732 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
734 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
737 * Program and erase have their own busy handlers status and sequential
742 case NAND_CMD_PAGEPROG
:
743 case NAND_CMD_ERASE1
:
744 case NAND_CMD_ERASE2
:
746 case NAND_CMD_STATUS
:
747 case NAND_CMD_READID
:
748 case NAND_CMD_SET_FEATURES
:
754 udelay(chip
->chip_delay
);
755 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
756 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
758 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
759 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
760 nand_wait_status_ready(mtd
, 250);
763 /* This applies to read commands */
766 * READ0 is sometimes used to exit GET STATUS mode. When this
767 * is the case no address cycles are requested, and we can use
768 * this information to detect that we should not wait for the
769 * device to be ready.
771 if (column
== -1 && page_addr
== -1)
776 * If we don't have access to the busy pin, we apply the given
779 if (!chip
->dev_ready
) {
780 udelay(chip
->chip_delay
);
785 * Apply this short delay always to ensure that we do wait tWB in
786 * any case on any machine.
790 nand_wait_ready(mtd
);
793 static void nand_ccs_delay(struct nand_chip
*chip
)
796 * The controller already takes care of waiting for tCCS when the RNDIN
797 * or RNDOUT command is sent, return directly.
799 if (!(chip
->options
& NAND_WAIT_TCCS
))
803 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
804 * (which should be safe for all NANDs).
806 if (chip
->data_interface
&& chip
->data_interface
->timings
.sdr
.tCCS_min
)
807 ndelay(chip
->data_interface
->timings
.sdr
.tCCS_min
/ 1000);
813 * nand_command_lp - [DEFAULT] Send command to NAND large page device
814 * @mtd: MTD device structure
815 * @command: the command to be sent
816 * @column: the column address for this command, -1 if none
817 * @page_addr: the page address for this command, -1 if none
819 * Send command to NAND device. This is the version for the new large page
820 * devices. We don't have the separate regions as we have in the small page
821 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
823 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
824 int column
, int page_addr
)
826 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
828 /* Emulate NAND_CMD_READOOB */
829 if (command
== NAND_CMD_READOOB
) {
830 column
+= mtd
->writesize
;
831 command
= NAND_CMD_READ0
;
834 /* Command latch cycle */
835 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
837 if (column
!= -1 || page_addr
!= -1) {
838 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
840 /* Serially input address */
842 /* Adjust columns for 16 bit buswidth */
843 if (chip
->options
& NAND_BUSWIDTH_16
&&
844 !nand_opcode_8bits(command
))
846 chip
->cmd_ctrl(mtd
, column
, ctrl
);
847 ctrl
&= ~NAND_CTRL_CHANGE
;
849 /* Only output a single addr cycle for 8bits opcodes. */
850 if (!nand_opcode_8bits(command
))
851 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
853 if (page_addr
!= -1) {
854 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
855 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
856 NAND_NCE
| NAND_ALE
);
857 /* One more address cycle for devices > 128MiB */
858 if (chip
->chipsize
> (128 << 20))
859 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
860 NAND_NCE
| NAND_ALE
);
863 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
866 * Program and erase have their own busy handlers status, sequential
867 * in and status need no delay.
871 case NAND_CMD_CACHEDPROG
:
872 case NAND_CMD_PAGEPROG
:
873 case NAND_CMD_ERASE1
:
874 case NAND_CMD_ERASE2
:
876 case NAND_CMD_STATUS
:
877 case NAND_CMD_READID
:
878 case NAND_CMD_SET_FEATURES
:
882 nand_ccs_delay(chip
);
888 udelay(chip
->chip_delay
);
889 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
890 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
891 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
892 NAND_NCE
| NAND_CTRL_CHANGE
);
893 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
894 nand_wait_status_ready(mtd
, 250);
897 case NAND_CMD_RNDOUT
:
898 /* No ready / busy check necessary */
899 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
900 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
901 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
902 NAND_NCE
| NAND_CTRL_CHANGE
);
904 nand_ccs_delay(chip
);
909 * READ0 is sometimes used to exit GET STATUS mode. When this
910 * is the case no address cycles are requested, and we can use
911 * this information to detect that READSTART should not be
914 if (column
== -1 && page_addr
== -1)
917 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
918 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
919 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
920 NAND_NCE
| NAND_CTRL_CHANGE
);
922 /* This applies to read commands */
925 * If we don't have access to the busy pin, we apply the given
928 if (!chip
->dev_ready
) {
929 udelay(chip
->chip_delay
);
935 * Apply this short delay always to ensure that we do wait tWB in
936 * any case on any machine.
940 nand_wait_ready(mtd
);
944 * panic_nand_get_device - [GENERIC] Get chip for selected access
945 * @chip: the nand chip descriptor
946 * @mtd: MTD device structure
947 * @new_state: the state which is requested
949 * Used when in panic, no locks are taken.
951 static void panic_nand_get_device(struct nand_chip
*chip
,
952 struct mtd_info
*mtd
, int new_state
)
954 /* Hardware controller shared among independent devices */
955 chip
->controller
->active
= chip
;
956 chip
->state
= new_state
;
960 * nand_get_device - [GENERIC] Get chip for selected access
961 * @mtd: MTD device structure
962 * @new_state: the state which is requested
964 * Get the device and lock it for exclusive access
967 nand_get_device(struct mtd_info
*mtd
, int new_state
)
969 struct nand_chip
*chip
= mtd_to_nand(mtd
);
970 spinlock_t
*lock
= &chip
->controller
->lock
;
971 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
972 DECLARE_WAITQUEUE(wait
, current
);
976 /* Hardware controller shared among independent devices */
977 if (!chip
->controller
->active
)
978 chip
->controller
->active
= chip
;
980 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
981 chip
->state
= new_state
;
985 if (new_state
== FL_PM_SUSPENDED
) {
986 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
987 chip
->state
= FL_PM_SUSPENDED
;
992 set_current_state(TASK_UNINTERRUPTIBLE
);
993 add_wait_queue(wq
, &wait
);
996 remove_wait_queue(wq
, &wait
);
1001 * panic_nand_wait - [GENERIC] wait until the command is done
1002 * @mtd: MTD device structure
1003 * @chip: NAND chip structure
1006 * Wait for command done. This is a helper function for nand_wait used when
1007 * we are in interrupt context. May happen when in panic and trying to write
1008 * an oops through mtdoops.
1010 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1011 unsigned long timeo
)
1014 for (i
= 0; i
< timeo
; i
++) {
1015 if (chip
->dev_ready
) {
1016 if (chip
->dev_ready(mtd
))
1019 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
1027 * nand_wait - [DEFAULT] wait until the command is done
1028 * @mtd: MTD device structure
1029 * @chip: NAND chip structure
1031 * Wait for command done. This applies to erase and program only.
1033 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
1037 unsigned long timeo
= 400;
1040 * Apply this short delay always to ensure that we do wait tWB in any
1041 * case on any machine.
1045 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
1047 if (in_interrupt() || oops_in_progress
)
1048 panic_nand_wait(mtd
, chip
, timeo
);
1050 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
1052 if (chip
->dev_ready
) {
1053 if (chip
->dev_ready(mtd
))
1056 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
1060 } while (time_before(jiffies
, timeo
));
1063 status
= (int)chip
->read_byte(mtd
);
1064 /* This can happen if in case of timeout or buggy dev_ready */
1065 WARN_ON(!(status
& NAND_STATUS_READY
));
1070 * nand_reset_data_interface - Reset data interface and timings
1071 * @chip: The NAND chip
1072 * @chipnr: Internal die id
1074 * Reset the Data interface and timings to ONFI mode 0.
1076 * Returns 0 for success or negative error code otherwise.
1078 static int nand_reset_data_interface(struct nand_chip
*chip
, int chipnr
)
1080 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1081 const struct nand_data_interface
*conf
;
1084 if (!chip
->setup_data_interface
)
1088 * The ONFI specification says:
1090 * To transition from NV-DDR or NV-DDR2 to the SDR data
1091 * interface, the host shall use the Reset (FFh) command
1092 * using SDR timing mode 0. A device in any timing mode is
1093 * required to recognize Reset (FFh) command issued in SDR
1097 * Configure the data interface in SDR mode and set the
1098 * timings to timing mode 0.
1101 conf
= nand_get_default_data_interface();
1102 ret
= chip
->setup_data_interface(mtd
, chipnr
, conf
);
1104 pr_err("Failed to configure data interface to SDR timing mode 0\n");
1110 * nand_setup_data_interface - Setup the best data interface and timings
1111 * @chip: The NAND chip
1112 * @chipnr: Internal die id
1114 * Find and configure the best data interface and NAND timings supported by
1115 * the chip and the driver.
1116 * First tries to retrieve supported timing modes from ONFI information,
1117 * and if the NAND chip does not support ONFI, relies on the
1118 * ->onfi_timing_mode_default specified in the nand_ids table.
1120 * Returns 0 for success or negative error code otherwise.
1122 static int nand_setup_data_interface(struct nand_chip
*chip
, int chipnr
)
1124 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1127 if (!chip
->setup_data_interface
|| !chip
->data_interface
)
1131 * Ensure the timing mode has been changed on the chip side
1132 * before changing timings on the controller side.
1134 if (chip
->onfi_version
&&
1135 (le16_to_cpu(chip
->onfi_params
.opt_cmd
) &
1136 ONFI_OPT_CMD_SET_GET_FEATURES
)) {
1137 u8 tmode_param
[ONFI_SUBFEATURE_PARAM_LEN
] = {
1138 chip
->onfi_timing_mode_default
,
1141 ret
= chip
->onfi_set_features(mtd
, chip
,
1142 ONFI_FEATURE_ADDR_TIMING_MODE
,
1148 ret
= chip
->setup_data_interface(mtd
, chipnr
, chip
->data_interface
);
1154 * nand_init_data_interface - find the best data interface and timings
1155 * @chip: The NAND chip
1157 * Find the best data interface and NAND timings supported by the chip
1159 * First tries to retrieve supported timing modes from ONFI information,
1160 * and if the NAND chip does not support ONFI, relies on the
1161 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1162 * function nand_chip->data_interface is initialized with the best timing mode
1165 * Returns 0 for success or negative error code otherwise.
1167 static int nand_init_data_interface(struct nand_chip
*chip
)
1169 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1170 int modes
, mode
, ret
;
1172 if (!chip
->setup_data_interface
)
1176 * First try to identify the best timings from ONFI parameters and
1177 * if the NAND does not support ONFI, fallback to the default ONFI
1180 modes
= onfi_get_async_timing_mode(chip
);
1181 if (modes
== ONFI_TIMING_MODE_UNKNOWN
) {
1182 if (!chip
->onfi_timing_mode_default
)
1185 modes
= GENMASK(chip
->onfi_timing_mode_default
, 0);
1188 chip
->data_interface
= kzalloc(sizeof(*chip
->data_interface
),
1190 if (!chip
->data_interface
)
1193 for (mode
= fls(modes
) - 1; mode
>= 0; mode
--) {
1194 ret
= onfi_init_data_interface(chip
, chip
->data_interface
,
1195 NAND_SDR_IFACE
, mode
);
1199 /* Pass -1 to only */
1200 ret
= chip
->setup_data_interface(mtd
,
1201 NAND_DATA_IFACE_CHECK_ONLY
,
1202 chip
->data_interface
);
1204 chip
->onfi_timing_mode_default
= mode
;
1212 static void nand_release_data_interface(struct nand_chip
*chip
)
1214 kfree(chip
->data_interface
);
1218 * nand_reset - Reset and initialize a NAND device
1219 * @chip: The NAND chip
1220 * @chipnr: Internal die id
1222 * Returns 0 for success or negative error code otherwise
1224 int nand_reset(struct nand_chip
*chip
, int chipnr
)
1226 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1229 ret
= nand_reset_data_interface(chip
, chipnr
);
1234 * The CS line has to be released before we can apply the new NAND
1235 * interface settings, hence this weird ->select_chip() dance.
1237 chip
->select_chip(mtd
, chipnr
);
1238 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1239 chip
->select_chip(mtd
, -1);
1241 chip
->select_chip(mtd
, chipnr
);
1242 ret
= nand_setup_data_interface(chip
, chipnr
);
1243 chip
->select_chip(mtd
, -1);
1251 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1252 * @buf: buffer to test
1253 * @len: buffer length
1254 * @bitflips_threshold: maximum number of bitflips
1256 * Check if a buffer contains only 0xff, which means the underlying region
1257 * has been erased and is ready to be programmed.
1258 * The bitflips_threshold specify the maximum number of bitflips before
1259 * considering the region is not erased.
1260 * Note: The logic of this function has been extracted from the memweight
1261 * implementation, except that nand_check_erased_buf function exit before
1262 * testing the whole buffer if the number of bitflips exceed the
1263 * bitflips_threshold value.
1265 * Returns a positive number of bitflips less than or equal to
1266 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1269 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1271 const unsigned char *bitmap
= buf
;
1275 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1277 weight
= hweight8(*bitmap
);
1278 bitflips
+= BITS_PER_BYTE
- weight
;
1279 if (unlikely(bitflips
> bitflips_threshold
))
1283 for (; len
>= sizeof(long);
1284 len
-= sizeof(long), bitmap
+= sizeof(long)) {
1285 unsigned long d
= *((unsigned long *)bitmap
);
1288 weight
= hweight_long(d
);
1289 bitflips
+= BITS_PER_LONG
- weight
;
1290 if (unlikely(bitflips
> bitflips_threshold
))
1294 for (; len
> 0; len
--, bitmap
++) {
1295 weight
= hweight8(*bitmap
);
1296 bitflips
+= BITS_PER_BYTE
- weight
;
1297 if (unlikely(bitflips
> bitflips_threshold
))
1305 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1307 * @data: data buffer to test
1308 * @datalen: data length
1310 * @ecclen: ECC length
1311 * @extraoob: extra OOB buffer
1312 * @extraooblen: extra OOB length
1313 * @bitflips_threshold: maximum number of bitflips
1315 * Check if a data buffer and its associated ECC and OOB data contains only
1316 * 0xff pattern, which means the underlying region has been erased and is
1317 * ready to be programmed.
1318 * The bitflips_threshold specify the maximum number of bitflips before
1319 * considering the region as not erased.
1322 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1323 * different from the NAND page size. When fixing bitflips, ECC engines will
1324 * report the number of errors per chunk, and the NAND core infrastructure
1325 * expect you to return the maximum number of bitflips for the whole page.
1326 * This is why you should always use this function on a single chunk and
1327 * not on the whole page. After checking each chunk you should update your
1328 * max_bitflips value accordingly.
1329 * 2/ When checking for bitflips in erased pages you should not only check
1330 * the payload data but also their associated ECC data, because a user might
1331 * have programmed almost all bits to 1 but a few. In this case, we
1332 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1334 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1335 * data are protected by the ECC engine.
1336 * It could also be used if you support subpages and want to attach some
1337 * extra OOB data to an ECC chunk.
1339 * Returns a positive number of bitflips less than or equal to
1340 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1341 * threshold. In case of success, the passed buffers are filled with 0xff.
1343 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1344 void *ecc
, int ecclen
,
1345 void *extraoob
, int extraooblen
,
1346 int bitflips_threshold
)
1348 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1350 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1351 bitflips_threshold
);
1352 if (data_bitflips
< 0)
1353 return data_bitflips
;
1355 bitflips_threshold
-= data_bitflips
;
1357 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1358 if (ecc_bitflips
< 0)
1359 return ecc_bitflips
;
1361 bitflips_threshold
-= ecc_bitflips
;
1363 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1364 bitflips_threshold
);
1365 if (extraoob_bitflips
< 0)
1366 return extraoob_bitflips
;
1369 memset(data
, 0xff, datalen
);
1372 memset(ecc
, 0xff, ecclen
);
1374 if (extraoob_bitflips
)
1375 memset(extraoob
, 0xff, extraooblen
);
1377 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1379 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1382 * nand_read_page_raw - [INTERN] read raw page data without ecc
1383 * @mtd: mtd info structure
1384 * @chip: nand chip info structure
1385 * @buf: buffer to store read data
1386 * @oob_required: caller requires OOB data read to chip->oob_poi
1387 * @page: page number to read
1389 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1391 int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1392 uint8_t *buf
, int oob_required
, int page
)
1394 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1396 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1399 EXPORT_SYMBOL(nand_read_page_raw
);
1402 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1403 * @mtd: mtd info structure
1404 * @chip: nand chip info structure
1405 * @buf: buffer to store read data
1406 * @oob_required: caller requires OOB data read to chip->oob_poi
1407 * @page: page number to read
1409 * We need a special oob layout and handling even when OOB isn't used.
1411 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1412 struct nand_chip
*chip
, uint8_t *buf
,
1413 int oob_required
, int page
)
1415 int eccsize
= chip
->ecc
.size
;
1416 int eccbytes
= chip
->ecc
.bytes
;
1417 uint8_t *oob
= chip
->oob_poi
;
1420 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1421 chip
->read_buf(mtd
, buf
, eccsize
);
1424 if (chip
->ecc
.prepad
) {
1425 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1426 oob
+= chip
->ecc
.prepad
;
1429 chip
->read_buf(mtd
, oob
, eccbytes
);
1432 if (chip
->ecc
.postpad
) {
1433 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1434 oob
+= chip
->ecc
.postpad
;
1438 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1440 chip
->read_buf(mtd
, oob
, size
);
1446 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1447 * @mtd: mtd info structure
1448 * @chip: nand chip info structure
1449 * @buf: buffer to store read data
1450 * @oob_required: caller requires OOB data read to chip->oob_poi
1451 * @page: page number to read
1453 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1454 uint8_t *buf
, int oob_required
, int page
)
1456 int i
, eccsize
= chip
->ecc
.size
, ret
;
1457 int eccbytes
= chip
->ecc
.bytes
;
1458 int eccsteps
= chip
->ecc
.steps
;
1460 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1461 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1462 unsigned int max_bitflips
= 0;
1464 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1466 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1467 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1469 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1474 eccsteps
= chip
->ecc
.steps
;
1477 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1480 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1482 mtd
->ecc_stats
.failed
++;
1484 mtd
->ecc_stats
.corrected
+= stat
;
1485 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1488 return max_bitflips
;
1492 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1493 * @mtd: mtd info structure
1494 * @chip: nand chip info structure
1495 * @data_offs: offset of requested data within the page
1496 * @readlen: data length
1497 * @bufpoi: buffer to store read data
1498 * @page: page number to read
1500 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1501 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1504 int start_step
, end_step
, num_steps
, ret
;
1506 int data_col_addr
, i
, gaps
= 0;
1507 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1508 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1509 int index
, section
= 0;
1510 unsigned int max_bitflips
= 0;
1511 struct mtd_oob_region oobregion
= { };
1513 /* Column address within the page aligned to ECC size (256bytes) */
1514 start_step
= data_offs
/ chip
->ecc
.size
;
1515 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1516 num_steps
= end_step
- start_step
+ 1;
1517 index
= start_step
* chip
->ecc
.bytes
;
1519 /* Data size aligned to ECC ecc.size */
1520 datafrag_len
= num_steps
* chip
->ecc
.size
;
1521 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1523 data_col_addr
= start_step
* chip
->ecc
.size
;
1524 /* If we read not a page aligned data */
1525 if (data_col_addr
!= 0)
1526 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1528 p
= bufpoi
+ data_col_addr
;
1529 chip
->read_buf(mtd
, p
, datafrag_len
);
1532 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1533 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1536 * The performance is faster if we position offsets according to
1537 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1539 ret
= mtd_ooblayout_find_eccregion(mtd
, index
, §ion
, &oobregion
);
1543 if (oobregion
.length
< eccfrag_len
)
1547 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1548 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1551 * Send the command to read the particular ECC bytes take care
1552 * about buswidth alignment in read_buf.
1554 aligned_pos
= oobregion
.offset
& ~(busw
- 1);
1555 aligned_len
= eccfrag_len
;
1556 if (oobregion
.offset
& (busw
- 1))
1558 if ((oobregion
.offset
+ (num_steps
* chip
->ecc
.bytes
)) &
1562 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1563 mtd
->writesize
+ aligned_pos
, -1);
1564 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1567 ret
= mtd_ooblayout_get_eccbytes(mtd
, chip
->buffers
->ecccode
,
1568 chip
->oob_poi
, index
, eccfrag_len
);
1572 p
= bufpoi
+ data_col_addr
;
1573 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1576 stat
= chip
->ecc
.correct(mtd
, p
,
1577 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1578 if (stat
== -EBADMSG
&&
1579 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1580 /* check for empty pages with bitflips */
1581 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1582 &chip
->buffers
->ecccode
[i
],
1585 chip
->ecc
.strength
);
1589 mtd
->ecc_stats
.failed
++;
1591 mtd
->ecc_stats
.corrected
+= stat
;
1592 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1595 return max_bitflips
;
1599 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1600 * @mtd: mtd info structure
1601 * @chip: nand chip info structure
1602 * @buf: buffer to store read data
1603 * @oob_required: caller requires OOB data read to chip->oob_poi
1604 * @page: page number to read
1606 * Not for syndrome calculating ECC controllers which need a special oob layout.
1608 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1609 uint8_t *buf
, int oob_required
, int page
)
1611 int i
, eccsize
= chip
->ecc
.size
, ret
;
1612 int eccbytes
= chip
->ecc
.bytes
;
1613 int eccsteps
= chip
->ecc
.steps
;
1615 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1616 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1617 unsigned int max_bitflips
= 0;
1619 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1620 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1621 chip
->read_buf(mtd
, p
, eccsize
);
1622 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1624 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1626 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1631 eccsteps
= chip
->ecc
.steps
;
1634 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1637 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1638 if (stat
== -EBADMSG
&&
1639 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1640 /* check for empty pages with bitflips */
1641 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1642 &ecc_code
[i
], eccbytes
,
1644 chip
->ecc
.strength
);
1648 mtd
->ecc_stats
.failed
++;
1650 mtd
->ecc_stats
.corrected
+= stat
;
1651 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1654 return max_bitflips
;
1658 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1659 * @mtd: mtd info structure
1660 * @chip: nand chip info structure
1661 * @buf: buffer to store read data
1662 * @oob_required: caller requires OOB data read to chip->oob_poi
1663 * @page: page number to read
1665 * Hardware ECC for large page chips, require OOB to be read first. For this
1666 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1667 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1668 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1669 * the data area, by overwriting the NAND manufacturer bad block markings.
1671 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1672 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1674 int i
, eccsize
= chip
->ecc
.size
, ret
;
1675 int eccbytes
= chip
->ecc
.bytes
;
1676 int eccsteps
= chip
->ecc
.steps
;
1678 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1679 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1680 unsigned int max_bitflips
= 0;
1682 /* Read the OOB area first */
1683 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1684 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1685 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1687 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1692 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1695 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1696 chip
->read_buf(mtd
, p
, eccsize
);
1697 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1699 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1700 if (stat
== -EBADMSG
&&
1701 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1702 /* check for empty pages with bitflips */
1703 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1704 &ecc_code
[i
], eccbytes
,
1706 chip
->ecc
.strength
);
1710 mtd
->ecc_stats
.failed
++;
1712 mtd
->ecc_stats
.corrected
+= stat
;
1713 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1716 return max_bitflips
;
1720 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1721 * @mtd: mtd info structure
1722 * @chip: nand chip info structure
1723 * @buf: buffer to store read data
1724 * @oob_required: caller requires OOB data read to chip->oob_poi
1725 * @page: page number to read
1727 * The hw generator calculates the error syndrome automatically. Therefore we
1728 * need a special oob layout and handling.
1730 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1731 uint8_t *buf
, int oob_required
, int page
)
1733 int i
, eccsize
= chip
->ecc
.size
;
1734 int eccbytes
= chip
->ecc
.bytes
;
1735 int eccsteps
= chip
->ecc
.steps
;
1736 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1738 uint8_t *oob
= chip
->oob_poi
;
1739 unsigned int max_bitflips
= 0;
1741 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1744 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1745 chip
->read_buf(mtd
, p
, eccsize
);
1747 if (chip
->ecc
.prepad
) {
1748 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1749 oob
+= chip
->ecc
.prepad
;
1752 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1753 chip
->read_buf(mtd
, oob
, eccbytes
);
1754 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1758 if (chip
->ecc
.postpad
) {
1759 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1760 oob
+= chip
->ecc
.postpad
;
1763 if (stat
== -EBADMSG
&&
1764 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1765 /* check for empty pages with bitflips */
1766 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1770 chip
->ecc
.strength
);
1774 mtd
->ecc_stats
.failed
++;
1776 mtd
->ecc_stats
.corrected
+= stat
;
1777 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1781 /* Calculate remaining oob bytes */
1782 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1784 chip
->read_buf(mtd
, oob
, i
);
1786 return max_bitflips
;
1790 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1791 * @mtd: mtd info structure
1792 * @oob: oob destination address
1793 * @ops: oob ops structure
1794 * @len: size of oob to transfer
1796 static uint8_t *nand_transfer_oob(struct mtd_info
*mtd
, uint8_t *oob
,
1797 struct mtd_oob_ops
*ops
, size_t len
)
1799 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1802 switch (ops
->mode
) {
1804 case MTD_OPS_PLACE_OOB
:
1806 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1809 case MTD_OPS_AUTO_OOB
:
1810 ret
= mtd_ooblayout_get_databytes(mtd
, oob
, chip
->oob_poi
,
1822 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1823 * @mtd: MTD device structure
1824 * @retry_mode: the retry mode to use
1826 * Some vendors supply a special command to shift the Vt threshold, to be used
1827 * when there are too many bitflips in a page (i.e., ECC error). After setting
1828 * a new threshold, the host should retry reading the page.
1830 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1832 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1834 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1836 if (retry_mode
>= chip
->read_retries
)
1839 if (!chip
->setup_read_retry
)
1842 return chip
->setup_read_retry(mtd
, retry_mode
);
1846 * nand_do_read_ops - [INTERN] Read data with ECC
1847 * @mtd: MTD device structure
1848 * @from: offset to read from
1849 * @ops: oob ops structure
1851 * Internal function. Called with chip held.
1853 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1854 struct mtd_oob_ops
*ops
)
1856 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1857 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1859 uint32_t readlen
= ops
->len
;
1860 uint32_t oobreadlen
= ops
->ooblen
;
1861 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1863 uint8_t *bufpoi
, *oob
, *buf
;
1865 unsigned int max_bitflips
= 0;
1867 bool ecc_fail
= false;
1869 chipnr
= (int)(from
>> chip
->chip_shift
);
1870 chip
->select_chip(mtd
, chipnr
);
1872 realpage
= (int)(from
>> chip
->page_shift
);
1873 page
= realpage
& chip
->pagemask
;
1875 col
= (int)(from
& (mtd
->writesize
- 1));
1879 oob_required
= oob
? 1 : 0;
1882 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1884 bytes
= min(mtd
->writesize
- col
, readlen
);
1885 aligned
= (bytes
== mtd
->writesize
);
1889 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
1890 use_bufpoi
= !virt_addr_valid(buf
) ||
1891 !IS_ALIGNED((unsigned long)buf
,
1896 /* Is the current page in the buffer? */
1897 if (realpage
!= chip
->pagebuf
|| oob
) {
1898 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1900 if (use_bufpoi
&& aligned
)
1901 pr_debug("%s: using read bounce buffer for buf@%p\n",
1905 if (nand_standard_page_accessors(&chip
->ecc
))
1906 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1909 * Now read the page into the buffer. Absent an error,
1910 * the read methods return max bitflips per ecc step.
1912 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1913 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1916 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1918 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1922 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1923 oob_required
, page
);
1926 /* Invalidate page cache */
1931 /* Transfer not aligned data */
1933 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1934 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1935 (ops
->mode
!= MTD_OPS_RAW
)) {
1936 chip
->pagebuf
= realpage
;
1937 chip
->pagebuf_bitflips
= ret
;
1939 /* Invalidate page cache */
1942 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1945 if (unlikely(oob
)) {
1946 int toread
= min(oobreadlen
, max_oobsize
);
1949 oob
= nand_transfer_oob(mtd
,
1951 oobreadlen
-= toread
;
1955 if (chip
->options
& NAND_NEED_READRDY
) {
1956 /* Apply delay or wait for ready/busy pin */
1957 if (!chip
->dev_ready
)
1958 udelay(chip
->chip_delay
);
1960 nand_wait_ready(mtd
);
1963 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1964 if (retry_mode
+ 1 < chip
->read_retries
) {
1966 ret
= nand_setup_read_retry(mtd
,
1971 /* Reset failures; retry */
1972 mtd
->ecc_stats
.failed
= ecc_failures
;
1975 /* No more retry modes; real failure */
1981 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1983 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1985 max_bitflips
= max_t(unsigned int, max_bitflips
,
1986 chip
->pagebuf_bitflips
);
1991 /* Reset to retry mode 0 */
1993 ret
= nand_setup_read_retry(mtd
, 0);
2002 /* For subsequent reads align to page boundary */
2004 /* Increment page address */
2007 page
= realpage
& chip
->pagemask
;
2008 /* Check, if we cross a chip boundary */
2011 chip
->select_chip(mtd
, -1);
2012 chip
->select_chip(mtd
, chipnr
);
2015 chip
->select_chip(mtd
, -1);
2017 ops
->retlen
= ops
->len
- (size_t) readlen
;
2019 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
2027 return max_bitflips
;
2031 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
2032 * @mtd: MTD device structure
2033 * @from: offset to read from
2034 * @len: number of bytes to read
2035 * @retlen: pointer to variable to store the number of read bytes
2036 * @buf: the databuffer to put data
2038 * Get hold of the chip and call nand_do_read.
2040 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
2041 size_t *retlen
, uint8_t *buf
)
2043 struct mtd_oob_ops ops
;
2046 nand_get_device(mtd
, FL_READING
);
2047 memset(&ops
, 0, sizeof(ops
));
2050 ops
.mode
= MTD_OPS_PLACE_OOB
;
2051 ret
= nand_do_read_ops(mtd
, from
, &ops
);
2052 *retlen
= ops
.retlen
;
2053 nand_release_device(mtd
);
2058 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
2059 * @mtd: mtd info structure
2060 * @chip: nand chip info structure
2061 * @page: page number to read
2063 int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
2065 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
2066 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2069 EXPORT_SYMBOL(nand_read_oob_std
);
2072 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
2074 * @mtd: mtd info structure
2075 * @chip: nand chip info structure
2076 * @page: page number to read
2078 int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2081 int length
= mtd
->oobsize
;
2082 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2083 int eccsize
= chip
->ecc
.size
;
2084 uint8_t *bufpoi
= chip
->oob_poi
;
2085 int i
, toread
, sndrnd
= 0, pos
;
2087 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
2088 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
2090 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2091 if (mtd
->writesize
> 512)
2092 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
2094 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
2097 toread
= min_t(int, length
, chunk
);
2098 chip
->read_buf(mtd
, bufpoi
, toread
);
2103 chip
->read_buf(mtd
, bufpoi
, length
);
2107 EXPORT_SYMBOL(nand_read_oob_syndrome
);
2110 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
2111 * @mtd: mtd info structure
2112 * @chip: nand chip info structure
2113 * @page: page number to write
2115 int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
2118 const uint8_t *buf
= chip
->oob_poi
;
2119 int length
= mtd
->oobsize
;
2121 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
2122 chip
->write_buf(mtd
, buf
, length
);
2123 /* Send command to program the OOB data */
2124 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2126 status
= chip
->waitfunc(mtd
, chip
);
2128 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2130 EXPORT_SYMBOL(nand_write_oob_std
);
2133 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
2134 * with syndrome - only for large page flash
2135 * @mtd: mtd info structure
2136 * @chip: nand chip info structure
2137 * @page: page number to write
2139 int nand_write_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2142 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2143 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
2144 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
2145 const uint8_t *bufpoi
= chip
->oob_poi
;
2148 * data-ecc-data-ecc ... ecc-oob
2150 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2152 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
2153 pos
= steps
* (eccsize
+ chunk
);
2158 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
2159 for (i
= 0; i
< steps
; i
++) {
2161 if (mtd
->writesize
<= 512) {
2162 uint32_t fill
= 0xFFFFFFFF;
2166 int num
= min_t(int, len
, 4);
2167 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2172 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2173 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2177 len
= min_t(int, length
, chunk
);
2178 chip
->write_buf(mtd
, bufpoi
, len
);
2183 chip
->write_buf(mtd
, bufpoi
, length
);
2185 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2186 status
= chip
->waitfunc(mtd
, chip
);
2188 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2190 EXPORT_SYMBOL(nand_write_oob_syndrome
);
2193 * nand_do_read_oob - [INTERN] NAND read out-of-band
2194 * @mtd: MTD device structure
2195 * @from: offset to read from
2196 * @ops: oob operations description structure
2198 * NAND read out-of-band data from the spare area.
2200 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2201 struct mtd_oob_ops
*ops
)
2203 int page
, realpage
, chipnr
;
2204 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2205 struct mtd_ecc_stats stats
;
2206 int readlen
= ops
->ooblen
;
2208 uint8_t *buf
= ops
->oobbuf
;
2211 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2212 __func__
, (unsigned long long)from
, readlen
);
2214 stats
= mtd
->ecc_stats
;
2216 len
= mtd_oobavail(mtd
, ops
);
2218 if (unlikely(ops
->ooboffs
>= len
)) {
2219 pr_debug("%s: attempt to start read outside oob\n",
2224 /* Do not allow reads past end of device */
2225 if (unlikely(from
>= mtd
->size
||
2226 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2227 (from
>> chip
->page_shift
)) * len
)) {
2228 pr_debug("%s: attempt to read beyond end of device\n",
2233 chipnr
= (int)(from
>> chip
->chip_shift
);
2234 chip
->select_chip(mtd
, chipnr
);
2236 /* Shift to get page */
2237 realpage
= (int)(from
>> chip
->page_shift
);
2238 page
= realpage
& chip
->pagemask
;
2241 if (ops
->mode
== MTD_OPS_RAW
)
2242 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2244 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2249 len
= min(len
, readlen
);
2250 buf
= nand_transfer_oob(mtd
, buf
, ops
, len
);
2252 if (chip
->options
& NAND_NEED_READRDY
) {
2253 /* Apply delay or wait for ready/busy pin */
2254 if (!chip
->dev_ready
)
2255 udelay(chip
->chip_delay
);
2257 nand_wait_ready(mtd
);
2264 /* Increment page address */
2267 page
= realpage
& chip
->pagemask
;
2268 /* Check, if we cross a chip boundary */
2271 chip
->select_chip(mtd
, -1);
2272 chip
->select_chip(mtd
, chipnr
);
2275 chip
->select_chip(mtd
, -1);
2277 ops
->oobretlen
= ops
->ooblen
- readlen
;
2282 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2285 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2289 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2290 * @mtd: MTD device structure
2291 * @from: offset to read from
2292 * @ops: oob operation description structure
2294 * NAND read data and/or out-of-band data.
2296 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2297 struct mtd_oob_ops
*ops
)
2303 /* Do not allow reads past end of device */
2304 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2305 pr_debug("%s: attempt to read beyond end of device\n",
2310 if (ops
->mode
!= MTD_OPS_PLACE_OOB
&&
2311 ops
->mode
!= MTD_OPS_AUTO_OOB
&&
2312 ops
->mode
!= MTD_OPS_RAW
)
2315 nand_get_device(mtd
, FL_READING
);
2318 ret
= nand_do_read_oob(mtd
, from
, ops
);
2320 ret
= nand_do_read_ops(mtd
, from
, ops
);
2322 nand_release_device(mtd
);
2328 * nand_write_page_raw - [INTERN] raw page write function
2329 * @mtd: mtd info structure
2330 * @chip: nand chip info structure
2332 * @oob_required: must write chip->oob_poi to OOB
2333 * @page: page number to write
2335 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2337 int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2338 const uint8_t *buf
, int oob_required
, int page
)
2340 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2342 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2346 EXPORT_SYMBOL(nand_write_page_raw
);
2349 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2350 * @mtd: mtd info structure
2351 * @chip: nand chip info structure
2353 * @oob_required: must write chip->oob_poi to OOB
2354 * @page: page number to write
2356 * We need a special oob layout and handling even when ECC isn't checked.
2358 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2359 struct nand_chip
*chip
,
2360 const uint8_t *buf
, int oob_required
,
2363 int eccsize
= chip
->ecc
.size
;
2364 int eccbytes
= chip
->ecc
.bytes
;
2365 uint8_t *oob
= chip
->oob_poi
;
2368 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2369 chip
->write_buf(mtd
, buf
, eccsize
);
2372 if (chip
->ecc
.prepad
) {
2373 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2374 oob
+= chip
->ecc
.prepad
;
2377 chip
->write_buf(mtd
, oob
, eccbytes
);
2380 if (chip
->ecc
.postpad
) {
2381 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2382 oob
+= chip
->ecc
.postpad
;
2386 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2388 chip
->write_buf(mtd
, oob
, size
);
2393 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2394 * @mtd: mtd info structure
2395 * @chip: nand chip info structure
2397 * @oob_required: must write chip->oob_poi to OOB
2398 * @page: page number to write
2400 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2401 const uint8_t *buf
, int oob_required
,
2404 int i
, eccsize
= chip
->ecc
.size
, ret
;
2405 int eccbytes
= chip
->ecc
.bytes
;
2406 int eccsteps
= chip
->ecc
.steps
;
2407 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2408 const uint8_t *p
= buf
;
2410 /* Software ECC calculation */
2411 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2412 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2414 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2419 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2423 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2424 * @mtd: mtd info structure
2425 * @chip: nand chip info structure
2427 * @oob_required: must write chip->oob_poi to OOB
2428 * @page: page number to write
2430 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2431 const uint8_t *buf
, int oob_required
,
2434 int i
, eccsize
= chip
->ecc
.size
, ret
;
2435 int eccbytes
= chip
->ecc
.bytes
;
2436 int eccsteps
= chip
->ecc
.steps
;
2437 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2438 const uint8_t *p
= buf
;
2440 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2441 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2442 chip
->write_buf(mtd
, p
, eccsize
);
2443 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2446 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2451 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2458 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2459 * @mtd: mtd info structure
2460 * @chip: nand chip info structure
2461 * @offset: column address of subpage within the page
2462 * @data_len: data length
2464 * @oob_required: must write chip->oob_poi to OOB
2465 * @page: page number to write
2467 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2468 struct nand_chip
*chip
, uint32_t offset
,
2469 uint32_t data_len
, const uint8_t *buf
,
2470 int oob_required
, int page
)
2472 uint8_t *oob_buf
= chip
->oob_poi
;
2473 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2474 int ecc_size
= chip
->ecc
.size
;
2475 int ecc_bytes
= chip
->ecc
.bytes
;
2476 int ecc_steps
= chip
->ecc
.steps
;
2477 uint32_t start_step
= offset
/ ecc_size
;
2478 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2479 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2482 for (step
= 0; step
< ecc_steps
; step
++) {
2483 /* configure controller for WRITE access */
2484 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2486 /* write data (untouched subpages already masked by 0xFF) */
2487 chip
->write_buf(mtd
, buf
, ecc_size
);
2489 /* mask ECC of un-touched subpages by padding 0xFF */
2490 if ((step
< start_step
) || (step
> end_step
))
2491 memset(ecc_calc
, 0xff, ecc_bytes
);
2493 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2495 /* mask OOB of un-touched subpages by padding 0xFF */
2496 /* if oob_required, preserve OOB metadata of written subpage */
2497 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2498 memset(oob_buf
, 0xff, oob_bytes
);
2501 ecc_calc
+= ecc_bytes
;
2502 oob_buf
+= oob_bytes
;
2505 /* copy calculated ECC for whole page to chip->buffer->oob */
2506 /* this include masked-value(0xFF) for unwritten subpages */
2507 ecc_calc
= chip
->buffers
->ecccalc
;
2508 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2513 /* write OOB buffer to NAND device */
2514 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2521 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2522 * @mtd: mtd info structure
2523 * @chip: nand chip info structure
2525 * @oob_required: must write chip->oob_poi to OOB
2526 * @page: page number to write
2528 * The hw generator calculates the error syndrome automatically. Therefore we
2529 * need a special oob layout and handling.
2531 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2532 struct nand_chip
*chip
,
2533 const uint8_t *buf
, int oob_required
,
2536 int i
, eccsize
= chip
->ecc
.size
;
2537 int eccbytes
= chip
->ecc
.bytes
;
2538 int eccsteps
= chip
->ecc
.steps
;
2539 const uint8_t *p
= buf
;
2540 uint8_t *oob
= chip
->oob_poi
;
2542 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2544 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2545 chip
->write_buf(mtd
, p
, eccsize
);
2547 if (chip
->ecc
.prepad
) {
2548 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2549 oob
+= chip
->ecc
.prepad
;
2552 chip
->ecc
.calculate(mtd
, p
, oob
);
2553 chip
->write_buf(mtd
, oob
, eccbytes
);
2556 if (chip
->ecc
.postpad
) {
2557 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2558 oob
+= chip
->ecc
.postpad
;
2562 /* Calculate remaining oob bytes */
2563 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2565 chip
->write_buf(mtd
, oob
, i
);
2571 * nand_write_page - write one page
2572 * @mtd: MTD device structure
2573 * @chip: NAND chip descriptor
2574 * @offset: address offset within the page
2575 * @data_len: length of actual data to be written
2576 * @buf: the data to write
2577 * @oob_required: must write chip->oob_poi to OOB
2578 * @page: page number to write
2579 * @raw: use _raw version of write_page
2581 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2582 uint32_t offset
, int data_len
, const uint8_t *buf
,
2583 int oob_required
, int page
, int raw
)
2585 int status
, subpage
;
2587 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2588 chip
->ecc
.write_subpage
)
2589 subpage
= offset
|| (data_len
< mtd
->writesize
);
2593 if (nand_standard_page_accessors(&chip
->ecc
))
2594 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2597 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2598 oob_required
, page
);
2600 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2601 buf
, oob_required
, page
);
2603 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2609 if (nand_standard_page_accessors(&chip
->ecc
)) {
2610 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2612 status
= chip
->waitfunc(mtd
, chip
);
2613 if (status
& NAND_STATUS_FAIL
)
2621 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2622 * @mtd: MTD device structure
2623 * @oob: oob data buffer
2624 * @len: oob data write length
2625 * @ops: oob ops structure
2627 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2628 struct mtd_oob_ops
*ops
)
2630 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2634 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2635 * data from a previous OOB read.
2637 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2639 switch (ops
->mode
) {
2641 case MTD_OPS_PLACE_OOB
:
2643 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2646 case MTD_OPS_AUTO_OOB
:
2647 ret
= mtd_ooblayout_set_databytes(mtd
, oob
, chip
->oob_poi
,
2658 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2661 * nand_do_write_ops - [INTERN] NAND write with ECC
2662 * @mtd: MTD device structure
2663 * @to: offset to write to
2664 * @ops: oob operations description structure
2666 * NAND write with ECC.
2668 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2669 struct mtd_oob_ops
*ops
)
2671 int chipnr
, realpage
, page
, column
;
2672 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2673 uint32_t writelen
= ops
->len
;
2675 uint32_t oobwritelen
= ops
->ooblen
;
2676 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2678 uint8_t *oob
= ops
->oobbuf
;
2679 uint8_t *buf
= ops
->datbuf
;
2681 int oob_required
= oob
? 1 : 0;
2687 /* Reject writes, which are not page aligned */
2688 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2689 pr_notice("%s: attempt to write non page aligned data\n",
2694 column
= to
& (mtd
->writesize
- 1);
2696 chipnr
= (int)(to
>> chip
->chip_shift
);
2697 chip
->select_chip(mtd
, chipnr
);
2699 /* Check, if it is write protected */
2700 if (nand_check_wp(mtd
)) {
2705 realpage
= (int)(to
>> chip
->page_shift
);
2706 page
= realpage
& chip
->pagemask
;
2708 /* Invalidate the page cache, when we write to the cached page */
2709 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2710 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2713 /* Don't allow multipage oob writes with offset */
2714 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2720 int bytes
= mtd
->writesize
;
2721 uint8_t *wbuf
= buf
;
2723 int part_pagewr
= (column
|| writelen
< mtd
->writesize
);
2727 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2728 use_bufpoi
= !virt_addr_valid(buf
) ||
2729 !IS_ALIGNED((unsigned long)buf
,
2734 /* Partial page write?, or need to use bounce buffer */
2736 pr_debug("%s: using write bounce buffer for buf@%p\n",
2739 bytes
= min_t(int, bytes
- column
, writelen
);
2741 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2742 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2743 wbuf
= chip
->buffers
->databuf
;
2746 if (unlikely(oob
)) {
2747 size_t len
= min(oobwritelen
, oobmaxlen
);
2748 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2751 /* We still need to erase leftover OOB data */
2752 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2755 ret
= nand_write_page(mtd
, chip
, column
, bytes
, wbuf
,
2757 (ops
->mode
== MTD_OPS_RAW
));
2769 page
= realpage
& chip
->pagemask
;
2770 /* Check, if we cross a chip boundary */
2773 chip
->select_chip(mtd
, -1);
2774 chip
->select_chip(mtd
, chipnr
);
2778 ops
->retlen
= ops
->len
- writelen
;
2780 ops
->oobretlen
= ops
->ooblen
;
2783 chip
->select_chip(mtd
, -1);
2788 * panic_nand_write - [MTD Interface] NAND write with ECC
2789 * @mtd: MTD device structure
2790 * @to: offset to write to
2791 * @len: number of bytes to write
2792 * @retlen: pointer to variable to store the number of written bytes
2793 * @buf: the data to write
2795 * NAND write with ECC. Used when performing writes in interrupt context, this
2796 * may for example be called by mtdoops when writing an oops while in panic.
2798 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2799 size_t *retlen
, const uint8_t *buf
)
2801 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2802 struct mtd_oob_ops ops
;
2805 /* Wait for the device to get ready */
2806 panic_nand_wait(mtd
, chip
, 400);
2808 /* Grab the device */
2809 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2811 memset(&ops
, 0, sizeof(ops
));
2813 ops
.datbuf
= (uint8_t *)buf
;
2814 ops
.mode
= MTD_OPS_PLACE_OOB
;
2816 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2818 *retlen
= ops
.retlen
;
2823 * nand_write - [MTD Interface] NAND write with ECC
2824 * @mtd: MTD device structure
2825 * @to: offset to write to
2826 * @len: number of bytes to write
2827 * @retlen: pointer to variable to store the number of written bytes
2828 * @buf: the data to write
2830 * NAND write with ECC.
2832 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2833 size_t *retlen
, const uint8_t *buf
)
2835 struct mtd_oob_ops ops
;
2838 nand_get_device(mtd
, FL_WRITING
);
2839 memset(&ops
, 0, sizeof(ops
));
2841 ops
.datbuf
= (uint8_t *)buf
;
2842 ops
.mode
= MTD_OPS_PLACE_OOB
;
2843 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2844 *retlen
= ops
.retlen
;
2845 nand_release_device(mtd
);
2850 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2851 * @mtd: MTD device structure
2852 * @to: offset to write to
2853 * @ops: oob operation description structure
2855 * NAND write out-of-band.
2857 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2858 struct mtd_oob_ops
*ops
)
2860 int chipnr
, page
, status
, len
;
2861 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2863 pr_debug("%s: to = 0x%08x, len = %i\n",
2864 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2866 len
= mtd_oobavail(mtd
, ops
);
2868 /* Do not allow write past end of page */
2869 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2870 pr_debug("%s: attempt to write past end of page\n",
2875 if (unlikely(ops
->ooboffs
>= len
)) {
2876 pr_debug("%s: attempt to start write outside oob\n",
2881 /* Do not allow write past end of device */
2882 if (unlikely(to
>= mtd
->size
||
2883 ops
->ooboffs
+ ops
->ooblen
>
2884 ((mtd
->size
>> chip
->page_shift
) -
2885 (to
>> chip
->page_shift
)) * len
)) {
2886 pr_debug("%s: attempt to write beyond end of device\n",
2891 chipnr
= (int)(to
>> chip
->chip_shift
);
2894 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2895 * of my DiskOnChip 2000 test units) will clear the whole data page too
2896 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2897 * it in the doc2000 driver in August 1999. dwmw2.
2899 nand_reset(chip
, chipnr
);
2901 chip
->select_chip(mtd
, chipnr
);
2903 /* Shift to get page */
2904 page
= (int)(to
>> chip
->page_shift
);
2906 /* Check, if it is write protected */
2907 if (nand_check_wp(mtd
)) {
2908 chip
->select_chip(mtd
, -1);
2912 /* Invalidate the page cache, if we write to the cached page */
2913 if (page
== chip
->pagebuf
)
2916 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2918 if (ops
->mode
== MTD_OPS_RAW
)
2919 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2921 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2923 chip
->select_chip(mtd
, -1);
2928 ops
->oobretlen
= ops
->ooblen
;
2934 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2935 * @mtd: MTD device structure
2936 * @to: offset to write to
2937 * @ops: oob operation description structure
2939 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2940 struct mtd_oob_ops
*ops
)
2942 int ret
= -ENOTSUPP
;
2946 /* Do not allow writes past end of device */
2947 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2948 pr_debug("%s: attempt to write beyond end of device\n",
2953 nand_get_device(mtd
, FL_WRITING
);
2955 switch (ops
->mode
) {
2956 case MTD_OPS_PLACE_OOB
:
2957 case MTD_OPS_AUTO_OOB
:
2966 ret
= nand_do_write_oob(mtd
, to
, ops
);
2968 ret
= nand_do_write_ops(mtd
, to
, ops
);
2971 nand_release_device(mtd
);
2976 * single_erase - [GENERIC] NAND standard block erase command function
2977 * @mtd: MTD device structure
2978 * @page: the page address of the block which will be erased
2980 * Standard erase command for NAND chips. Returns NAND status.
2982 static int single_erase(struct mtd_info
*mtd
, int page
)
2984 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2985 /* Send commands to erase a block */
2986 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2987 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2989 return chip
->waitfunc(mtd
, chip
);
2993 * nand_erase - [MTD Interface] erase block(s)
2994 * @mtd: MTD device structure
2995 * @instr: erase instruction
2997 * Erase one ore more blocks.
2999 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
3001 return nand_erase_nand(mtd
, instr
, 0);
3005 * nand_erase_nand - [INTERN] erase block(s)
3006 * @mtd: MTD device structure
3007 * @instr: erase instruction
3008 * @allowbbt: allow erasing the bbt area
3010 * Erase one ore more blocks.
3012 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
3015 int page
, status
, pages_per_block
, ret
, chipnr
;
3016 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3020 __func__
, (unsigned long long)instr
->addr
,
3021 (unsigned long long)instr
->len
);
3023 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
3026 /* Grab the lock and see if the device is available */
3027 nand_get_device(mtd
, FL_ERASING
);
3029 /* Shift to get first page */
3030 page
= (int)(instr
->addr
>> chip
->page_shift
);
3031 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
3033 /* Calculate pages in each block */
3034 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
3036 /* Select the NAND device */
3037 chip
->select_chip(mtd
, chipnr
);
3039 /* Check, if it is write protected */
3040 if (nand_check_wp(mtd
)) {
3041 pr_debug("%s: device is write protected!\n",
3043 instr
->state
= MTD_ERASE_FAILED
;
3047 /* Loop through the pages */
3050 instr
->state
= MTD_ERASING
;
3053 /* Check if we have a bad block, we do not erase bad blocks! */
3054 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
3055 chip
->page_shift
, allowbbt
)) {
3056 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3058 instr
->state
= MTD_ERASE_FAILED
;
3063 * Invalidate the page cache, if we erase the block which
3064 * contains the current cached page.
3066 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
3067 (page
+ pages_per_block
))
3070 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
3072 /* See if block erase succeeded */
3073 if (status
& NAND_STATUS_FAIL
) {
3074 pr_debug("%s: failed erase, page 0x%08x\n",
3076 instr
->state
= MTD_ERASE_FAILED
;
3078 ((loff_t
)page
<< chip
->page_shift
);
3082 /* Increment page address and decrement length */
3083 len
-= (1ULL << chip
->phys_erase_shift
);
3084 page
+= pages_per_block
;
3086 /* Check, if we cross a chip boundary */
3087 if (len
&& !(page
& chip
->pagemask
)) {
3089 chip
->select_chip(mtd
, -1);
3090 chip
->select_chip(mtd
, chipnr
);
3093 instr
->state
= MTD_ERASE_DONE
;
3097 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
3099 /* Deselect and wake up anyone waiting on the device */
3100 chip
->select_chip(mtd
, -1);
3101 nand_release_device(mtd
);
3103 /* Do call back function */
3105 mtd_erase_callback(instr
);
3107 /* Return more or less happy */
3112 * nand_sync - [MTD Interface] sync
3113 * @mtd: MTD device structure
3115 * Sync is actually a wait for chip ready function.
3117 static void nand_sync(struct mtd_info
*mtd
)
3119 pr_debug("%s: called\n", __func__
);
3121 /* Grab the lock and see if the device is available */
3122 nand_get_device(mtd
, FL_SYNCING
);
3123 /* Release it and go back */
3124 nand_release_device(mtd
);
3128 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3129 * @mtd: MTD device structure
3130 * @offs: offset relative to mtd start
3132 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
3134 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3135 int chipnr
= (int)(offs
>> chip
->chip_shift
);
3138 /* Select the NAND device */
3139 nand_get_device(mtd
, FL_READING
);
3140 chip
->select_chip(mtd
, chipnr
);
3142 ret
= nand_block_checkbad(mtd
, offs
, 0);
3144 chip
->select_chip(mtd
, -1);
3145 nand_release_device(mtd
);
3151 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3152 * @mtd: MTD device structure
3153 * @ofs: offset relative to mtd start
3155 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3159 ret
= nand_block_isbad(mtd
, ofs
);
3161 /* If it was bad already, return success and do nothing */
3167 return nand_block_markbad_lowlevel(mtd
, ofs
);
3171 * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd
3172 * @mtd: MTD device structure
3173 * @ofs: offset relative to mtd start
3174 * @len: length of mtd
3176 static int nand_max_bad_blocks(struct mtd_info
*mtd
, loff_t ofs
, size_t len
)
3178 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3179 u32 part_start_block
;
3185 * max_bb_per_die and blocks_per_die used to determine
3186 * the maximum bad block count.
3188 if (!chip
->max_bb_per_die
|| !chip
->blocks_per_die
)
3191 /* Get the start and end of the partition in erase blocks. */
3192 part_start_block
= mtd_div_by_eb(ofs
, mtd
);
3193 part_end_block
= mtd_div_by_eb(len
, mtd
) + part_start_block
- 1;
3195 /* Get the start and end LUNs of the partition. */
3196 part_start_die
= part_start_block
/ chip
->blocks_per_die
;
3197 part_end_die
= part_end_block
/ chip
->blocks_per_die
;
3200 * Look up the bad blocks per unit and multiply by the number of units
3201 * that the partition spans.
3203 return chip
->max_bb_per_die
* (part_end_die
- part_start_die
+ 1);
3207 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3208 * @mtd: MTD device structure
3209 * @chip: nand chip info structure
3210 * @addr: feature address.
3211 * @subfeature_param: the subfeature parameters, a four bytes array.
3213 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3214 int addr
, uint8_t *subfeature_param
)
3219 if (!chip
->onfi_version
||
3220 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3221 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3224 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3225 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3226 chip
->write_byte(mtd
, subfeature_param
[i
]);
3228 status
= chip
->waitfunc(mtd
, chip
);
3229 if (status
& NAND_STATUS_FAIL
)
3235 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3236 * @mtd: MTD device structure
3237 * @chip: nand chip info structure
3238 * @addr: feature address.
3239 * @subfeature_param: the subfeature parameters, a four bytes array.
3241 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3242 int addr
, uint8_t *subfeature_param
)
3246 if (!chip
->onfi_version
||
3247 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3248 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3251 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3252 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3253 *subfeature_param
++ = chip
->read_byte(mtd
);
3258 * nand_onfi_get_set_features_notsupp - set/get features stub returning
3260 * @mtd: MTD device structure
3261 * @chip: nand chip info structure
3262 * @addr: feature address.
3263 * @subfeature_param: the subfeature parameters, a four bytes array.
3265 * Should be used by NAND controller drivers that do not support the SET/GET
3266 * FEATURES operations.
3268 int nand_onfi_get_set_features_notsupp(struct mtd_info
*mtd
,
3269 struct nand_chip
*chip
, int addr
,
3270 u8
*subfeature_param
)
3274 EXPORT_SYMBOL(nand_onfi_get_set_features_notsupp
);
3277 * nand_suspend - [MTD Interface] Suspend the NAND flash
3278 * @mtd: MTD device structure
3280 static int nand_suspend(struct mtd_info
*mtd
)
3282 return nand_get_device(mtd
, FL_PM_SUSPENDED
);
3286 * nand_resume - [MTD Interface] Resume the NAND flash
3287 * @mtd: MTD device structure
3289 static void nand_resume(struct mtd_info
*mtd
)
3291 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3293 if (chip
->state
== FL_PM_SUSPENDED
)
3294 nand_release_device(mtd
);
3296 pr_err("%s called for a chip which is not in suspended state\n",
3301 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3302 * prevent further operations
3303 * @mtd: MTD device structure
3305 static void nand_shutdown(struct mtd_info
*mtd
)
3307 nand_get_device(mtd
, FL_PM_SUSPENDED
);
3310 /* Set default functions */
3311 static void nand_set_defaults(struct nand_chip
*chip
)
3313 unsigned int busw
= chip
->options
& NAND_BUSWIDTH_16
;
3315 /* check for proper chip_delay setup, set 20us if not */
3316 if (!chip
->chip_delay
)
3317 chip
->chip_delay
= 20;
3319 /* check, if a user supplied command function given */
3320 if (chip
->cmdfunc
== NULL
)
3321 chip
->cmdfunc
= nand_command
;
3323 /* check, if a user supplied wait function given */
3324 if (chip
->waitfunc
== NULL
)
3325 chip
->waitfunc
= nand_wait
;
3327 if (!chip
->select_chip
)
3328 chip
->select_chip
= nand_select_chip
;
3330 /* set for ONFI nand */
3331 if (!chip
->onfi_set_features
)
3332 chip
->onfi_set_features
= nand_onfi_set_features
;
3333 if (!chip
->onfi_get_features
)
3334 chip
->onfi_get_features
= nand_onfi_get_features
;
3336 /* If called twice, pointers that depend on busw may need to be reset */
3337 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3338 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3339 if (!chip
->read_word
)
3340 chip
->read_word
= nand_read_word
;
3341 if (!chip
->block_bad
)
3342 chip
->block_bad
= nand_block_bad
;
3343 if (!chip
->block_markbad
)
3344 chip
->block_markbad
= nand_default_block_markbad
;
3345 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3346 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3347 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3348 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3349 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3350 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3351 if (!chip
->scan_bbt
)
3352 chip
->scan_bbt
= nand_default_bbt
;
3354 if (!chip
->controller
) {
3355 chip
->controller
= &chip
->hwcontrol
;
3356 nand_hw_control_init(chip
->controller
);
3359 if (!chip
->buf_align
)
3360 chip
->buf_align
= 1;
3363 /* Sanitize ONFI strings so we can safely print them */
3364 static void sanitize_string(uint8_t *s
, size_t len
)
3368 /* Null terminate */
3371 /* Remove non printable chars */
3372 for (i
= 0; i
< len
- 1; i
++) {
3373 if (s
[i
] < ' ' || s
[i
] > 127)
3377 /* Remove trailing spaces */
3381 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3386 for (i
= 0; i
< 8; i
++)
3387 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3393 /* Parse the Extended Parameter Page. */
3394 static int nand_flash_detect_ext_param_page(struct nand_chip
*chip
,
3395 struct nand_onfi_params
*p
)
3397 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3398 struct onfi_ext_param_page
*ep
;
3399 struct onfi_ext_section
*s
;
3400 struct onfi_ext_ecc_info
*ecc
;
3406 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3407 ep
= kmalloc(len
, GFP_KERNEL
);
3411 /* Send our own NAND_CMD_PARAM. */
3412 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3414 /* Use the Change Read Column command to skip the ONFI param pages. */
3415 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3416 sizeof(*p
) * p
->num_of_param_pages
, -1);
3418 /* Read out the Extended Parameter Page. */
3419 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3420 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3421 != le16_to_cpu(ep
->crc
))) {
3422 pr_debug("fail in the CRC.\n");
3427 * Check the signature.
3428 * Do not strictly follow the ONFI spec, maybe changed in future.
3430 if (strncmp(ep
->sig
, "EPPS", 4)) {
3431 pr_debug("The signature is invalid.\n");
3435 /* find the ECC section. */
3436 cursor
= (uint8_t *)(ep
+ 1);
3437 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3438 s
= ep
->sections
+ i
;
3439 if (s
->type
== ONFI_SECTION_TYPE_2
)
3441 cursor
+= s
->length
* 16;
3443 if (i
== ONFI_EXT_SECTION_MAX
) {
3444 pr_debug("We can not find the ECC section.\n");
3448 /* get the info we want. */
3449 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3451 if (!ecc
->codeword_size
) {
3452 pr_debug("Invalid codeword size\n");
3456 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3457 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3466 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3468 static int nand_flash_detect_onfi(struct nand_chip
*chip
)
3470 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3471 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3475 /* Try ONFI for unknown chip or LP */
3476 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3477 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3478 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3481 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3482 for (i
= 0; i
< 3; i
++) {
3483 for (j
= 0; j
< sizeof(*p
); j
++)
3484 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3485 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3486 le16_to_cpu(p
->crc
)) {
3492 pr_err("Could not find valid ONFI parameter page; aborting\n");
3497 val
= le16_to_cpu(p
->revision
);
3499 chip
->onfi_version
= 23;
3500 else if (val
& (1 << 4))
3501 chip
->onfi_version
= 22;
3502 else if (val
& (1 << 3))
3503 chip
->onfi_version
= 21;
3504 else if (val
& (1 << 2))
3505 chip
->onfi_version
= 20;
3506 else if (val
& (1 << 1))
3507 chip
->onfi_version
= 10;
3509 if (!chip
->onfi_version
) {
3510 pr_info("unsupported ONFI version: %d\n", val
);
3514 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3515 sanitize_string(p
->model
, sizeof(p
->model
));
3517 mtd
->name
= p
->model
;
3519 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3522 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3523 * (don't ask me who thought of this...). MTD assumes that these
3524 * dimensions will be power-of-2, so just truncate the remaining area.
3526 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3527 mtd
->erasesize
*= mtd
->writesize
;
3529 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3531 /* See erasesize comment */
3532 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3533 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3534 chip
->bits_per_cell
= p
->bits_per_cell
;
3536 chip
->max_bb_per_die
= le16_to_cpu(p
->bb_per_lun
);
3537 chip
->blocks_per_die
= le32_to_cpu(p
->blocks_per_lun
);
3539 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3540 chip
->options
|= NAND_BUSWIDTH_16
;
3542 if (p
->ecc_bits
!= 0xff) {
3543 chip
->ecc_strength_ds
= p
->ecc_bits
;
3544 chip
->ecc_step_ds
= 512;
3545 } else if (chip
->onfi_version
>= 21 &&
3546 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3549 * The nand_flash_detect_ext_param_page() uses the
3550 * Change Read Column command which maybe not supported
3551 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3552 * now. We do not replace user supplied command function.
3554 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3555 chip
->cmdfunc
= nand_command_lp
;
3557 /* The Extended Parameter Page is supported since ONFI 2.1. */
3558 if (nand_flash_detect_ext_param_page(chip
, p
))
3559 pr_warn("Failed to detect ONFI extended param page\n");
3561 pr_warn("Could not retrieve ONFI ECC requirements\n");
3568 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3570 static int nand_flash_detect_jedec(struct nand_chip
*chip
)
3572 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3573 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3574 struct jedec_ecc_info
*ecc
;
3578 /* Try JEDEC for unknown chip or LP */
3579 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3580 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3581 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3582 chip
->read_byte(mtd
) != 'C')
3585 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3586 for (i
= 0; i
< 3; i
++) {
3587 for (j
= 0; j
< sizeof(*p
); j
++)
3588 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3590 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3591 le16_to_cpu(p
->crc
))
3596 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3601 val
= le16_to_cpu(p
->revision
);
3603 chip
->jedec_version
= 10;
3604 else if (val
& (1 << 1))
3605 chip
->jedec_version
= 1; /* vendor specific version */
3607 if (!chip
->jedec_version
) {
3608 pr_info("unsupported JEDEC version: %d\n", val
);
3612 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3613 sanitize_string(p
->model
, sizeof(p
->model
));
3615 mtd
->name
= p
->model
;
3617 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3619 /* Please reference to the comment for nand_flash_detect_onfi. */
3620 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3621 mtd
->erasesize
*= mtd
->writesize
;
3623 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3625 /* Please reference to the comment for nand_flash_detect_onfi. */
3626 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3627 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3628 chip
->bits_per_cell
= p
->bits_per_cell
;
3630 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3631 chip
->options
|= NAND_BUSWIDTH_16
;
3634 ecc
= &p
->ecc_info
[0];
3636 if (ecc
->codeword_size
>= 9) {
3637 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3638 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3640 pr_warn("Invalid codeword size\n");
3647 * nand_id_has_period - Check if an ID string has a given wraparound period
3648 * @id_data: the ID string
3649 * @arrlen: the length of the @id_data array
3650 * @period: the period of repitition
3652 * Check if an ID string is repeated within a given sequence of bytes at
3653 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3654 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3655 * if the repetition has a period of @period; otherwise, returns zero.
3657 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3660 for (i
= 0; i
< period
; i
++)
3661 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3662 if (id_data
[i
] != id_data
[j
])
3668 * nand_id_len - Get the length of an ID string returned by CMD_READID
3669 * @id_data: the ID string
3670 * @arrlen: the length of the @id_data array
3672 * Returns the length of the ID string, according to known wraparound/trailing
3673 * zero patterns. If no pattern exists, returns the length of the array.
3675 static int nand_id_len(u8
*id_data
, int arrlen
)
3677 int last_nonzero
, period
;
3679 /* Find last non-zero byte */
3680 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3681 if (id_data
[last_nonzero
])
3685 if (last_nonzero
< 0)
3688 /* Calculate wraparound period */
3689 for (period
= 1; period
< arrlen
; period
++)
3690 if (nand_id_has_period(id_data
, arrlen
, period
))
3693 /* There's a repeated pattern */
3694 if (period
< arrlen
)
3697 /* There are trailing zeros */
3698 if (last_nonzero
< arrlen
- 1)
3699 return last_nonzero
+ 1;
3701 /* No pattern detected */
3705 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3706 static int nand_get_bits_per_cell(u8 cellinfo
)
3710 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3711 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3716 * Many new NAND share similar device ID codes, which represent the size of the
3717 * chip. The rest of the parameters must be decoded according to generic or
3718 * manufacturer-specific "extended ID" decoding patterns.
3720 void nand_decode_ext_id(struct nand_chip
*chip
)
3722 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3724 u8
*id_data
= chip
->id
.data
;
3725 /* The 3rd id byte holds MLC / multichip data */
3726 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3727 /* The 4th id byte is the important one */
3731 mtd
->writesize
= 1024 << (extid
& 0x03);
3734 mtd
->oobsize
= (8 << (extid
& 0x01)) * (mtd
->writesize
>> 9);
3736 /* Calc blocksize. Blocksize is multiples of 64KiB */
3737 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3739 /* Get buswidth information */
3741 chip
->options
|= NAND_BUSWIDTH_16
;
3743 EXPORT_SYMBOL_GPL(nand_decode_ext_id
);
3746 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3747 * decodes a matching ID table entry and assigns the MTD size parameters for
3750 static void nand_decode_id(struct nand_chip
*chip
, struct nand_flash_dev
*type
)
3752 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3754 mtd
->erasesize
= type
->erasesize
;
3755 mtd
->writesize
= type
->pagesize
;
3756 mtd
->oobsize
= mtd
->writesize
/ 32;
3758 /* All legacy ID NAND are small-page, SLC */
3759 chip
->bits_per_cell
= 1;
3763 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3764 * heuristic patterns using various detected parameters (e.g., manufacturer,
3765 * page size, cell-type information).
3767 static void nand_decode_bbm_options(struct nand_chip
*chip
)
3769 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3771 /* Set the bad block position */
3772 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3773 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3775 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3778 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3780 return type
->id_len
;
3783 static bool find_full_id_nand(struct nand_chip
*chip
,
3784 struct nand_flash_dev
*type
)
3786 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3787 u8
*id_data
= chip
->id
.data
;
3789 if (!strncmp(type
->id
, id_data
, type
->id_len
)) {
3790 mtd
->writesize
= type
->pagesize
;
3791 mtd
->erasesize
= type
->erasesize
;
3792 mtd
->oobsize
= type
->oobsize
;
3794 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3795 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3796 chip
->options
|= type
->options
;
3797 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3798 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3799 chip
->onfi_timing_mode_default
=
3800 type
->onfi_timing_mode_default
;
3803 mtd
->name
= type
->name
;
3811 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
3812 * compliant and does not have a full-id or legacy-id entry in the nand_ids
3815 static void nand_manufacturer_detect(struct nand_chip
*chip
)
3818 * Try manufacturer detection if available and use
3819 * nand_decode_ext_id() otherwise.
3821 if (chip
->manufacturer
.desc
&& chip
->manufacturer
.desc
->ops
&&
3822 chip
->manufacturer
.desc
->ops
->detect
) {
3823 /* The 3rd id byte holds MLC / multichip data */
3824 chip
->bits_per_cell
= nand_get_bits_per_cell(chip
->id
.data
[2]);
3825 chip
->manufacturer
.desc
->ops
->detect(chip
);
3827 nand_decode_ext_id(chip
);
3832 * Manufacturer initialization. This function is called for all NANDs including
3833 * ONFI and JEDEC compliant ones.
3834 * Manufacturer drivers should put all their specific initialization code in
3835 * their ->init() hook.
3837 static int nand_manufacturer_init(struct nand_chip
*chip
)
3839 if (!chip
->manufacturer
.desc
|| !chip
->manufacturer
.desc
->ops
||
3840 !chip
->manufacturer
.desc
->ops
->init
)
3843 return chip
->manufacturer
.desc
->ops
->init(chip
);
3847 * Manufacturer cleanup. This function is called for all NANDs including
3848 * ONFI and JEDEC compliant ones.
3849 * Manufacturer drivers should put all their specific cleanup code in their
3852 static void nand_manufacturer_cleanup(struct nand_chip
*chip
)
3854 /* Release manufacturer private data */
3855 if (chip
->manufacturer
.desc
&& chip
->manufacturer
.desc
->ops
&&
3856 chip
->manufacturer
.desc
->ops
->cleanup
)
3857 chip
->manufacturer
.desc
->ops
->cleanup(chip
);
3861 * Get the flash and manufacturer id and lookup if the type is supported.
3863 static int nand_detect(struct nand_chip
*chip
, struct nand_flash_dev
*type
)
3865 const struct nand_manufacturer
*manufacturer
;
3866 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3869 u8
*id_data
= chip
->id
.data
;
3873 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3876 nand_reset(chip
, 0);
3878 /* Select the device */
3879 chip
->select_chip(mtd
, 0);
3881 /* Send the command for reading device ID */
3882 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3884 /* Read manufacturer and device IDs */
3885 maf_id
= chip
->read_byte(mtd
);
3886 dev_id
= chip
->read_byte(mtd
);
3889 * Try again to make sure, as some systems the bus-hold or other
3890 * interface concerns can cause random data which looks like a
3891 * possibly credible NAND flash to appear. If the two results do
3892 * not match, ignore the device completely.
3895 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3897 /* Read entire ID string */
3898 for (i
= 0; i
< ARRAY_SIZE(chip
->id
.data
); i
++)
3899 id_data
[i
] = chip
->read_byte(mtd
);
3901 if (id_data
[0] != maf_id
|| id_data
[1] != dev_id
) {
3902 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3903 maf_id
, dev_id
, id_data
[0], id_data
[1]);
3907 chip
->id
.len
= nand_id_len(id_data
, ARRAY_SIZE(chip
->id
.data
));
3909 /* Try to identify manufacturer */
3910 manufacturer
= nand_get_manufacturer(maf_id
);
3911 chip
->manufacturer
.desc
= manufacturer
;
3914 type
= nand_flash_ids
;
3917 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
3919 * This is required to make sure initial NAND bus width set by the
3920 * NAND controller driver is coherent with the real NAND bus width
3921 * (extracted by auto-detection code).
3923 busw
= chip
->options
& NAND_BUSWIDTH_16
;
3926 * The flag is only set (never cleared), reset it to its default value
3927 * before starting auto-detection.
3929 chip
->options
&= ~NAND_BUSWIDTH_16
;
3931 for (; type
->name
!= NULL
; type
++) {
3932 if (is_full_id_nand(type
)) {
3933 if (find_full_id_nand(chip
, type
))
3935 } else if (dev_id
== type
->dev_id
) {
3940 chip
->onfi_version
= 0;
3941 if (!type
->name
|| !type
->pagesize
) {
3942 /* Check if the chip is ONFI compliant */
3943 if (nand_flash_detect_onfi(chip
))
3946 /* Check if the chip is JEDEC compliant */
3947 if (nand_flash_detect_jedec(chip
))
3955 mtd
->name
= type
->name
;
3957 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3959 if (!type
->pagesize
)
3960 nand_manufacturer_detect(chip
);
3962 nand_decode_id(chip
, type
);
3964 /* Get chip options */
3965 chip
->options
|= type
->options
;
3969 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3970 WARN_ON(busw
& NAND_BUSWIDTH_16
);
3971 nand_set_defaults(chip
);
3972 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3974 * Check, if buswidth is correct. Hardware drivers should set
3977 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3979 pr_info("%s %s\n", nand_manufacturer_name(manufacturer
),
3981 pr_warn("bus width %d instead of %d bits\n", busw
? 16 : 8,
3982 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8);
3986 nand_decode_bbm_options(chip
);
3988 /* Calculate the address shift from the page size */
3989 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3990 /* Convert chipsize to number of pages per chip -1 */
3991 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3993 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3994 ffs(mtd
->erasesize
) - 1;
3995 if (chip
->chipsize
& 0xffffffff)
3996 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3998 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3999 chip
->chip_shift
+= 32 - 1;
4002 chip
->badblockbits
= 8;
4003 chip
->erase
= single_erase
;
4005 /* Do not replace user supplied command function! */
4006 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
4007 chip
->cmdfunc
= nand_command_lp
;
4009 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4012 if (chip
->onfi_version
)
4013 pr_info("%s %s\n", nand_manufacturer_name(manufacturer
),
4014 chip
->onfi_params
.model
);
4015 else if (chip
->jedec_version
)
4016 pr_info("%s %s\n", nand_manufacturer_name(manufacturer
),
4017 chip
->jedec_params
.model
);
4019 pr_info("%s %s\n", nand_manufacturer_name(manufacturer
),
4022 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4023 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
4024 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
4028 static const char * const nand_ecc_modes
[] = {
4029 [NAND_ECC_NONE
] = "none",
4030 [NAND_ECC_SOFT
] = "soft",
4031 [NAND_ECC_HW
] = "hw",
4032 [NAND_ECC_HW_SYNDROME
] = "hw_syndrome",
4033 [NAND_ECC_HW_OOB_FIRST
] = "hw_oob_first",
4034 [NAND_ECC_ON_DIE
] = "on-die",
4037 static int of_get_nand_ecc_mode(struct device_node
*np
)
4042 err
= of_property_read_string(np
, "nand-ecc-mode", &pm
);
4046 for (i
= 0; i
< ARRAY_SIZE(nand_ecc_modes
); i
++)
4047 if (!strcasecmp(pm
, nand_ecc_modes
[i
]))
4051 * For backward compatibility we support few obsoleted values that don't
4052 * have their mappings into nand_ecc_modes_t anymore (they were merged
4053 * with other enums).
4055 if (!strcasecmp(pm
, "soft_bch"))
4056 return NAND_ECC_SOFT
;
4061 static const char * const nand_ecc_algos
[] = {
4062 [NAND_ECC_HAMMING
] = "hamming",
4063 [NAND_ECC_BCH
] = "bch",
4066 static int of_get_nand_ecc_algo(struct device_node
*np
)
4071 err
= of_property_read_string(np
, "nand-ecc-algo", &pm
);
4073 for (i
= NAND_ECC_HAMMING
; i
< ARRAY_SIZE(nand_ecc_algos
); i
++)
4074 if (!strcasecmp(pm
, nand_ecc_algos
[i
]))
4080 * For backward compatibility we also read "nand-ecc-mode" checking
4081 * for some obsoleted values that were specifying ECC algorithm.
4083 err
= of_property_read_string(np
, "nand-ecc-mode", &pm
);
4087 if (!strcasecmp(pm
, "soft"))
4088 return NAND_ECC_HAMMING
;
4089 else if (!strcasecmp(pm
, "soft_bch"))
4090 return NAND_ECC_BCH
;
4095 static int of_get_nand_ecc_step_size(struct device_node
*np
)
4100 ret
= of_property_read_u32(np
, "nand-ecc-step-size", &val
);
4101 return ret
? ret
: val
;
4104 static int of_get_nand_ecc_strength(struct device_node
*np
)
4109 ret
= of_property_read_u32(np
, "nand-ecc-strength", &val
);
4110 return ret
? ret
: val
;
4113 static int of_get_nand_bus_width(struct device_node
*np
)
4117 if (of_property_read_u32(np
, "nand-bus-width", &val
))
4129 static bool of_get_nand_on_flash_bbt(struct device_node
*np
)
4131 return of_property_read_bool(np
, "nand-on-flash-bbt");
4134 static int nand_dt_init(struct nand_chip
*chip
)
4136 struct device_node
*dn
= nand_get_flash_node(chip
);
4137 int ecc_mode
, ecc_algo
, ecc_strength
, ecc_step
;
4142 if (of_get_nand_bus_width(dn
) == 16)
4143 chip
->options
|= NAND_BUSWIDTH_16
;
4145 if (of_get_nand_on_flash_bbt(dn
))
4146 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
4148 ecc_mode
= of_get_nand_ecc_mode(dn
);
4149 ecc_algo
= of_get_nand_ecc_algo(dn
);
4150 ecc_strength
= of_get_nand_ecc_strength(dn
);
4151 ecc_step
= of_get_nand_ecc_step_size(dn
);
4154 chip
->ecc
.mode
= ecc_mode
;
4157 chip
->ecc
.algo
= ecc_algo
;
4159 if (ecc_strength
>= 0)
4160 chip
->ecc
.strength
= ecc_strength
;
4163 chip
->ecc
.size
= ecc_step
;
4165 if (of_property_read_bool(dn
, "nand-ecc-maximize"))
4166 chip
->ecc
.options
|= NAND_ECC_MAXIMIZE
;
4172 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4173 * @mtd: MTD device structure
4174 * @maxchips: number of chips to scan for
4175 * @table: alternative NAND ID table
4177 * This is the first phase of the normal nand_scan() function. It reads the
4178 * flash ID and sets up MTD fields accordingly.
4181 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4182 struct nand_flash_dev
*table
)
4184 int i
, nand_maf_id
, nand_dev_id
;
4185 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4188 ret
= nand_dt_init(chip
);
4192 if (!mtd
->name
&& mtd
->dev
.parent
)
4193 mtd
->name
= dev_name(mtd
->dev
.parent
);
4195 if ((!chip
->cmdfunc
|| !chip
->select_chip
) && !chip
->cmd_ctrl
) {
4197 * Default functions assigned for chip_select() and
4198 * cmdfunc() both expect cmd_ctrl() to be populated,
4199 * so we need to check that that's the case
4201 pr_err("chip.cmd_ctrl() callback is not provided");
4204 /* Set the default functions */
4205 nand_set_defaults(chip
);
4207 /* Read the flash type */
4208 ret
= nand_detect(chip
, table
);
4210 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4211 pr_warn("No NAND device found\n");
4212 chip
->select_chip(mtd
, -1);
4216 nand_maf_id
= chip
->id
.data
[0];
4217 nand_dev_id
= chip
->id
.data
[1];
4219 chip
->select_chip(mtd
, -1);
4221 /* Check for a chip array */
4222 for (i
= 1; i
< maxchips
; i
++) {
4223 /* See comment in nand_get_flash_type for reset */
4224 nand_reset(chip
, i
);
4226 chip
->select_chip(mtd
, i
);
4227 /* Send the command for reading device ID */
4228 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4229 /* Read manufacturer and device IDs */
4230 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4231 nand_dev_id
!= chip
->read_byte(mtd
)) {
4232 chip
->select_chip(mtd
, -1);
4235 chip
->select_chip(mtd
, -1);
4238 pr_info("%d chips detected\n", i
);
4240 /* Store the number of chips and calc total size for mtd */
4242 mtd
->size
= i
* chip
->chipsize
;
4246 EXPORT_SYMBOL(nand_scan_ident
);
4248 static int nand_set_ecc_soft_ops(struct mtd_info
*mtd
)
4250 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4251 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4253 if (WARN_ON(ecc
->mode
!= NAND_ECC_SOFT
))
4256 switch (ecc
->algo
) {
4257 case NAND_ECC_HAMMING
:
4258 ecc
->calculate
= nand_calculate_ecc
;
4259 ecc
->correct
= nand_correct_data
;
4260 ecc
->read_page
= nand_read_page_swecc
;
4261 ecc
->read_subpage
= nand_read_subpage
;
4262 ecc
->write_page
= nand_write_page_swecc
;
4263 ecc
->read_page_raw
= nand_read_page_raw
;
4264 ecc
->write_page_raw
= nand_write_page_raw
;
4265 ecc
->read_oob
= nand_read_oob_std
;
4266 ecc
->write_oob
= nand_write_oob_std
;
4273 if (!mtd_nand_has_bch()) {
4274 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4277 ecc
->calculate
= nand_bch_calculate_ecc
;
4278 ecc
->correct
= nand_bch_correct_data
;
4279 ecc
->read_page
= nand_read_page_swecc
;
4280 ecc
->read_subpage
= nand_read_subpage
;
4281 ecc
->write_page
= nand_write_page_swecc
;
4282 ecc
->read_page_raw
= nand_read_page_raw
;
4283 ecc
->write_page_raw
= nand_write_page_raw
;
4284 ecc
->read_oob
= nand_read_oob_std
;
4285 ecc
->write_oob
= nand_write_oob_std
;
4288 * Board driver should supply ecc.size and ecc.strength
4289 * values to select how many bits are correctable.
4290 * Otherwise, default to 4 bits for large page devices.
4292 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4298 * if no ecc placement scheme was provided pickup the default
4301 if (!mtd
->ooblayout
) {
4302 /* handle large page devices only */
4303 if (mtd
->oobsize
< 64) {
4304 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4308 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
4313 * We can only maximize ECC config when the default layout is
4314 * used, otherwise we don't know how many bytes can really be
4317 if (mtd
->ooblayout
== &nand_ooblayout_lp_ops
&&
4318 ecc
->options
& NAND_ECC_MAXIMIZE
) {
4321 /* Always prefer 1k blocks over 512bytes ones */
4323 steps
= mtd
->writesize
/ ecc
->size
;
4325 /* Reserve 2 bytes for the BBM */
4326 bytes
= (mtd
->oobsize
- 2) / steps
;
4327 ecc
->strength
= bytes
* 8 / fls(8 * ecc
->size
);
4330 /* See nand_bch_init() for details. */
4332 ecc
->priv
= nand_bch_init(mtd
);
4334 WARN(1, "BCH ECC initialization failed!\n");
4339 WARN(1, "Unsupported ECC algorithm!\n");
4345 * nand_check_ecc_caps - check the sanity of preset ECC settings
4346 * @chip: nand chip info structure
4347 * @caps: ECC caps info structure
4348 * @oobavail: OOB size that the ECC engine can use
4350 * When ECC step size and strength are already set, check if they are supported
4351 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4352 * On success, the calculated ECC bytes is set.
4354 int nand_check_ecc_caps(struct nand_chip
*chip
,
4355 const struct nand_ecc_caps
*caps
, int oobavail
)
4357 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4358 const struct nand_ecc_step_info
*stepinfo
;
4359 int preset_step
= chip
->ecc
.size
;
4360 int preset_strength
= chip
->ecc
.strength
;
4361 int nsteps
, ecc_bytes
;
4364 if (WARN_ON(oobavail
< 0))
4367 if (!preset_step
|| !preset_strength
)
4370 nsteps
= mtd
->writesize
/ preset_step
;
4372 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4373 stepinfo
= &caps
->stepinfos
[i
];
4375 if (stepinfo
->stepsize
!= preset_step
)
4378 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4379 if (stepinfo
->strengths
[j
] != preset_strength
)
4382 ecc_bytes
= caps
->calc_ecc_bytes(preset_step
,
4384 if (WARN_ON_ONCE(ecc_bytes
< 0))
4387 if (ecc_bytes
* nsteps
> oobavail
) {
4388 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4389 preset_step
, preset_strength
);
4393 chip
->ecc
.bytes
= ecc_bytes
;
4399 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4400 preset_step
, preset_strength
);
4404 EXPORT_SYMBOL_GPL(nand_check_ecc_caps
);
4407 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4408 * @chip: nand chip info structure
4409 * @caps: ECC engine caps info structure
4410 * @oobavail: OOB size that the ECC engine can use
4412 * If a chip's ECC requirement is provided, try to meet it with the least
4413 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4414 * On success, the chosen ECC settings are set.
4416 int nand_match_ecc_req(struct nand_chip
*chip
,
4417 const struct nand_ecc_caps
*caps
, int oobavail
)
4419 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4420 const struct nand_ecc_step_info
*stepinfo
;
4421 int req_step
= chip
->ecc_step_ds
;
4422 int req_strength
= chip
->ecc_strength_ds
;
4423 int req_corr
, step_size
, strength
, nsteps
, ecc_bytes
, ecc_bytes_total
;
4424 int best_step
, best_strength
, best_ecc_bytes
;
4425 int best_ecc_bytes_total
= INT_MAX
;
4428 if (WARN_ON(oobavail
< 0))
4431 /* No information provided by the NAND chip */
4432 if (!req_step
|| !req_strength
)
4435 /* number of correctable bits the chip requires in a page */
4436 req_corr
= mtd
->writesize
/ req_step
* req_strength
;
4438 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4439 stepinfo
= &caps
->stepinfos
[i
];
4440 step_size
= stepinfo
->stepsize
;
4442 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4443 strength
= stepinfo
->strengths
[j
];
4446 * If both step size and strength are smaller than the
4447 * chip's requirement, it is not easy to compare the
4448 * resulted reliability.
4450 if (step_size
< req_step
&& strength
< req_strength
)
4453 if (mtd
->writesize
% step_size
)
4456 nsteps
= mtd
->writesize
/ step_size
;
4458 ecc_bytes
= caps
->calc_ecc_bytes(step_size
, strength
);
4459 if (WARN_ON_ONCE(ecc_bytes
< 0))
4461 ecc_bytes_total
= ecc_bytes
* nsteps
;
4463 if (ecc_bytes_total
> oobavail
||
4464 strength
* nsteps
< req_corr
)
4468 * We assume the best is to meet the chip's requrement
4469 * with the least number of ECC bytes.
4471 if (ecc_bytes_total
< best_ecc_bytes_total
) {
4472 best_ecc_bytes_total
= ecc_bytes_total
;
4473 best_step
= step_size
;
4474 best_strength
= strength
;
4475 best_ecc_bytes
= ecc_bytes
;
4480 if (best_ecc_bytes_total
== INT_MAX
)
4483 chip
->ecc
.size
= best_step
;
4484 chip
->ecc
.strength
= best_strength
;
4485 chip
->ecc
.bytes
= best_ecc_bytes
;
4489 EXPORT_SYMBOL_GPL(nand_match_ecc_req
);
4492 * nand_maximize_ecc - choose the max ECC strength available
4493 * @chip: nand chip info structure
4494 * @caps: ECC engine caps info structure
4495 * @oobavail: OOB size that the ECC engine can use
4497 * Choose the max ECC strength that is supported on the controller, and can fit
4498 * within the chip's OOB. On success, the chosen ECC settings are set.
4500 int nand_maximize_ecc(struct nand_chip
*chip
,
4501 const struct nand_ecc_caps
*caps
, int oobavail
)
4503 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4504 const struct nand_ecc_step_info
*stepinfo
;
4505 int step_size
, strength
, nsteps
, ecc_bytes
, corr
;
4508 int best_strength
, best_ecc_bytes
;
4511 if (WARN_ON(oobavail
< 0))
4514 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4515 stepinfo
= &caps
->stepinfos
[i
];
4516 step_size
= stepinfo
->stepsize
;
4518 /* If chip->ecc.size is already set, respect it */
4519 if (chip
->ecc
.size
&& step_size
!= chip
->ecc
.size
)
4522 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4523 strength
= stepinfo
->strengths
[j
];
4525 if (mtd
->writesize
% step_size
)
4528 nsteps
= mtd
->writesize
/ step_size
;
4530 ecc_bytes
= caps
->calc_ecc_bytes(step_size
, strength
);
4531 if (WARN_ON_ONCE(ecc_bytes
< 0))
4534 if (ecc_bytes
* nsteps
> oobavail
)
4537 corr
= strength
* nsteps
;
4540 * If the number of correctable bits is the same,
4541 * bigger step_size has more reliability.
4543 if (corr
> best_corr
||
4544 (corr
== best_corr
&& step_size
> best_step
)) {
4546 best_step
= step_size
;
4547 best_strength
= strength
;
4548 best_ecc_bytes
= ecc_bytes
;
4556 chip
->ecc
.size
= best_step
;
4557 chip
->ecc
.strength
= best_strength
;
4558 chip
->ecc
.bytes
= best_ecc_bytes
;
4562 EXPORT_SYMBOL_GPL(nand_maximize_ecc
);
4565 * Check if the chip configuration meet the datasheet requirements.
4567 * If our configuration corrects A bits per B bytes and the minimum
4568 * required correction level is X bits per Y bytes, then we must ensure
4569 * both of the following are true:
4571 * (1) A / B >= X / Y
4574 * Requirement (1) ensures we can correct for the required bitflip density.
4575 * Requirement (2) ensures we can correct even when all bitflips are clumped
4576 * in the same sector.
4578 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4580 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4581 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4584 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4585 /* Not enough information */
4589 * We get the number of corrected bits per page to compare
4590 * the correction density.
4592 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4593 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4595 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4598 static bool invalid_ecc_page_accessors(struct nand_chip
*chip
)
4600 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4602 if (nand_standard_page_accessors(ecc
))
4606 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4607 * controller driver implements all the page accessors because
4608 * default helpers are not suitable when the core does not
4609 * send the READ0/PAGEPROG commands.
4611 return (!ecc
->read_page
|| !ecc
->write_page
||
4612 !ecc
->read_page_raw
|| !ecc
->write_page_raw
||
4613 (NAND_HAS_SUBPAGE_READ(chip
) && !ecc
->read_subpage
) ||
4614 (NAND_HAS_SUBPAGE_WRITE(chip
) && !ecc
->write_subpage
&&
4615 ecc
->hwctl
&& ecc
->calculate
));
4619 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4620 * @mtd: MTD device structure
4622 * This is the second phase of the normal nand_scan() function. It fills out
4623 * all the uninitialized function pointers with the defaults and scans for a
4624 * bad block table if appropriate.
4626 int nand_scan_tail(struct mtd_info
*mtd
)
4628 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4629 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4630 struct nand_buffers
*nbuf
= NULL
;
4633 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4634 if (WARN_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4635 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
))) {
4639 if (invalid_ecc_page_accessors(chip
)) {
4640 pr_err("Invalid ECC page accessors setup\n");
4644 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4645 nbuf
= kzalloc(sizeof(*nbuf
), GFP_KERNEL
);
4649 nbuf
->ecccalc
= kmalloc(mtd
->oobsize
, GFP_KERNEL
);
4650 if (!nbuf
->ecccalc
) {
4655 nbuf
->ecccode
= kmalloc(mtd
->oobsize
, GFP_KERNEL
);
4656 if (!nbuf
->ecccode
) {
4661 nbuf
->databuf
= kmalloc(mtd
->writesize
+ mtd
->oobsize
,
4663 if (!nbuf
->databuf
) {
4668 chip
->buffers
= nbuf
;
4669 } else if (!chip
->buffers
) {
4674 * FIXME: some NAND manufacturer drivers expect the first die to be
4675 * selected when manufacturer->init() is called. They should be fixed
4676 * to explictly select the relevant die when interacting with the NAND
4679 chip
->select_chip(mtd
, 0);
4680 ret
= nand_manufacturer_init(chip
);
4681 chip
->select_chip(mtd
, -1);
4685 /* Set the internal oob buffer location, just after the page data */
4686 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4689 * If no default placement scheme is given, select an appropriate one.
4691 if (!mtd
->ooblayout
&&
4692 !(ecc
->mode
== NAND_ECC_SOFT
&& ecc
->algo
== NAND_ECC_BCH
)) {
4693 switch (mtd
->oobsize
) {
4696 mtd_set_ooblayout(mtd
, &nand_ooblayout_sp_ops
);
4700 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_hamming_ops
);
4703 WARN(1, "No oob scheme defined for oobsize %d\n",
4706 goto err_nand_manuf_cleanup
;
4711 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4712 * selected and we have 256 byte pagesize fallback to software ECC
4715 switch (ecc
->mode
) {
4716 case NAND_ECC_HW_OOB_FIRST
:
4717 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4718 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4719 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4721 goto err_nand_manuf_cleanup
;
4723 if (!ecc
->read_page
)
4724 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4727 /* Use standard hwecc read page function? */
4728 if (!ecc
->read_page
)
4729 ecc
->read_page
= nand_read_page_hwecc
;
4730 if (!ecc
->write_page
)
4731 ecc
->write_page
= nand_write_page_hwecc
;
4732 if (!ecc
->read_page_raw
)
4733 ecc
->read_page_raw
= nand_read_page_raw
;
4734 if (!ecc
->write_page_raw
)
4735 ecc
->write_page_raw
= nand_write_page_raw
;
4737 ecc
->read_oob
= nand_read_oob_std
;
4738 if (!ecc
->write_oob
)
4739 ecc
->write_oob
= nand_write_oob_std
;
4740 if (!ecc
->read_subpage
)
4741 ecc
->read_subpage
= nand_read_subpage
;
4742 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4743 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4745 case NAND_ECC_HW_SYNDROME
:
4746 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4748 ecc
->read_page
== nand_read_page_hwecc
||
4750 ecc
->write_page
== nand_write_page_hwecc
)) {
4751 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4753 goto err_nand_manuf_cleanup
;
4755 /* Use standard syndrome read/write page function? */
4756 if (!ecc
->read_page
)
4757 ecc
->read_page
= nand_read_page_syndrome
;
4758 if (!ecc
->write_page
)
4759 ecc
->write_page
= nand_write_page_syndrome
;
4760 if (!ecc
->read_page_raw
)
4761 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4762 if (!ecc
->write_page_raw
)
4763 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4765 ecc
->read_oob
= nand_read_oob_syndrome
;
4766 if (!ecc
->write_oob
)
4767 ecc
->write_oob
= nand_write_oob_syndrome
;
4769 if (mtd
->writesize
>= ecc
->size
) {
4770 if (!ecc
->strength
) {
4771 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4773 goto err_nand_manuf_cleanup
;
4777 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4778 ecc
->size
, mtd
->writesize
);
4779 ecc
->mode
= NAND_ECC_SOFT
;
4780 ecc
->algo
= NAND_ECC_HAMMING
;
4783 ret
= nand_set_ecc_soft_ops(mtd
);
4786 goto err_nand_manuf_cleanup
;
4790 case NAND_ECC_ON_DIE
:
4791 if (!ecc
->read_page
|| !ecc
->write_page
) {
4792 WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
4794 goto err_nand_manuf_cleanup
;
4797 ecc
->read_oob
= nand_read_oob_std
;
4798 if (!ecc
->write_oob
)
4799 ecc
->write_oob
= nand_write_oob_std
;
4803 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4804 ecc
->read_page
= nand_read_page_raw
;
4805 ecc
->write_page
= nand_write_page_raw
;
4806 ecc
->read_oob
= nand_read_oob_std
;
4807 ecc
->read_page_raw
= nand_read_page_raw
;
4808 ecc
->write_page_raw
= nand_write_page_raw
;
4809 ecc
->write_oob
= nand_write_oob_std
;
4810 ecc
->size
= mtd
->writesize
;
4816 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4818 goto err_nand_manuf_cleanup
;
4821 /* For many systems, the standard OOB write also works for raw */
4822 if (!ecc
->read_oob_raw
)
4823 ecc
->read_oob_raw
= ecc
->read_oob
;
4824 if (!ecc
->write_oob_raw
)
4825 ecc
->write_oob_raw
= ecc
->write_oob
;
4827 /* propagate ecc info to mtd_info */
4828 mtd
->ecc_strength
= ecc
->strength
;
4829 mtd
->ecc_step_size
= ecc
->size
;
4832 * Set the number of read / write steps for one page depending on ECC
4835 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4836 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4837 WARN(1, "Invalid ECC parameters\n");
4839 goto err_nand_manuf_cleanup
;
4841 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4842 if (ecc
->total
> mtd
->oobsize
) {
4843 WARN(1, "Total number of ECC bytes exceeded oobsize\n");
4845 goto err_nand_manuf_cleanup
;
4849 * The number of bytes available for a client to place data into
4850 * the out of band area.
4852 ret
= mtd_ooblayout_count_freebytes(mtd
);
4856 mtd
->oobavail
= ret
;
4858 /* ECC sanity check: warn if it's too weak */
4859 if (!nand_ecc_strength_good(mtd
))
4860 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4863 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4864 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4865 switch (ecc
->steps
) {
4867 mtd
->subpage_sft
= 1;
4872 mtd
->subpage_sft
= 2;
4876 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4878 /* Initialize state */
4879 chip
->state
= FL_READY
;
4881 /* Invalidate the pagebuffer reference */
4884 /* Large page NAND with SOFT_ECC should support subpage reads */
4885 switch (ecc
->mode
) {
4887 if (chip
->page_shift
> 9)
4888 chip
->options
|= NAND_SUBPAGE_READ
;
4895 /* Fill in remaining MTD driver data */
4896 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4897 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4899 mtd
->_erase
= nand_erase
;
4901 mtd
->_unpoint
= NULL
;
4902 mtd
->_read
= nand_read
;
4903 mtd
->_write
= nand_write
;
4904 mtd
->_panic_write
= panic_nand_write
;
4905 mtd
->_read_oob
= nand_read_oob
;
4906 mtd
->_write_oob
= nand_write_oob
;
4907 mtd
->_sync
= nand_sync
;
4909 mtd
->_unlock
= NULL
;
4910 mtd
->_suspend
= nand_suspend
;
4911 mtd
->_resume
= nand_resume
;
4912 mtd
->_reboot
= nand_shutdown
;
4913 mtd
->_block_isreserved
= nand_block_isreserved
;
4914 mtd
->_block_isbad
= nand_block_isbad
;
4915 mtd
->_block_markbad
= nand_block_markbad
;
4916 mtd
->_max_bad_blocks
= nand_max_bad_blocks
;
4917 mtd
->writebufsize
= mtd
->writesize
;
4920 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4921 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4924 if (!mtd
->bitflip_threshold
)
4925 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4927 /* Initialize the ->data_interface field. */
4928 ret
= nand_init_data_interface(chip
);
4930 goto err_nand_manuf_cleanup
;
4932 /* Enter fastest possible mode on all dies. */
4933 for (i
= 0; i
< chip
->numchips
; i
++) {
4934 chip
->select_chip(mtd
, i
);
4935 ret
= nand_setup_data_interface(chip
, i
);
4936 chip
->select_chip(mtd
, -1);
4939 goto err_nand_data_iface_cleanup
;
4942 /* Check, if we should skip the bad block table scan */
4943 if (chip
->options
& NAND_SKIP_BBTSCAN
)
4946 /* Build bad block table */
4947 ret
= chip
->scan_bbt(mtd
);
4949 goto err_nand_data_iface_cleanup
;
4953 err_nand_data_iface_cleanup
:
4954 nand_release_data_interface(chip
);
4956 err_nand_manuf_cleanup
:
4957 nand_manufacturer_cleanup(chip
);
4961 kfree(nbuf
->databuf
);
4962 kfree(nbuf
->ecccode
);
4963 kfree(nbuf
->ecccalc
);
4969 EXPORT_SYMBOL(nand_scan_tail
);
4972 * is_module_text_address() isn't exported, and it's mostly a pointless
4973 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4974 * to call us from in-kernel code if the core NAND support is modular.
4977 #define caller_is_module() (1)
4979 #define caller_is_module() \
4980 is_module_text_address((unsigned long)__builtin_return_address(0))
4984 * nand_scan - [NAND Interface] Scan for the NAND device
4985 * @mtd: MTD device structure
4986 * @maxchips: number of chips to scan for
4988 * This fills out all the uninitialized function pointers with the defaults.
4989 * The flash ID is read and the mtd/chip structures are filled with the
4990 * appropriate values.
4992 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4996 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4998 ret
= nand_scan_tail(mtd
);
5001 EXPORT_SYMBOL(nand_scan
);
5004 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
5005 * @chip: NAND chip object
5007 void nand_cleanup(struct nand_chip
*chip
)
5009 if (chip
->ecc
.mode
== NAND_ECC_SOFT
&&
5010 chip
->ecc
.algo
== NAND_ECC_BCH
)
5011 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
5013 nand_release_data_interface(chip
);
5015 /* Free bad block table memory */
5017 if (!(chip
->options
& NAND_OWN_BUFFERS
) && chip
->buffers
) {
5018 kfree(chip
->buffers
->databuf
);
5019 kfree(chip
->buffers
->ecccode
);
5020 kfree(chip
->buffers
->ecccalc
);
5021 kfree(chip
->buffers
);
5024 /* Free bad block descriptor memory */
5025 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
5026 & NAND_BBT_DYNAMICSTRUCT
)
5027 kfree(chip
->badblock_pattern
);
5029 /* Free manufacturer priv data. */
5030 nand_manufacturer_cleanup(chip
);
5032 EXPORT_SYMBOL_GPL(nand_cleanup
);
5035 * nand_release - [NAND Interface] Unregister the MTD device and free resources
5036 * held by the NAND device
5037 * @mtd: MTD device structure
5039 void nand_release(struct mtd_info
*mtd
)
5041 mtd_device_unregister(mtd
);
5042 nand_cleanup(mtd_to_nand(mtd
));
5044 EXPORT_SYMBOL_GPL(nand_release
);
5046 MODULE_LICENSE("GPL");
5047 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
5048 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
5049 MODULE_DESCRIPTION("Generic NAND flash driver code");