5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
47 #include <linux/leds.h>
50 #ifdef CONFIG_MTD_PARTITIONS
51 #include <linux/mtd/partitions.h>
54 /* Define default oob placement schemes for large and small page devices */
55 static struct nand_ecclayout nand_oob_8
= {
65 static struct nand_ecclayout nand_oob_16
= {
67 .eccpos
= {0, 1, 2, 3, 6, 7},
73 static struct nand_ecclayout nand_oob_64
= {
76 40, 41, 42, 43, 44, 45, 46, 47,
77 48, 49, 50, 51, 52, 53, 54, 55,
78 56, 57, 58, 59, 60, 61, 62, 63},
84 static struct nand_ecclayout nand_oob_128
= {
87 80, 81, 82, 83, 84, 85, 86, 87,
88 88, 89, 90, 91, 92, 93, 94, 95,
89 96, 97, 98, 99, 100, 101, 102, 103,
90 104, 105, 106, 107, 108, 109, 110, 111,
91 112, 113, 114, 115, 116, 117, 118, 119,
92 120, 121, 122, 123, 124, 125, 126, 127},
98 static int nand_get_device(struct nand_chip
*chip
, struct mtd_info
*mtd
,
101 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
102 struct mtd_oob_ops
*ops
);
105 * For devices which display every fart in the system on a separate LED. Is
106 * compiled away when LED support is disabled.
108 DEFINE_LED_TRIGGER(nand_led_trigger
);
110 static int check_offs_len(struct mtd_info
*mtd
,
111 loff_t ofs
, uint64_t len
)
113 struct nand_chip
*chip
= mtd
->priv
;
116 /* Start address must align on block boundary */
117 if (ofs
& ((1 << chip
->phys_erase_shift
) - 1)) {
118 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Unaligned address\n", __func__
);
122 /* Length must align on block boundary */
123 if (len
& ((1 << chip
->phys_erase_shift
) - 1)) {
124 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Length not block aligned\n",
129 /* Do not allow past end of device */
130 if (ofs
+ len
> mtd
->size
) {
131 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Past end of device\n",
140 * nand_release_device - [GENERIC] release chip
141 * @mtd: MTD device structure
143 * Deselect, release chip lock and wake up anyone waiting on the device
145 static void nand_release_device(struct mtd_info
*mtd
)
147 struct nand_chip
*chip
= mtd
->priv
;
149 /* De-select the NAND device */
150 chip
->select_chip(mtd
, -1);
152 /* Release the controller and the chip */
153 spin_lock(&chip
->controller
->lock
);
154 chip
->controller
->active
= NULL
;
155 chip
->state
= FL_READY
;
156 wake_up(&chip
->controller
->wq
);
157 spin_unlock(&chip
->controller
->lock
);
161 * nand_read_byte - [DEFAULT] read one byte from the chip
162 * @mtd: MTD device structure
164 * Default read function for 8bit buswith
166 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
168 struct nand_chip
*chip
= mtd
->priv
;
169 return readb(chip
->IO_ADDR_R
);
173 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
174 * @mtd: MTD device structure
176 * Default read function for 16bit buswith with
177 * endianess conversion
179 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
181 struct nand_chip
*chip
= mtd
->priv
;
182 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
186 * nand_read_word - [DEFAULT] read one word from the chip
187 * @mtd: MTD device structure
189 * Default read function for 16bit buswith without
190 * endianess conversion
192 static u16
nand_read_word(struct mtd_info
*mtd
)
194 struct nand_chip
*chip
= mtd
->priv
;
195 return readw(chip
->IO_ADDR_R
);
199 * nand_select_chip - [DEFAULT] control CE line
200 * @mtd: MTD device structure
201 * @chipnr: chipnumber to select, -1 for deselect
203 * Default select function for 1 chip devices.
205 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
207 struct nand_chip
*chip
= mtd
->priv
;
211 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
222 * nand_write_buf - [DEFAULT] write buffer to chip
223 * @mtd: MTD device structure
225 * @len: number of bytes to write
227 * Default write function for 8bit buswith
229 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
232 struct nand_chip
*chip
= mtd
->priv
;
234 for (i
= 0; i
< len
; i
++)
235 writeb(buf
[i
], chip
->IO_ADDR_W
);
239 * nand_read_buf - [DEFAULT] read chip data into buffer
240 * @mtd: MTD device structure
241 * @buf: buffer to store date
242 * @len: number of bytes to read
244 * Default read function for 8bit buswith
246 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
249 struct nand_chip
*chip
= mtd
->priv
;
251 for (i
= 0; i
< len
; i
++)
252 buf
[i
] = readb(chip
->IO_ADDR_R
);
256 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
257 * @mtd: MTD device structure
258 * @buf: buffer containing the data to compare
259 * @len: number of bytes to compare
261 * Default verify function for 8bit buswith
263 static int nand_verify_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
266 struct nand_chip
*chip
= mtd
->priv
;
268 for (i
= 0; i
< len
; i
++)
269 if (buf
[i
] != readb(chip
->IO_ADDR_R
))
275 * nand_write_buf16 - [DEFAULT] write buffer to chip
276 * @mtd: MTD device structure
278 * @len: number of bytes to write
280 * Default write function for 16bit buswith
282 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
285 struct nand_chip
*chip
= mtd
->priv
;
286 u16
*p
= (u16
*) buf
;
289 for (i
= 0; i
< len
; i
++)
290 writew(p
[i
], chip
->IO_ADDR_W
);
295 * nand_read_buf16 - [DEFAULT] read chip data into buffer
296 * @mtd: MTD device structure
297 * @buf: buffer to store date
298 * @len: number of bytes to read
300 * Default read function for 16bit buswith
302 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
305 struct nand_chip
*chip
= mtd
->priv
;
306 u16
*p
= (u16
*) buf
;
309 for (i
= 0; i
< len
; i
++)
310 p
[i
] = readw(chip
->IO_ADDR_R
);
314 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
315 * @mtd: MTD device structure
316 * @buf: buffer containing the data to compare
317 * @len: number of bytes to compare
319 * Default verify function for 16bit buswith
321 static int nand_verify_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
324 struct nand_chip
*chip
= mtd
->priv
;
325 u16
*p
= (u16
*) buf
;
328 for (i
= 0; i
< len
; i
++)
329 if (p
[i
] != readw(chip
->IO_ADDR_R
))
336 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
337 * @mtd: MTD device structure
338 * @ofs: offset from device start
339 * @getchip: 0, if the chip is already selected
341 * Check, if the block is bad.
343 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
345 int page
, chipnr
, res
= 0;
346 struct nand_chip
*chip
= mtd
->priv
;
349 if (chip
->options
& NAND_BBT_SCANLASTPAGE
)
350 ofs
+= mtd
->erasesize
- mtd
->writesize
;
352 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
355 chipnr
= (int)(ofs
>> chip
->chip_shift
);
357 nand_get_device(chip
, mtd
, FL_READING
);
359 /* Select the NAND device */
360 chip
->select_chip(mtd
, chipnr
);
363 if (chip
->options
& NAND_BUSWIDTH_16
) {
364 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
& 0xFE,
366 bad
= cpu_to_le16(chip
->read_word(mtd
));
367 if (chip
->badblockpos
& 0x1)
372 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
, page
);
373 bad
= chip
->read_byte(mtd
);
376 if (likely(chip
->badblockbits
== 8))
379 res
= hweight8(bad
) < chip
->badblockbits
;
382 nand_release_device(mtd
);
388 * nand_default_block_markbad - [DEFAULT] mark a block bad
389 * @mtd: MTD device structure
390 * @ofs: offset from device start
392 * This is the default implementation, which can be overridden by
393 * a hardware specific driver.
395 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
397 struct nand_chip
*chip
= mtd
->priv
;
398 uint8_t buf
[2] = { 0, 0 };
399 int block
, ret
, i
= 0;
401 if (chip
->options
& NAND_BBT_SCANLASTPAGE
)
402 ofs
+= mtd
->erasesize
- mtd
->writesize
;
404 /* Get block number */
405 block
= (int)(ofs
>> chip
->bbt_erase_shift
);
407 chip
->bbt
[block
>> 2] |= 0x01 << ((block
& 0x03) << 1);
409 /* Do we have a flash based bad block table ? */
410 if (chip
->options
& NAND_USE_FLASH_BBT
)
411 ret
= nand_update_bbt(mtd
, ofs
);
413 nand_get_device(chip
, mtd
, FL_WRITING
);
415 /* Write to first two pages and to byte 1 and 6 if necessary.
416 * If we write to more than one location, the first error
417 * encountered quits the procedure. We write two bytes per
418 * location, so we dont have to mess with 16 bit access.
421 chip
->ops
.len
= chip
->ops
.ooblen
= 2;
422 chip
->ops
.datbuf
= NULL
;
423 chip
->ops
.oobbuf
= buf
;
424 chip
->ops
.ooboffs
= chip
->badblockpos
& ~0x01;
426 ret
= nand_do_write_oob(mtd
, ofs
, &chip
->ops
);
428 if (!ret
&& (chip
->options
& NAND_BBT_SCANBYTE1AND6
)) {
429 chip
->ops
.ooboffs
= NAND_SMALL_BADBLOCK_POS
431 ret
= nand_do_write_oob(mtd
, ofs
, &chip
->ops
);
434 ofs
+= mtd
->writesize
;
435 } while (!ret
&& (chip
->options
& NAND_BBT_SCAN2NDPAGE
) &&
438 nand_release_device(mtd
);
441 mtd
->ecc_stats
.badblocks
++;
447 * nand_check_wp - [GENERIC] check if the chip is write protected
448 * @mtd: MTD device structure
449 * Check, if the device is write protected
451 * The function expects, that the device is already selected
453 static int nand_check_wp(struct mtd_info
*mtd
)
455 struct nand_chip
*chip
= mtd
->priv
;
457 /* broken xD cards report WP despite being writable */
458 if (chip
->options
& NAND_BROKEN_XD
)
461 /* Check the WP bit */
462 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
463 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
467 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
468 * @mtd: MTD device structure
469 * @ofs: offset from device start
470 * @getchip: 0, if the chip is already selected
471 * @allowbbt: 1, if its allowed to access the bbt area
473 * Check, if the block is bad. Either by reading the bad block table or
474 * calling of the scan function.
476 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
,
479 struct nand_chip
*chip
= mtd
->priv
;
482 return chip
->block_bad(mtd
, ofs
, getchip
);
484 /* Return info from the table */
485 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
489 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
490 * @mtd: MTD device structure
493 * Helper function for nand_wait_ready used when needing to wait in interrupt
496 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
498 struct nand_chip
*chip
= mtd
->priv
;
501 /* Wait for the device to get ready */
502 for (i
= 0; i
< timeo
; i
++) {
503 if (chip
->dev_ready(mtd
))
505 touch_softlockup_watchdog();
511 * Wait for the ready pin, after a command
512 * The timeout is catched later.
514 void nand_wait_ready(struct mtd_info
*mtd
)
516 struct nand_chip
*chip
= mtd
->priv
;
517 unsigned long timeo
= jiffies
+ 2;
520 if (in_interrupt() || oops_in_progress
)
521 return panic_nand_wait_ready(mtd
, 400);
523 led_trigger_event(nand_led_trigger
, LED_FULL
);
524 /* wait until command is processed or timeout occures */
526 if (chip
->dev_ready(mtd
))
528 touch_softlockup_watchdog();
529 } while (time_before(jiffies
, timeo
));
530 led_trigger_event(nand_led_trigger
, LED_OFF
);
532 EXPORT_SYMBOL_GPL(nand_wait_ready
);
535 * nand_command - [DEFAULT] Send command to NAND device
536 * @mtd: MTD device structure
537 * @command: the command to be sent
538 * @column: the column address for this command, -1 if none
539 * @page_addr: the page address for this command, -1 if none
541 * Send command to NAND device. This function is used for small page
542 * devices (256/512 Bytes per page)
544 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
545 int column
, int page_addr
)
547 register struct nand_chip
*chip
= mtd
->priv
;
548 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
551 * Write out the command to the device.
553 if (command
== NAND_CMD_SEQIN
) {
556 if (column
>= mtd
->writesize
) {
558 column
-= mtd
->writesize
;
559 readcmd
= NAND_CMD_READOOB
;
560 } else if (column
< 256) {
561 /* First 256 bytes --> READ0 */
562 readcmd
= NAND_CMD_READ0
;
565 readcmd
= NAND_CMD_READ1
;
567 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
568 ctrl
&= ~NAND_CTRL_CHANGE
;
570 chip
->cmd_ctrl(mtd
, command
, ctrl
);
573 * Address cycle, when necessary
575 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
576 /* Serially input address */
578 /* Adjust columns for 16 bit buswidth */
579 if (chip
->options
& NAND_BUSWIDTH_16
)
581 chip
->cmd_ctrl(mtd
, column
, ctrl
);
582 ctrl
&= ~NAND_CTRL_CHANGE
;
584 if (page_addr
!= -1) {
585 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
586 ctrl
&= ~NAND_CTRL_CHANGE
;
587 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
588 /* One more address cycle for devices > 32MiB */
589 if (chip
->chipsize
> (32 << 20))
590 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
592 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
595 * program and erase have their own busy handlers
596 * status and sequential in needs no delay
600 case NAND_CMD_PAGEPROG
:
601 case NAND_CMD_ERASE1
:
602 case NAND_CMD_ERASE2
:
604 case NAND_CMD_STATUS
:
610 udelay(chip
->chip_delay
);
611 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
612 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
614 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
615 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
619 /* This applies to read commands */
622 * If we don't have access to the busy pin, we apply the given
625 if (!chip
->dev_ready
) {
626 udelay(chip
->chip_delay
);
630 /* Apply this short delay always to ensure that we do wait tWB in
631 * any case on any machine. */
634 nand_wait_ready(mtd
);
638 * nand_command_lp - [DEFAULT] Send command to NAND large page device
639 * @mtd: MTD device structure
640 * @command: the command to be sent
641 * @column: the column address for this command, -1 if none
642 * @page_addr: the page address for this command, -1 if none
644 * Send command to NAND device. This is the version for the new large page
645 * devices We dont have the separate regions as we have in the small page
646 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
648 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
649 int column
, int page_addr
)
651 register struct nand_chip
*chip
= mtd
->priv
;
653 /* Emulate NAND_CMD_READOOB */
654 if (command
== NAND_CMD_READOOB
) {
655 column
+= mtd
->writesize
;
656 command
= NAND_CMD_READ0
;
659 /* Command latch cycle */
660 chip
->cmd_ctrl(mtd
, command
& 0xff,
661 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
663 if (column
!= -1 || page_addr
!= -1) {
664 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
666 /* Serially input address */
668 /* Adjust columns for 16 bit buswidth */
669 if (chip
->options
& NAND_BUSWIDTH_16
)
671 chip
->cmd_ctrl(mtd
, column
, ctrl
);
672 ctrl
&= ~NAND_CTRL_CHANGE
;
673 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
675 if (page_addr
!= -1) {
676 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
677 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
678 NAND_NCE
| NAND_ALE
);
679 /* One more address cycle for devices > 128MiB */
680 if (chip
->chipsize
> (128 << 20))
681 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
682 NAND_NCE
| NAND_ALE
);
685 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
688 * program and erase have their own busy handlers
689 * status, sequential in, and deplete1 need no delay
693 case NAND_CMD_CACHEDPROG
:
694 case NAND_CMD_PAGEPROG
:
695 case NAND_CMD_ERASE1
:
696 case NAND_CMD_ERASE2
:
699 case NAND_CMD_STATUS
:
700 case NAND_CMD_DEPLETE1
:
704 * read error status commands require only a short delay
706 case NAND_CMD_STATUS_ERROR
:
707 case NAND_CMD_STATUS_ERROR0
:
708 case NAND_CMD_STATUS_ERROR1
:
709 case NAND_CMD_STATUS_ERROR2
:
710 case NAND_CMD_STATUS_ERROR3
:
711 udelay(chip
->chip_delay
);
717 udelay(chip
->chip_delay
);
718 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
719 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
720 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
721 NAND_NCE
| NAND_CTRL_CHANGE
);
722 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
726 case NAND_CMD_RNDOUT
:
727 /* No ready / busy check necessary */
728 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
729 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
730 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
731 NAND_NCE
| NAND_CTRL_CHANGE
);
735 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
736 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
737 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
738 NAND_NCE
| NAND_CTRL_CHANGE
);
740 /* This applies to read commands */
743 * If we don't have access to the busy pin, we apply the given
746 if (!chip
->dev_ready
) {
747 udelay(chip
->chip_delay
);
752 /* Apply this short delay always to ensure that we do wait tWB in
753 * any case on any machine. */
756 nand_wait_ready(mtd
);
760 * panic_nand_get_device - [GENERIC] Get chip for selected access
761 * @chip: the nand chip descriptor
762 * @mtd: MTD device structure
763 * @new_state: the state which is requested
765 * Used when in panic, no locks are taken.
767 static void panic_nand_get_device(struct nand_chip
*chip
,
768 struct mtd_info
*mtd
, int new_state
)
770 /* Hardware controller shared among independend devices */
771 chip
->controller
->active
= chip
;
772 chip
->state
= new_state
;
776 * nand_get_device - [GENERIC] Get chip for selected access
777 * @chip: the nand chip descriptor
778 * @mtd: MTD device structure
779 * @new_state: the state which is requested
781 * Get the device and lock it for exclusive access
784 nand_get_device(struct nand_chip
*chip
, struct mtd_info
*mtd
, int new_state
)
786 spinlock_t
*lock
= &chip
->controller
->lock
;
787 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
788 DECLARE_WAITQUEUE(wait
, current
);
792 /* Hardware controller shared among independent devices */
793 if (!chip
->controller
->active
)
794 chip
->controller
->active
= chip
;
796 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
797 chip
->state
= new_state
;
801 if (new_state
== FL_PM_SUSPENDED
) {
802 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
803 chip
->state
= FL_PM_SUSPENDED
;
808 set_current_state(TASK_UNINTERRUPTIBLE
);
809 add_wait_queue(wq
, &wait
);
812 remove_wait_queue(wq
, &wait
);
817 * panic_nand_wait - [GENERIC] wait until the command is done
818 * @mtd: MTD device structure
819 * @chip: NAND chip structure
822 * Wait for command done. This is a helper function for nand_wait used when
823 * we are in interrupt context. May happen when in panic and trying to write
824 * an oops through mtdoops.
826 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
830 for (i
= 0; i
< timeo
; i
++) {
831 if (chip
->dev_ready
) {
832 if (chip
->dev_ready(mtd
))
835 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
843 * nand_wait - [DEFAULT] wait until the command is done
844 * @mtd: MTD device structure
845 * @chip: NAND chip structure
847 * Wait for command done. This applies to erase and program only
848 * Erase can take up to 400ms and program up to 20ms according to
849 * general NAND and SmartMedia specs
851 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
854 unsigned long timeo
= jiffies
;
855 int status
, state
= chip
->state
;
857 if (state
== FL_ERASING
)
858 timeo
+= (HZ
* 400) / 1000;
860 timeo
+= (HZ
* 20) / 1000;
862 led_trigger_event(nand_led_trigger
, LED_FULL
);
864 /* Apply this short delay always to ensure that we do wait tWB in
865 * any case on any machine. */
868 if ((state
== FL_ERASING
) && (chip
->options
& NAND_IS_AND
))
869 chip
->cmdfunc(mtd
, NAND_CMD_STATUS_MULTI
, -1, -1);
871 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
873 if (in_interrupt() || oops_in_progress
)
874 panic_nand_wait(mtd
, chip
, timeo
);
876 while (time_before(jiffies
, timeo
)) {
877 if (chip
->dev_ready
) {
878 if (chip
->dev_ready(mtd
))
881 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
887 led_trigger_event(nand_led_trigger
, LED_OFF
);
889 status
= (int)chip
->read_byte(mtd
);
894 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
897 * @ofs: offset to start unlock from
898 * @len: length to unlock
899 * @invert: when = 0, unlock the range of blocks within the lower and
900 * upper boundary address
901 * when = 1, unlock the range of blocks outside the boundaries
902 * of the lower and upper boundary address
904 * return - unlock status
906 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
907 uint64_t len
, int invert
)
911 struct nand_chip
*chip
= mtd
->priv
;
913 /* Submit address of first page to unlock */
914 page
= ofs
>> chip
->page_shift
;
915 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
917 /* Submit address of last page to unlock */
918 page
= (ofs
+ len
) >> chip
->page_shift
;
919 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
920 (page
| invert
) & chip
->pagemask
);
922 /* Call wait ready function */
923 status
= chip
->waitfunc(mtd
, chip
);
925 /* See if device thinks it succeeded */
927 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Error status = 0x%08x\n",
936 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
942 * return - unlock status
944 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
948 struct nand_chip
*chip
= mtd
->priv
;
950 DEBUG(MTD_DEBUG_LEVEL3
, "%s: start = 0x%012llx, len = %llu\n",
951 __func__
, (unsigned long long)ofs
, len
);
953 if (check_offs_len(mtd
, ofs
, len
))
956 /* Align to last block address if size addresses end of the device */
957 if (ofs
+ len
== mtd
->size
)
958 len
-= mtd
->erasesize
;
960 nand_get_device(chip
, mtd
, FL_UNLOCKING
);
962 /* Shift to get chip number */
963 chipnr
= ofs
>> chip
->chip_shift
;
965 chip
->select_chip(mtd
, chipnr
);
967 /* Check, if it is write protected */
968 if (nand_check_wp(mtd
)) {
969 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Device is write protected!!!\n",
975 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
978 /* de-select the NAND device */
979 chip
->select_chip(mtd
, -1);
981 nand_release_device(mtd
);
985 EXPORT_SYMBOL(nand_unlock
);
988 * nand_lock - [REPLACEABLE] locks all blocks present in the device
991 * @ofs: offset to start unlock from
992 * @len: length to unlock
994 * return - lock status
996 * This feature is not supported in many NAND parts. 'Micron' NAND parts
997 * do have this feature, but it allows only to lock all blocks, not for
998 * specified range for block.
1000 * Implementing 'lock' feature by making use of 'unlock', for now.
1002 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1005 int chipnr
, status
, page
;
1006 struct nand_chip
*chip
= mtd
->priv
;
1008 DEBUG(MTD_DEBUG_LEVEL3
, "%s: start = 0x%012llx, len = %llu\n",
1009 __func__
, (unsigned long long)ofs
, len
);
1011 if (check_offs_len(mtd
, ofs
, len
))
1014 nand_get_device(chip
, mtd
, FL_LOCKING
);
1016 /* Shift to get chip number */
1017 chipnr
= ofs
>> chip
->chip_shift
;
1019 chip
->select_chip(mtd
, chipnr
);
1021 /* Check, if it is write protected */
1022 if (nand_check_wp(mtd
)) {
1023 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Device is write protected!!!\n",
1025 status
= MTD_ERASE_FAILED
;
1030 /* Submit address of first page to lock */
1031 page
= ofs
>> chip
->page_shift
;
1032 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1034 /* Call wait ready function */
1035 status
= chip
->waitfunc(mtd
, chip
);
1037 /* See if device thinks it succeeded */
1038 if (status
& 0x01) {
1039 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Error status = 0x%08x\n",
1045 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1048 /* de-select the NAND device */
1049 chip
->select_chip(mtd
, -1);
1051 nand_release_device(mtd
);
1055 EXPORT_SYMBOL(nand_lock
);
1058 * nand_read_page_raw - [Intern] read raw page data without ecc
1059 * @mtd: mtd info structure
1060 * @chip: nand chip info structure
1061 * @buf: buffer to store read data
1062 * @page: page number to read
1064 * Not for syndrome calculating ecc controllers, which use a special oob layout
1066 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1067 uint8_t *buf
, int page
)
1069 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1070 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1075 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1076 * @mtd: mtd info structure
1077 * @chip: nand chip info structure
1078 * @buf: buffer to store read data
1079 * @page: page number to read
1081 * We need a special oob layout and handling even when OOB isn't used.
1083 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1084 struct nand_chip
*chip
,
1085 uint8_t *buf
, int page
)
1087 int eccsize
= chip
->ecc
.size
;
1088 int eccbytes
= chip
->ecc
.bytes
;
1089 uint8_t *oob
= chip
->oob_poi
;
1092 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1093 chip
->read_buf(mtd
, buf
, eccsize
);
1096 if (chip
->ecc
.prepad
) {
1097 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1098 oob
+= chip
->ecc
.prepad
;
1101 chip
->read_buf(mtd
, oob
, eccbytes
);
1104 if (chip
->ecc
.postpad
) {
1105 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1106 oob
+= chip
->ecc
.postpad
;
1110 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1112 chip
->read_buf(mtd
, oob
, size
);
1118 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1119 * @mtd: mtd info structure
1120 * @chip: nand chip info structure
1121 * @buf: buffer to store read data
1122 * @page: page number to read
1124 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1125 uint8_t *buf
, int page
)
1127 int i
, eccsize
= chip
->ecc
.size
;
1128 int eccbytes
= chip
->ecc
.bytes
;
1129 int eccsteps
= chip
->ecc
.steps
;
1131 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1132 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1133 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1135 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, page
);
1137 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1138 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1140 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1141 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1143 eccsteps
= chip
->ecc
.steps
;
1146 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1149 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1151 mtd
->ecc_stats
.failed
++;
1153 mtd
->ecc_stats
.corrected
+= stat
;
1159 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1160 * @mtd: mtd info structure
1161 * @chip: nand chip info structure
1162 * @data_offs: offset of requested data within the page
1163 * @readlen: data length
1164 * @bufpoi: buffer to store read data
1166 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1167 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
)
1169 int start_step
, end_step
, num_steps
;
1170 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1172 int data_col_addr
, i
, gaps
= 0;
1173 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1174 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1177 /* Column address wihin the page aligned to ECC size (256bytes). */
1178 start_step
= data_offs
/ chip
->ecc
.size
;
1179 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1180 num_steps
= end_step
- start_step
+ 1;
1182 /* Data size aligned to ECC ecc.size*/
1183 datafrag_len
= num_steps
* chip
->ecc
.size
;
1184 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1186 data_col_addr
= start_step
* chip
->ecc
.size
;
1187 /* If we read not a page aligned data */
1188 if (data_col_addr
!= 0)
1189 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1191 p
= bufpoi
+ data_col_addr
;
1192 chip
->read_buf(mtd
, p
, datafrag_len
);
1195 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1196 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1198 /* The performance is faster if to position offsets
1199 according to ecc.pos. Let make sure here that
1200 there are no gaps in ecc positions */
1201 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1202 if (eccpos
[i
+ start_step
* chip
->ecc
.bytes
] + 1 !=
1203 eccpos
[i
+ start_step
* chip
->ecc
.bytes
+ 1]) {
1209 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1210 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1212 /* send the command to read the particular ecc bytes */
1213 /* take care about buswidth alignment in read_buf */
1214 index
= start_step
* chip
->ecc
.bytes
;
1216 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1217 aligned_len
= eccfrag_len
;
1218 if (eccpos
[index
] & (busw
- 1))
1220 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1223 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1224 mtd
->writesize
+ aligned_pos
, -1);
1225 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1228 for (i
= 0; i
< eccfrag_len
; i
++)
1229 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1231 p
= bufpoi
+ data_col_addr
;
1232 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1235 stat
= chip
->ecc
.correct(mtd
, p
,
1236 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1238 mtd
->ecc_stats
.failed
++;
1240 mtd
->ecc_stats
.corrected
+= stat
;
1246 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1247 * @mtd: mtd info structure
1248 * @chip: nand chip info structure
1249 * @buf: buffer to store read data
1250 * @page: page number to read
1252 * Not for syndrome calculating ecc controllers which need a special oob layout
1254 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1255 uint8_t *buf
, int page
)
1257 int i
, eccsize
= chip
->ecc
.size
;
1258 int eccbytes
= chip
->ecc
.bytes
;
1259 int eccsteps
= chip
->ecc
.steps
;
1261 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1262 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1263 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1265 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1266 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1267 chip
->read_buf(mtd
, p
, eccsize
);
1268 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1270 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1272 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1273 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1275 eccsteps
= chip
->ecc
.steps
;
1278 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1281 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1283 mtd
->ecc_stats
.failed
++;
1285 mtd
->ecc_stats
.corrected
+= stat
;
1291 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1292 * @mtd: mtd info structure
1293 * @chip: nand chip info structure
1294 * @buf: buffer to store read data
1295 * @page: page number to read
1297 * Hardware ECC for large page chips, require OOB to be read first.
1298 * For this ECC mode, the write_page method is re-used from ECC_HW.
1299 * These methods read/write ECC from the OOB area, unlike the
1300 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1301 * "infix ECC" scheme and reads/writes ECC from the data area, by
1302 * overwriting the NAND manufacturer bad block markings.
1304 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1305 struct nand_chip
*chip
, uint8_t *buf
, int page
)
1307 int i
, eccsize
= chip
->ecc
.size
;
1308 int eccbytes
= chip
->ecc
.bytes
;
1309 int eccsteps
= chip
->ecc
.steps
;
1311 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1312 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1313 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1315 /* Read the OOB area first */
1316 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1317 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1318 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1320 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1321 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1323 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1326 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1327 chip
->read_buf(mtd
, p
, eccsize
);
1328 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1330 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1332 mtd
->ecc_stats
.failed
++;
1334 mtd
->ecc_stats
.corrected
+= stat
;
1340 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1341 * @mtd: mtd info structure
1342 * @chip: nand chip info structure
1343 * @buf: buffer to store read data
1344 * @page: page number to read
1346 * The hw generator calculates the error syndrome automatically. Therefor
1347 * we need a special oob layout and handling.
1349 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1350 uint8_t *buf
, int page
)
1352 int i
, eccsize
= chip
->ecc
.size
;
1353 int eccbytes
= chip
->ecc
.bytes
;
1354 int eccsteps
= chip
->ecc
.steps
;
1356 uint8_t *oob
= chip
->oob_poi
;
1358 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1361 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1362 chip
->read_buf(mtd
, p
, eccsize
);
1364 if (chip
->ecc
.prepad
) {
1365 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1366 oob
+= chip
->ecc
.prepad
;
1369 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1370 chip
->read_buf(mtd
, oob
, eccbytes
);
1371 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1374 mtd
->ecc_stats
.failed
++;
1376 mtd
->ecc_stats
.corrected
+= stat
;
1380 if (chip
->ecc
.postpad
) {
1381 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1382 oob
+= chip
->ecc
.postpad
;
1386 /* Calculate remaining oob bytes */
1387 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1389 chip
->read_buf(mtd
, oob
, i
);
1395 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1396 * @chip: nand chip structure
1397 * @oob: oob destination address
1398 * @ops: oob ops structure
1399 * @len: size of oob to transfer
1401 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1402 struct mtd_oob_ops
*ops
, size_t len
)
1404 switch (ops
->mode
) {
1408 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1411 case MTD_OOB_AUTO
: {
1412 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1413 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1416 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1417 /* Read request not from offset 0 ? */
1418 if (unlikely(roffs
)) {
1419 if (roffs
>= free
->length
) {
1420 roffs
-= free
->length
;
1423 boffs
= free
->offset
+ roffs
;
1424 bytes
= min_t(size_t, len
,
1425 (free
->length
- roffs
));
1428 bytes
= min_t(size_t, len
, free
->length
);
1429 boffs
= free
->offset
;
1431 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1443 * nand_do_read_ops - [Internal] Read data with ECC
1445 * @mtd: MTD device structure
1446 * @from: offset to read from
1447 * @ops: oob ops structure
1449 * Internal function. Called with chip held.
1451 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1452 struct mtd_oob_ops
*ops
)
1454 int chipnr
, page
, realpage
, col
, bytes
, aligned
;
1455 struct nand_chip
*chip
= mtd
->priv
;
1456 struct mtd_ecc_stats stats
;
1457 int blkcheck
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
1460 uint32_t readlen
= ops
->len
;
1461 uint32_t oobreadlen
= ops
->ooblen
;
1462 uint32_t max_oobsize
= ops
->mode
== MTD_OOB_AUTO
?
1463 mtd
->oobavail
: mtd
->oobsize
;
1465 uint8_t *bufpoi
, *oob
, *buf
;
1467 stats
= mtd
->ecc_stats
;
1469 chipnr
= (int)(from
>> chip
->chip_shift
);
1470 chip
->select_chip(mtd
, chipnr
);
1472 realpage
= (int)(from
>> chip
->page_shift
);
1473 page
= realpage
& chip
->pagemask
;
1475 col
= (int)(from
& (mtd
->writesize
- 1));
1481 bytes
= min(mtd
->writesize
- col
, readlen
);
1482 aligned
= (bytes
== mtd
->writesize
);
1484 /* Is the current page in the buffer ? */
1485 if (realpage
!= chip
->pagebuf
|| oob
) {
1486 bufpoi
= aligned
? buf
: chip
->buffers
->databuf
;
1488 if (likely(sndcmd
)) {
1489 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1493 /* Now read the page into the buffer */
1494 if (unlikely(ops
->mode
== MTD_OOB_RAW
))
1495 ret
= chip
->ecc
.read_page_raw(mtd
, chip
,
1497 else if (!aligned
&& NAND_SUBPAGE_READ(chip
) && !oob
)
1498 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1499 col
, bytes
, bufpoi
);
1501 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1506 /* Transfer not aligned data */
1508 if (!NAND_SUBPAGE_READ(chip
) && !oob
&&
1509 !(mtd
->ecc_stats
.failed
- stats
.failed
))
1510 chip
->pagebuf
= realpage
;
1511 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1516 if (unlikely(oob
)) {
1518 int toread
= min(oobreadlen
, max_oobsize
);
1521 oob
= nand_transfer_oob(chip
,
1523 oobreadlen
-= toread
;
1527 if (!(chip
->options
& NAND_NO_READRDY
)) {
1529 * Apply delay or wait for ready/busy pin. Do
1530 * this before the AUTOINCR check, so no
1531 * problems arise if a chip which does auto
1532 * increment is marked as NOAUTOINCR by the
1535 if (!chip
->dev_ready
)
1536 udelay(chip
->chip_delay
);
1538 nand_wait_ready(mtd
);
1541 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1550 /* For subsequent reads align to page boundary. */
1552 /* Increment page address */
1555 page
= realpage
& chip
->pagemask
;
1556 /* Check, if we cross a chip boundary */
1559 chip
->select_chip(mtd
, -1);
1560 chip
->select_chip(mtd
, chipnr
);
1563 /* Check, if the chip supports auto page increment
1564 * or if we have hit a block boundary.
1566 if (!NAND_CANAUTOINCR(chip
) || !(page
& blkcheck
))
1570 ops
->retlen
= ops
->len
- (size_t) readlen
;
1572 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1577 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1580 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
1584 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1585 * @mtd: MTD device structure
1586 * @from: offset to read from
1587 * @len: number of bytes to read
1588 * @retlen: pointer to variable to store the number of read bytes
1589 * @buf: the databuffer to put data
1591 * Get hold of the chip and call nand_do_read
1593 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1594 size_t *retlen
, uint8_t *buf
)
1596 struct nand_chip
*chip
= mtd
->priv
;
1599 /* Do not allow reads past end of device */
1600 if ((from
+ len
) > mtd
->size
)
1605 nand_get_device(chip
, mtd
, FL_READING
);
1607 chip
->ops
.len
= len
;
1608 chip
->ops
.datbuf
= buf
;
1609 chip
->ops
.oobbuf
= NULL
;
1611 ret
= nand_do_read_ops(mtd
, from
, &chip
->ops
);
1613 *retlen
= chip
->ops
.retlen
;
1615 nand_release_device(mtd
);
1621 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1622 * @mtd: mtd info structure
1623 * @chip: nand chip info structure
1624 * @page: page number to read
1625 * @sndcmd: flag whether to issue read command or not
1627 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1628 int page
, int sndcmd
)
1631 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1634 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1639 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1641 * @mtd: mtd info structure
1642 * @chip: nand chip info structure
1643 * @page: page number to read
1644 * @sndcmd: flag whether to issue read command or not
1646 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1647 int page
, int sndcmd
)
1649 uint8_t *buf
= chip
->oob_poi
;
1650 int length
= mtd
->oobsize
;
1651 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1652 int eccsize
= chip
->ecc
.size
;
1653 uint8_t *bufpoi
= buf
;
1654 int i
, toread
, sndrnd
= 0, pos
;
1656 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1657 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1659 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1660 if (mtd
->writesize
> 512)
1661 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1663 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1666 toread
= min_t(int, length
, chunk
);
1667 chip
->read_buf(mtd
, bufpoi
, toread
);
1672 chip
->read_buf(mtd
, bufpoi
, length
);
1678 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1679 * @mtd: mtd info structure
1680 * @chip: nand chip info structure
1681 * @page: page number to write
1683 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1687 const uint8_t *buf
= chip
->oob_poi
;
1688 int length
= mtd
->oobsize
;
1690 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1691 chip
->write_buf(mtd
, buf
, length
);
1692 /* Send command to program the OOB data */
1693 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1695 status
= chip
->waitfunc(mtd
, chip
);
1697 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1701 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1702 * with syndrome - only for large page flash !
1703 * @mtd: mtd info structure
1704 * @chip: nand chip info structure
1705 * @page: page number to write
1707 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1708 struct nand_chip
*chip
, int page
)
1710 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1711 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1712 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1713 const uint8_t *bufpoi
= chip
->oob_poi
;
1716 * data-ecc-data-ecc ... ecc-oob
1718 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1720 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1721 pos
= steps
* (eccsize
+ chunk
);
1726 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1727 for (i
= 0; i
< steps
; i
++) {
1729 if (mtd
->writesize
<= 512) {
1730 uint32_t fill
= 0xFFFFFFFF;
1734 int num
= min_t(int, len
, 4);
1735 chip
->write_buf(mtd
, (uint8_t *)&fill
,
1740 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1741 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
1745 len
= min_t(int, length
, chunk
);
1746 chip
->write_buf(mtd
, bufpoi
, len
);
1751 chip
->write_buf(mtd
, bufpoi
, length
);
1753 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1754 status
= chip
->waitfunc(mtd
, chip
);
1756 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1760 * nand_do_read_oob - [Intern] NAND read out-of-band
1761 * @mtd: MTD device structure
1762 * @from: offset to read from
1763 * @ops: oob operations description structure
1765 * NAND read out-of-band data from the spare area
1767 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
1768 struct mtd_oob_ops
*ops
)
1770 int page
, realpage
, chipnr
, sndcmd
= 1;
1771 struct nand_chip
*chip
= mtd
->priv
;
1772 int blkcheck
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
1773 int readlen
= ops
->ooblen
;
1775 uint8_t *buf
= ops
->oobbuf
;
1777 DEBUG(MTD_DEBUG_LEVEL3
, "%s: from = 0x%08Lx, len = %i\n",
1778 __func__
, (unsigned long long)from
, readlen
);
1780 if (ops
->mode
== MTD_OOB_AUTO
)
1781 len
= chip
->ecc
.layout
->oobavail
;
1785 if (unlikely(ops
->ooboffs
>= len
)) {
1786 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt to start read "
1787 "outside oob\n", __func__
);
1791 /* Do not allow reads past end of device */
1792 if (unlikely(from
>= mtd
->size
||
1793 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
1794 (from
>> chip
->page_shift
)) * len
)) {
1795 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt read beyond end "
1796 "of device\n", __func__
);
1800 chipnr
= (int)(from
>> chip
->chip_shift
);
1801 chip
->select_chip(mtd
, chipnr
);
1803 /* Shift to get page */
1804 realpage
= (int)(from
>> chip
->page_shift
);
1805 page
= realpage
& chip
->pagemask
;
1808 sndcmd
= chip
->ecc
.read_oob(mtd
, chip
, page
, sndcmd
);
1810 len
= min(len
, readlen
);
1811 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
1813 if (!(chip
->options
& NAND_NO_READRDY
)) {
1815 * Apply delay or wait for ready/busy pin. Do this
1816 * before the AUTOINCR check, so no problems arise if a
1817 * chip which does auto increment is marked as
1818 * NOAUTOINCR by the board driver.
1820 if (!chip
->dev_ready
)
1821 udelay(chip
->chip_delay
);
1823 nand_wait_ready(mtd
);
1830 /* Increment page address */
1833 page
= realpage
& chip
->pagemask
;
1834 /* Check, if we cross a chip boundary */
1837 chip
->select_chip(mtd
, -1);
1838 chip
->select_chip(mtd
, chipnr
);
1841 /* Check, if the chip supports auto page increment
1842 * or if we have hit a block boundary.
1844 if (!NAND_CANAUTOINCR(chip
) || !(page
& blkcheck
))
1848 ops
->oobretlen
= ops
->ooblen
;
1853 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1854 * @mtd: MTD device structure
1855 * @from: offset to read from
1856 * @ops: oob operation description structure
1858 * NAND read data and/or out-of-band data
1860 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
1861 struct mtd_oob_ops
*ops
)
1863 struct nand_chip
*chip
= mtd
->priv
;
1864 int ret
= -ENOTSUPP
;
1868 /* Do not allow reads past end of device */
1869 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
1870 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt read "
1871 "beyond end of device\n", __func__
);
1875 nand_get_device(chip
, mtd
, FL_READING
);
1877 switch (ops
->mode
) {
1888 ret
= nand_do_read_oob(mtd
, from
, ops
);
1890 ret
= nand_do_read_ops(mtd
, from
, ops
);
1893 nand_release_device(mtd
);
1899 * nand_write_page_raw - [Intern] raw page write function
1900 * @mtd: mtd info structure
1901 * @chip: nand chip info structure
1904 * Not for syndrome calculating ecc controllers, which use a special oob layout
1906 static void nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1909 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
1910 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1914 * nand_write_page_raw_syndrome - [Intern] raw page write function
1915 * @mtd: mtd info structure
1916 * @chip: nand chip info structure
1919 * We need a special oob layout and handling even when ECC isn't checked.
1921 static void nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
1922 struct nand_chip
*chip
,
1925 int eccsize
= chip
->ecc
.size
;
1926 int eccbytes
= chip
->ecc
.bytes
;
1927 uint8_t *oob
= chip
->oob_poi
;
1930 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1931 chip
->write_buf(mtd
, buf
, eccsize
);
1934 if (chip
->ecc
.prepad
) {
1935 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
1936 oob
+= chip
->ecc
.prepad
;
1939 chip
->read_buf(mtd
, oob
, eccbytes
);
1942 if (chip
->ecc
.postpad
) {
1943 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
1944 oob
+= chip
->ecc
.postpad
;
1948 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1950 chip
->write_buf(mtd
, oob
, size
);
1953 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1954 * @mtd: mtd info structure
1955 * @chip: nand chip info structure
1958 static void nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1961 int i
, eccsize
= chip
->ecc
.size
;
1962 int eccbytes
= chip
->ecc
.bytes
;
1963 int eccsteps
= chip
->ecc
.steps
;
1964 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1965 const uint8_t *p
= buf
;
1966 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1968 /* Software ecc calculation */
1969 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1970 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1972 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1973 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1975 chip
->ecc
.write_page_raw(mtd
, chip
, buf
);
1979 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1980 * @mtd: mtd info structure
1981 * @chip: nand chip info structure
1984 static void nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1987 int i
, eccsize
= chip
->ecc
.size
;
1988 int eccbytes
= chip
->ecc
.bytes
;
1989 int eccsteps
= chip
->ecc
.steps
;
1990 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1991 const uint8_t *p
= buf
;
1992 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1994 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1995 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
1996 chip
->write_buf(mtd
, p
, eccsize
);
1997 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2000 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2001 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2003 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2007 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
2008 * @mtd: mtd info structure
2009 * @chip: nand chip info structure
2012 * The hw generator calculates the error syndrome automatically. Therefor
2013 * we need a special oob layout and handling.
2015 static void nand_write_page_syndrome(struct mtd_info
*mtd
,
2016 struct nand_chip
*chip
, const uint8_t *buf
)
2018 int i
, eccsize
= chip
->ecc
.size
;
2019 int eccbytes
= chip
->ecc
.bytes
;
2020 int eccsteps
= chip
->ecc
.steps
;
2021 const uint8_t *p
= buf
;
2022 uint8_t *oob
= chip
->oob_poi
;
2024 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2026 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2027 chip
->write_buf(mtd
, p
, eccsize
);
2029 if (chip
->ecc
.prepad
) {
2030 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2031 oob
+= chip
->ecc
.prepad
;
2034 chip
->ecc
.calculate(mtd
, p
, oob
);
2035 chip
->write_buf(mtd
, oob
, eccbytes
);
2038 if (chip
->ecc
.postpad
) {
2039 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2040 oob
+= chip
->ecc
.postpad
;
2044 /* Calculate remaining oob bytes */
2045 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2047 chip
->write_buf(mtd
, oob
, i
);
2051 * nand_write_page - [REPLACEABLE] write one page
2052 * @mtd: MTD device structure
2053 * @chip: NAND chip descriptor
2054 * @buf: the data to write
2055 * @page: page number to write
2056 * @cached: cached programming
2057 * @raw: use _raw version of write_page
2059 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2060 const uint8_t *buf
, int page
, int cached
, int raw
)
2064 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2067 chip
->ecc
.write_page_raw(mtd
, chip
, buf
);
2069 chip
->ecc
.write_page(mtd
, chip
, buf
);
2072 * Cached progamming disabled for now, Not sure if its worth the
2073 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2077 if (!cached
|| !(chip
->options
& NAND_CACHEPRG
)) {
2079 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2080 status
= chip
->waitfunc(mtd
, chip
);
2082 * See if operation failed and additional status checks are
2085 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2086 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2089 if (status
& NAND_STATUS_FAIL
)
2092 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2093 status
= chip
->waitfunc(mtd
, chip
);
2096 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2097 /* Send command to read back the data */
2098 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
2100 if (chip
->verify_buf(mtd
, buf
, mtd
->writesize
))
2107 * nand_fill_oob - [Internal] Transfer client buffer to oob
2108 * @chip: nand chip structure
2109 * @oob: oob data buffer
2110 * @len: oob data write length
2111 * @ops: oob ops structure
2113 static uint8_t *nand_fill_oob(struct nand_chip
*chip
, uint8_t *oob
, size_t len
,
2114 struct mtd_oob_ops
*ops
)
2116 switch (ops
->mode
) {
2120 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2123 case MTD_OOB_AUTO
: {
2124 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2125 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2128 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2129 /* Write request not from offset 0 ? */
2130 if (unlikely(woffs
)) {
2131 if (woffs
>= free
->length
) {
2132 woffs
-= free
->length
;
2135 boffs
= free
->offset
+ woffs
;
2136 bytes
= min_t(size_t, len
,
2137 (free
->length
- woffs
));
2140 bytes
= min_t(size_t, len
, free
->length
);
2141 boffs
= free
->offset
;
2143 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2154 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2157 * nand_do_write_ops - [Internal] NAND write with ECC
2158 * @mtd: MTD device structure
2159 * @to: offset to write to
2160 * @ops: oob operations description structure
2162 * NAND write with ECC
2164 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2165 struct mtd_oob_ops
*ops
)
2167 int chipnr
, realpage
, page
, blockmask
, column
;
2168 struct nand_chip
*chip
= mtd
->priv
;
2169 uint32_t writelen
= ops
->len
;
2171 uint32_t oobwritelen
= ops
->ooblen
;
2172 uint32_t oobmaxlen
= ops
->mode
== MTD_OOB_AUTO
?
2173 mtd
->oobavail
: mtd
->oobsize
;
2175 uint8_t *oob
= ops
->oobbuf
;
2176 uint8_t *buf
= ops
->datbuf
;
2183 /* reject writes, which are not page aligned */
2184 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2185 printk(KERN_NOTICE
"%s: Attempt to write not "
2186 "page aligned data\n", __func__
);
2190 column
= to
& (mtd
->writesize
- 1);
2191 subpage
= column
|| (writelen
& (mtd
->writesize
- 1));
2196 chipnr
= (int)(to
>> chip
->chip_shift
);
2197 chip
->select_chip(mtd
, chipnr
);
2199 /* Check, if it is write protected */
2200 if (nand_check_wp(mtd
))
2203 realpage
= (int)(to
>> chip
->page_shift
);
2204 page
= realpage
& chip
->pagemask
;
2205 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2207 /* Invalidate the page cache, when we write to the cached page */
2208 if (to
<= (chip
->pagebuf
<< chip
->page_shift
) &&
2209 (chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2212 /* If we're not given explicit OOB data, let it be 0xFF */
2214 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2216 /* Don't allow multipage oob writes with offset */
2217 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
))
2221 int bytes
= mtd
->writesize
;
2222 int cached
= writelen
> bytes
&& page
!= blockmask
;
2223 uint8_t *wbuf
= buf
;
2225 /* Partial page write ? */
2226 if (unlikely(column
|| writelen
< (mtd
->writesize
- 1))) {
2228 bytes
= min_t(int, bytes
- column
, (int) writelen
);
2230 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2231 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2232 wbuf
= chip
->buffers
->databuf
;
2235 if (unlikely(oob
)) {
2236 size_t len
= min(oobwritelen
, oobmaxlen
);
2237 oob
= nand_fill_oob(chip
, oob
, len
, ops
);
2241 ret
= chip
->write_page(mtd
, chip
, wbuf
, page
, cached
,
2242 (ops
->mode
== MTD_OOB_RAW
));
2254 page
= realpage
& chip
->pagemask
;
2255 /* Check, if we cross a chip boundary */
2258 chip
->select_chip(mtd
, -1);
2259 chip
->select_chip(mtd
, chipnr
);
2263 ops
->retlen
= ops
->len
- writelen
;
2265 ops
->oobretlen
= ops
->ooblen
;
2270 * panic_nand_write - [MTD Interface] NAND write with ECC
2271 * @mtd: MTD device structure
2272 * @to: offset to write to
2273 * @len: number of bytes to write
2274 * @retlen: pointer to variable to store the number of written bytes
2275 * @buf: the data to write
2277 * NAND write with ECC. Used when performing writes in interrupt context, this
2278 * may for example be called by mtdoops when writing an oops while in panic.
2280 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2281 size_t *retlen
, const uint8_t *buf
)
2283 struct nand_chip
*chip
= mtd
->priv
;
2286 /* Do not allow reads past end of device */
2287 if ((to
+ len
) > mtd
->size
)
2292 /* Wait for the device to get ready. */
2293 panic_nand_wait(mtd
, chip
, 400);
2295 /* Grab the device. */
2296 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2298 chip
->ops
.len
= len
;
2299 chip
->ops
.datbuf
= (uint8_t *)buf
;
2300 chip
->ops
.oobbuf
= NULL
;
2302 ret
= nand_do_write_ops(mtd
, to
, &chip
->ops
);
2304 *retlen
= chip
->ops
.retlen
;
2309 * nand_write - [MTD Interface] NAND write with ECC
2310 * @mtd: MTD device structure
2311 * @to: offset to write to
2312 * @len: number of bytes to write
2313 * @retlen: pointer to variable to store the number of written bytes
2314 * @buf: the data to write
2316 * NAND write with ECC
2318 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2319 size_t *retlen
, const uint8_t *buf
)
2321 struct nand_chip
*chip
= mtd
->priv
;
2324 /* Do not allow reads past end of device */
2325 if ((to
+ len
) > mtd
->size
)
2330 nand_get_device(chip
, mtd
, FL_WRITING
);
2332 chip
->ops
.len
= len
;
2333 chip
->ops
.datbuf
= (uint8_t *)buf
;
2334 chip
->ops
.oobbuf
= NULL
;
2336 ret
= nand_do_write_ops(mtd
, to
, &chip
->ops
);
2338 *retlen
= chip
->ops
.retlen
;
2340 nand_release_device(mtd
);
2346 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2347 * @mtd: MTD device structure
2348 * @to: offset to write to
2349 * @ops: oob operation description structure
2351 * NAND write out-of-band
2353 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2354 struct mtd_oob_ops
*ops
)
2356 int chipnr
, page
, status
, len
;
2357 struct nand_chip
*chip
= mtd
->priv
;
2359 DEBUG(MTD_DEBUG_LEVEL3
, "%s: to = 0x%08x, len = %i\n",
2360 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2362 if (ops
->mode
== MTD_OOB_AUTO
)
2363 len
= chip
->ecc
.layout
->oobavail
;
2367 /* Do not allow write past end of page */
2368 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2369 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt to write "
2370 "past end of page\n", __func__
);
2374 if (unlikely(ops
->ooboffs
>= len
)) {
2375 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt to start "
2376 "write outside oob\n", __func__
);
2380 /* Do not allow reads past end of device */
2381 if (unlikely(to
>= mtd
->size
||
2382 ops
->ooboffs
+ ops
->ooblen
>
2383 ((mtd
->size
>> chip
->page_shift
) -
2384 (to
>> chip
->page_shift
)) * len
)) {
2385 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt write beyond "
2386 "end of device\n", __func__
);
2390 chipnr
= (int)(to
>> chip
->chip_shift
);
2391 chip
->select_chip(mtd
, chipnr
);
2393 /* Shift to get page */
2394 page
= (int)(to
>> chip
->page_shift
);
2397 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2398 * of my DiskOnChip 2000 test units) will clear the whole data page too
2399 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2400 * it in the doc2000 driver in August 1999. dwmw2.
2402 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2404 /* Check, if it is write protected */
2405 if (nand_check_wp(mtd
))
2408 /* Invalidate the page cache, if we write to the cached page */
2409 if (page
== chip
->pagebuf
)
2412 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2413 nand_fill_oob(chip
, ops
->oobbuf
, ops
->ooblen
, ops
);
2414 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2415 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2420 ops
->oobretlen
= ops
->ooblen
;
2426 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2427 * @mtd: MTD device structure
2428 * @to: offset to write to
2429 * @ops: oob operation description structure
2431 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2432 struct mtd_oob_ops
*ops
)
2434 struct nand_chip
*chip
= mtd
->priv
;
2435 int ret
= -ENOTSUPP
;
2439 /* Do not allow writes past end of device */
2440 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2441 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Attempt write beyond "
2442 "end of device\n", __func__
);
2446 nand_get_device(chip
, mtd
, FL_WRITING
);
2448 switch (ops
->mode
) {
2459 ret
= nand_do_write_oob(mtd
, to
, ops
);
2461 ret
= nand_do_write_ops(mtd
, to
, ops
);
2464 nand_release_device(mtd
);
2469 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2470 * @mtd: MTD device structure
2471 * @page: the page address of the block which will be erased
2473 * Standard erase command for NAND chips
2475 static void single_erase_cmd(struct mtd_info
*mtd
, int page
)
2477 struct nand_chip
*chip
= mtd
->priv
;
2478 /* Send commands to erase a block */
2479 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2480 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2484 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2485 * @mtd: MTD device structure
2486 * @page: the page address of the block which will be erased
2488 * AND multi block erase command function
2489 * Erase 4 consecutive blocks
2491 static void multi_erase_cmd(struct mtd_info
*mtd
, int page
)
2493 struct nand_chip
*chip
= mtd
->priv
;
2494 /* Send commands to erase a block */
2495 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2496 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2497 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2498 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2499 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2503 * nand_erase - [MTD Interface] erase block(s)
2504 * @mtd: MTD device structure
2505 * @instr: erase instruction
2507 * Erase one ore more blocks
2509 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2511 return nand_erase_nand(mtd
, instr
, 0);
2514 #define BBT_PAGE_MASK 0xffffff3f
2516 * nand_erase_nand - [Internal] erase block(s)
2517 * @mtd: MTD device structure
2518 * @instr: erase instruction
2519 * @allowbbt: allow erasing the bbt area
2521 * Erase one ore more blocks
2523 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2526 int page
, status
, pages_per_block
, ret
, chipnr
;
2527 struct nand_chip
*chip
= mtd
->priv
;
2528 loff_t rewrite_bbt
[NAND_MAX_CHIPS
] = {0};
2529 unsigned int bbt_masked_page
= 0xffffffff;
2532 DEBUG(MTD_DEBUG_LEVEL3
, "%s: start = 0x%012llx, len = %llu\n",
2533 __func__
, (unsigned long long)instr
->addr
,
2534 (unsigned long long)instr
->len
);
2536 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2539 instr
->fail_addr
= MTD_FAIL_ADDR_UNKNOWN
;
2541 /* Grab the lock and see if the device is available */
2542 nand_get_device(chip
, mtd
, FL_ERASING
);
2544 /* Shift to get first page */
2545 page
= (int)(instr
->addr
>> chip
->page_shift
);
2546 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2548 /* Calculate pages in each block */
2549 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2551 /* Select the NAND device */
2552 chip
->select_chip(mtd
, chipnr
);
2554 /* Check, if it is write protected */
2555 if (nand_check_wp(mtd
)) {
2556 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Device is write protected!!!\n",
2558 instr
->state
= MTD_ERASE_FAILED
;
2563 * If BBT requires refresh, set the BBT page mask to see if the BBT
2564 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2565 * can not be matched. This is also done when the bbt is actually
2566 * erased to avoid recusrsive updates
2568 if (chip
->options
& BBT_AUTO_REFRESH
&& !allowbbt
)
2569 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] & BBT_PAGE_MASK
;
2571 /* Loop through the pages */
2574 instr
->state
= MTD_ERASING
;
2578 * heck if we have a bad block, we do not erase bad blocks !
2580 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2581 chip
->page_shift
, 0, allowbbt
)) {
2582 printk(KERN_WARNING
"%s: attempt to erase a bad block "
2583 "at page 0x%08x\n", __func__
, page
);
2584 instr
->state
= MTD_ERASE_FAILED
;
2589 * Invalidate the page cache, if we erase the block which
2590 * contains the current cached page
2592 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2593 (page
+ pages_per_block
))
2596 chip
->erase_cmd(mtd
, page
& chip
->pagemask
);
2598 status
= chip
->waitfunc(mtd
, chip
);
2601 * See if operation failed and additional status checks are
2604 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2605 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2608 /* See if block erase succeeded */
2609 if (status
& NAND_STATUS_FAIL
) {
2610 DEBUG(MTD_DEBUG_LEVEL0
, "%s: Failed erase, "
2611 "page 0x%08x\n", __func__
, page
);
2612 instr
->state
= MTD_ERASE_FAILED
;
2614 ((loff_t
)page
<< chip
->page_shift
);
2619 * If BBT requires refresh, set the BBT rewrite flag to the
2622 if (bbt_masked_page
!= 0xffffffff &&
2623 (page
& BBT_PAGE_MASK
) == bbt_masked_page
)
2624 rewrite_bbt
[chipnr
] =
2625 ((loff_t
)page
<< chip
->page_shift
);
2627 /* Increment page address and decrement length */
2628 len
-= (1 << chip
->phys_erase_shift
);
2629 page
+= pages_per_block
;
2631 /* Check, if we cross a chip boundary */
2632 if (len
&& !(page
& chip
->pagemask
)) {
2634 chip
->select_chip(mtd
, -1);
2635 chip
->select_chip(mtd
, chipnr
);
2638 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2639 * page mask to see if this BBT should be rewritten
2641 if (bbt_masked_page
!= 0xffffffff &&
2642 (chip
->bbt_td
->options
& NAND_BBT_PERCHIP
))
2643 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] &
2647 instr
->state
= MTD_ERASE_DONE
;
2651 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2653 /* Deselect and wake up anyone waiting on the device */
2654 nand_release_device(mtd
);
2656 /* Do call back function */
2658 mtd_erase_callback(instr
);
2661 * If BBT requires refresh and erase was successful, rewrite any
2662 * selected bad block tables
2664 if (bbt_masked_page
== 0xffffffff || ret
)
2667 for (chipnr
= 0; chipnr
< chip
->numchips
; chipnr
++) {
2668 if (!rewrite_bbt
[chipnr
])
2670 /* update the BBT for chip */
2671 DEBUG(MTD_DEBUG_LEVEL0
, "%s: nand_update_bbt "
2672 "(%d:0x%0llx 0x%0x)\n", __func__
, chipnr
,
2673 rewrite_bbt
[chipnr
], chip
->bbt_td
->pages
[chipnr
]);
2674 nand_update_bbt(mtd
, rewrite_bbt
[chipnr
]);
2677 /* Return more or less happy */
2682 * nand_sync - [MTD Interface] sync
2683 * @mtd: MTD device structure
2685 * Sync is actually a wait for chip ready function
2687 static void nand_sync(struct mtd_info
*mtd
)
2689 struct nand_chip
*chip
= mtd
->priv
;
2691 DEBUG(MTD_DEBUG_LEVEL3
, "%s: called\n", __func__
);
2693 /* Grab the lock and see if the device is available */
2694 nand_get_device(chip
, mtd
, FL_SYNCING
);
2695 /* Release it and go back */
2696 nand_release_device(mtd
);
2700 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2701 * @mtd: MTD device structure
2702 * @offs: offset relative to mtd start
2704 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2706 /* Check for invalid offset */
2707 if (offs
> mtd
->size
)
2710 return nand_block_checkbad(mtd
, offs
, 1, 0);
2714 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2715 * @mtd: MTD device structure
2716 * @ofs: offset relative to mtd start
2718 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
2720 struct nand_chip
*chip
= mtd
->priv
;
2723 ret
= nand_block_isbad(mtd
, ofs
);
2725 /* If it was bad already, return success and do nothing. */
2731 return chip
->block_markbad(mtd
, ofs
);
2735 * nand_suspend - [MTD Interface] Suspend the NAND flash
2736 * @mtd: MTD device structure
2738 static int nand_suspend(struct mtd_info
*mtd
)
2740 struct nand_chip
*chip
= mtd
->priv
;
2742 return nand_get_device(chip
, mtd
, FL_PM_SUSPENDED
);
2746 * nand_resume - [MTD Interface] Resume the NAND flash
2747 * @mtd: MTD device structure
2749 static void nand_resume(struct mtd_info
*mtd
)
2751 struct nand_chip
*chip
= mtd
->priv
;
2753 if (chip
->state
== FL_PM_SUSPENDED
)
2754 nand_release_device(mtd
);
2756 printk(KERN_ERR
"%s called for a chip which is not "
2757 "in suspended state\n", __func__
);
2761 * Set default functions
2763 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
2765 /* check for proper chip_delay setup, set 20us if not */
2766 if (!chip
->chip_delay
)
2767 chip
->chip_delay
= 20;
2769 /* check, if a user supplied command function given */
2770 if (chip
->cmdfunc
== NULL
)
2771 chip
->cmdfunc
= nand_command
;
2773 /* check, if a user supplied wait function given */
2774 if (chip
->waitfunc
== NULL
)
2775 chip
->waitfunc
= nand_wait
;
2777 if (!chip
->select_chip
)
2778 chip
->select_chip
= nand_select_chip
;
2779 if (!chip
->read_byte
)
2780 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
2781 if (!chip
->read_word
)
2782 chip
->read_word
= nand_read_word
;
2783 if (!chip
->block_bad
)
2784 chip
->block_bad
= nand_block_bad
;
2785 if (!chip
->block_markbad
)
2786 chip
->block_markbad
= nand_default_block_markbad
;
2787 if (!chip
->write_buf
)
2788 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
2789 if (!chip
->read_buf
)
2790 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
2791 if (!chip
->verify_buf
)
2792 chip
->verify_buf
= busw
? nand_verify_buf16
: nand_verify_buf
;
2793 if (!chip
->scan_bbt
)
2794 chip
->scan_bbt
= nand_default_bbt
;
2796 if (!chip
->controller
) {
2797 chip
->controller
= &chip
->hwcontrol
;
2798 spin_lock_init(&chip
->controller
->lock
);
2799 init_waitqueue_head(&chip
->controller
->wq
);
2805 * sanitize ONFI strings so we can safely print them
2807 static void sanitize_string(uint8_t *s
, size_t len
)
2811 /* null terminate */
2814 /* remove non printable chars */
2815 for (i
= 0; i
< len
- 1; i
++) {
2816 if (s
[i
] < ' ' || s
[i
] > 127)
2820 /* remove trailing spaces */
2824 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
2829 for (i
= 0; i
< 8; i
++)
2830 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
2837 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2839 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2842 struct nand_onfi_params
*p
= &chip
->onfi_params
;
2846 /* try ONFI for unknow chip or LP */
2847 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
2848 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
2849 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
2852 printk(KERN_INFO
"ONFI flash detected\n");
2853 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
2854 for (i
= 0; i
< 3; i
++) {
2855 chip
->read_buf(mtd
, (uint8_t *)p
, sizeof(*p
));
2856 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
2857 le16_to_cpu(p
->crc
)) {
2858 printk(KERN_INFO
"ONFI param page %d valid\n", i
);
2867 val
= le16_to_cpu(p
->revision
);
2869 chip
->onfi_version
= 23;
2870 else if (val
& (1 << 4))
2871 chip
->onfi_version
= 22;
2872 else if (val
& (1 << 3))
2873 chip
->onfi_version
= 21;
2874 else if (val
& (1 << 2))
2875 chip
->onfi_version
= 20;
2876 else if (val
& (1 << 1))
2877 chip
->onfi_version
= 10;
2879 chip
->onfi_version
= 0;
2881 if (!chip
->onfi_version
) {
2882 printk(KERN_INFO
"%s: unsupported ONFI version: %d\n",
2887 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
2888 sanitize_string(p
->model
, sizeof(p
->model
));
2890 mtd
->name
= p
->model
;
2891 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
2892 mtd
->erasesize
= le32_to_cpu(p
->pages_per_block
) * mtd
->writesize
;
2893 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
2894 chip
->chipsize
= (uint64_t)le32_to_cpu(p
->blocks_per_lun
) * mtd
->erasesize
;
2896 if (le16_to_cpu(p
->features
) & 1)
2897 busw
= NAND_BUSWIDTH_16
;
2899 chip
->options
&= ~NAND_CHIPOPTIONS_MSK
;
2900 chip
->options
|= (NAND_NO_READRDY
|
2901 NAND_NO_AUTOINCR
) & NAND_CHIPOPTIONS_MSK
;
2907 * Get the flash and manufacturer id and lookup if the type is supported
2909 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
2910 struct nand_chip
*chip
,
2912 int *maf_id
, int *dev_id
,
2913 struct nand_flash_dev
*type
)
2919 /* Select the device */
2920 chip
->select_chip(mtd
, 0);
2923 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2926 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2928 /* Send the command for reading device ID */
2929 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2931 /* Read manufacturer and device IDs */
2932 *maf_id
= chip
->read_byte(mtd
);
2933 *dev_id
= chip
->read_byte(mtd
);
2935 /* Try again to make sure, as some systems the bus-hold or other
2936 * interface concerns can cause random data which looks like a
2937 * possibly credible NAND flash to appear. If the two results do
2938 * not match, ignore the device completely.
2941 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2943 for (i
= 0; i
< 2; i
++)
2944 id_data
[i
] = chip
->read_byte(mtd
);
2946 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
2947 printk(KERN_INFO
"%s: second ID read did not match "
2948 "%02x,%02x against %02x,%02x\n", __func__
,
2949 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
2950 return ERR_PTR(-ENODEV
);
2954 type
= nand_flash_ids
;
2956 for (; type
->name
!= NULL
; type
++)
2957 if (*dev_id
== type
->id
)
2960 chip
->onfi_version
= 0;
2961 if (!type
->name
|| !type
->pagesize
) {
2962 /* Check is chip is ONFI compliant */
2963 ret
= nand_flash_detect_onfi(mtd
, chip
, busw
);
2968 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
2970 /* Read entire ID string */
2972 for (i
= 0; i
< 8; i
++)
2973 id_data
[i
] = chip
->read_byte(mtd
);
2976 return ERR_PTR(-ENODEV
);
2979 mtd
->name
= type
->name
;
2981 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
2983 if (!type
->pagesize
&& chip
->init_size
) {
2984 /* set the pagesize, oobsize, erasesize by the driver*/
2985 busw
= chip
->init_size(mtd
, chip
, id_data
);
2986 } else if (!type
->pagesize
) {
2988 /* The 3rd id byte holds MLC / multichip data */
2989 chip
->cellinfo
= id_data
[2];
2990 /* The 4th id byte is the important one */
2994 * Field definitions are in the following datasheets:
2995 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2996 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2998 * Check for wraparound + Samsung ID + nonzero 6th byte
2999 * to decide what to do.
3001 if (id_data
[0] == id_data
[6] && id_data
[1] == id_data
[7] &&
3002 id_data
[0] == NAND_MFR_SAMSUNG
&&
3003 (chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3004 id_data
[5] != 0x00) {
3006 mtd
->writesize
= 2048 << (extid
& 0x03);
3009 switch (extid
& 0x03) {
3024 /* Calc blocksize */
3025 mtd
->erasesize
= (128 * 1024) <<
3026 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3030 mtd
->writesize
= 1024 << (extid
& 0x03);
3033 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3034 (mtd
->writesize
>> 9);
3036 /* Calc blocksize. Blocksize is multiples of 64KiB */
3037 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3039 /* Get buswidth information */
3040 busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3044 * Old devices have chip data hardcoded in the device id table
3046 mtd
->erasesize
= type
->erasesize
;
3047 mtd
->writesize
= type
->pagesize
;
3048 mtd
->oobsize
= mtd
->writesize
/ 32;
3049 busw
= type
->options
& NAND_BUSWIDTH_16
;
3052 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3053 * some Spansion chips have erasesize that conflicts with size
3054 * listed in nand_ids table
3055 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3057 if (*maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 &&
3058 id_data
[5] == 0x00 && id_data
[6] == 0x00 &&
3059 id_data
[7] == 0x00 && mtd
->writesize
== 512) {
3060 mtd
->erasesize
= 128 * 1024;
3061 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3064 /* Get chip options, preserve non chip based options */
3065 chip
->options
&= ~NAND_CHIPOPTIONS_MSK
;
3066 chip
->options
|= type
->options
& NAND_CHIPOPTIONS_MSK
;
3068 /* Check if chip is a not a samsung device. Do not clear the
3069 * options for chips which are not having an extended id.
3071 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3072 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3076 * Set chip as a default. Board drivers can override it, if necessary
3078 chip
->options
|= NAND_NO_AUTOINCR
;
3080 /* Try to identify manufacturer */
3081 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3082 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3087 * Check, if buswidth is correct. Hardware drivers should set
3090 if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3091 printk(KERN_INFO
"NAND device: Manufacturer ID:"
3092 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id
,
3093 *dev_id
, nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3094 printk(KERN_WARNING
"NAND bus width %d instead %d bit\n",
3095 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3097 return ERR_PTR(-EINVAL
);
3100 /* Calculate the address shift from the page size */
3101 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3102 /* Convert chipsize to number of pages per chip -1. */
3103 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3105 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3106 ffs(mtd
->erasesize
) - 1;
3107 if (chip
->chipsize
& 0xffffffff)
3108 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3110 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3111 chip
->chip_shift
+= 32 - 1;
3114 /* Set the bad block position */
3115 if (mtd
->writesize
> 512 || (busw
& NAND_BUSWIDTH_16
))
3116 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3118 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3121 * Bad block marker is stored in the last page of each block
3122 * on Samsung and Hynix MLC devices; stored in first two pages
3123 * of each block on Micron devices with 2KiB pages and on
3124 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3125 * only the first page.
3127 if ((chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3128 (*maf_id
== NAND_MFR_SAMSUNG
||
3129 *maf_id
== NAND_MFR_HYNIX
))
3130 chip
->options
|= NAND_BBT_SCANLASTPAGE
;
3131 else if ((!(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3132 (*maf_id
== NAND_MFR_SAMSUNG
||
3133 *maf_id
== NAND_MFR_HYNIX
||
3134 *maf_id
== NAND_MFR_TOSHIBA
||
3135 *maf_id
== NAND_MFR_AMD
)) ||
3136 (mtd
->writesize
== 2048 &&
3137 *maf_id
== NAND_MFR_MICRON
))
3138 chip
->options
|= NAND_BBT_SCAN2NDPAGE
;
3141 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
3143 if (!(busw
& NAND_BUSWIDTH_16
) &&
3144 *maf_id
== NAND_MFR_STMICRO
&&
3145 mtd
->writesize
== 2048) {
3146 chip
->options
|= NAND_BBT_SCANBYTE1AND6
;
3147 chip
->badblockpos
= 0;
3150 /* Check for AND chips with 4 page planes */
3151 if (chip
->options
& NAND_4PAGE_ARRAY
)
3152 chip
->erase_cmd
= multi_erase_cmd
;
3154 chip
->erase_cmd
= single_erase_cmd
;
3156 /* Do not replace user supplied command function ! */
3157 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3158 chip
->cmdfunc
= nand_command_lp
;
3160 /* TODO onfi flash name */
3161 printk(KERN_INFO
"NAND device: Manufacturer ID:"
3162 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id
, *dev_id
,
3163 nand_manuf_ids
[maf_idx
].name
,
3164 chip
->onfi_version
? chip
->onfi_params
.model
: type
->name
);
3170 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3171 * @mtd: MTD device structure
3172 * @maxchips: Number of chips to scan for
3173 * @table: Alternative NAND ID table
3175 * This is the first phase of the normal nand_scan() function. It
3176 * reads the flash ID and sets up MTD fields accordingly.
3178 * The mtd->owner field must be set to the module of the caller.
3180 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
3181 struct nand_flash_dev
*table
)
3183 int i
, busw
, nand_maf_id
, nand_dev_id
;
3184 struct nand_chip
*chip
= mtd
->priv
;
3185 struct nand_flash_dev
*type
;
3187 /* Get buswidth to select the correct functions */
3188 busw
= chip
->options
& NAND_BUSWIDTH_16
;
3189 /* Set the default functions */
3190 nand_set_defaults(chip
, busw
);
3192 /* Read the flash type */
3193 type
= nand_get_flash_type(mtd
, chip
, busw
,
3194 &nand_maf_id
, &nand_dev_id
, table
);
3197 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
3198 printk(KERN_WARNING
"No NAND device found.\n");
3199 chip
->select_chip(mtd
, -1);
3200 return PTR_ERR(type
);
3203 /* Check for a chip array */
3204 for (i
= 1; i
< maxchips
; i
++) {
3205 chip
->select_chip(mtd
, i
);
3206 /* See comment in nand_get_flash_type for reset */
3207 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3208 /* Send the command for reading device ID */
3209 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3210 /* Read manufacturer and device IDs */
3211 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
3212 nand_dev_id
!= chip
->read_byte(mtd
))
3216 printk(KERN_INFO
"%d NAND chips detected\n", i
);
3218 /* Store the number of chips and calc total size for mtd */
3220 mtd
->size
= i
* chip
->chipsize
;
3224 EXPORT_SYMBOL(nand_scan_ident
);
3228 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3229 * @mtd: MTD device structure
3231 * This is the second phase of the normal nand_scan() function. It
3232 * fills out all the uninitialized function pointers with the defaults
3233 * and scans for a bad block table if appropriate.
3235 int nand_scan_tail(struct mtd_info
*mtd
)
3238 struct nand_chip
*chip
= mtd
->priv
;
3240 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3241 chip
->buffers
= kmalloc(sizeof(*chip
->buffers
), GFP_KERNEL
);
3245 /* Set the internal oob buffer location, just after the page data */
3246 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
3249 * If no default placement scheme is given, select an appropriate one
3251 if (!chip
->ecc
.layout
) {
3252 switch (mtd
->oobsize
) {
3254 chip
->ecc
.layout
= &nand_oob_8
;
3257 chip
->ecc
.layout
= &nand_oob_16
;
3260 chip
->ecc
.layout
= &nand_oob_64
;
3263 chip
->ecc
.layout
= &nand_oob_128
;
3266 printk(KERN_WARNING
"No oob scheme defined for "
3267 "oobsize %d\n", mtd
->oobsize
);
3272 if (!chip
->write_page
)
3273 chip
->write_page
= nand_write_page
;
3276 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3277 * selected and we have 256 byte pagesize fallback to software ECC
3280 switch (chip
->ecc
.mode
) {
3281 case NAND_ECC_HW_OOB_FIRST
:
3282 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3283 if (!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3285 printk(KERN_WARNING
"No ECC functions supplied; "
3286 "Hardware ECC not possible\n");
3289 if (!chip
->ecc
.read_page
)
3290 chip
->ecc
.read_page
= nand_read_page_hwecc_oob_first
;
3293 /* Use standard hwecc read page function ? */
3294 if (!chip
->ecc
.read_page
)
3295 chip
->ecc
.read_page
= nand_read_page_hwecc
;
3296 if (!chip
->ecc
.write_page
)
3297 chip
->ecc
.write_page
= nand_write_page_hwecc
;
3298 if (!chip
->ecc
.read_page_raw
)
3299 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3300 if (!chip
->ecc
.write_page_raw
)
3301 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3302 if (!chip
->ecc
.read_oob
)
3303 chip
->ecc
.read_oob
= nand_read_oob_std
;
3304 if (!chip
->ecc
.write_oob
)
3305 chip
->ecc
.write_oob
= nand_write_oob_std
;
3307 case NAND_ECC_HW_SYNDROME
:
3308 if ((!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3309 !chip
->ecc
.hwctl
) &&
3310 (!chip
->ecc
.read_page
||
3311 chip
->ecc
.read_page
== nand_read_page_hwecc
||
3312 !chip
->ecc
.write_page
||
3313 chip
->ecc
.write_page
== nand_write_page_hwecc
)) {
3314 printk(KERN_WARNING
"No ECC functions supplied; "
3315 "Hardware ECC not possible\n");
3318 /* Use standard syndrome read/write page function ? */
3319 if (!chip
->ecc
.read_page
)
3320 chip
->ecc
.read_page
= nand_read_page_syndrome
;
3321 if (!chip
->ecc
.write_page
)
3322 chip
->ecc
.write_page
= nand_write_page_syndrome
;
3323 if (!chip
->ecc
.read_page_raw
)
3324 chip
->ecc
.read_page_raw
= nand_read_page_raw_syndrome
;
3325 if (!chip
->ecc
.write_page_raw
)
3326 chip
->ecc
.write_page_raw
= nand_write_page_raw_syndrome
;
3327 if (!chip
->ecc
.read_oob
)
3328 chip
->ecc
.read_oob
= nand_read_oob_syndrome
;
3329 if (!chip
->ecc
.write_oob
)
3330 chip
->ecc
.write_oob
= nand_write_oob_syndrome
;
3332 if (mtd
->writesize
>= chip
->ecc
.size
)
3334 printk(KERN_WARNING
"%d byte HW ECC not possible on "
3335 "%d byte page size, fallback to SW ECC\n",
3336 chip
->ecc
.size
, mtd
->writesize
);
3337 chip
->ecc
.mode
= NAND_ECC_SOFT
;
3340 chip
->ecc
.calculate
= nand_calculate_ecc
;
3341 chip
->ecc
.correct
= nand_correct_data
;
3342 chip
->ecc
.read_page
= nand_read_page_swecc
;
3343 chip
->ecc
.read_subpage
= nand_read_subpage
;
3344 chip
->ecc
.write_page
= nand_write_page_swecc
;
3345 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3346 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3347 chip
->ecc
.read_oob
= nand_read_oob_std
;
3348 chip
->ecc
.write_oob
= nand_write_oob_std
;
3349 if (!chip
->ecc
.size
)
3350 chip
->ecc
.size
= 256;
3351 chip
->ecc
.bytes
= 3;
3355 printk(KERN_WARNING
"NAND_ECC_NONE selected by board driver. "
3356 "This is not recommended !!\n");
3357 chip
->ecc
.read_page
= nand_read_page_raw
;
3358 chip
->ecc
.write_page
= nand_write_page_raw
;
3359 chip
->ecc
.read_oob
= nand_read_oob_std
;
3360 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3361 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3362 chip
->ecc
.write_oob
= nand_write_oob_std
;
3363 chip
->ecc
.size
= mtd
->writesize
;
3364 chip
->ecc
.bytes
= 0;
3368 printk(KERN_WARNING
"Invalid NAND_ECC_MODE %d\n",
3374 * The number of bytes available for a client to place data into
3375 * the out of band area
3377 chip
->ecc
.layout
->oobavail
= 0;
3378 for (i
= 0; chip
->ecc
.layout
->oobfree
[i
].length
3379 && i
< ARRAY_SIZE(chip
->ecc
.layout
->oobfree
); i
++)
3380 chip
->ecc
.layout
->oobavail
+=
3381 chip
->ecc
.layout
->oobfree
[i
].length
;
3382 mtd
->oobavail
= chip
->ecc
.layout
->oobavail
;
3385 * Set the number of read / write steps for one page depending on ECC
3388 chip
->ecc
.steps
= mtd
->writesize
/ chip
->ecc
.size
;
3389 if (chip
->ecc
.steps
* chip
->ecc
.size
!= mtd
->writesize
) {
3390 printk(KERN_WARNING
"Invalid ecc parameters\n");
3393 chip
->ecc
.total
= chip
->ecc
.steps
* chip
->ecc
.bytes
;
3396 * Allow subpage writes up to ecc.steps. Not possible for MLC
3399 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
3400 !(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
)) {
3401 switch (chip
->ecc
.steps
) {
3403 mtd
->subpage_sft
= 1;
3408 mtd
->subpage_sft
= 2;
3412 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
3414 /* Initialize state */
3415 chip
->state
= FL_READY
;
3417 /* De-select the device */
3418 chip
->select_chip(mtd
, -1);
3420 /* Invalidate the pagebuffer reference */
3423 /* Fill in remaining MTD driver data */
3424 mtd
->type
= MTD_NANDFLASH
;
3425 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
3427 mtd
->erase
= nand_erase
;
3429 mtd
->unpoint
= NULL
;
3430 mtd
->read
= nand_read
;
3431 mtd
->write
= nand_write
;
3432 mtd
->panic_write
= panic_nand_write
;
3433 mtd
->read_oob
= nand_read_oob
;
3434 mtd
->write_oob
= nand_write_oob
;
3435 mtd
->sync
= nand_sync
;
3438 mtd
->suspend
= nand_suspend
;
3439 mtd
->resume
= nand_resume
;
3440 mtd
->block_isbad
= nand_block_isbad
;
3441 mtd
->block_markbad
= nand_block_markbad
;
3442 mtd
->writebufsize
= mtd
->writesize
;
3444 /* propagate ecc.layout to mtd_info */
3445 mtd
->ecclayout
= chip
->ecc
.layout
;
3447 /* Check, if we should skip the bad block table scan */
3448 if (chip
->options
& NAND_SKIP_BBTSCAN
)
3451 /* Build bad block table */
3452 return chip
->scan_bbt(mtd
);
3454 EXPORT_SYMBOL(nand_scan_tail
);
3456 /* is_module_text_address() isn't exported, and it's mostly a pointless
3457 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3458 * to call us from in-kernel code if the core NAND support is modular. */
3460 #define caller_is_module() (1)
3462 #define caller_is_module() \
3463 is_module_text_address((unsigned long)__builtin_return_address(0))
3467 * nand_scan - [NAND Interface] Scan for the NAND device
3468 * @mtd: MTD device structure
3469 * @maxchips: Number of chips to scan for
3471 * This fills out all the uninitialized function pointers
3472 * with the defaults.
3473 * The flash ID is read and the mtd/chip structures are
3474 * filled with the appropriate values.
3475 * The mtd->owner field must be set to the module of the caller
3478 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
3482 /* Many callers got this wrong, so check for it for a while... */
3483 if (!mtd
->owner
&& caller_is_module()) {
3484 printk(KERN_CRIT
"%s called with NULL mtd->owner!\n",
3489 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
3491 ret
= nand_scan_tail(mtd
);
3494 EXPORT_SYMBOL(nand_scan
);
3497 * nand_release - [NAND Interface] Free resources held by the NAND device
3498 * @mtd: MTD device structure
3500 void nand_release(struct mtd_info
*mtd
)
3502 struct nand_chip
*chip
= mtd
->priv
;
3504 #ifdef CONFIG_MTD_PARTITIONS
3505 /* Deregister partitions */
3506 del_mtd_partitions(mtd
);
3508 /* Deregister the device */
3509 del_mtd_device(mtd
);
3511 /* Free bad block table memory */
3513 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3514 kfree(chip
->buffers
);
3516 /* Free bad block descriptor memory */
3517 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
3518 & NAND_BBT_DYNAMICSTRUCT
)
3519 kfree(chip
->badblock_pattern
);
3521 EXPORT_SYMBOL_GPL(nand_release
);
3523 static int __init
nand_base_init(void)
3525 led_trigger_register_simple("nand-disk", &nand_led_trigger
);
3529 static void __exit
nand_base_exit(void)
3531 led_trigger_unregister_simple(nand_led_trigger
);
3534 module_init(nand_base_init
);
3535 module_exit(nand_base_exit
);
3537 MODULE_LICENSE("GPL");
3538 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3539 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3540 MODULE_DESCRIPTION("Generic NAND flash driver code");