3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
47 #include <linux/mtd/partitions.h>
50 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
52 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
53 struct mtd_oob_ops
*ops
);
55 /* Define default oob placement schemes for large and small page devices */
56 static int nand_ooblayout_ecc_sp(struct mtd_info
*mtd
, int section
,
57 struct mtd_oob_region
*oobregion
)
59 struct nand_chip
*chip
= mtd_to_nand(mtd
);
60 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
66 oobregion
->offset
= 0;
67 oobregion
->length
= 4;
69 oobregion
->offset
= 6;
70 oobregion
->length
= ecc
->total
- 4;
76 static int nand_ooblayout_free_sp(struct mtd_info
*mtd
, int section
,
77 struct mtd_oob_region
*oobregion
)
82 if (mtd
->oobsize
== 16) {
86 oobregion
->length
= 8;
87 oobregion
->offset
= 8;
89 oobregion
->length
= 2;
91 oobregion
->offset
= 3;
93 oobregion
->offset
= 6;
99 const struct mtd_ooblayout_ops nand_ooblayout_sp_ops
= {
100 .ecc
= nand_ooblayout_ecc_sp
,
101 .free
= nand_ooblayout_free_sp
,
103 EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops
);
105 static int nand_ooblayout_ecc_lp(struct mtd_info
*mtd
, int section
,
106 struct mtd_oob_region
*oobregion
)
108 struct nand_chip
*chip
= mtd_to_nand(mtd
);
109 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
114 oobregion
->length
= ecc
->total
;
115 oobregion
->offset
= mtd
->oobsize
- oobregion
->length
;
120 static int nand_ooblayout_free_lp(struct mtd_info
*mtd
, int section
,
121 struct mtd_oob_region
*oobregion
)
123 struct nand_chip
*chip
= mtd_to_nand(mtd
);
124 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
129 oobregion
->length
= mtd
->oobsize
- ecc
->total
- 2;
130 oobregion
->offset
= 2;
135 const struct mtd_ooblayout_ops nand_ooblayout_lp_ops
= {
136 .ecc
= nand_ooblayout_ecc_lp
,
137 .free
= nand_ooblayout_free_lp
,
139 EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops
);
141 static int check_offs_len(struct mtd_info
*mtd
,
142 loff_t ofs
, uint64_t len
)
144 struct nand_chip
*chip
= mtd_to_nand(mtd
);
147 /* Start address must align on block boundary */
148 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
149 pr_debug("%s: unaligned address\n", __func__
);
153 /* Length must align on block boundary */
154 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
155 pr_debug("%s: length not block aligned\n", __func__
);
163 * nand_release_device - [GENERIC] release chip
164 * @mtd: MTD device structure
166 * Release chip lock and wake up anyone waiting on the device.
168 static void nand_release_device(struct mtd_info
*mtd
)
170 struct nand_chip
*chip
= mtd_to_nand(mtd
);
172 /* Release the controller and the chip */
173 spin_lock(&chip
->controller
->lock
);
174 chip
->controller
->active
= NULL
;
175 chip
->state
= FL_READY
;
176 wake_up(&chip
->controller
->wq
);
177 spin_unlock(&chip
->controller
->lock
);
181 * nand_read_byte - [DEFAULT] read one byte from the chip
182 * @mtd: MTD device structure
184 * Default read function for 8bit buswidth
186 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
188 struct nand_chip
*chip
= mtd_to_nand(mtd
);
189 return readb(chip
->IO_ADDR_R
);
193 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
194 * @mtd: MTD device structure
196 * Default read function for 16bit buswidth with endianness conversion.
199 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
201 struct nand_chip
*chip
= mtd_to_nand(mtd
);
202 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
206 * nand_read_word - [DEFAULT] read one word from the chip
207 * @mtd: MTD device structure
209 * Default read function for 16bit buswidth without endianness conversion.
211 static u16
nand_read_word(struct mtd_info
*mtd
)
213 struct nand_chip
*chip
= mtd_to_nand(mtd
);
214 return readw(chip
->IO_ADDR_R
);
218 * nand_select_chip - [DEFAULT] control CE line
219 * @mtd: MTD device structure
220 * @chipnr: chipnumber to select, -1 for deselect
222 * Default select function for 1 chip devices.
224 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
226 struct nand_chip
*chip
= mtd_to_nand(mtd
);
230 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
241 * nand_write_byte - [DEFAULT] write single byte to chip
242 * @mtd: MTD device structure
243 * @byte: value to write
245 * Default function to write a byte to I/O[7:0]
247 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
249 struct nand_chip
*chip
= mtd_to_nand(mtd
);
251 chip
->write_buf(mtd
, &byte
, 1);
255 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
256 * @mtd: MTD device structure
257 * @byte: value to write
259 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
261 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
263 struct nand_chip
*chip
= mtd_to_nand(mtd
);
264 uint16_t word
= byte
;
267 * It's not entirely clear what should happen to I/O[15:8] when writing
268 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
270 * When the host supports a 16-bit bus width, only data is
271 * transferred at the 16-bit width. All address and command line
272 * transfers shall use only the lower 8-bits of the data bus. During
273 * command transfers, the host may place any value on the upper
274 * 8-bits of the data bus. During address transfers, the host shall
275 * set the upper 8-bits of the data bus to 00h.
277 * One user of the write_byte callback is nand_onfi_set_features. The
278 * four parameters are specified to be written to I/O[7:0], but this is
279 * neither an address nor a command transfer. Let's assume a 0 on the
280 * upper I/O lines is OK.
282 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
286 * nand_write_buf - [DEFAULT] write buffer to chip
287 * @mtd: MTD device structure
289 * @len: number of bytes to write
291 * Default write function for 8bit buswidth.
293 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
295 struct nand_chip
*chip
= mtd_to_nand(mtd
);
297 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
301 * nand_read_buf - [DEFAULT] read chip data into buffer
302 * @mtd: MTD device structure
303 * @buf: buffer to store date
304 * @len: number of bytes to read
306 * Default read function for 8bit buswidth.
308 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
310 struct nand_chip
*chip
= mtd_to_nand(mtd
);
312 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
316 * nand_write_buf16 - [DEFAULT] write buffer to chip
317 * @mtd: MTD device structure
319 * @len: number of bytes to write
321 * Default write function for 16bit buswidth.
323 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
325 struct nand_chip
*chip
= mtd_to_nand(mtd
);
326 u16
*p
= (u16
*) buf
;
328 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
332 * nand_read_buf16 - [DEFAULT] read chip data into buffer
333 * @mtd: MTD device structure
334 * @buf: buffer to store date
335 * @len: number of bytes to read
337 * Default read function for 16bit buswidth.
339 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
341 struct nand_chip
*chip
= mtd_to_nand(mtd
);
342 u16
*p
= (u16
*) buf
;
344 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
348 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
349 * @mtd: MTD device structure
350 * @ofs: offset from device start
352 * Check, if the block is bad.
354 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
356 int page
, res
= 0, i
= 0;
357 struct nand_chip
*chip
= mtd_to_nand(mtd
);
360 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
361 ofs
+= mtd
->erasesize
- mtd
->writesize
;
363 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
366 if (chip
->options
& NAND_BUSWIDTH_16
) {
367 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
368 chip
->badblockpos
& 0xFE, page
);
369 bad
= cpu_to_le16(chip
->read_word(mtd
));
370 if (chip
->badblockpos
& 0x1)
375 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
377 bad
= chip
->read_byte(mtd
);
380 if (likely(chip
->badblockbits
== 8))
383 res
= hweight8(bad
) < chip
->badblockbits
;
384 ofs
+= mtd
->writesize
;
385 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
387 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
393 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
394 * @mtd: MTD device structure
395 * @ofs: offset from device start
397 * This is the default implementation, which can be overridden by a hardware
398 * specific driver. It provides the details for writing a bad block marker to a
401 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
403 struct nand_chip
*chip
= mtd_to_nand(mtd
);
404 struct mtd_oob_ops ops
;
405 uint8_t buf
[2] = { 0, 0 };
406 int ret
= 0, res
, i
= 0;
408 memset(&ops
, 0, sizeof(ops
));
410 ops
.ooboffs
= chip
->badblockpos
;
411 if (chip
->options
& NAND_BUSWIDTH_16
) {
412 ops
.ooboffs
&= ~0x01;
413 ops
.len
= ops
.ooblen
= 2;
415 ops
.len
= ops
.ooblen
= 1;
417 ops
.mode
= MTD_OPS_PLACE_OOB
;
419 /* Write to first/last page(s) if necessary */
420 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
421 ofs
+= mtd
->erasesize
- mtd
->writesize
;
423 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
428 ofs
+= mtd
->writesize
;
429 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
435 * nand_block_markbad_lowlevel - mark a block bad
436 * @mtd: MTD device structure
437 * @ofs: offset from device start
439 * This function performs the generic NAND bad block marking steps (i.e., bad
440 * block table(s) and/or marker(s)). We only allow the hardware driver to
441 * specify how to write bad block markers to OOB (chip->block_markbad).
443 * We try operations in the following order:
444 * (1) erase the affected block, to allow OOB marker to be written cleanly
445 * (2) write bad block marker to OOB area of affected block (unless flag
446 * NAND_BBT_NO_OOB_BBM is present)
448 * Note that we retain the first error encountered in (2) or (3), finish the
449 * procedures, and dump the error in the end.
451 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
453 struct nand_chip
*chip
= mtd_to_nand(mtd
);
456 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
457 struct erase_info einfo
;
459 /* Attempt erase before marking OOB */
460 memset(&einfo
, 0, sizeof(einfo
));
463 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
464 nand_erase_nand(mtd
, &einfo
, 0);
466 /* Write bad block marker to OOB */
467 nand_get_device(mtd
, FL_WRITING
);
468 ret
= chip
->block_markbad(mtd
, ofs
);
469 nand_release_device(mtd
);
472 /* Mark block bad in BBT */
474 res
= nand_markbad_bbt(mtd
, ofs
);
480 mtd
->ecc_stats
.badblocks
++;
486 * nand_check_wp - [GENERIC] check if the chip is write protected
487 * @mtd: MTD device structure
489 * Check, if the device is write protected. The function expects, that the
490 * device is already selected.
492 static int nand_check_wp(struct mtd_info
*mtd
)
494 struct nand_chip
*chip
= mtd_to_nand(mtd
);
496 /* Broken xD cards report WP despite being writable */
497 if (chip
->options
& NAND_BROKEN_XD
)
500 /* Check the WP bit */
501 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
502 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
506 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
507 * @mtd: MTD device structure
508 * @ofs: offset from device start
510 * Check if the block is marked as reserved.
512 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
514 struct nand_chip
*chip
= mtd_to_nand(mtd
);
518 /* Return info from the table */
519 return nand_isreserved_bbt(mtd
, ofs
);
523 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
524 * @mtd: MTD device structure
525 * @ofs: offset from device start
526 * @allowbbt: 1, if its allowed to access the bbt area
528 * Check, if the block is bad. Either by reading the bad block table or
529 * calling of the scan function.
531 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
533 struct nand_chip
*chip
= mtd_to_nand(mtd
);
536 return chip
->block_bad(mtd
, ofs
);
538 /* Return info from the table */
539 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
543 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
544 * @mtd: MTD device structure
547 * Helper function for nand_wait_ready used when needing to wait in interrupt
550 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
552 struct nand_chip
*chip
= mtd_to_nand(mtd
);
555 /* Wait for the device to get ready */
556 for (i
= 0; i
< timeo
; i
++) {
557 if (chip
->dev_ready(mtd
))
559 touch_softlockup_watchdog();
565 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
566 * @mtd: MTD device structure
568 * Wait for the ready pin after a command, and warn if a timeout occurs.
570 void nand_wait_ready(struct mtd_info
*mtd
)
572 struct nand_chip
*chip
= mtd_to_nand(mtd
);
573 unsigned long timeo
= 400;
575 if (in_interrupt() || oops_in_progress
)
576 return panic_nand_wait_ready(mtd
, timeo
);
578 /* Wait until command is processed or timeout occurs */
579 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
581 if (chip
->dev_ready(mtd
))
584 } while (time_before(jiffies
, timeo
));
586 if (!chip
->dev_ready(mtd
))
587 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
589 EXPORT_SYMBOL_GPL(nand_wait_ready
);
592 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
593 * @mtd: MTD device structure
594 * @timeo: Timeout in ms
596 * Wait for status ready (i.e. command done) or timeout.
598 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
600 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
602 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
604 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
606 touch_softlockup_watchdog();
607 } while (time_before(jiffies
, timeo
));
611 * nand_command - [DEFAULT] Send command to NAND device
612 * @mtd: MTD device structure
613 * @command: the command to be sent
614 * @column: the column address for this command, -1 if none
615 * @page_addr: the page address for this command, -1 if none
617 * Send command to NAND device. This function is used for small page devices
618 * (512 Bytes per page).
620 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
621 int column
, int page_addr
)
623 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
624 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
626 /* Write out the command to the device */
627 if (command
== NAND_CMD_SEQIN
) {
630 if (column
>= mtd
->writesize
) {
632 column
-= mtd
->writesize
;
633 readcmd
= NAND_CMD_READOOB
;
634 } else if (column
< 256) {
635 /* First 256 bytes --> READ0 */
636 readcmd
= NAND_CMD_READ0
;
639 readcmd
= NAND_CMD_READ1
;
641 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
642 ctrl
&= ~NAND_CTRL_CHANGE
;
644 chip
->cmd_ctrl(mtd
, command
, ctrl
);
646 /* Address cycle, when necessary */
647 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
648 /* Serially input address */
650 /* Adjust columns for 16 bit buswidth */
651 if (chip
->options
& NAND_BUSWIDTH_16
&&
652 !nand_opcode_8bits(command
))
654 chip
->cmd_ctrl(mtd
, column
, ctrl
);
655 ctrl
&= ~NAND_CTRL_CHANGE
;
657 if (page_addr
!= -1) {
658 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
659 ctrl
&= ~NAND_CTRL_CHANGE
;
660 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
661 /* One more address cycle for devices > 32MiB */
662 if (chip
->chipsize
> (32 << 20))
663 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
665 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
668 * Program and erase have their own busy handlers status and sequential
673 case NAND_CMD_PAGEPROG
:
674 case NAND_CMD_ERASE1
:
675 case NAND_CMD_ERASE2
:
677 case NAND_CMD_STATUS
:
683 udelay(chip
->chip_delay
);
684 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
685 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
687 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
688 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
689 nand_wait_status_ready(mtd
, 250);
692 /* This applies to read commands */
695 * If we don't have access to the busy pin, we apply the given
698 if (!chip
->dev_ready
) {
699 udelay(chip
->chip_delay
);
704 * Apply this short delay always to ensure that we do wait tWB in
705 * any case on any machine.
709 nand_wait_ready(mtd
);
713 * nand_command_lp - [DEFAULT] Send command to NAND large page device
714 * @mtd: MTD device structure
715 * @command: the command to be sent
716 * @column: the column address for this command, -1 if none
717 * @page_addr: the page address for this command, -1 if none
719 * Send command to NAND device. This is the version for the new large page
720 * devices. We don't have the separate regions as we have in the small page
721 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
723 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
724 int column
, int page_addr
)
726 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
728 /* Emulate NAND_CMD_READOOB */
729 if (command
== NAND_CMD_READOOB
) {
730 column
+= mtd
->writesize
;
731 command
= NAND_CMD_READ0
;
734 /* Command latch cycle */
735 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
737 if (column
!= -1 || page_addr
!= -1) {
738 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
740 /* Serially input address */
742 /* Adjust columns for 16 bit buswidth */
743 if (chip
->options
& NAND_BUSWIDTH_16
&&
744 !nand_opcode_8bits(command
))
746 chip
->cmd_ctrl(mtd
, column
, ctrl
);
747 ctrl
&= ~NAND_CTRL_CHANGE
;
749 /* Only output a single addr cycle for 8bits opcodes. */
750 if (!nand_opcode_8bits(command
))
751 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
753 if (page_addr
!= -1) {
754 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
755 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
756 NAND_NCE
| NAND_ALE
);
757 /* One more address cycle for devices > 128MiB */
758 if (chip
->chipsize
> (128 << 20))
759 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
760 NAND_NCE
| NAND_ALE
);
763 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
766 * Program and erase have their own busy handlers status, sequential
767 * in and status need no delay.
771 case NAND_CMD_CACHEDPROG
:
772 case NAND_CMD_PAGEPROG
:
773 case NAND_CMD_ERASE1
:
774 case NAND_CMD_ERASE2
:
777 case NAND_CMD_STATUS
:
783 udelay(chip
->chip_delay
);
784 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
785 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
786 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
787 NAND_NCE
| NAND_CTRL_CHANGE
);
788 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
789 nand_wait_status_ready(mtd
, 250);
792 case NAND_CMD_RNDOUT
:
793 /* No ready / busy check necessary */
794 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
795 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
796 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
797 NAND_NCE
| NAND_CTRL_CHANGE
);
801 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
802 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
803 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
804 NAND_NCE
| NAND_CTRL_CHANGE
);
806 /* This applies to read commands */
809 * If we don't have access to the busy pin, we apply the given
812 if (!chip
->dev_ready
) {
813 udelay(chip
->chip_delay
);
819 * Apply this short delay always to ensure that we do wait tWB in
820 * any case on any machine.
824 nand_wait_ready(mtd
);
828 * panic_nand_get_device - [GENERIC] Get chip for selected access
829 * @chip: the nand chip descriptor
830 * @mtd: MTD device structure
831 * @new_state: the state which is requested
833 * Used when in panic, no locks are taken.
835 static void panic_nand_get_device(struct nand_chip
*chip
,
836 struct mtd_info
*mtd
, int new_state
)
838 /* Hardware controller shared among independent devices */
839 chip
->controller
->active
= chip
;
840 chip
->state
= new_state
;
844 * nand_get_device - [GENERIC] Get chip for selected access
845 * @mtd: MTD device structure
846 * @new_state: the state which is requested
848 * Get the device and lock it for exclusive access
851 nand_get_device(struct mtd_info
*mtd
, int new_state
)
853 struct nand_chip
*chip
= mtd_to_nand(mtd
);
854 spinlock_t
*lock
= &chip
->controller
->lock
;
855 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
856 DECLARE_WAITQUEUE(wait
, current
);
860 /* Hardware controller shared among independent devices */
861 if (!chip
->controller
->active
)
862 chip
->controller
->active
= chip
;
864 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
865 chip
->state
= new_state
;
869 if (new_state
== FL_PM_SUSPENDED
) {
870 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
871 chip
->state
= FL_PM_SUSPENDED
;
876 set_current_state(TASK_UNINTERRUPTIBLE
);
877 add_wait_queue(wq
, &wait
);
880 remove_wait_queue(wq
, &wait
);
885 * panic_nand_wait - [GENERIC] wait until the command is done
886 * @mtd: MTD device structure
887 * @chip: NAND chip structure
890 * Wait for command done. This is a helper function for nand_wait used when
891 * we are in interrupt context. May happen when in panic and trying to write
892 * an oops through mtdoops.
894 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
898 for (i
= 0; i
< timeo
; i
++) {
899 if (chip
->dev_ready
) {
900 if (chip
->dev_ready(mtd
))
903 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
911 * nand_wait - [DEFAULT] wait until the command is done
912 * @mtd: MTD device structure
913 * @chip: NAND chip structure
915 * Wait for command done. This applies to erase and program only.
917 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
921 unsigned long timeo
= 400;
924 * Apply this short delay always to ensure that we do wait tWB in any
925 * case on any machine.
929 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
931 if (in_interrupt() || oops_in_progress
)
932 panic_nand_wait(mtd
, chip
, timeo
);
934 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
936 if (chip
->dev_ready
) {
937 if (chip
->dev_ready(mtd
))
940 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
944 } while (time_before(jiffies
, timeo
));
947 status
= (int)chip
->read_byte(mtd
);
948 /* This can happen if in case of timeout or buggy dev_ready */
949 WARN_ON(!(status
& NAND_STATUS_READY
));
954 * nand_reset_data_interface - Reset data interface and timings
955 * @chip: The NAND chip
957 * Reset the Data interface and timings to ONFI mode 0.
959 * Returns 0 for success or negative error code otherwise.
961 static int nand_reset_data_interface(struct nand_chip
*chip
)
963 struct mtd_info
*mtd
= nand_to_mtd(chip
);
964 const struct nand_data_interface
*conf
;
967 if (!chip
->setup_data_interface
)
971 * The ONFI specification says:
973 * To transition from NV-DDR or NV-DDR2 to the SDR data
974 * interface, the host shall use the Reset (FFh) command
975 * using SDR timing mode 0. A device in any timing mode is
976 * required to recognize Reset (FFh) command issued in SDR
980 * Configure the data interface in SDR mode and set the
981 * timings to timing mode 0.
984 conf
= nand_get_default_data_interface();
985 ret
= chip
->setup_data_interface(mtd
, conf
, false);
987 pr_err("Failed to configure data interface to SDR timing mode 0\n");
993 * nand_setup_data_interface - Setup the best data interface and timings
994 * @chip: The NAND chip
996 * Find and configure the best data interface and NAND timings supported by
997 * the chip and the driver.
998 * First tries to retrieve supported timing modes from ONFI information,
999 * and if the NAND chip does not support ONFI, relies on the
1000 * ->onfi_timing_mode_default specified in the nand_ids table.
1002 * Returns 0 for success or negative error code otherwise.
1004 static int nand_setup_data_interface(struct nand_chip
*chip
)
1006 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1009 if (!chip
->setup_data_interface
|| !chip
->data_interface
)
1013 * Ensure the timing mode has been changed on the chip side
1014 * before changing timings on the controller side.
1016 if (chip
->onfi_version
) {
1017 u8 tmode_param
[ONFI_SUBFEATURE_PARAM_LEN
] = {
1018 chip
->onfi_timing_mode_default
,
1021 ret
= chip
->onfi_set_features(mtd
, chip
,
1022 ONFI_FEATURE_ADDR_TIMING_MODE
,
1028 ret
= chip
->setup_data_interface(mtd
, chip
->data_interface
, false);
1034 * nand_init_data_interface - find the best data interface and timings
1035 * @chip: The NAND chip
1037 * Find the best data interface and NAND timings supported by the chip
1039 * First tries to retrieve supported timing modes from ONFI information,
1040 * and if the NAND chip does not support ONFI, relies on the
1041 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1042 * function nand_chip->data_interface is initialized with the best timing mode
1045 * Returns 0 for success or negative error code otherwise.
1047 static int nand_init_data_interface(struct nand_chip
*chip
)
1049 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1050 int modes
, mode
, ret
;
1052 if (!chip
->setup_data_interface
)
1056 * First try to identify the best timings from ONFI parameters and
1057 * if the NAND does not support ONFI, fallback to the default ONFI
1060 modes
= onfi_get_async_timing_mode(chip
);
1061 if (modes
== ONFI_TIMING_MODE_UNKNOWN
) {
1062 if (!chip
->onfi_timing_mode_default
)
1065 modes
= GENMASK(chip
->onfi_timing_mode_default
, 0);
1068 chip
->data_interface
= kzalloc(sizeof(*chip
->data_interface
),
1070 if (!chip
->data_interface
)
1073 for (mode
= fls(modes
) - 1; mode
>= 0; mode
--) {
1074 ret
= onfi_init_data_interface(chip
, chip
->data_interface
,
1075 NAND_SDR_IFACE
, mode
);
1079 ret
= chip
->setup_data_interface(mtd
, chip
->data_interface
,
1082 chip
->onfi_timing_mode_default
= mode
;
1090 static void nand_release_data_interface(struct nand_chip
*chip
)
1092 kfree(chip
->data_interface
);
1096 * nand_reset - Reset and initialize a NAND device
1097 * @chip: The NAND chip
1099 * Returns 0 for success or negative error code otherwise
1101 int nand_reset(struct nand_chip
*chip
)
1103 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1106 ret
= nand_reset_data_interface(chip
);
1110 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1112 ret
= nand_setup_data_interface(chip
);
1120 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1122 * @ofs: offset to start unlock from
1123 * @len: length to unlock
1124 * @invert: when = 0, unlock the range of blocks within the lower and
1125 * upper boundary address
1126 * when = 1, unlock the range of blocks outside the boundaries
1127 * of the lower and upper boundary address
1129 * Returs unlock status.
1131 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
1132 uint64_t len
, int invert
)
1136 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1138 /* Submit address of first page to unlock */
1139 page
= ofs
>> chip
->page_shift
;
1140 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
1142 /* Submit address of last page to unlock */
1143 page
= (ofs
+ len
) >> chip
->page_shift
;
1144 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
1145 (page
| invert
) & chip
->pagemask
);
1147 /* Call wait ready function */
1148 status
= chip
->waitfunc(mtd
, chip
);
1149 /* See if device thinks it succeeded */
1150 if (status
& NAND_STATUS_FAIL
) {
1151 pr_debug("%s: error status = 0x%08x\n",
1160 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1162 * @ofs: offset to start unlock from
1163 * @len: length to unlock
1165 * Returns unlock status.
1167 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1171 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1173 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1174 __func__
, (unsigned long long)ofs
, len
);
1176 if (check_offs_len(mtd
, ofs
, len
))
1179 /* Align to last block address if size addresses end of the device */
1180 if (ofs
+ len
== mtd
->size
)
1181 len
-= mtd
->erasesize
;
1183 nand_get_device(mtd
, FL_UNLOCKING
);
1185 /* Shift to get chip number */
1186 chipnr
= ofs
>> chip
->chip_shift
;
1188 chip
->select_chip(mtd
, chipnr
);
1192 * If we want to check the WP through READ STATUS and check the bit 7
1193 * we must reset the chip
1194 * some operation can also clear the bit 7 of status register
1195 * eg. erase/program a locked block
1199 /* Check, if it is write protected */
1200 if (nand_check_wp(mtd
)) {
1201 pr_debug("%s: device is write protected!\n",
1207 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
1210 chip
->select_chip(mtd
, -1);
1211 nand_release_device(mtd
);
1215 EXPORT_SYMBOL(nand_unlock
);
1218 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1220 * @ofs: offset to start unlock from
1221 * @len: length to unlock
1223 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1224 * have this feature, but it allows only to lock all blocks, not for specified
1225 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1228 * Returns lock status.
1230 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1233 int chipnr
, status
, page
;
1234 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1236 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1237 __func__
, (unsigned long long)ofs
, len
);
1239 if (check_offs_len(mtd
, ofs
, len
))
1242 nand_get_device(mtd
, FL_LOCKING
);
1244 /* Shift to get chip number */
1245 chipnr
= ofs
>> chip
->chip_shift
;
1247 chip
->select_chip(mtd
, chipnr
);
1251 * If we want to check the WP through READ STATUS and check the bit 7
1252 * we must reset the chip
1253 * some operation can also clear the bit 7 of status register
1254 * eg. erase/program a locked block
1258 /* Check, if it is write protected */
1259 if (nand_check_wp(mtd
)) {
1260 pr_debug("%s: device is write protected!\n",
1262 status
= MTD_ERASE_FAILED
;
1267 /* Submit address of first page to lock */
1268 page
= ofs
>> chip
->page_shift
;
1269 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1271 /* Call wait ready function */
1272 status
= chip
->waitfunc(mtd
, chip
);
1273 /* See if device thinks it succeeded */
1274 if (status
& NAND_STATUS_FAIL
) {
1275 pr_debug("%s: error status = 0x%08x\n",
1281 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1284 chip
->select_chip(mtd
, -1);
1285 nand_release_device(mtd
);
1289 EXPORT_SYMBOL(nand_lock
);
1292 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1293 * @buf: buffer to test
1294 * @len: buffer length
1295 * @bitflips_threshold: maximum number of bitflips
1297 * Check if a buffer contains only 0xff, which means the underlying region
1298 * has been erased and is ready to be programmed.
1299 * The bitflips_threshold specify the maximum number of bitflips before
1300 * considering the region is not erased.
1301 * Note: The logic of this function has been extracted from the memweight
1302 * implementation, except that nand_check_erased_buf function exit before
1303 * testing the whole buffer if the number of bitflips exceed the
1304 * bitflips_threshold value.
1306 * Returns a positive number of bitflips less than or equal to
1307 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1310 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1312 const unsigned char *bitmap
= buf
;
1316 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1318 weight
= hweight8(*bitmap
);
1319 bitflips
+= BITS_PER_BYTE
- weight
;
1320 if (unlikely(bitflips
> bitflips_threshold
))
1324 for (; len
>= sizeof(long);
1325 len
-= sizeof(long), bitmap
+= sizeof(long)) {
1326 weight
= hweight_long(*((unsigned long *)bitmap
));
1327 bitflips
+= BITS_PER_LONG
- weight
;
1328 if (unlikely(bitflips
> bitflips_threshold
))
1332 for (; len
> 0; len
--, bitmap
++) {
1333 weight
= hweight8(*bitmap
);
1334 bitflips
+= BITS_PER_BYTE
- weight
;
1335 if (unlikely(bitflips
> bitflips_threshold
))
1343 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1345 * @data: data buffer to test
1346 * @datalen: data length
1348 * @ecclen: ECC length
1349 * @extraoob: extra OOB buffer
1350 * @extraooblen: extra OOB length
1351 * @bitflips_threshold: maximum number of bitflips
1353 * Check if a data buffer and its associated ECC and OOB data contains only
1354 * 0xff pattern, which means the underlying region has been erased and is
1355 * ready to be programmed.
1356 * The bitflips_threshold specify the maximum number of bitflips before
1357 * considering the region as not erased.
1360 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1361 * different from the NAND page size. When fixing bitflips, ECC engines will
1362 * report the number of errors per chunk, and the NAND core infrastructure
1363 * expect you to return the maximum number of bitflips for the whole page.
1364 * This is why you should always use this function on a single chunk and
1365 * not on the whole page. After checking each chunk you should update your
1366 * max_bitflips value accordingly.
1367 * 2/ When checking for bitflips in erased pages you should not only check
1368 * the payload data but also their associated ECC data, because a user might
1369 * have programmed almost all bits to 1 but a few. In this case, we
1370 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1372 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1373 * data are protected by the ECC engine.
1374 * It could also be used if you support subpages and want to attach some
1375 * extra OOB data to an ECC chunk.
1377 * Returns a positive number of bitflips less than or equal to
1378 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1379 * threshold. In case of success, the passed buffers are filled with 0xff.
1381 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1382 void *ecc
, int ecclen
,
1383 void *extraoob
, int extraooblen
,
1384 int bitflips_threshold
)
1386 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1388 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1389 bitflips_threshold
);
1390 if (data_bitflips
< 0)
1391 return data_bitflips
;
1393 bitflips_threshold
-= data_bitflips
;
1395 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1396 if (ecc_bitflips
< 0)
1397 return ecc_bitflips
;
1399 bitflips_threshold
-= ecc_bitflips
;
1401 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1402 bitflips_threshold
);
1403 if (extraoob_bitflips
< 0)
1404 return extraoob_bitflips
;
1407 memset(data
, 0xff, datalen
);
1410 memset(ecc
, 0xff, ecclen
);
1412 if (extraoob_bitflips
)
1413 memset(extraoob
, 0xff, extraooblen
);
1415 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1417 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1420 * nand_read_page_raw - [INTERN] read raw page data without ecc
1421 * @mtd: mtd info structure
1422 * @chip: nand chip info structure
1423 * @buf: buffer to store read data
1424 * @oob_required: caller requires OOB data read to chip->oob_poi
1425 * @page: page number to read
1427 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1429 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1430 uint8_t *buf
, int oob_required
, int page
)
1432 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1434 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1439 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1440 * @mtd: mtd info structure
1441 * @chip: nand chip info structure
1442 * @buf: buffer to store read data
1443 * @oob_required: caller requires OOB data read to chip->oob_poi
1444 * @page: page number to read
1446 * We need a special oob layout and handling even when OOB isn't used.
1448 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1449 struct nand_chip
*chip
, uint8_t *buf
,
1450 int oob_required
, int page
)
1452 int eccsize
= chip
->ecc
.size
;
1453 int eccbytes
= chip
->ecc
.bytes
;
1454 uint8_t *oob
= chip
->oob_poi
;
1457 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1458 chip
->read_buf(mtd
, buf
, eccsize
);
1461 if (chip
->ecc
.prepad
) {
1462 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1463 oob
+= chip
->ecc
.prepad
;
1466 chip
->read_buf(mtd
, oob
, eccbytes
);
1469 if (chip
->ecc
.postpad
) {
1470 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1471 oob
+= chip
->ecc
.postpad
;
1475 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1477 chip
->read_buf(mtd
, oob
, size
);
1483 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1484 * @mtd: mtd info structure
1485 * @chip: nand chip info structure
1486 * @buf: buffer to store read data
1487 * @oob_required: caller requires OOB data read to chip->oob_poi
1488 * @page: page number to read
1490 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1491 uint8_t *buf
, int oob_required
, int page
)
1493 int i
, eccsize
= chip
->ecc
.size
, ret
;
1494 int eccbytes
= chip
->ecc
.bytes
;
1495 int eccsteps
= chip
->ecc
.steps
;
1497 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1498 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1499 unsigned int max_bitflips
= 0;
1501 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1503 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1504 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1506 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1511 eccsteps
= chip
->ecc
.steps
;
1514 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1517 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1519 mtd
->ecc_stats
.failed
++;
1521 mtd
->ecc_stats
.corrected
+= stat
;
1522 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1525 return max_bitflips
;
1529 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1530 * @mtd: mtd info structure
1531 * @chip: nand chip info structure
1532 * @data_offs: offset of requested data within the page
1533 * @readlen: data length
1534 * @bufpoi: buffer to store read data
1535 * @page: page number to read
1537 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1538 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1541 int start_step
, end_step
, num_steps
, ret
;
1543 int data_col_addr
, i
, gaps
= 0;
1544 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1545 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1546 int index
, section
= 0;
1547 unsigned int max_bitflips
= 0;
1548 struct mtd_oob_region oobregion
= { };
1550 /* Column address within the page aligned to ECC size (256bytes) */
1551 start_step
= data_offs
/ chip
->ecc
.size
;
1552 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1553 num_steps
= end_step
- start_step
+ 1;
1554 index
= start_step
* chip
->ecc
.bytes
;
1556 /* Data size aligned to ECC ecc.size */
1557 datafrag_len
= num_steps
* chip
->ecc
.size
;
1558 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1560 data_col_addr
= start_step
* chip
->ecc
.size
;
1561 /* If we read not a page aligned data */
1562 if (data_col_addr
!= 0)
1563 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1565 p
= bufpoi
+ data_col_addr
;
1566 chip
->read_buf(mtd
, p
, datafrag_len
);
1569 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1570 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1573 * The performance is faster if we position offsets according to
1574 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1576 ret
= mtd_ooblayout_find_eccregion(mtd
, index
, §ion
, &oobregion
);
1580 if (oobregion
.length
< eccfrag_len
)
1584 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1585 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1588 * Send the command to read the particular ECC bytes take care
1589 * about buswidth alignment in read_buf.
1591 aligned_pos
= oobregion
.offset
& ~(busw
- 1);
1592 aligned_len
= eccfrag_len
;
1593 if (oobregion
.offset
& (busw
- 1))
1595 if ((oobregion
.offset
+ (num_steps
* chip
->ecc
.bytes
)) &
1599 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1600 mtd
->writesize
+ aligned_pos
, -1);
1601 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1604 ret
= mtd_ooblayout_get_eccbytes(mtd
, chip
->buffers
->ecccode
,
1605 chip
->oob_poi
, index
, eccfrag_len
);
1609 p
= bufpoi
+ data_col_addr
;
1610 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1613 stat
= chip
->ecc
.correct(mtd
, p
,
1614 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1615 if (stat
== -EBADMSG
&&
1616 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1617 /* check for empty pages with bitflips */
1618 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1619 &chip
->buffers
->ecccode
[i
],
1622 chip
->ecc
.strength
);
1626 mtd
->ecc_stats
.failed
++;
1628 mtd
->ecc_stats
.corrected
+= stat
;
1629 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1632 return max_bitflips
;
1636 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1637 * @mtd: mtd info structure
1638 * @chip: nand chip info structure
1639 * @buf: buffer to store read data
1640 * @oob_required: caller requires OOB data read to chip->oob_poi
1641 * @page: page number to read
1643 * Not for syndrome calculating ECC controllers which need a special oob layout.
1645 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1646 uint8_t *buf
, int oob_required
, int page
)
1648 int i
, eccsize
= chip
->ecc
.size
, ret
;
1649 int eccbytes
= chip
->ecc
.bytes
;
1650 int eccsteps
= chip
->ecc
.steps
;
1652 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1653 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1654 unsigned int max_bitflips
= 0;
1656 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1657 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1658 chip
->read_buf(mtd
, p
, eccsize
);
1659 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1661 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1663 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1668 eccsteps
= chip
->ecc
.steps
;
1671 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1674 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1675 if (stat
== -EBADMSG
&&
1676 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1677 /* check for empty pages with bitflips */
1678 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1679 &ecc_code
[i
], eccbytes
,
1681 chip
->ecc
.strength
);
1685 mtd
->ecc_stats
.failed
++;
1687 mtd
->ecc_stats
.corrected
+= stat
;
1688 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1691 return max_bitflips
;
1695 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1696 * @mtd: mtd info structure
1697 * @chip: nand chip info structure
1698 * @buf: buffer to store read data
1699 * @oob_required: caller requires OOB data read to chip->oob_poi
1700 * @page: page number to read
1702 * Hardware ECC for large page chips, require OOB to be read first. For this
1703 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1704 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1705 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1706 * the data area, by overwriting the NAND manufacturer bad block markings.
1708 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1709 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1711 int i
, eccsize
= chip
->ecc
.size
, ret
;
1712 int eccbytes
= chip
->ecc
.bytes
;
1713 int eccsteps
= chip
->ecc
.steps
;
1715 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1716 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1717 unsigned int max_bitflips
= 0;
1719 /* Read the OOB area first */
1720 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1721 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1722 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1724 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1729 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1732 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1733 chip
->read_buf(mtd
, p
, eccsize
);
1734 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1736 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1737 if (stat
== -EBADMSG
&&
1738 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1739 /* check for empty pages with bitflips */
1740 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1741 &ecc_code
[i
], eccbytes
,
1743 chip
->ecc
.strength
);
1747 mtd
->ecc_stats
.failed
++;
1749 mtd
->ecc_stats
.corrected
+= stat
;
1750 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1753 return max_bitflips
;
1757 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1758 * @mtd: mtd info structure
1759 * @chip: nand chip info structure
1760 * @buf: buffer to store read data
1761 * @oob_required: caller requires OOB data read to chip->oob_poi
1762 * @page: page number to read
1764 * The hw generator calculates the error syndrome automatically. Therefore we
1765 * need a special oob layout and handling.
1767 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1768 uint8_t *buf
, int oob_required
, int page
)
1770 int i
, eccsize
= chip
->ecc
.size
;
1771 int eccbytes
= chip
->ecc
.bytes
;
1772 int eccsteps
= chip
->ecc
.steps
;
1773 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1775 uint8_t *oob
= chip
->oob_poi
;
1776 unsigned int max_bitflips
= 0;
1778 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1781 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1782 chip
->read_buf(mtd
, p
, eccsize
);
1784 if (chip
->ecc
.prepad
) {
1785 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1786 oob
+= chip
->ecc
.prepad
;
1789 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1790 chip
->read_buf(mtd
, oob
, eccbytes
);
1791 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1795 if (chip
->ecc
.postpad
) {
1796 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1797 oob
+= chip
->ecc
.postpad
;
1800 if (stat
== -EBADMSG
&&
1801 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1802 /* check for empty pages with bitflips */
1803 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1807 chip
->ecc
.strength
);
1811 mtd
->ecc_stats
.failed
++;
1813 mtd
->ecc_stats
.corrected
+= stat
;
1814 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1818 /* Calculate remaining oob bytes */
1819 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1821 chip
->read_buf(mtd
, oob
, i
);
1823 return max_bitflips
;
1827 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1828 * @mtd: mtd info structure
1829 * @oob: oob destination address
1830 * @ops: oob ops structure
1831 * @len: size of oob to transfer
1833 static uint8_t *nand_transfer_oob(struct mtd_info
*mtd
, uint8_t *oob
,
1834 struct mtd_oob_ops
*ops
, size_t len
)
1836 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1839 switch (ops
->mode
) {
1841 case MTD_OPS_PLACE_OOB
:
1843 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1846 case MTD_OPS_AUTO_OOB
:
1847 ret
= mtd_ooblayout_get_databytes(mtd
, oob
, chip
->oob_poi
,
1859 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1860 * @mtd: MTD device structure
1861 * @retry_mode: the retry mode to use
1863 * Some vendors supply a special command to shift the Vt threshold, to be used
1864 * when there are too many bitflips in a page (i.e., ECC error). After setting
1865 * a new threshold, the host should retry reading the page.
1867 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1869 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1871 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1873 if (retry_mode
>= chip
->read_retries
)
1876 if (!chip
->setup_read_retry
)
1879 return chip
->setup_read_retry(mtd
, retry_mode
);
1883 * nand_do_read_ops - [INTERN] Read data with ECC
1884 * @mtd: MTD device structure
1885 * @from: offset to read from
1886 * @ops: oob ops structure
1888 * Internal function. Called with chip held.
1890 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1891 struct mtd_oob_ops
*ops
)
1893 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1894 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1896 uint32_t readlen
= ops
->len
;
1897 uint32_t oobreadlen
= ops
->ooblen
;
1898 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1900 uint8_t *bufpoi
, *oob
, *buf
;
1902 unsigned int max_bitflips
= 0;
1904 bool ecc_fail
= false;
1906 chipnr
= (int)(from
>> chip
->chip_shift
);
1907 chip
->select_chip(mtd
, chipnr
);
1909 realpage
= (int)(from
>> chip
->page_shift
);
1910 page
= realpage
& chip
->pagemask
;
1912 col
= (int)(from
& (mtd
->writesize
- 1));
1916 oob_required
= oob
? 1 : 0;
1919 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1921 bytes
= min(mtd
->writesize
- col
, readlen
);
1922 aligned
= (bytes
== mtd
->writesize
);
1926 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
1927 use_bufpoi
= !virt_addr_valid(buf
);
1931 /* Is the current page in the buffer? */
1932 if (realpage
!= chip
->pagebuf
|| oob
) {
1933 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1935 if (use_bufpoi
&& aligned
)
1936 pr_debug("%s: using read bounce buffer for buf@%p\n",
1940 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1943 * Now read the page into the buffer. Absent an error,
1944 * the read methods return max bitflips per ecc step.
1946 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1947 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1950 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1952 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1956 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1957 oob_required
, page
);
1960 /* Invalidate page cache */
1965 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1967 /* Transfer not aligned data */
1969 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1970 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1971 (ops
->mode
!= MTD_OPS_RAW
)) {
1972 chip
->pagebuf
= realpage
;
1973 chip
->pagebuf_bitflips
= ret
;
1975 /* Invalidate page cache */
1978 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1981 if (unlikely(oob
)) {
1982 int toread
= min(oobreadlen
, max_oobsize
);
1985 oob
= nand_transfer_oob(mtd
,
1987 oobreadlen
-= toread
;
1991 if (chip
->options
& NAND_NEED_READRDY
) {
1992 /* Apply delay or wait for ready/busy pin */
1993 if (!chip
->dev_ready
)
1994 udelay(chip
->chip_delay
);
1996 nand_wait_ready(mtd
);
1999 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
2000 if (retry_mode
+ 1 < chip
->read_retries
) {
2002 ret
= nand_setup_read_retry(mtd
,
2007 /* Reset failures; retry */
2008 mtd
->ecc_stats
.failed
= ecc_failures
;
2011 /* No more retry modes; real failure */
2018 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
2020 max_bitflips
= max_t(unsigned int, max_bitflips
,
2021 chip
->pagebuf_bitflips
);
2026 /* Reset to retry mode 0 */
2028 ret
= nand_setup_read_retry(mtd
, 0);
2037 /* For subsequent reads align to page boundary */
2039 /* Increment page address */
2042 page
= realpage
& chip
->pagemask
;
2043 /* Check, if we cross a chip boundary */
2046 chip
->select_chip(mtd
, -1);
2047 chip
->select_chip(mtd
, chipnr
);
2050 chip
->select_chip(mtd
, -1);
2052 ops
->retlen
= ops
->len
- (size_t) readlen
;
2054 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
2062 return max_bitflips
;
2066 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
2067 * @mtd: MTD device structure
2068 * @from: offset to read from
2069 * @len: number of bytes to read
2070 * @retlen: pointer to variable to store the number of read bytes
2071 * @buf: the databuffer to put data
2073 * Get hold of the chip and call nand_do_read.
2075 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
2076 size_t *retlen
, uint8_t *buf
)
2078 struct mtd_oob_ops ops
;
2081 nand_get_device(mtd
, FL_READING
);
2082 memset(&ops
, 0, sizeof(ops
));
2085 ops
.mode
= MTD_OPS_PLACE_OOB
;
2086 ret
= nand_do_read_ops(mtd
, from
, &ops
);
2087 *retlen
= ops
.retlen
;
2088 nand_release_device(mtd
);
2093 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
2094 * @mtd: mtd info structure
2095 * @chip: nand chip info structure
2096 * @page: page number to read
2098 int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
2100 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
2101 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2104 EXPORT_SYMBOL(nand_read_oob_std
);
2107 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
2109 * @mtd: mtd info structure
2110 * @chip: nand chip info structure
2111 * @page: page number to read
2113 int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2116 int length
= mtd
->oobsize
;
2117 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2118 int eccsize
= chip
->ecc
.size
;
2119 uint8_t *bufpoi
= chip
->oob_poi
;
2120 int i
, toread
, sndrnd
= 0, pos
;
2122 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
2123 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
2125 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2126 if (mtd
->writesize
> 512)
2127 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
2129 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
2132 toread
= min_t(int, length
, chunk
);
2133 chip
->read_buf(mtd
, bufpoi
, toread
);
2138 chip
->read_buf(mtd
, bufpoi
, length
);
2142 EXPORT_SYMBOL(nand_read_oob_syndrome
);
2145 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
2146 * @mtd: mtd info structure
2147 * @chip: nand chip info structure
2148 * @page: page number to write
2150 int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
2153 const uint8_t *buf
= chip
->oob_poi
;
2154 int length
= mtd
->oobsize
;
2156 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
2157 chip
->write_buf(mtd
, buf
, length
);
2158 /* Send command to program the OOB data */
2159 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2161 status
= chip
->waitfunc(mtd
, chip
);
2163 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2165 EXPORT_SYMBOL(nand_write_oob_std
);
2168 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
2169 * with syndrome - only for large page flash
2170 * @mtd: mtd info structure
2171 * @chip: nand chip info structure
2172 * @page: page number to write
2174 int nand_write_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2177 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2178 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
2179 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
2180 const uint8_t *bufpoi
= chip
->oob_poi
;
2183 * data-ecc-data-ecc ... ecc-oob
2185 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2187 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
2188 pos
= steps
* (eccsize
+ chunk
);
2193 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
2194 for (i
= 0; i
< steps
; i
++) {
2196 if (mtd
->writesize
<= 512) {
2197 uint32_t fill
= 0xFFFFFFFF;
2201 int num
= min_t(int, len
, 4);
2202 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2207 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2208 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2212 len
= min_t(int, length
, chunk
);
2213 chip
->write_buf(mtd
, bufpoi
, len
);
2218 chip
->write_buf(mtd
, bufpoi
, length
);
2220 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2221 status
= chip
->waitfunc(mtd
, chip
);
2223 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2225 EXPORT_SYMBOL(nand_write_oob_syndrome
);
2228 * nand_do_read_oob - [INTERN] NAND read out-of-band
2229 * @mtd: MTD device structure
2230 * @from: offset to read from
2231 * @ops: oob operations description structure
2233 * NAND read out-of-band data from the spare area.
2235 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2236 struct mtd_oob_ops
*ops
)
2238 int page
, realpage
, chipnr
;
2239 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2240 struct mtd_ecc_stats stats
;
2241 int readlen
= ops
->ooblen
;
2243 uint8_t *buf
= ops
->oobbuf
;
2246 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2247 __func__
, (unsigned long long)from
, readlen
);
2249 stats
= mtd
->ecc_stats
;
2251 len
= mtd_oobavail(mtd
, ops
);
2253 if (unlikely(ops
->ooboffs
>= len
)) {
2254 pr_debug("%s: attempt to start read outside oob\n",
2259 /* Do not allow reads past end of device */
2260 if (unlikely(from
>= mtd
->size
||
2261 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2262 (from
>> chip
->page_shift
)) * len
)) {
2263 pr_debug("%s: attempt to read beyond end of device\n",
2268 chipnr
= (int)(from
>> chip
->chip_shift
);
2269 chip
->select_chip(mtd
, chipnr
);
2271 /* Shift to get page */
2272 realpage
= (int)(from
>> chip
->page_shift
);
2273 page
= realpage
& chip
->pagemask
;
2276 if (ops
->mode
== MTD_OPS_RAW
)
2277 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2279 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2284 len
= min(len
, readlen
);
2285 buf
= nand_transfer_oob(mtd
, buf
, ops
, len
);
2287 if (chip
->options
& NAND_NEED_READRDY
) {
2288 /* Apply delay or wait for ready/busy pin */
2289 if (!chip
->dev_ready
)
2290 udelay(chip
->chip_delay
);
2292 nand_wait_ready(mtd
);
2299 /* Increment page address */
2302 page
= realpage
& chip
->pagemask
;
2303 /* Check, if we cross a chip boundary */
2306 chip
->select_chip(mtd
, -1);
2307 chip
->select_chip(mtd
, chipnr
);
2310 chip
->select_chip(mtd
, -1);
2312 ops
->oobretlen
= ops
->ooblen
- readlen
;
2317 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2320 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2324 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2325 * @mtd: MTD device structure
2326 * @from: offset to read from
2327 * @ops: oob operation description structure
2329 * NAND read data and/or out-of-band data.
2331 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2332 struct mtd_oob_ops
*ops
)
2338 /* Do not allow reads past end of device */
2339 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2340 pr_debug("%s: attempt to read beyond end of device\n",
2345 if (ops
->mode
!= MTD_OPS_PLACE_OOB
&&
2346 ops
->mode
!= MTD_OPS_AUTO_OOB
&&
2347 ops
->mode
!= MTD_OPS_RAW
)
2350 nand_get_device(mtd
, FL_READING
);
2353 ret
= nand_do_read_oob(mtd
, from
, ops
);
2355 ret
= nand_do_read_ops(mtd
, from
, ops
);
2357 nand_release_device(mtd
);
2363 * nand_write_page_raw - [INTERN] raw page write function
2364 * @mtd: mtd info structure
2365 * @chip: nand chip info structure
2367 * @oob_required: must write chip->oob_poi to OOB
2368 * @page: page number to write
2370 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2372 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2373 const uint8_t *buf
, int oob_required
, int page
)
2375 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2377 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2383 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2384 * @mtd: mtd info structure
2385 * @chip: nand chip info structure
2387 * @oob_required: must write chip->oob_poi to OOB
2388 * @page: page number to write
2390 * We need a special oob layout and handling even when ECC isn't checked.
2392 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2393 struct nand_chip
*chip
,
2394 const uint8_t *buf
, int oob_required
,
2397 int eccsize
= chip
->ecc
.size
;
2398 int eccbytes
= chip
->ecc
.bytes
;
2399 uint8_t *oob
= chip
->oob_poi
;
2402 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2403 chip
->write_buf(mtd
, buf
, eccsize
);
2406 if (chip
->ecc
.prepad
) {
2407 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2408 oob
+= chip
->ecc
.prepad
;
2411 chip
->write_buf(mtd
, oob
, eccbytes
);
2414 if (chip
->ecc
.postpad
) {
2415 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2416 oob
+= chip
->ecc
.postpad
;
2420 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2422 chip
->write_buf(mtd
, oob
, size
);
2427 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2428 * @mtd: mtd info structure
2429 * @chip: nand chip info structure
2431 * @oob_required: must write chip->oob_poi to OOB
2432 * @page: page number to write
2434 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2435 const uint8_t *buf
, int oob_required
,
2438 int i
, eccsize
= chip
->ecc
.size
, ret
;
2439 int eccbytes
= chip
->ecc
.bytes
;
2440 int eccsteps
= chip
->ecc
.steps
;
2441 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2442 const uint8_t *p
= buf
;
2444 /* Software ECC calculation */
2445 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2446 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2448 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2453 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2457 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2458 * @mtd: mtd info structure
2459 * @chip: nand chip info structure
2461 * @oob_required: must write chip->oob_poi to OOB
2462 * @page: page number to write
2464 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2465 const uint8_t *buf
, int oob_required
,
2468 int i
, eccsize
= chip
->ecc
.size
, ret
;
2469 int eccbytes
= chip
->ecc
.bytes
;
2470 int eccsteps
= chip
->ecc
.steps
;
2471 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2472 const uint8_t *p
= buf
;
2474 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2475 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2476 chip
->write_buf(mtd
, p
, eccsize
);
2477 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2480 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2485 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2492 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2493 * @mtd: mtd info structure
2494 * @chip: nand chip info structure
2495 * @offset: column address of subpage within the page
2496 * @data_len: data length
2498 * @oob_required: must write chip->oob_poi to OOB
2499 * @page: page number to write
2501 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2502 struct nand_chip
*chip
, uint32_t offset
,
2503 uint32_t data_len
, const uint8_t *buf
,
2504 int oob_required
, int page
)
2506 uint8_t *oob_buf
= chip
->oob_poi
;
2507 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2508 int ecc_size
= chip
->ecc
.size
;
2509 int ecc_bytes
= chip
->ecc
.bytes
;
2510 int ecc_steps
= chip
->ecc
.steps
;
2511 uint32_t start_step
= offset
/ ecc_size
;
2512 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2513 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2516 for (step
= 0; step
< ecc_steps
; step
++) {
2517 /* configure controller for WRITE access */
2518 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2520 /* write data (untouched subpages already masked by 0xFF) */
2521 chip
->write_buf(mtd
, buf
, ecc_size
);
2523 /* mask ECC of un-touched subpages by padding 0xFF */
2524 if ((step
< start_step
) || (step
> end_step
))
2525 memset(ecc_calc
, 0xff, ecc_bytes
);
2527 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2529 /* mask OOB of un-touched subpages by padding 0xFF */
2530 /* if oob_required, preserve OOB metadata of written subpage */
2531 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2532 memset(oob_buf
, 0xff, oob_bytes
);
2535 ecc_calc
+= ecc_bytes
;
2536 oob_buf
+= oob_bytes
;
2539 /* copy calculated ECC for whole page to chip->buffer->oob */
2540 /* this include masked-value(0xFF) for unwritten subpages */
2541 ecc_calc
= chip
->buffers
->ecccalc
;
2542 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2547 /* write OOB buffer to NAND device */
2548 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2555 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2556 * @mtd: mtd info structure
2557 * @chip: nand chip info structure
2559 * @oob_required: must write chip->oob_poi to OOB
2560 * @page: page number to write
2562 * The hw generator calculates the error syndrome automatically. Therefore we
2563 * need a special oob layout and handling.
2565 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2566 struct nand_chip
*chip
,
2567 const uint8_t *buf
, int oob_required
,
2570 int i
, eccsize
= chip
->ecc
.size
;
2571 int eccbytes
= chip
->ecc
.bytes
;
2572 int eccsteps
= chip
->ecc
.steps
;
2573 const uint8_t *p
= buf
;
2574 uint8_t *oob
= chip
->oob_poi
;
2576 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2578 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2579 chip
->write_buf(mtd
, p
, eccsize
);
2581 if (chip
->ecc
.prepad
) {
2582 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2583 oob
+= chip
->ecc
.prepad
;
2586 chip
->ecc
.calculate(mtd
, p
, oob
);
2587 chip
->write_buf(mtd
, oob
, eccbytes
);
2590 if (chip
->ecc
.postpad
) {
2591 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2592 oob
+= chip
->ecc
.postpad
;
2596 /* Calculate remaining oob bytes */
2597 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2599 chip
->write_buf(mtd
, oob
, i
);
2605 * nand_write_page - [REPLACEABLE] write one page
2606 * @mtd: MTD device structure
2607 * @chip: NAND chip descriptor
2608 * @offset: address offset within the page
2609 * @data_len: length of actual data to be written
2610 * @buf: the data to write
2611 * @oob_required: must write chip->oob_poi to OOB
2612 * @page: page number to write
2613 * @cached: cached programming
2614 * @raw: use _raw version of write_page
2616 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2617 uint32_t offset
, int data_len
, const uint8_t *buf
,
2618 int oob_required
, int page
, int cached
, int raw
)
2620 int status
, subpage
;
2622 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2623 chip
->ecc
.write_subpage
)
2624 subpage
= offset
|| (data_len
< mtd
->writesize
);
2628 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2631 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2632 oob_required
, page
);
2634 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2635 buf
, oob_required
, page
);
2637 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2644 * Cached progamming disabled for now. Not sure if it's worth the
2645 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2649 if (!cached
|| !NAND_HAS_CACHEPROG(chip
)) {
2651 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2652 status
= chip
->waitfunc(mtd
, chip
);
2654 * See if operation failed and additional status checks are
2657 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2658 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2661 if (status
& NAND_STATUS_FAIL
)
2664 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2665 status
= chip
->waitfunc(mtd
, chip
);
2672 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2673 * @mtd: MTD device structure
2674 * @oob: oob data buffer
2675 * @len: oob data write length
2676 * @ops: oob ops structure
2678 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2679 struct mtd_oob_ops
*ops
)
2681 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2685 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2686 * data from a previous OOB read.
2688 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2690 switch (ops
->mode
) {
2692 case MTD_OPS_PLACE_OOB
:
2694 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2697 case MTD_OPS_AUTO_OOB
:
2698 ret
= mtd_ooblayout_set_databytes(mtd
, oob
, chip
->oob_poi
,
2709 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2712 * nand_do_write_ops - [INTERN] NAND write with ECC
2713 * @mtd: MTD device structure
2714 * @to: offset to write to
2715 * @ops: oob operations description structure
2717 * NAND write with ECC.
2719 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2720 struct mtd_oob_ops
*ops
)
2722 int chipnr
, realpage
, page
, blockmask
, column
;
2723 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2724 uint32_t writelen
= ops
->len
;
2726 uint32_t oobwritelen
= ops
->ooblen
;
2727 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2729 uint8_t *oob
= ops
->oobbuf
;
2730 uint8_t *buf
= ops
->datbuf
;
2732 int oob_required
= oob
? 1 : 0;
2738 /* Reject writes, which are not page aligned */
2739 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2740 pr_notice("%s: attempt to write non page aligned data\n",
2745 column
= to
& (mtd
->writesize
- 1);
2747 chipnr
= (int)(to
>> chip
->chip_shift
);
2748 chip
->select_chip(mtd
, chipnr
);
2750 /* Check, if it is write protected */
2751 if (nand_check_wp(mtd
)) {
2756 realpage
= (int)(to
>> chip
->page_shift
);
2757 page
= realpage
& chip
->pagemask
;
2758 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2760 /* Invalidate the page cache, when we write to the cached page */
2761 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2762 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2765 /* Don't allow multipage oob writes with offset */
2766 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2772 int bytes
= mtd
->writesize
;
2773 int cached
= writelen
> bytes
&& page
!= blockmask
;
2774 uint8_t *wbuf
= buf
;
2776 int part_pagewr
= (column
|| writelen
< mtd
->writesize
);
2780 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2781 use_bufpoi
= !virt_addr_valid(buf
);
2785 /* Partial page write?, or need to use bounce buffer */
2787 pr_debug("%s: using write bounce buffer for buf@%p\n",
2791 bytes
= min_t(int, bytes
- column
, writelen
);
2793 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2794 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2795 wbuf
= chip
->buffers
->databuf
;
2798 if (unlikely(oob
)) {
2799 size_t len
= min(oobwritelen
, oobmaxlen
);
2800 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2803 /* We still need to erase leftover OOB data */
2804 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2806 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2807 oob_required
, page
, cached
,
2808 (ops
->mode
== MTD_OPS_RAW
));
2820 page
= realpage
& chip
->pagemask
;
2821 /* Check, if we cross a chip boundary */
2824 chip
->select_chip(mtd
, -1);
2825 chip
->select_chip(mtd
, chipnr
);
2829 ops
->retlen
= ops
->len
- writelen
;
2831 ops
->oobretlen
= ops
->ooblen
;
2834 chip
->select_chip(mtd
, -1);
2839 * panic_nand_write - [MTD Interface] NAND write with ECC
2840 * @mtd: MTD device structure
2841 * @to: offset to write to
2842 * @len: number of bytes to write
2843 * @retlen: pointer to variable to store the number of written bytes
2844 * @buf: the data to write
2846 * NAND write with ECC. Used when performing writes in interrupt context, this
2847 * may for example be called by mtdoops when writing an oops while in panic.
2849 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2850 size_t *retlen
, const uint8_t *buf
)
2852 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2853 struct mtd_oob_ops ops
;
2856 /* Wait for the device to get ready */
2857 panic_nand_wait(mtd
, chip
, 400);
2859 /* Grab the device */
2860 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2862 memset(&ops
, 0, sizeof(ops
));
2864 ops
.datbuf
= (uint8_t *)buf
;
2865 ops
.mode
= MTD_OPS_PLACE_OOB
;
2867 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2869 *retlen
= ops
.retlen
;
2874 * nand_write - [MTD Interface] NAND write with ECC
2875 * @mtd: MTD device structure
2876 * @to: offset to write to
2877 * @len: number of bytes to write
2878 * @retlen: pointer to variable to store the number of written bytes
2879 * @buf: the data to write
2881 * NAND write with ECC.
2883 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2884 size_t *retlen
, const uint8_t *buf
)
2886 struct mtd_oob_ops ops
;
2889 nand_get_device(mtd
, FL_WRITING
);
2890 memset(&ops
, 0, sizeof(ops
));
2892 ops
.datbuf
= (uint8_t *)buf
;
2893 ops
.mode
= MTD_OPS_PLACE_OOB
;
2894 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2895 *retlen
= ops
.retlen
;
2896 nand_release_device(mtd
);
2901 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2902 * @mtd: MTD device structure
2903 * @to: offset to write to
2904 * @ops: oob operation description structure
2906 * NAND write out-of-band.
2908 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2909 struct mtd_oob_ops
*ops
)
2911 int chipnr
, page
, status
, len
;
2912 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2914 pr_debug("%s: to = 0x%08x, len = %i\n",
2915 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2917 len
= mtd_oobavail(mtd
, ops
);
2919 /* Do not allow write past end of page */
2920 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2921 pr_debug("%s: attempt to write past end of page\n",
2926 if (unlikely(ops
->ooboffs
>= len
)) {
2927 pr_debug("%s: attempt to start write outside oob\n",
2932 /* Do not allow write past end of device */
2933 if (unlikely(to
>= mtd
->size
||
2934 ops
->ooboffs
+ ops
->ooblen
>
2935 ((mtd
->size
>> chip
->page_shift
) -
2936 (to
>> chip
->page_shift
)) * len
)) {
2937 pr_debug("%s: attempt to write beyond end of device\n",
2942 chipnr
= (int)(to
>> chip
->chip_shift
);
2943 chip
->select_chip(mtd
, chipnr
);
2945 /* Shift to get page */
2946 page
= (int)(to
>> chip
->page_shift
);
2949 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2950 * of my DiskOnChip 2000 test units) will clear the whole data page too
2951 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2952 * it in the doc2000 driver in August 1999. dwmw2.
2956 /* Check, if it is write protected */
2957 if (nand_check_wp(mtd
)) {
2958 chip
->select_chip(mtd
, -1);
2962 /* Invalidate the page cache, if we write to the cached page */
2963 if (page
== chip
->pagebuf
)
2966 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2968 if (ops
->mode
== MTD_OPS_RAW
)
2969 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2971 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2973 chip
->select_chip(mtd
, -1);
2978 ops
->oobretlen
= ops
->ooblen
;
2984 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2985 * @mtd: MTD device structure
2986 * @to: offset to write to
2987 * @ops: oob operation description structure
2989 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2990 struct mtd_oob_ops
*ops
)
2992 int ret
= -ENOTSUPP
;
2996 /* Do not allow writes past end of device */
2997 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2998 pr_debug("%s: attempt to write beyond end of device\n",
3003 nand_get_device(mtd
, FL_WRITING
);
3005 switch (ops
->mode
) {
3006 case MTD_OPS_PLACE_OOB
:
3007 case MTD_OPS_AUTO_OOB
:
3016 ret
= nand_do_write_oob(mtd
, to
, ops
);
3018 ret
= nand_do_write_ops(mtd
, to
, ops
);
3021 nand_release_device(mtd
);
3026 * single_erase - [GENERIC] NAND standard block erase command function
3027 * @mtd: MTD device structure
3028 * @page: the page address of the block which will be erased
3030 * Standard erase command for NAND chips. Returns NAND status.
3032 static int single_erase(struct mtd_info
*mtd
, int page
)
3034 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3035 /* Send commands to erase a block */
3036 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
3037 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
3039 return chip
->waitfunc(mtd
, chip
);
3043 * nand_erase - [MTD Interface] erase block(s)
3044 * @mtd: MTD device structure
3045 * @instr: erase instruction
3047 * Erase one ore more blocks.
3049 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
3051 return nand_erase_nand(mtd
, instr
, 0);
3055 * nand_erase_nand - [INTERN] erase block(s)
3056 * @mtd: MTD device structure
3057 * @instr: erase instruction
3058 * @allowbbt: allow erasing the bbt area
3060 * Erase one ore more blocks.
3062 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
3065 int page
, status
, pages_per_block
, ret
, chipnr
;
3066 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3069 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3070 __func__
, (unsigned long long)instr
->addr
,
3071 (unsigned long long)instr
->len
);
3073 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
3076 /* Grab the lock and see if the device is available */
3077 nand_get_device(mtd
, FL_ERASING
);
3079 /* Shift to get first page */
3080 page
= (int)(instr
->addr
>> chip
->page_shift
);
3081 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
3083 /* Calculate pages in each block */
3084 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
3086 /* Select the NAND device */
3087 chip
->select_chip(mtd
, chipnr
);
3089 /* Check, if it is write protected */
3090 if (nand_check_wp(mtd
)) {
3091 pr_debug("%s: device is write protected!\n",
3093 instr
->state
= MTD_ERASE_FAILED
;
3097 /* Loop through the pages */
3100 instr
->state
= MTD_ERASING
;
3103 /* Check if we have a bad block, we do not erase bad blocks! */
3104 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
3105 chip
->page_shift
, allowbbt
)) {
3106 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3108 instr
->state
= MTD_ERASE_FAILED
;
3113 * Invalidate the page cache, if we erase the block which
3114 * contains the current cached page.
3116 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
3117 (page
+ pages_per_block
))
3120 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
3123 * See if operation failed and additional status checks are
3126 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
3127 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
3130 /* See if block erase succeeded */
3131 if (status
& NAND_STATUS_FAIL
) {
3132 pr_debug("%s: failed erase, page 0x%08x\n",
3134 instr
->state
= MTD_ERASE_FAILED
;
3136 ((loff_t
)page
<< chip
->page_shift
);
3140 /* Increment page address and decrement length */
3141 len
-= (1ULL << chip
->phys_erase_shift
);
3142 page
+= pages_per_block
;
3144 /* Check, if we cross a chip boundary */
3145 if (len
&& !(page
& chip
->pagemask
)) {
3147 chip
->select_chip(mtd
, -1);
3148 chip
->select_chip(mtd
, chipnr
);
3151 instr
->state
= MTD_ERASE_DONE
;
3155 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
3157 /* Deselect and wake up anyone waiting on the device */
3158 chip
->select_chip(mtd
, -1);
3159 nand_release_device(mtd
);
3161 /* Do call back function */
3163 mtd_erase_callback(instr
);
3165 /* Return more or less happy */
3170 * nand_sync - [MTD Interface] sync
3171 * @mtd: MTD device structure
3173 * Sync is actually a wait for chip ready function.
3175 static void nand_sync(struct mtd_info
*mtd
)
3177 pr_debug("%s: called\n", __func__
);
3179 /* Grab the lock and see if the device is available */
3180 nand_get_device(mtd
, FL_SYNCING
);
3181 /* Release it and go back */
3182 nand_release_device(mtd
);
3186 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3187 * @mtd: MTD device structure
3188 * @offs: offset relative to mtd start
3190 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
3192 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3193 int chipnr
= (int)(offs
>> chip
->chip_shift
);
3196 /* Select the NAND device */
3197 nand_get_device(mtd
, FL_READING
);
3198 chip
->select_chip(mtd
, chipnr
);
3200 ret
= nand_block_checkbad(mtd
, offs
, 0);
3202 chip
->select_chip(mtd
, -1);
3203 nand_release_device(mtd
);
3209 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3210 * @mtd: MTD device structure
3211 * @ofs: offset relative to mtd start
3213 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3217 ret
= nand_block_isbad(mtd
, ofs
);
3219 /* If it was bad already, return success and do nothing */
3225 return nand_block_markbad_lowlevel(mtd
, ofs
);
3229 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3230 * @mtd: MTD device structure
3231 * @chip: nand chip info structure
3232 * @addr: feature address.
3233 * @subfeature_param: the subfeature parameters, a four bytes array.
3235 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3236 int addr
, uint8_t *subfeature_param
)
3241 if (!chip
->onfi_version
||
3242 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3243 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3246 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3247 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3248 chip
->write_byte(mtd
, subfeature_param
[i
]);
3250 status
= chip
->waitfunc(mtd
, chip
);
3251 if (status
& NAND_STATUS_FAIL
)
3257 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3258 * @mtd: MTD device structure
3259 * @chip: nand chip info structure
3260 * @addr: feature address.
3261 * @subfeature_param: the subfeature parameters, a four bytes array.
3263 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3264 int addr
, uint8_t *subfeature_param
)
3268 if (!chip
->onfi_version
||
3269 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3270 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3273 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3274 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3275 *subfeature_param
++ = chip
->read_byte(mtd
);
3280 * nand_suspend - [MTD Interface] Suspend the NAND flash
3281 * @mtd: MTD device structure
3283 static int nand_suspend(struct mtd_info
*mtd
)
3285 return nand_get_device(mtd
, FL_PM_SUSPENDED
);
3289 * nand_resume - [MTD Interface] Resume the NAND flash
3290 * @mtd: MTD device structure
3292 static void nand_resume(struct mtd_info
*mtd
)
3294 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3296 if (chip
->state
== FL_PM_SUSPENDED
)
3297 nand_release_device(mtd
);
3299 pr_err("%s called for a chip which is not in suspended state\n",
3304 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3305 * prevent further operations
3306 * @mtd: MTD device structure
3308 static void nand_shutdown(struct mtd_info
*mtd
)
3310 nand_get_device(mtd
, FL_PM_SUSPENDED
);
3313 /* Set default functions */
3314 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
3316 /* check for proper chip_delay setup, set 20us if not */
3317 if (!chip
->chip_delay
)
3318 chip
->chip_delay
= 20;
3320 /* check, if a user supplied command function given */
3321 if (chip
->cmdfunc
== NULL
)
3322 chip
->cmdfunc
= nand_command
;
3324 /* check, if a user supplied wait function given */
3325 if (chip
->waitfunc
== NULL
)
3326 chip
->waitfunc
= nand_wait
;
3328 if (!chip
->select_chip
)
3329 chip
->select_chip
= nand_select_chip
;
3331 /* set for ONFI nand */
3332 if (!chip
->onfi_set_features
)
3333 chip
->onfi_set_features
= nand_onfi_set_features
;
3334 if (!chip
->onfi_get_features
)
3335 chip
->onfi_get_features
= nand_onfi_get_features
;
3337 /* If called twice, pointers that depend on busw may need to be reset */
3338 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3339 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3340 if (!chip
->read_word
)
3341 chip
->read_word
= nand_read_word
;
3342 if (!chip
->block_bad
)
3343 chip
->block_bad
= nand_block_bad
;
3344 if (!chip
->block_markbad
)
3345 chip
->block_markbad
= nand_default_block_markbad
;
3346 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3347 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3348 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3349 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3350 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3351 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3352 if (!chip
->scan_bbt
)
3353 chip
->scan_bbt
= nand_default_bbt
;
3355 if (!chip
->controller
) {
3356 chip
->controller
= &chip
->hwcontrol
;
3357 nand_hw_control_init(chip
->controller
);
3362 /* Sanitize ONFI strings so we can safely print them */
3363 static void sanitize_string(uint8_t *s
, size_t len
)
3367 /* Null terminate */
3370 /* Remove non printable chars */
3371 for (i
= 0; i
< len
- 1; i
++) {
3372 if (s
[i
] < ' ' || s
[i
] > 127)
3376 /* Remove trailing spaces */
3380 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3385 for (i
= 0; i
< 8; i
++)
3386 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3392 /* Parse the Extended Parameter Page. */
3393 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3394 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3396 struct onfi_ext_param_page
*ep
;
3397 struct onfi_ext_section
*s
;
3398 struct onfi_ext_ecc_info
*ecc
;
3404 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3405 ep
= kmalloc(len
, GFP_KERNEL
);
3409 /* Send our own NAND_CMD_PARAM. */
3410 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3412 /* Use the Change Read Column command to skip the ONFI param pages. */
3413 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3414 sizeof(*p
) * p
->num_of_param_pages
, -1);
3416 /* Read out the Extended Parameter Page. */
3417 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3418 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3419 != le16_to_cpu(ep
->crc
))) {
3420 pr_debug("fail in the CRC.\n");
3425 * Check the signature.
3426 * Do not strictly follow the ONFI spec, maybe changed in future.
3428 if (strncmp(ep
->sig
, "EPPS", 4)) {
3429 pr_debug("The signature is invalid.\n");
3433 /* find the ECC section. */
3434 cursor
= (uint8_t *)(ep
+ 1);
3435 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3436 s
= ep
->sections
+ i
;
3437 if (s
->type
== ONFI_SECTION_TYPE_2
)
3439 cursor
+= s
->length
* 16;
3441 if (i
== ONFI_EXT_SECTION_MAX
) {
3442 pr_debug("We can not find the ECC section.\n");
3446 /* get the info we want. */
3447 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3449 if (!ecc
->codeword_size
) {
3450 pr_debug("Invalid codeword size\n");
3454 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3455 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3463 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3465 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3466 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3468 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3473 * Configure chip properties from Micron vendor-specific ONFI table
3475 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3476 struct nand_onfi_params
*p
)
3478 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3480 if (le16_to_cpu(p
->vendor_revision
) < 1)
3483 chip
->read_retries
= micron
->read_retry_options
;
3484 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3488 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3490 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3493 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3497 /* Try ONFI for unknown chip or LP */
3498 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3499 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3500 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3503 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3504 for (i
= 0; i
< 3; i
++) {
3505 for (j
= 0; j
< sizeof(*p
); j
++)
3506 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3507 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3508 le16_to_cpu(p
->crc
)) {
3514 pr_err("Could not find valid ONFI parameter page; aborting\n");
3519 val
= le16_to_cpu(p
->revision
);
3521 chip
->onfi_version
= 23;
3522 else if (val
& (1 << 4))
3523 chip
->onfi_version
= 22;
3524 else if (val
& (1 << 3))
3525 chip
->onfi_version
= 21;
3526 else if (val
& (1 << 2))
3527 chip
->onfi_version
= 20;
3528 else if (val
& (1 << 1))
3529 chip
->onfi_version
= 10;
3531 if (!chip
->onfi_version
) {
3532 pr_info("unsupported ONFI version: %d\n", val
);
3536 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3537 sanitize_string(p
->model
, sizeof(p
->model
));
3539 mtd
->name
= p
->model
;
3541 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3544 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3545 * (don't ask me who thought of this...). MTD assumes that these
3546 * dimensions will be power-of-2, so just truncate the remaining area.
3548 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3549 mtd
->erasesize
*= mtd
->writesize
;
3551 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3553 /* See erasesize comment */
3554 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3555 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3556 chip
->bits_per_cell
= p
->bits_per_cell
;
3558 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3559 *busw
= NAND_BUSWIDTH_16
;
3563 if (p
->ecc_bits
!= 0xff) {
3564 chip
->ecc_strength_ds
= p
->ecc_bits
;
3565 chip
->ecc_step_ds
= 512;
3566 } else if (chip
->onfi_version
>= 21 &&
3567 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3570 * The nand_flash_detect_ext_param_page() uses the
3571 * Change Read Column command which maybe not supported
3572 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3573 * now. We do not replace user supplied command function.
3575 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3576 chip
->cmdfunc
= nand_command_lp
;
3578 /* The Extended Parameter Page is supported since ONFI 2.1. */
3579 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3580 pr_warn("Failed to detect ONFI extended param page\n");
3582 pr_warn("Could not retrieve ONFI ECC requirements\n");
3585 if (p
->jedec_id
== NAND_MFR_MICRON
)
3586 nand_onfi_detect_micron(chip
, p
);
3592 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3594 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3597 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3598 struct jedec_ecc_info
*ecc
;
3602 /* Try JEDEC for unknown chip or LP */
3603 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3604 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3605 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3606 chip
->read_byte(mtd
) != 'C')
3609 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3610 for (i
= 0; i
< 3; i
++) {
3611 for (j
= 0; j
< sizeof(*p
); j
++)
3612 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3614 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3615 le16_to_cpu(p
->crc
))
3620 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3625 val
= le16_to_cpu(p
->revision
);
3627 chip
->jedec_version
= 10;
3628 else if (val
& (1 << 1))
3629 chip
->jedec_version
= 1; /* vendor specific version */
3631 if (!chip
->jedec_version
) {
3632 pr_info("unsupported JEDEC version: %d\n", val
);
3636 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3637 sanitize_string(p
->model
, sizeof(p
->model
));
3639 mtd
->name
= p
->model
;
3641 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3643 /* Please reference to the comment for nand_flash_detect_onfi. */
3644 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3645 mtd
->erasesize
*= mtd
->writesize
;
3647 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3649 /* Please reference to the comment for nand_flash_detect_onfi. */
3650 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3651 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3652 chip
->bits_per_cell
= p
->bits_per_cell
;
3654 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3655 *busw
= NAND_BUSWIDTH_16
;
3660 ecc
= &p
->ecc_info
[0];
3662 if (ecc
->codeword_size
>= 9) {
3663 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3664 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3666 pr_warn("Invalid codeword size\n");
3673 * nand_id_has_period - Check if an ID string has a given wraparound period
3674 * @id_data: the ID string
3675 * @arrlen: the length of the @id_data array
3676 * @period: the period of repitition
3678 * Check if an ID string is repeated within a given sequence of bytes at
3679 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3680 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3681 * if the repetition has a period of @period; otherwise, returns zero.
3683 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3686 for (i
= 0; i
< period
; i
++)
3687 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3688 if (id_data
[i
] != id_data
[j
])
3694 * nand_id_len - Get the length of an ID string returned by CMD_READID
3695 * @id_data: the ID string
3696 * @arrlen: the length of the @id_data array
3698 * Returns the length of the ID string, according to known wraparound/trailing
3699 * zero patterns. If no pattern exists, returns the length of the array.
3701 static int nand_id_len(u8
*id_data
, int arrlen
)
3703 int last_nonzero
, period
;
3705 /* Find last non-zero byte */
3706 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3707 if (id_data
[last_nonzero
])
3711 if (last_nonzero
< 0)
3714 /* Calculate wraparound period */
3715 for (period
= 1; period
< arrlen
; period
++)
3716 if (nand_id_has_period(id_data
, arrlen
, period
))
3719 /* There's a repeated pattern */
3720 if (period
< arrlen
)
3723 /* There are trailing zeros */
3724 if (last_nonzero
< arrlen
- 1)
3725 return last_nonzero
+ 1;
3727 /* No pattern detected */
3731 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3732 static int nand_get_bits_per_cell(u8 cellinfo
)
3736 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3737 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3742 * Many new NAND share similar device ID codes, which represent the size of the
3743 * chip. The rest of the parameters must be decoded according to generic or
3744 * manufacturer-specific "extended ID" decoding patterns.
3746 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3747 u8 id_data
[8], int *busw
)
3750 /* The 3rd id byte holds MLC / multichip data */
3751 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3752 /* The 4th id byte is the important one */
3755 id_len
= nand_id_len(id_data
, 8);
3758 * Field definitions are in the following datasheets:
3759 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3760 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3761 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3763 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3764 * ID to decide what to do.
3766 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3767 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3769 mtd
->writesize
= 2048 << (extid
& 0x03);
3772 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3792 default: /* Other cases are "reserved" (unknown) */
3793 mtd
->oobsize
= 1024;
3797 /* Calc blocksize */
3798 mtd
->erasesize
= (128 * 1024) <<
3799 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3801 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3802 !nand_is_slc(chip
)) {
3806 mtd
->writesize
= 2048 << (extid
& 0x03);
3809 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3833 /* Calc blocksize */
3834 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3836 mtd
->erasesize
= (128 * 1024) << tmp
;
3837 else if (tmp
== 0x03)
3838 mtd
->erasesize
= 768 * 1024;
3840 mtd
->erasesize
= (64 * 1024) << tmp
;
3844 mtd
->writesize
= 1024 << (extid
& 0x03);
3847 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3848 (mtd
->writesize
>> 9);
3850 /* Calc blocksize. Blocksize is multiples of 64KiB */
3851 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3853 /* Get buswidth information */
3854 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3857 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3858 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3860 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3862 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3864 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3865 nand_is_slc(chip
) &&
3866 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3867 !(id_data
[4] & 0x80) /* !BENAND */) {
3868 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3875 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3876 * decodes a matching ID table entry and assigns the MTD size parameters for
3879 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3880 struct nand_flash_dev
*type
, u8 id_data
[8],
3883 int maf_id
= id_data
[0];
3885 mtd
->erasesize
= type
->erasesize
;
3886 mtd
->writesize
= type
->pagesize
;
3887 mtd
->oobsize
= mtd
->writesize
/ 32;
3888 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3890 /* All legacy ID NAND are small-page, SLC */
3891 chip
->bits_per_cell
= 1;
3894 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3895 * some Spansion chips have erasesize that conflicts with size
3896 * listed in nand_ids table.
3897 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3899 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3900 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3901 && mtd
->writesize
== 512) {
3902 mtd
->erasesize
= 128 * 1024;
3903 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3908 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3909 * heuristic patterns using various detected parameters (e.g., manufacturer,
3910 * page size, cell-type information).
3912 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3913 struct nand_chip
*chip
, u8 id_data
[8])
3915 int maf_id
= id_data
[0];
3917 /* Set the bad block position */
3918 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3919 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3921 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3924 * Bad block marker is stored in the last page of each block on Samsung
3925 * and Hynix MLC devices; stored in first two pages of each block on
3926 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3927 * AMD/Spansion, and Macronix. All others scan only the first page.
3929 if (!nand_is_slc(chip
) &&
3930 (maf_id
== NAND_MFR_SAMSUNG
||
3931 maf_id
== NAND_MFR_HYNIX
))
3932 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3933 else if ((nand_is_slc(chip
) &&
3934 (maf_id
== NAND_MFR_SAMSUNG
||
3935 maf_id
== NAND_MFR_HYNIX
||
3936 maf_id
== NAND_MFR_TOSHIBA
||
3937 maf_id
== NAND_MFR_AMD
||
3938 maf_id
== NAND_MFR_MACRONIX
)) ||
3939 (mtd
->writesize
== 2048 &&
3940 maf_id
== NAND_MFR_MICRON
))
3941 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3944 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3946 return type
->id_len
;
3949 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3950 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3952 if (!strncmp(type
->id
, id_data
, type
->id_len
)) {
3953 mtd
->writesize
= type
->pagesize
;
3954 mtd
->erasesize
= type
->erasesize
;
3955 mtd
->oobsize
= type
->oobsize
;
3957 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3958 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3959 chip
->options
|= type
->options
;
3960 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3961 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3962 chip
->onfi_timing_mode_default
=
3963 type
->onfi_timing_mode_default
;
3965 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3968 mtd
->name
= type
->name
;
3976 * Get the flash and manufacturer id and lookup if the type is supported.
3978 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3979 struct nand_chip
*chip
,
3980 int *maf_id
, int *dev_id
,
3981 struct nand_flash_dev
*type
)
3987 /* Select the device */
3988 chip
->select_chip(mtd
, 0);
3991 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3996 /* Send the command for reading device ID */
3997 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3999 /* Read manufacturer and device IDs */
4000 *maf_id
= chip
->read_byte(mtd
);
4001 *dev_id
= chip
->read_byte(mtd
);
4004 * Try again to make sure, as some systems the bus-hold or other
4005 * interface concerns can cause random data which looks like a
4006 * possibly credible NAND flash to appear. If the two results do
4007 * not match, ignore the device completely.
4010 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4012 /* Read entire ID string */
4013 for (i
= 0; i
< 8; i
++)
4014 id_data
[i
] = chip
->read_byte(mtd
);
4016 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
4017 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4018 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
4019 return ERR_PTR(-ENODEV
);
4023 type
= nand_flash_ids
;
4025 for (; type
->name
!= NULL
; type
++) {
4026 if (is_full_id_nand(type
)) {
4027 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
4029 } else if (*dev_id
== type
->dev_id
) {
4034 chip
->onfi_version
= 0;
4035 if (!type
->name
|| !type
->pagesize
) {
4036 /* Check if the chip is ONFI compliant */
4037 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
4040 /* Check if the chip is JEDEC compliant */
4041 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
4046 return ERR_PTR(-ENODEV
);
4049 mtd
->name
= type
->name
;
4051 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
4053 if (!type
->pagesize
) {
4054 /* Decode parameters from extended ID */
4055 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
4057 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
4059 /* Get chip options */
4060 chip
->options
|= type
->options
;
4063 * Check if chip is not a Samsung device. Do not clear the
4064 * options for chips which do not have an extended id.
4066 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
4067 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
4070 /* Try to identify manufacturer */
4071 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
4072 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
4076 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
4077 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
4078 chip
->options
|= busw
;
4079 nand_set_defaults(chip
, busw
);
4080 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
4082 * Check, if buswidth is correct. Hardware drivers should set
4085 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4087 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
4088 pr_warn("bus width %d instead %d bit\n",
4089 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
4091 return ERR_PTR(-EINVAL
);
4094 nand_decode_bbm_options(mtd
, chip
, id_data
);
4096 /* Calculate the address shift from the page size */
4097 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
4098 /* Convert chipsize to number of pages per chip -1 */
4099 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
4101 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
4102 ffs(mtd
->erasesize
) - 1;
4103 if (chip
->chipsize
& 0xffffffff)
4104 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
4106 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
4107 chip
->chip_shift
+= 32 - 1;
4110 chip
->badblockbits
= 8;
4111 chip
->erase
= single_erase
;
4113 /* Do not replace user supplied command function! */
4114 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
4115 chip
->cmdfunc
= nand_command_lp
;
4117 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4120 if (chip
->onfi_version
)
4121 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
4122 chip
->onfi_params
.model
);
4123 else if (chip
->jedec_version
)
4124 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
4125 chip
->jedec_params
.model
);
4127 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
4130 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4131 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
4132 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
4136 static const char * const nand_ecc_modes
[] = {
4137 [NAND_ECC_NONE
] = "none",
4138 [NAND_ECC_SOFT
] = "soft",
4139 [NAND_ECC_HW
] = "hw",
4140 [NAND_ECC_HW_SYNDROME
] = "hw_syndrome",
4141 [NAND_ECC_HW_OOB_FIRST
] = "hw_oob_first",
4144 static int of_get_nand_ecc_mode(struct device_node
*np
)
4149 err
= of_property_read_string(np
, "nand-ecc-mode", &pm
);
4153 for (i
= 0; i
< ARRAY_SIZE(nand_ecc_modes
); i
++)
4154 if (!strcasecmp(pm
, nand_ecc_modes
[i
]))
4158 * For backward compatibility we support few obsoleted values that don't
4159 * have their mappings into nand_ecc_modes_t anymore (they were merged
4160 * with other enums).
4162 if (!strcasecmp(pm
, "soft_bch"))
4163 return NAND_ECC_SOFT
;
4168 static const char * const nand_ecc_algos
[] = {
4169 [NAND_ECC_HAMMING
] = "hamming",
4170 [NAND_ECC_BCH
] = "bch",
4173 static int of_get_nand_ecc_algo(struct device_node
*np
)
4178 err
= of_property_read_string(np
, "nand-ecc-algo", &pm
);
4180 for (i
= NAND_ECC_HAMMING
; i
< ARRAY_SIZE(nand_ecc_algos
); i
++)
4181 if (!strcasecmp(pm
, nand_ecc_algos
[i
]))
4187 * For backward compatibility we also read "nand-ecc-mode" checking
4188 * for some obsoleted values that were specifying ECC algorithm.
4190 err
= of_property_read_string(np
, "nand-ecc-mode", &pm
);
4194 if (!strcasecmp(pm
, "soft"))
4195 return NAND_ECC_HAMMING
;
4196 else if (!strcasecmp(pm
, "soft_bch"))
4197 return NAND_ECC_BCH
;
4202 static int of_get_nand_ecc_step_size(struct device_node
*np
)
4207 ret
= of_property_read_u32(np
, "nand-ecc-step-size", &val
);
4208 return ret
? ret
: val
;
4211 static int of_get_nand_ecc_strength(struct device_node
*np
)
4216 ret
= of_property_read_u32(np
, "nand-ecc-strength", &val
);
4217 return ret
? ret
: val
;
4220 static int of_get_nand_bus_width(struct device_node
*np
)
4224 if (of_property_read_u32(np
, "nand-bus-width", &val
))
4236 static bool of_get_nand_on_flash_bbt(struct device_node
*np
)
4238 return of_property_read_bool(np
, "nand-on-flash-bbt");
4241 static int nand_dt_init(struct nand_chip
*chip
)
4243 struct device_node
*dn
= nand_get_flash_node(chip
);
4244 int ecc_mode
, ecc_algo
, ecc_strength
, ecc_step
;
4249 if (of_get_nand_bus_width(dn
) == 16)
4250 chip
->options
|= NAND_BUSWIDTH_16
;
4252 if (of_get_nand_on_flash_bbt(dn
))
4253 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
4255 ecc_mode
= of_get_nand_ecc_mode(dn
);
4256 ecc_algo
= of_get_nand_ecc_algo(dn
);
4257 ecc_strength
= of_get_nand_ecc_strength(dn
);
4258 ecc_step
= of_get_nand_ecc_step_size(dn
);
4260 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
4261 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
4262 pr_err("must set both strength and step size in DT\n");
4267 chip
->ecc
.mode
= ecc_mode
;
4270 chip
->ecc
.algo
= ecc_algo
;
4272 if (ecc_strength
>= 0)
4273 chip
->ecc
.strength
= ecc_strength
;
4276 chip
->ecc
.size
= ecc_step
;
4278 if (of_property_read_bool(dn
, "nand-ecc-maximize"))
4279 chip
->ecc
.options
|= NAND_ECC_MAXIMIZE
;
4285 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4286 * @mtd: MTD device structure
4287 * @maxchips: number of chips to scan for
4288 * @table: alternative NAND ID table
4290 * This is the first phase of the normal nand_scan() function. It reads the
4291 * flash ID and sets up MTD fields accordingly.
4294 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4295 struct nand_flash_dev
*table
)
4297 int i
, nand_maf_id
, nand_dev_id
;
4298 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4299 struct nand_flash_dev
*type
;
4302 ret
= nand_dt_init(chip
);
4306 if (!mtd
->name
&& mtd
->dev
.parent
)
4307 mtd
->name
= dev_name(mtd
->dev
.parent
);
4309 if ((!chip
->cmdfunc
|| !chip
->select_chip
) && !chip
->cmd_ctrl
) {
4311 * Default functions assigned for chip_select() and
4312 * cmdfunc() both expect cmd_ctrl() to be populated,
4313 * so we need to check that that's the case
4315 pr_err("chip.cmd_ctrl() callback is not provided");
4318 /* Set the default functions */
4319 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
4321 /* Read the flash type */
4322 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
4323 &nand_dev_id
, table
);
4326 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4327 pr_warn("No NAND device found\n");
4328 chip
->select_chip(mtd
, -1);
4329 return PTR_ERR(type
);
4332 ret
= nand_init_data_interface(chip
);
4336 chip
->select_chip(mtd
, -1);
4338 /* Check for a chip array */
4339 for (i
= 1; i
< maxchips
; i
++) {
4340 chip
->select_chip(mtd
, i
);
4341 /* See comment in nand_get_flash_type for reset */
4343 /* Send the command for reading device ID */
4344 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4345 /* Read manufacturer and device IDs */
4346 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4347 nand_dev_id
!= chip
->read_byte(mtd
)) {
4348 chip
->select_chip(mtd
, -1);
4351 chip
->select_chip(mtd
, -1);
4354 pr_info("%d chips detected\n", i
);
4356 /* Store the number of chips and calc total size for mtd */
4358 mtd
->size
= i
* chip
->chipsize
;
4362 EXPORT_SYMBOL(nand_scan_ident
);
4364 static int nand_set_ecc_soft_ops(struct mtd_info
*mtd
)
4366 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4367 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4369 if (WARN_ON(ecc
->mode
!= NAND_ECC_SOFT
))
4372 switch (ecc
->algo
) {
4373 case NAND_ECC_HAMMING
:
4374 ecc
->calculate
= nand_calculate_ecc
;
4375 ecc
->correct
= nand_correct_data
;
4376 ecc
->read_page
= nand_read_page_swecc
;
4377 ecc
->read_subpage
= nand_read_subpage
;
4378 ecc
->write_page
= nand_write_page_swecc
;
4379 ecc
->read_page_raw
= nand_read_page_raw
;
4380 ecc
->write_page_raw
= nand_write_page_raw
;
4381 ecc
->read_oob
= nand_read_oob_std
;
4382 ecc
->write_oob
= nand_write_oob_std
;
4389 if (!mtd_nand_has_bch()) {
4390 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4393 ecc
->calculate
= nand_bch_calculate_ecc
;
4394 ecc
->correct
= nand_bch_correct_data
;
4395 ecc
->read_page
= nand_read_page_swecc
;
4396 ecc
->read_subpage
= nand_read_subpage
;
4397 ecc
->write_page
= nand_write_page_swecc
;
4398 ecc
->read_page_raw
= nand_read_page_raw
;
4399 ecc
->write_page_raw
= nand_write_page_raw
;
4400 ecc
->read_oob
= nand_read_oob_std
;
4401 ecc
->write_oob
= nand_write_oob_std
;
4404 * Board driver should supply ecc.size and ecc.strength
4405 * values to select how many bits are correctable.
4406 * Otherwise, default to 4 bits for large page devices.
4408 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4414 * if no ecc placement scheme was provided pickup the default
4417 if (!mtd
->ooblayout
) {
4418 /* handle large page devices only */
4419 if (mtd
->oobsize
< 64) {
4420 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4424 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
4429 * We can only maximize ECC config when the default layout is
4430 * used, otherwise we don't know how many bytes can really be
4433 if (mtd
->ooblayout
== &nand_ooblayout_lp_ops
&&
4434 ecc
->options
& NAND_ECC_MAXIMIZE
) {
4437 /* Always prefer 1k blocks over 512bytes ones */
4439 steps
= mtd
->writesize
/ ecc
->size
;
4441 /* Reserve 2 bytes for the BBM */
4442 bytes
= (mtd
->oobsize
- 2) / steps
;
4443 ecc
->strength
= bytes
* 8 / fls(8 * ecc
->size
);
4446 /* See nand_bch_init() for details. */
4448 ecc
->priv
= nand_bch_init(mtd
);
4450 WARN(1, "BCH ECC initialization failed!\n");
4455 WARN(1, "Unsupported ECC algorithm!\n");
4461 * Check if the chip configuration meet the datasheet requirements.
4463 * If our configuration corrects A bits per B bytes and the minimum
4464 * required correction level is X bits per Y bytes, then we must ensure
4465 * both of the following are true:
4467 * (1) A / B >= X / Y
4470 * Requirement (1) ensures we can correct for the required bitflip density.
4471 * Requirement (2) ensures we can correct even when all bitflips are clumped
4472 * in the same sector.
4474 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4476 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4477 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4480 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4481 /* Not enough information */
4485 * We get the number of corrected bits per page to compare
4486 * the correction density.
4488 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4489 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4491 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4495 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4496 * @mtd: MTD device structure
4498 * This is the second phase of the normal nand_scan() function. It fills out
4499 * all the uninitialized function pointers with the defaults and scans for a
4500 * bad block table if appropriate.
4502 int nand_scan_tail(struct mtd_info
*mtd
)
4504 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4505 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4506 struct nand_buffers
*nbuf
;
4509 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4510 if (WARN_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4511 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
)))
4514 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4515 nbuf
= kzalloc(sizeof(*nbuf
) + mtd
->writesize
4516 + mtd
->oobsize
* 3, GFP_KERNEL
);
4519 nbuf
->ecccalc
= (uint8_t *)(nbuf
+ 1);
4520 nbuf
->ecccode
= nbuf
->ecccalc
+ mtd
->oobsize
;
4521 nbuf
->databuf
= nbuf
->ecccode
+ mtd
->oobsize
;
4523 chip
->buffers
= nbuf
;
4529 /* Set the internal oob buffer location, just after the page data */
4530 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4533 * If no default placement scheme is given, select an appropriate one.
4535 if (!mtd
->ooblayout
&&
4536 !(ecc
->mode
== NAND_ECC_SOFT
&& ecc
->algo
== NAND_ECC_BCH
)) {
4537 switch (mtd
->oobsize
) {
4540 mtd_set_ooblayout(mtd
, &nand_ooblayout_sp_ops
);
4544 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
4547 WARN(1, "No oob scheme defined for oobsize %d\n",
4554 if (!chip
->write_page
)
4555 chip
->write_page
= nand_write_page
;
4558 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4559 * selected and we have 256 byte pagesize fallback to software ECC
4562 switch (ecc
->mode
) {
4563 case NAND_ECC_HW_OOB_FIRST
:
4564 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4565 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4566 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4570 if (!ecc
->read_page
)
4571 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4574 /* Use standard hwecc read page function? */
4575 if (!ecc
->read_page
)
4576 ecc
->read_page
= nand_read_page_hwecc
;
4577 if (!ecc
->write_page
)
4578 ecc
->write_page
= nand_write_page_hwecc
;
4579 if (!ecc
->read_page_raw
)
4580 ecc
->read_page_raw
= nand_read_page_raw
;
4581 if (!ecc
->write_page_raw
)
4582 ecc
->write_page_raw
= nand_write_page_raw
;
4584 ecc
->read_oob
= nand_read_oob_std
;
4585 if (!ecc
->write_oob
)
4586 ecc
->write_oob
= nand_write_oob_std
;
4587 if (!ecc
->read_subpage
)
4588 ecc
->read_subpage
= nand_read_subpage
;
4589 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4590 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4592 case NAND_ECC_HW_SYNDROME
:
4593 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4595 ecc
->read_page
== nand_read_page_hwecc
||
4597 ecc
->write_page
== nand_write_page_hwecc
)) {
4598 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4602 /* Use standard syndrome read/write page function? */
4603 if (!ecc
->read_page
)
4604 ecc
->read_page
= nand_read_page_syndrome
;
4605 if (!ecc
->write_page
)
4606 ecc
->write_page
= nand_write_page_syndrome
;
4607 if (!ecc
->read_page_raw
)
4608 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4609 if (!ecc
->write_page_raw
)
4610 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4612 ecc
->read_oob
= nand_read_oob_syndrome
;
4613 if (!ecc
->write_oob
)
4614 ecc
->write_oob
= nand_write_oob_syndrome
;
4616 if (mtd
->writesize
>= ecc
->size
) {
4617 if (!ecc
->strength
) {
4618 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4624 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4625 ecc
->size
, mtd
->writesize
);
4626 ecc
->mode
= NAND_ECC_SOFT
;
4627 ecc
->algo
= NAND_ECC_HAMMING
;
4630 ret
= nand_set_ecc_soft_ops(mtd
);
4638 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4639 ecc
->read_page
= nand_read_page_raw
;
4640 ecc
->write_page
= nand_write_page_raw
;
4641 ecc
->read_oob
= nand_read_oob_std
;
4642 ecc
->read_page_raw
= nand_read_page_raw
;
4643 ecc
->write_page_raw
= nand_write_page_raw
;
4644 ecc
->write_oob
= nand_write_oob_std
;
4645 ecc
->size
= mtd
->writesize
;
4651 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4656 /* For many systems, the standard OOB write also works for raw */
4657 if (!ecc
->read_oob_raw
)
4658 ecc
->read_oob_raw
= ecc
->read_oob
;
4659 if (!ecc
->write_oob_raw
)
4660 ecc
->write_oob_raw
= ecc
->write_oob
;
4662 /* propagate ecc info to mtd_info */
4663 mtd
->ecc_strength
= ecc
->strength
;
4664 mtd
->ecc_step_size
= ecc
->size
;
4667 * Set the number of read / write steps for one page depending on ECC
4670 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4671 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4672 WARN(1, "Invalid ECC parameters\n");
4676 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4679 * The number of bytes available for a client to place data into
4680 * the out of band area.
4682 ret
= mtd_ooblayout_count_freebytes(mtd
);
4686 mtd
->oobavail
= ret
;
4688 /* ECC sanity check: warn if it's too weak */
4689 if (!nand_ecc_strength_good(mtd
))
4690 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4693 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4694 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4695 switch (ecc
->steps
) {
4697 mtd
->subpage_sft
= 1;
4702 mtd
->subpage_sft
= 2;
4706 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4708 /* Initialize state */
4709 chip
->state
= FL_READY
;
4711 /* Invalidate the pagebuffer reference */
4714 /* Large page NAND with SOFT_ECC should support subpage reads */
4715 switch (ecc
->mode
) {
4717 if (chip
->page_shift
> 9)
4718 chip
->options
|= NAND_SUBPAGE_READ
;
4725 /* Fill in remaining MTD driver data */
4726 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4727 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4729 mtd
->_erase
= nand_erase
;
4731 mtd
->_unpoint
= NULL
;
4732 mtd
->_read
= nand_read
;
4733 mtd
->_write
= nand_write
;
4734 mtd
->_panic_write
= panic_nand_write
;
4735 mtd
->_read_oob
= nand_read_oob
;
4736 mtd
->_write_oob
= nand_write_oob
;
4737 mtd
->_sync
= nand_sync
;
4739 mtd
->_unlock
= NULL
;
4740 mtd
->_suspend
= nand_suspend
;
4741 mtd
->_resume
= nand_resume
;
4742 mtd
->_reboot
= nand_shutdown
;
4743 mtd
->_block_isreserved
= nand_block_isreserved
;
4744 mtd
->_block_isbad
= nand_block_isbad
;
4745 mtd
->_block_markbad
= nand_block_markbad
;
4746 mtd
->writebufsize
= mtd
->writesize
;
4749 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4750 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4753 if (!mtd
->bitflip_threshold
)
4754 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4756 /* Check, if we should skip the bad block table scan */
4757 if (chip
->options
& NAND_SKIP_BBTSCAN
)
4760 /* Build bad block table */
4761 return chip
->scan_bbt(mtd
);
4763 if (!(chip
->options
& NAND_OWN_BUFFERS
))
4764 kfree(chip
->buffers
);
4767 EXPORT_SYMBOL(nand_scan_tail
);
4770 * is_module_text_address() isn't exported, and it's mostly a pointless
4771 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4772 * to call us from in-kernel code if the core NAND support is modular.
4775 #define caller_is_module() (1)
4777 #define caller_is_module() \
4778 is_module_text_address((unsigned long)__builtin_return_address(0))
4782 * nand_scan - [NAND Interface] Scan for the NAND device
4783 * @mtd: MTD device structure
4784 * @maxchips: number of chips to scan for
4786 * This fills out all the uninitialized function pointers with the defaults.
4787 * The flash ID is read and the mtd/chip structures are filled with the
4788 * appropriate values.
4790 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4794 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4796 ret
= nand_scan_tail(mtd
);
4799 EXPORT_SYMBOL(nand_scan
);
4802 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
4803 * @chip: NAND chip object
4805 void nand_cleanup(struct nand_chip
*chip
)
4807 if (chip
->ecc
.mode
== NAND_ECC_SOFT
&&
4808 chip
->ecc
.algo
== NAND_ECC_BCH
)
4809 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
4811 nand_release_data_interface(chip
);
4813 /* Free bad block table memory */
4815 if (!(chip
->options
& NAND_OWN_BUFFERS
))
4816 kfree(chip
->buffers
);
4818 /* Free bad block descriptor memory */
4819 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
4820 & NAND_BBT_DYNAMICSTRUCT
)
4821 kfree(chip
->badblock_pattern
);
4823 EXPORT_SYMBOL_GPL(nand_cleanup
);
4826 * nand_release - [NAND Interface] Unregister the MTD device and free resources
4827 * held by the NAND device
4828 * @mtd: MTD device structure
4830 void nand_release(struct mtd_info
*mtd
)
4832 mtd_device_unregister(mtd
);
4833 nand_cleanup(mtd_to_nand(mtd
));
4835 EXPORT_SYMBOL_GPL(nand_release
);
4837 MODULE_LICENSE("GPL");
4838 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4839 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4840 MODULE_DESCRIPTION("Generic NAND flash driver code");