3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/nmi.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/nand_bch.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
48 #include <linux/mtd/partitions.h>
51 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
53 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
54 struct mtd_oob_ops
*ops
);
56 /* Define default oob placement schemes for large and small page devices */
57 static int nand_ooblayout_ecc_sp(struct mtd_info
*mtd
, int section
,
58 struct mtd_oob_region
*oobregion
)
60 struct nand_chip
*chip
= mtd_to_nand(mtd
);
61 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
67 oobregion
->offset
= 0;
68 if (mtd
->oobsize
== 16)
69 oobregion
->length
= 4;
71 oobregion
->length
= 3;
73 if (mtd
->oobsize
== 8)
76 oobregion
->offset
= 6;
77 oobregion
->length
= ecc
->total
- 4;
83 static int nand_ooblayout_free_sp(struct mtd_info
*mtd
, int section
,
84 struct mtd_oob_region
*oobregion
)
89 if (mtd
->oobsize
== 16) {
93 oobregion
->length
= 8;
94 oobregion
->offset
= 8;
96 oobregion
->length
= 2;
98 oobregion
->offset
= 3;
100 oobregion
->offset
= 6;
106 const struct mtd_ooblayout_ops nand_ooblayout_sp_ops
= {
107 .ecc
= nand_ooblayout_ecc_sp
,
108 .free
= nand_ooblayout_free_sp
,
110 EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops
);
112 static int nand_ooblayout_ecc_lp(struct mtd_info
*mtd
, int section
,
113 struct mtd_oob_region
*oobregion
)
115 struct nand_chip
*chip
= mtd_to_nand(mtd
);
116 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
121 oobregion
->length
= ecc
->total
;
122 oobregion
->offset
= mtd
->oobsize
- oobregion
->length
;
127 static int nand_ooblayout_free_lp(struct mtd_info
*mtd
, int section
,
128 struct mtd_oob_region
*oobregion
)
130 struct nand_chip
*chip
= mtd_to_nand(mtd
);
131 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
136 oobregion
->length
= mtd
->oobsize
- ecc
->total
- 2;
137 oobregion
->offset
= 2;
142 const struct mtd_ooblayout_ops nand_ooblayout_lp_ops
= {
143 .ecc
= nand_ooblayout_ecc_lp
,
144 .free
= nand_ooblayout_free_lp
,
146 EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops
);
149 * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
150 * are placed at a fixed offset.
152 static int nand_ooblayout_ecc_lp_hamming(struct mtd_info
*mtd
, int section
,
153 struct mtd_oob_region
*oobregion
)
155 struct nand_chip
*chip
= mtd_to_nand(mtd
);
156 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
161 switch (mtd
->oobsize
) {
163 oobregion
->offset
= 40;
166 oobregion
->offset
= 80;
172 oobregion
->length
= ecc
->total
;
173 if (oobregion
->offset
+ oobregion
->length
> mtd
->oobsize
)
179 static int nand_ooblayout_free_lp_hamming(struct mtd_info
*mtd
, int section
,
180 struct mtd_oob_region
*oobregion
)
182 struct nand_chip
*chip
= mtd_to_nand(mtd
);
183 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
186 if (section
< 0 || section
> 1)
189 switch (mtd
->oobsize
) {
201 oobregion
->offset
= 2;
202 oobregion
->length
= ecc_offset
- 2;
204 oobregion
->offset
= ecc_offset
+ ecc
->total
;
205 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
211 static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops
= {
212 .ecc
= nand_ooblayout_ecc_lp_hamming
,
213 .free
= nand_ooblayout_free_lp_hamming
,
216 static int check_offs_len(struct mtd_info
*mtd
,
217 loff_t ofs
, uint64_t len
)
219 struct nand_chip
*chip
= mtd_to_nand(mtd
);
222 /* Start address must align on block boundary */
223 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
224 pr_debug("%s: unaligned address\n", __func__
);
228 /* Length must align on block boundary */
229 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
230 pr_debug("%s: length not block aligned\n", __func__
);
238 * nand_release_device - [GENERIC] release chip
239 * @mtd: MTD device structure
241 * Release chip lock and wake up anyone waiting on the device.
243 static void nand_release_device(struct mtd_info
*mtd
)
245 struct nand_chip
*chip
= mtd_to_nand(mtd
);
247 /* Release the controller and the chip */
248 spin_lock(&chip
->controller
->lock
);
249 chip
->controller
->active
= NULL
;
250 chip
->state
= FL_READY
;
251 wake_up(&chip
->controller
->wq
);
252 spin_unlock(&chip
->controller
->lock
);
256 * nand_read_byte - [DEFAULT] read one byte from the chip
257 * @mtd: MTD device structure
259 * Default read function for 8bit buswidth
261 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
263 struct nand_chip
*chip
= mtd_to_nand(mtd
);
264 return readb(chip
->IO_ADDR_R
);
268 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
269 * @mtd: MTD device structure
271 * Default read function for 16bit buswidth with endianness conversion.
274 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
276 struct nand_chip
*chip
= mtd_to_nand(mtd
);
277 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
281 * nand_read_word - [DEFAULT] read one word from the chip
282 * @mtd: MTD device structure
284 * Default read function for 16bit buswidth without endianness conversion.
286 static u16
nand_read_word(struct mtd_info
*mtd
)
288 struct nand_chip
*chip
= mtd_to_nand(mtd
);
289 return readw(chip
->IO_ADDR_R
);
293 * nand_select_chip - [DEFAULT] control CE line
294 * @mtd: MTD device structure
295 * @chipnr: chipnumber to select, -1 for deselect
297 * Default select function for 1 chip devices.
299 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
301 struct nand_chip
*chip
= mtd_to_nand(mtd
);
305 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
316 * nand_write_byte - [DEFAULT] write single byte to chip
317 * @mtd: MTD device structure
318 * @byte: value to write
320 * Default function to write a byte to I/O[7:0]
322 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
324 struct nand_chip
*chip
= mtd_to_nand(mtd
);
326 chip
->write_buf(mtd
, &byte
, 1);
330 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
331 * @mtd: MTD device structure
332 * @byte: value to write
334 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
336 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
338 struct nand_chip
*chip
= mtd_to_nand(mtd
);
339 uint16_t word
= byte
;
342 * It's not entirely clear what should happen to I/O[15:8] when writing
343 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
345 * When the host supports a 16-bit bus width, only data is
346 * transferred at the 16-bit width. All address and command line
347 * transfers shall use only the lower 8-bits of the data bus. During
348 * command transfers, the host may place any value on the upper
349 * 8-bits of the data bus. During address transfers, the host shall
350 * set the upper 8-bits of the data bus to 00h.
352 * One user of the write_byte callback is nand_onfi_set_features. The
353 * four parameters are specified to be written to I/O[7:0], but this is
354 * neither an address nor a command transfer. Let's assume a 0 on the
355 * upper I/O lines is OK.
357 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
361 * nand_write_buf - [DEFAULT] write buffer to chip
362 * @mtd: MTD device structure
364 * @len: number of bytes to write
366 * Default write function for 8bit buswidth.
368 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
370 struct nand_chip
*chip
= mtd_to_nand(mtd
);
372 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
376 * nand_read_buf - [DEFAULT] read chip data into buffer
377 * @mtd: MTD device structure
378 * @buf: buffer to store date
379 * @len: number of bytes to read
381 * Default read function for 8bit buswidth.
383 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
385 struct nand_chip
*chip
= mtd_to_nand(mtd
);
387 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
391 * nand_write_buf16 - [DEFAULT] write buffer to chip
392 * @mtd: MTD device structure
394 * @len: number of bytes to write
396 * Default write function for 16bit buswidth.
398 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
400 struct nand_chip
*chip
= mtd_to_nand(mtd
);
401 u16
*p
= (u16
*) buf
;
403 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
407 * nand_read_buf16 - [DEFAULT] read chip data into buffer
408 * @mtd: MTD device structure
409 * @buf: buffer to store date
410 * @len: number of bytes to read
412 * Default read function for 16bit buswidth.
414 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
416 struct nand_chip
*chip
= mtd_to_nand(mtd
);
417 u16
*p
= (u16
*) buf
;
419 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
423 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
424 * @mtd: MTD device structure
425 * @ofs: offset from device start
427 * Check, if the block is bad.
429 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
431 int page
, page_end
, res
;
432 struct nand_chip
*chip
= mtd_to_nand(mtd
);
435 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
436 ofs
+= mtd
->erasesize
- mtd
->writesize
;
438 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
439 page_end
= page
+ (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
? 2 : 1);
441 for (; page
< page_end
; page
++) {
442 res
= chip
->ecc
.read_oob(mtd
, chip
, page
);
446 bad
= chip
->oob_poi
[chip
->badblockpos
];
448 if (likely(chip
->badblockbits
== 8))
451 res
= hweight8(bad
) < chip
->badblockbits
;
460 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
461 * @mtd: MTD device structure
462 * @ofs: offset from device start
464 * This is the default implementation, which can be overridden by a hardware
465 * specific driver. It provides the details for writing a bad block marker to a
468 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
470 struct nand_chip
*chip
= mtd_to_nand(mtd
);
471 struct mtd_oob_ops ops
;
472 uint8_t buf
[2] = { 0, 0 };
473 int ret
= 0, res
, i
= 0;
475 memset(&ops
, 0, sizeof(ops
));
477 ops
.ooboffs
= chip
->badblockpos
;
478 if (chip
->options
& NAND_BUSWIDTH_16
) {
479 ops
.ooboffs
&= ~0x01;
480 ops
.len
= ops
.ooblen
= 2;
482 ops
.len
= ops
.ooblen
= 1;
484 ops
.mode
= MTD_OPS_PLACE_OOB
;
486 /* Write to first/last page(s) if necessary */
487 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
488 ofs
+= mtd
->erasesize
- mtd
->writesize
;
490 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
495 ofs
+= mtd
->writesize
;
496 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
502 * nand_block_markbad_lowlevel - mark a block bad
503 * @mtd: MTD device structure
504 * @ofs: offset from device start
506 * This function performs the generic NAND bad block marking steps (i.e., bad
507 * block table(s) and/or marker(s)). We only allow the hardware driver to
508 * specify how to write bad block markers to OOB (chip->block_markbad).
510 * We try operations in the following order:
512 * (1) erase the affected block, to allow OOB marker to be written cleanly
513 * (2) write bad block marker to OOB area of affected block (unless flag
514 * NAND_BBT_NO_OOB_BBM is present)
517 * Note that we retain the first error encountered in (2) or (3), finish the
518 * procedures, and dump the error in the end.
520 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
522 struct nand_chip
*chip
= mtd_to_nand(mtd
);
525 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
526 struct erase_info einfo
;
528 /* Attempt erase before marking OOB */
529 memset(&einfo
, 0, sizeof(einfo
));
532 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
533 nand_erase_nand(mtd
, &einfo
, 0);
535 /* Write bad block marker to OOB */
536 nand_get_device(mtd
, FL_WRITING
);
537 ret
= chip
->block_markbad(mtd
, ofs
);
538 nand_release_device(mtd
);
541 /* Mark block bad in BBT */
543 res
= nand_markbad_bbt(mtd
, ofs
);
549 mtd
->ecc_stats
.badblocks
++;
555 * nand_check_wp - [GENERIC] check if the chip is write protected
556 * @mtd: MTD device structure
558 * Check, if the device is write protected. The function expects, that the
559 * device is already selected.
561 static int nand_check_wp(struct mtd_info
*mtd
)
563 struct nand_chip
*chip
= mtd_to_nand(mtd
);
565 /* Broken xD cards report WP despite being writable */
566 if (chip
->options
& NAND_BROKEN_XD
)
569 /* Check the WP bit */
570 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
571 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
575 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
576 * @mtd: MTD device structure
577 * @ofs: offset from device start
579 * Check if the block is marked as reserved.
581 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
583 struct nand_chip
*chip
= mtd_to_nand(mtd
);
587 /* Return info from the table */
588 return nand_isreserved_bbt(mtd
, ofs
);
592 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
593 * @mtd: MTD device structure
594 * @ofs: offset from device start
595 * @allowbbt: 1, if its allowed to access the bbt area
597 * Check, if the block is bad. Either by reading the bad block table or
598 * calling of the scan function.
600 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
602 struct nand_chip
*chip
= mtd_to_nand(mtd
);
605 return chip
->block_bad(mtd
, ofs
);
607 /* Return info from the table */
608 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
612 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
613 * @mtd: MTD device structure
616 * Helper function for nand_wait_ready used when needing to wait in interrupt
619 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
621 struct nand_chip
*chip
= mtd_to_nand(mtd
);
624 /* Wait for the device to get ready */
625 for (i
= 0; i
< timeo
; i
++) {
626 if (chip
->dev_ready(mtd
))
628 touch_softlockup_watchdog();
634 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
635 * @mtd: MTD device structure
637 * Wait for the ready pin after a command, and warn if a timeout occurs.
639 void nand_wait_ready(struct mtd_info
*mtd
)
641 struct nand_chip
*chip
= mtd_to_nand(mtd
);
642 unsigned long timeo
= 400;
644 if (in_interrupt() || oops_in_progress
)
645 return panic_nand_wait_ready(mtd
, timeo
);
647 /* Wait until command is processed or timeout occurs */
648 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
650 if (chip
->dev_ready(mtd
))
653 } while (time_before(jiffies
, timeo
));
655 if (!chip
->dev_ready(mtd
))
656 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
658 EXPORT_SYMBOL_GPL(nand_wait_ready
);
661 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
662 * @mtd: MTD device structure
663 * @timeo: Timeout in ms
665 * Wait for status ready (i.e. command done) or timeout.
667 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
669 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
671 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
673 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
675 touch_softlockup_watchdog();
676 } while (time_before(jiffies
, timeo
));
680 * nand_command - [DEFAULT] Send command to NAND device
681 * @mtd: MTD device structure
682 * @command: the command to be sent
683 * @column: the column address for this command, -1 if none
684 * @page_addr: the page address for this command, -1 if none
686 * Send command to NAND device. This function is used for small page devices
687 * (512 Bytes per page).
689 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
690 int column
, int page_addr
)
692 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
693 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
695 /* Write out the command to the device */
696 if (command
== NAND_CMD_SEQIN
) {
699 if (column
>= mtd
->writesize
) {
701 column
-= mtd
->writesize
;
702 readcmd
= NAND_CMD_READOOB
;
703 } else if (column
< 256) {
704 /* First 256 bytes --> READ0 */
705 readcmd
= NAND_CMD_READ0
;
708 readcmd
= NAND_CMD_READ1
;
710 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
711 ctrl
&= ~NAND_CTRL_CHANGE
;
713 chip
->cmd_ctrl(mtd
, command
, ctrl
);
715 /* Address cycle, when necessary */
716 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
717 /* Serially input address */
719 /* Adjust columns for 16 bit buswidth */
720 if (chip
->options
& NAND_BUSWIDTH_16
&&
721 !nand_opcode_8bits(command
))
723 chip
->cmd_ctrl(mtd
, column
, ctrl
);
724 ctrl
&= ~NAND_CTRL_CHANGE
;
726 if (page_addr
!= -1) {
727 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
728 ctrl
&= ~NAND_CTRL_CHANGE
;
729 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
730 /* One more address cycle for devices > 32MiB */
731 if (chip
->chipsize
> (32 << 20))
732 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
734 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
737 * Program and erase have their own busy handlers status and sequential
742 case NAND_CMD_PAGEPROG
:
743 case NAND_CMD_ERASE1
:
744 case NAND_CMD_ERASE2
:
746 case NAND_CMD_STATUS
:
747 case NAND_CMD_READID
:
748 case NAND_CMD_SET_FEATURES
:
754 udelay(chip
->chip_delay
);
755 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
756 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
758 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
759 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
760 nand_wait_status_ready(mtd
, 250);
763 /* This applies to read commands */
766 * READ0 is sometimes used to exit GET STATUS mode. When this
767 * is the case no address cycles are requested, and we can use
768 * this information to detect that we should not wait for the
769 * device to be ready.
771 if (column
== -1 && page_addr
== -1)
776 * If we don't have access to the busy pin, we apply the given
779 if (!chip
->dev_ready
) {
780 udelay(chip
->chip_delay
);
785 * Apply this short delay always to ensure that we do wait tWB in
786 * any case on any machine.
790 nand_wait_ready(mtd
);
793 static void nand_ccs_delay(struct nand_chip
*chip
)
796 * The controller already takes care of waiting for tCCS when the RNDIN
797 * or RNDOUT command is sent, return directly.
799 if (!(chip
->options
& NAND_WAIT_TCCS
))
803 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
804 * (which should be safe for all NANDs).
806 if (chip
->data_interface
&& chip
->data_interface
->timings
.sdr
.tCCS_min
)
807 ndelay(chip
->data_interface
->timings
.sdr
.tCCS_min
/ 1000);
813 * nand_command_lp - [DEFAULT] Send command to NAND large page device
814 * @mtd: MTD device structure
815 * @command: the command to be sent
816 * @column: the column address for this command, -1 if none
817 * @page_addr: the page address for this command, -1 if none
819 * Send command to NAND device. This is the version for the new large page
820 * devices. We don't have the separate regions as we have in the small page
821 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
823 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
824 int column
, int page_addr
)
826 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
828 /* Emulate NAND_CMD_READOOB */
829 if (command
== NAND_CMD_READOOB
) {
830 column
+= mtd
->writesize
;
831 command
= NAND_CMD_READ0
;
834 /* Command latch cycle */
835 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
837 if (column
!= -1 || page_addr
!= -1) {
838 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
840 /* Serially input address */
842 /* Adjust columns for 16 bit buswidth */
843 if (chip
->options
& NAND_BUSWIDTH_16
&&
844 !nand_opcode_8bits(command
))
846 chip
->cmd_ctrl(mtd
, column
, ctrl
);
847 ctrl
&= ~NAND_CTRL_CHANGE
;
849 /* Only output a single addr cycle for 8bits opcodes. */
850 if (!nand_opcode_8bits(command
))
851 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
853 if (page_addr
!= -1) {
854 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
855 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
856 NAND_NCE
| NAND_ALE
);
857 /* One more address cycle for devices > 128MiB */
858 if (chip
->chipsize
> (128 << 20))
859 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
860 NAND_NCE
| NAND_ALE
);
863 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
866 * Program and erase have their own busy handlers status, sequential
867 * in and status need no delay.
871 case NAND_CMD_CACHEDPROG
:
872 case NAND_CMD_PAGEPROG
:
873 case NAND_CMD_ERASE1
:
874 case NAND_CMD_ERASE2
:
876 case NAND_CMD_STATUS
:
877 case NAND_CMD_READID
:
878 case NAND_CMD_SET_FEATURES
:
882 nand_ccs_delay(chip
);
888 udelay(chip
->chip_delay
);
889 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
890 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
891 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
892 NAND_NCE
| NAND_CTRL_CHANGE
);
893 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
894 nand_wait_status_ready(mtd
, 250);
897 case NAND_CMD_RNDOUT
:
898 /* No ready / busy check necessary */
899 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
900 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
901 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
902 NAND_NCE
| NAND_CTRL_CHANGE
);
904 nand_ccs_delay(chip
);
909 * READ0 is sometimes used to exit GET STATUS mode. When this
910 * is the case no address cycles are requested, and we can use
911 * this information to detect that READSTART should not be
914 if (column
== -1 && page_addr
== -1)
917 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
918 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
919 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
920 NAND_NCE
| NAND_CTRL_CHANGE
);
922 /* This applies to read commands */
925 * If we don't have access to the busy pin, we apply the given
928 if (!chip
->dev_ready
) {
929 udelay(chip
->chip_delay
);
935 * Apply this short delay always to ensure that we do wait tWB in
936 * any case on any machine.
940 nand_wait_ready(mtd
);
944 * panic_nand_get_device - [GENERIC] Get chip for selected access
945 * @chip: the nand chip descriptor
946 * @mtd: MTD device structure
947 * @new_state: the state which is requested
949 * Used when in panic, no locks are taken.
951 static void panic_nand_get_device(struct nand_chip
*chip
,
952 struct mtd_info
*mtd
, int new_state
)
954 /* Hardware controller shared among independent devices */
955 chip
->controller
->active
= chip
;
956 chip
->state
= new_state
;
960 * nand_get_device - [GENERIC] Get chip for selected access
961 * @mtd: MTD device structure
962 * @new_state: the state which is requested
964 * Get the device and lock it for exclusive access
967 nand_get_device(struct mtd_info
*mtd
, int new_state
)
969 struct nand_chip
*chip
= mtd_to_nand(mtd
);
970 spinlock_t
*lock
= &chip
->controller
->lock
;
971 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
972 DECLARE_WAITQUEUE(wait
, current
);
976 /* Hardware controller shared among independent devices */
977 if (!chip
->controller
->active
)
978 chip
->controller
->active
= chip
;
980 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
981 chip
->state
= new_state
;
985 if (new_state
== FL_PM_SUSPENDED
) {
986 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
987 chip
->state
= FL_PM_SUSPENDED
;
992 set_current_state(TASK_UNINTERRUPTIBLE
);
993 add_wait_queue(wq
, &wait
);
996 remove_wait_queue(wq
, &wait
);
1001 * panic_nand_wait - [GENERIC] wait until the command is done
1002 * @mtd: MTD device structure
1003 * @chip: NAND chip structure
1006 * Wait for command done. This is a helper function for nand_wait used when
1007 * we are in interrupt context. May happen when in panic and trying to write
1008 * an oops through mtdoops.
1010 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1011 unsigned long timeo
)
1014 for (i
= 0; i
< timeo
; i
++) {
1015 if (chip
->dev_ready
) {
1016 if (chip
->dev_ready(mtd
))
1019 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
1027 * nand_wait - [DEFAULT] wait until the command is done
1028 * @mtd: MTD device structure
1029 * @chip: NAND chip structure
1031 * Wait for command done. This applies to erase and program only.
1033 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
1037 unsigned long timeo
= 400;
1040 * Apply this short delay always to ensure that we do wait tWB in any
1041 * case on any machine.
1045 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
1047 if (in_interrupt() || oops_in_progress
)
1048 panic_nand_wait(mtd
, chip
, timeo
);
1050 timeo
= jiffies
+ msecs_to_jiffies(timeo
);
1052 if (chip
->dev_ready
) {
1053 if (chip
->dev_ready(mtd
))
1056 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
1060 } while (time_before(jiffies
, timeo
));
1063 status
= (int)chip
->read_byte(mtd
);
1064 /* This can happen if in case of timeout or buggy dev_ready */
1065 WARN_ON(!(status
& NAND_STATUS_READY
));
1070 * nand_reset_data_interface - Reset data interface and timings
1071 * @chip: The NAND chip
1072 * @chipnr: Internal die id
1074 * Reset the Data interface and timings to ONFI mode 0.
1076 * Returns 0 for success or negative error code otherwise.
1078 static int nand_reset_data_interface(struct nand_chip
*chip
, int chipnr
)
1080 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1081 const struct nand_data_interface
*conf
;
1084 if (!chip
->setup_data_interface
)
1088 * The ONFI specification says:
1090 * To transition from NV-DDR or NV-DDR2 to the SDR data
1091 * interface, the host shall use the Reset (FFh) command
1092 * using SDR timing mode 0. A device in any timing mode is
1093 * required to recognize Reset (FFh) command issued in SDR
1097 * Configure the data interface in SDR mode and set the
1098 * timings to timing mode 0.
1101 conf
= nand_get_default_data_interface();
1102 ret
= chip
->setup_data_interface(mtd
, chipnr
, conf
);
1104 pr_err("Failed to configure data interface to SDR timing mode 0\n");
1110 * nand_setup_data_interface - Setup the best data interface and timings
1111 * @chip: The NAND chip
1112 * @chipnr: Internal die id
1114 * Find and configure the best data interface and NAND timings supported by
1115 * the chip and the driver.
1116 * First tries to retrieve supported timing modes from ONFI information,
1117 * and if the NAND chip does not support ONFI, relies on the
1118 * ->onfi_timing_mode_default specified in the nand_ids table.
1120 * Returns 0 for success or negative error code otherwise.
1122 static int nand_setup_data_interface(struct nand_chip
*chip
, int chipnr
)
1124 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1127 if (!chip
->setup_data_interface
|| !chip
->data_interface
)
1131 * Ensure the timing mode has been changed on the chip side
1132 * before changing timings on the controller side.
1134 if (chip
->onfi_version
&&
1135 (le16_to_cpu(chip
->onfi_params
.opt_cmd
) &
1136 ONFI_OPT_CMD_SET_GET_FEATURES
)) {
1137 u8 tmode_param
[ONFI_SUBFEATURE_PARAM_LEN
] = {
1138 chip
->onfi_timing_mode_default
,
1141 ret
= chip
->onfi_set_features(mtd
, chip
,
1142 ONFI_FEATURE_ADDR_TIMING_MODE
,
1148 ret
= chip
->setup_data_interface(mtd
, chipnr
, chip
->data_interface
);
1154 * nand_init_data_interface - find the best data interface and timings
1155 * @chip: The NAND chip
1157 * Find the best data interface and NAND timings supported by the chip
1159 * First tries to retrieve supported timing modes from ONFI information,
1160 * and if the NAND chip does not support ONFI, relies on the
1161 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1162 * function nand_chip->data_interface is initialized with the best timing mode
1165 * Returns 0 for success or negative error code otherwise.
1167 static int nand_init_data_interface(struct nand_chip
*chip
)
1169 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1170 int modes
, mode
, ret
;
1172 if (!chip
->setup_data_interface
)
1176 * First try to identify the best timings from ONFI parameters and
1177 * if the NAND does not support ONFI, fallback to the default ONFI
1180 modes
= onfi_get_async_timing_mode(chip
);
1181 if (modes
== ONFI_TIMING_MODE_UNKNOWN
) {
1182 if (!chip
->onfi_timing_mode_default
)
1185 modes
= GENMASK(chip
->onfi_timing_mode_default
, 0);
1188 chip
->data_interface
= kzalloc(sizeof(*chip
->data_interface
),
1190 if (!chip
->data_interface
)
1193 for (mode
= fls(modes
) - 1; mode
>= 0; mode
--) {
1194 ret
= onfi_init_data_interface(chip
, chip
->data_interface
,
1195 NAND_SDR_IFACE
, mode
);
1199 /* Pass -1 to only */
1200 ret
= chip
->setup_data_interface(mtd
,
1201 NAND_DATA_IFACE_CHECK_ONLY
,
1202 chip
->data_interface
);
1204 chip
->onfi_timing_mode_default
= mode
;
1212 static void nand_release_data_interface(struct nand_chip
*chip
)
1214 kfree(chip
->data_interface
);
1218 * nand_reset - Reset and initialize a NAND device
1219 * @chip: The NAND chip
1220 * @chipnr: Internal die id
1222 * Returns 0 for success or negative error code otherwise
1224 int nand_reset(struct nand_chip
*chip
, int chipnr
)
1226 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1229 ret
= nand_reset_data_interface(chip
, chipnr
);
1234 * The CS line has to be released before we can apply the new NAND
1235 * interface settings, hence this weird ->select_chip() dance.
1237 chip
->select_chip(mtd
, chipnr
);
1238 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1239 chip
->select_chip(mtd
, -1);
1241 chip
->select_chip(mtd
, chipnr
);
1242 ret
= nand_setup_data_interface(chip
, chipnr
);
1243 chip
->select_chip(mtd
, -1);
1251 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1253 * @ofs: offset to start unlock from
1254 * @len: length to unlock
1256 * - when = 0, unlock the range of blocks within the lower and
1257 * upper boundary address
1258 * - when = 1, unlock the range of blocks outside the boundaries
1259 * of the lower and upper boundary address
1261 * Returs unlock status.
1263 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
1264 uint64_t len
, int invert
)
1268 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1270 /* Submit address of first page to unlock */
1271 page
= ofs
>> chip
->page_shift
;
1272 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
1274 /* Submit address of last page to unlock */
1275 page
= (ofs
+ len
) >> chip
->page_shift
;
1276 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
1277 (page
| invert
) & chip
->pagemask
);
1279 /* Call wait ready function */
1280 status
= chip
->waitfunc(mtd
, chip
);
1281 /* See if device thinks it succeeded */
1282 if (status
& NAND_STATUS_FAIL
) {
1283 pr_debug("%s: error status = 0x%08x\n",
1292 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1294 * @ofs: offset to start unlock from
1295 * @len: length to unlock
1297 * Returns unlock status.
1299 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1303 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1305 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1306 __func__
, (unsigned long long)ofs
, len
);
1308 if (check_offs_len(mtd
, ofs
, len
))
1311 /* Align to last block address if size addresses end of the device */
1312 if (ofs
+ len
== mtd
->size
)
1313 len
-= mtd
->erasesize
;
1315 nand_get_device(mtd
, FL_UNLOCKING
);
1317 /* Shift to get chip number */
1318 chipnr
= ofs
>> chip
->chip_shift
;
1322 * If we want to check the WP through READ STATUS and check the bit 7
1323 * we must reset the chip
1324 * some operation can also clear the bit 7 of status register
1325 * eg. erase/program a locked block
1327 nand_reset(chip
, chipnr
);
1329 chip
->select_chip(mtd
, chipnr
);
1331 /* Check, if it is write protected */
1332 if (nand_check_wp(mtd
)) {
1333 pr_debug("%s: device is write protected!\n",
1339 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
1342 chip
->select_chip(mtd
, -1);
1343 nand_release_device(mtd
);
1347 EXPORT_SYMBOL(nand_unlock
);
1350 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1352 * @ofs: offset to start unlock from
1353 * @len: length to unlock
1355 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1356 * have this feature, but it allows only to lock all blocks, not for specified
1357 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1360 * Returns lock status.
1362 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
1365 int chipnr
, status
, page
;
1366 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1368 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1369 __func__
, (unsigned long long)ofs
, len
);
1371 if (check_offs_len(mtd
, ofs
, len
))
1374 nand_get_device(mtd
, FL_LOCKING
);
1376 /* Shift to get chip number */
1377 chipnr
= ofs
>> chip
->chip_shift
;
1381 * If we want to check the WP through READ STATUS and check the bit 7
1382 * we must reset the chip
1383 * some operation can also clear the bit 7 of status register
1384 * eg. erase/program a locked block
1386 nand_reset(chip
, chipnr
);
1388 chip
->select_chip(mtd
, chipnr
);
1390 /* Check, if it is write protected */
1391 if (nand_check_wp(mtd
)) {
1392 pr_debug("%s: device is write protected!\n",
1394 status
= MTD_ERASE_FAILED
;
1399 /* Submit address of first page to lock */
1400 page
= ofs
>> chip
->page_shift
;
1401 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1403 /* Call wait ready function */
1404 status
= chip
->waitfunc(mtd
, chip
);
1405 /* See if device thinks it succeeded */
1406 if (status
& NAND_STATUS_FAIL
) {
1407 pr_debug("%s: error status = 0x%08x\n",
1413 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1416 chip
->select_chip(mtd
, -1);
1417 nand_release_device(mtd
);
1421 EXPORT_SYMBOL(nand_lock
);
1424 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1425 * @buf: buffer to test
1426 * @len: buffer length
1427 * @bitflips_threshold: maximum number of bitflips
1429 * Check if a buffer contains only 0xff, which means the underlying region
1430 * has been erased and is ready to be programmed.
1431 * The bitflips_threshold specify the maximum number of bitflips before
1432 * considering the region is not erased.
1433 * Note: The logic of this function has been extracted from the memweight
1434 * implementation, except that nand_check_erased_buf function exit before
1435 * testing the whole buffer if the number of bitflips exceed the
1436 * bitflips_threshold value.
1438 * Returns a positive number of bitflips less than or equal to
1439 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1442 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1444 const unsigned char *bitmap
= buf
;
1448 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1450 weight
= hweight8(*bitmap
);
1451 bitflips
+= BITS_PER_BYTE
- weight
;
1452 if (unlikely(bitflips
> bitflips_threshold
))
1456 for (; len
>= sizeof(long);
1457 len
-= sizeof(long), bitmap
+= sizeof(long)) {
1458 unsigned long d
= *((unsigned long *)bitmap
);
1461 weight
= hweight_long(d
);
1462 bitflips
+= BITS_PER_LONG
- weight
;
1463 if (unlikely(bitflips
> bitflips_threshold
))
1467 for (; len
> 0; len
--, bitmap
++) {
1468 weight
= hweight8(*bitmap
);
1469 bitflips
+= BITS_PER_BYTE
- weight
;
1470 if (unlikely(bitflips
> bitflips_threshold
))
1478 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1480 * @data: data buffer to test
1481 * @datalen: data length
1483 * @ecclen: ECC length
1484 * @extraoob: extra OOB buffer
1485 * @extraooblen: extra OOB length
1486 * @bitflips_threshold: maximum number of bitflips
1488 * Check if a data buffer and its associated ECC and OOB data contains only
1489 * 0xff pattern, which means the underlying region has been erased and is
1490 * ready to be programmed.
1491 * The bitflips_threshold specify the maximum number of bitflips before
1492 * considering the region as not erased.
1495 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1496 * different from the NAND page size. When fixing bitflips, ECC engines will
1497 * report the number of errors per chunk, and the NAND core infrastructure
1498 * expect you to return the maximum number of bitflips for the whole page.
1499 * This is why you should always use this function on a single chunk and
1500 * not on the whole page. After checking each chunk you should update your
1501 * max_bitflips value accordingly.
1502 * 2/ When checking for bitflips in erased pages you should not only check
1503 * the payload data but also their associated ECC data, because a user might
1504 * have programmed almost all bits to 1 but a few. In this case, we
1505 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1507 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1508 * data are protected by the ECC engine.
1509 * It could also be used if you support subpages and want to attach some
1510 * extra OOB data to an ECC chunk.
1512 * Returns a positive number of bitflips less than or equal to
1513 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1514 * threshold. In case of success, the passed buffers are filled with 0xff.
1516 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1517 void *ecc
, int ecclen
,
1518 void *extraoob
, int extraooblen
,
1519 int bitflips_threshold
)
1521 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1523 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1524 bitflips_threshold
);
1525 if (data_bitflips
< 0)
1526 return data_bitflips
;
1528 bitflips_threshold
-= data_bitflips
;
1530 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1531 if (ecc_bitflips
< 0)
1532 return ecc_bitflips
;
1534 bitflips_threshold
-= ecc_bitflips
;
1536 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1537 bitflips_threshold
);
1538 if (extraoob_bitflips
< 0)
1539 return extraoob_bitflips
;
1542 memset(data
, 0xff, datalen
);
1545 memset(ecc
, 0xff, ecclen
);
1547 if (extraoob_bitflips
)
1548 memset(extraoob
, 0xff, extraooblen
);
1550 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1552 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1555 * nand_read_page_raw - [INTERN] read raw page data without ecc
1556 * @mtd: mtd info structure
1557 * @chip: nand chip info structure
1558 * @buf: buffer to store read data
1559 * @oob_required: caller requires OOB data read to chip->oob_poi
1560 * @page: page number to read
1562 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1564 int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1565 uint8_t *buf
, int oob_required
, int page
)
1567 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1569 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1572 EXPORT_SYMBOL(nand_read_page_raw
);
1575 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1576 * @mtd: mtd info structure
1577 * @chip: nand chip info structure
1578 * @buf: buffer to store read data
1579 * @oob_required: caller requires OOB data read to chip->oob_poi
1580 * @page: page number to read
1582 * We need a special oob layout and handling even when OOB isn't used.
1584 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1585 struct nand_chip
*chip
, uint8_t *buf
,
1586 int oob_required
, int page
)
1588 int eccsize
= chip
->ecc
.size
;
1589 int eccbytes
= chip
->ecc
.bytes
;
1590 uint8_t *oob
= chip
->oob_poi
;
1593 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1594 chip
->read_buf(mtd
, buf
, eccsize
);
1597 if (chip
->ecc
.prepad
) {
1598 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1599 oob
+= chip
->ecc
.prepad
;
1602 chip
->read_buf(mtd
, oob
, eccbytes
);
1605 if (chip
->ecc
.postpad
) {
1606 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1607 oob
+= chip
->ecc
.postpad
;
1611 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1613 chip
->read_buf(mtd
, oob
, size
);
1619 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1620 * @mtd: mtd info structure
1621 * @chip: nand chip info structure
1622 * @buf: buffer to store read data
1623 * @oob_required: caller requires OOB data read to chip->oob_poi
1624 * @page: page number to read
1626 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1627 uint8_t *buf
, int oob_required
, int page
)
1629 int i
, eccsize
= chip
->ecc
.size
, ret
;
1630 int eccbytes
= chip
->ecc
.bytes
;
1631 int eccsteps
= chip
->ecc
.steps
;
1633 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1634 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1635 unsigned int max_bitflips
= 0;
1637 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1639 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1640 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1642 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1647 eccsteps
= chip
->ecc
.steps
;
1650 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1653 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1655 mtd
->ecc_stats
.failed
++;
1657 mtd
->ecc_stats
.corrected
+= stat
;
1658 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1661 return max_bitflips
;
1665 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1666 * @mtd: mtd info structure
1667 * @chip: nand chip info structure
1668 * @data_offs: offset of requested data within the page
1669 * @readlen: data length
1670 * @bufpoi: buffer to store read data
1671 * @page: page number to read
1673 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1674 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1677 int start_step
, end_step
, num_steps
, ret
;
1679 int data_col_addr
, i
, gaps
= 0;
1680 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1681 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1682 int index
, section
= 0;
1683 unsigned int max_bitflips
= 0;
1684 struct mtd_oob_region oobregion
= { };
1686 /* Column address within the page aligned to ECC size (256bytes) */
1687 start_step
= data_offs
/ chip
->ecc
.size
;
1688 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1689 num_steps
= end_step
- start_step
+ 1;
1690 index
= start_step
* chip
->ecc
.bytes
;
1692 /* Data size aligned to ECC ecc.size */
1693 datafrag_len
= num_steps
* chip
->ecc
.size
;
1694 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1696 data_col_addr
= start_step
* chip
->ecc
.size
;
1697 /* If we read not a page aligned data */
1698 if (data_col_addr
!= 0)
1699 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1701 p
= bufpoi
+ data_col_addr
;
1702 chip
->read_buf(mtd
, p
, datafrag_len
);
1705 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1706 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1709 * The performance is faster if we position offsets according to
1710 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1712 ret
= mtd_ooblayout_find_eccregion(mtd
, index
, §ion
, &oobregion
);
1716 if (oobregion
.length
< eccfrag_len
)
1720 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1721 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1724 * Send the command to read the particular ECC bytes take care
1725 * about buswidth alignment in read_buf.
1727 aligned_pos
= oobregion
.offset
& ~(busw
- 1);
1728 aligned_len
= eccfrag_len
;
1729 if (oobregion
.offset
& (busw
- 1))
1731 if ((oobregion
.offset
+ (num_steps
* chip
->ecc
.bytes
)) &
1735 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1736 mtd
->writesize
+ aligned_pos
, -1);
1737 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1740 ret
= mtd_ooblayout_get_eccbytes(mtd
, chip
->buffers
->ecccode
,
1741 chip
->oob_poi
, index
, eccfrag_len
);
1745 p
= bufpoi
+ data_col_addr
;
1746 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1749 stat
= chip
->ecc
.correct(mtd
, p
,
1750 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1751 if (stat
== -EBADMSG
&&
1752 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1753 /* check for empty pages with bitflips */
1754 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1755 &chip
->buffers
->ecccode
[i
],
1758 chip
->ecc
.strength
);
1762 mtd
->ecc_stats
.failed
++;
1764 mtd
->ecc_stats
.corrected
+= stat
;
1765 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1768 return max_bitflips
;
1772 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1773 * @mtd: mtd info structure
1774 * @chip: nand chip info structure
1775 * @buf: buffer to store read data
1776 * @oob_required: caller requires OOB data read to chip->oob_poi
1777 * @page: page number to read
1779 * Not for syndrome calculating ECC controllers which need a special oob layout.
1781 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1782 uint8_t *buf
, int oob_required
, int page
)
1784 int i
, eccsize
= chip
->ecc
.size
, ret
;
1785 int eccbytes
= chip
->ecc
.bytes
;
1786 int eccsteps
= chip
->ecc
.steps
;
1788 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1789 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1790 unsigned int max_bitflips
= 0;
1792 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1793 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1794 chip
->read_buf(mtd
, p
, eccsize
);
1795 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1797 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1799 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1804 eccsteps
= chip
->ecc
.steps
;
1807 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1810 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1811 if (stat
== -EBADMSG
&&
1812 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1813 /* check for empty pages with bitflips */
1814 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1815 &ecc_code
[i
], eccbytes
,
1817 chip
->ecc
.strength
);
1821 mtd
->ecc_stats
.failed
++;
1823 mtd
->ecc_stats
.corrected
+= stat
;
1824 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1827 return max_bitflips
;
1831 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1832 * @mtd: mtd info structure
1833 * @chip: nand chip info structure
1834 * @buf: buffer to store read data
1835 * @oob_required: caller requires OOB data read to chip->oob_poi
1836 * @page: page number to read
1838 * Hardware ECC for large page chips, require OOB to be read first. For this
1839 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1840 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1841 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1842 * the data area, by overwriting the NAND manufacturer bad block markings.
1844 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1845 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1847 int i
, eccsize
= chip
->ecc
.size
, ret
;
1848 int eccbytes
= chip
->ecc
.bytes
;
1849 int eccsteps
= chip
->ecc
.steps
;
1851 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1852 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1853 unsigned int max_bitflips
= 0;
1855 /* Read the OOB area first */
1856 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1857 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1858 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1860 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1865 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1868 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1869 chip
->read_buf(mtd
, p
, eccsize
);
1870 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1872 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1873 if (stat
== -EBADMSG
&&
1874 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1875 /* check for empty pages with bitflips */
1876 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1877 &ecc_code
[i
], eccbytes
,
1879 chip
->ecc
.strength
);
1883 mtd
->ecc_stats
.failed
++;
1885 mtd
->ecc_stats
.corrected
+= stat
;
1886 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1889 return max_bitflips
;
1893 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1894 * @mtd: mtd info structure
1895 * @chip: nand chip info structure
1896 * @buf: buffer to store read data
1897 * @oob_required: caller requires OOB data read to chip->oob_poi
1898 * @page: page number to read
1900 * The hw generator calculates the error syndrome automatically. Therefore we
1901 * need a special oob layout and handling.
1903 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1904 uint8_t *buf
, int oob_required
, int page
)
1906 int i
, eccsize
= chip
->ecc
.size
;
1907 int eccbytes
= chip
->ecc
.bytes
;
1908 int eccsteps
= chip
->ecc
.steps
;
1909 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1911 uint8_t *oob
= chip
->oob_poi
;
1912 unsigned int max_bitflips
= 0;
1914 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1917 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1918 chip
->read_buf(mtd
, p
, eccsize
);
1920 if (chip
->ecc
.prepad
) {
1921 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1922 oob
+= chip
->ecc
.prepad
;
1925 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1926 chip
->read_buf(mtd
, oob
, eccbytes
);
1927 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1931 if (chip
->ecc
.postpad
) {
1932 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1933 oob
+= chip
->ecc
.postpad
;
1936 if (stat
== -EBADMSG
&&
1937 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1938 /* check for empty pages with bitflips */
1939 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1943 chip
->ecc
.strength
);
1947 mtd
->ecc_stats
.failed
++;
1949 mtd
->ecc_stats
.corrected
+= stat
;
1950 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1954 /* Calculate remaining oob bytes */
1955 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1957 chip
->read_buf(mtd
, oob
, i
);
1959 return max_bitflips
;
1963 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1964 * @mtd: mtd info structure
1965 * @oob: oob destination address
1966 * @ops: oob ops structure
1967 * @len: size of oob to transfer
1969 static uint8_t *nand_transfer_oob(struct mtd_info
*mtd
, uint8_t *oob
,
1970 struct mtd_oob_ops
*ops
, size_t len
)
1972 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1975 switch (ops
->mode
) {
1977 case MTD_OPS_PLACE_OOB
:
1979 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1982 case MTD_OPS_AUTO_OOB
:
1983 ret
= mtd_ooblayout_get_databytes(mtd
, oob
, chip
->oob_poi
,
1995 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1996 * @mtd: MTD device structure
1997 * @retry_mode: the retry mode to use
1999 * Some vendors supply a special command to shift the Vt threshold, to be used
2000 * when there are too many bitflips in a page (i.e., ECC error). After setting
2001 * a new threshold, the host should retry reading the page.
2003 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
2005 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2007 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
2009 if (retry_mode
>= chip
->read_retries
)
2012 if (!chip
->setup_read_retry
)
2015 return chip
->setup_read_retry(mtd
, retry_mode
);
2019 * nand_do_read_ops - [INTERN] Read data with ECC
2020 * @mtd: MTD device structure
2021 * @from: offset to read from
2022 * @ops: oob ops structure
2024 * Internal function. Called with chip held.
2026 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
2027 struct mtd_oob_ops
*ops
)
2029 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
2030 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2032 uint32_t readlen
= ops
->len
;
2033 uint32_t oobreadlen
= ops
->ooblen
;
2034 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
2036 uint8_t *bufpoi
, *oob
, *buf
;
2038 unsigned int max_bitflips
= 0;
2040 bool ecc_fail
= false;
2042 chipnr
= (int)(from
>> chip
->chip_shift
);
2043 chip
->select_chip(mtd
, chipnr
);
2045 realpage
= (int)(from
>> chip
->page_shift
);
2046 page
= realpage
& chip
->pagemask
;
2048 col
= (int)(from
& (mtd
->writesize
- 1));
2052 oob_required
= oob
? 1 : 0;
2055 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
2057 bytes
= min(mtd
->writesize
- col
, readlen
);
2058 aligned
= (bytes
== mtd
->writesize
);
2062 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2063 use_bufpoi
= !virt_addr_valid(buf
) ||
2064 !IS_ALIGNED((unsigned long)buf
,
2069 /* Is the current page in the buffer? */
2070 if (realpage
!= chip
->pagebuf
|| oob
) {
2071 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
2073 if (use_bufpoi
&& aligned
)
2074 pr_debug("%s: using read bounce buffer for buf@%p\n",
2078 if (nand_standard_page_accessors(&chip
->ecc
))
2079 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
2082 * Now read the page into the buffer. Absent an error,
2083 * the read methods return max bitflips per ecc step.
2085 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
2086 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
2089 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
2091 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
2095 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
2096 oob_required
, page
);
2099 /* Invalidate page cache */
2104 /* Transfer not aligned data */
2106 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
2107 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
2108 (ops
->mode
!= MTD_OPS_RAW
)) {
2109 chip
->pagebuf
= realpage
;
2110 chip
->pagebuf_bitflips
= ret
;
2112 /* Invalidate page cache */
2115 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
2118 if (unlikely(oob
)) {
2119 int toread
= min(oobreadlen
, max_oobsize
);
2122 oob
= nand_transfer_oob(mtd
,
2124 oobreadlen
-= toread
;
2128 if (chip
->options
& NAND_NEED_READRDY
) {
2129 /* Apply delay or wait for ready/busy pin */
2130 if (!chip
->dev_ready
)
2131 udelay(chip
->chip_delay
);
2133 nand_wait_ready(mtd
);
2136 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
2137 if (retry_mode
+ 1 < chip
->read_retries
) {
2139 ret
= nand_setup_read_retry(mtd
,
2144 /* Reset failures; retry */
2145 mtd
->ecc_stats
.failed
= ecc_failures
;
2148 /* No more retry modes; real failure */
2154 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
2156 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
2158 max_bitflips
= max_t(unsigned int, max_bitflips
,
2159 chip
->pagebuf_bitflips
);
2164 /* Reset to retry mode 0 */
2166 ret
= nand_setup_read_retry(mtd
, 0);
2175 /* For subsequent reads align to page boundary */
2177 /* Increment page address */
2180 page
= realpage
& chip
->pagemask
;
2181 /* Check, if we cross a chip boundary */
2184 chip
->select_chip(mtd
, -1);
2185 chip
->select_chip(mtd
, chipnr
);
2188 chip
->select_chip(mtd
, -1);
2190 ops
->retlen
= ops
->len
- (size_t) readlen
;
2192 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
2200 return max_bitflips
;
2204 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
2205 * @mtd: MTD device structure
2206 * @from: offset to read from
2207 * @len: number of bytes to read
2208 * @retlen: pointer to variable to store the number of read bytes
2209 * @buf: the databuffer to put data
2211 * Get hold of the chip and call nand_do_read.
2213 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
2214 size_t *retlen
, uint8_t *buf
)
2216 struct mtd_oob_ops ops
;
2219 nand_get_device(mtd
, FL_READING
);
2220 memset(&ops
, 0, sizeof(ops
));
2223 ops
.mode
= MTD_OPS_PLACE_OOB
;
2224 ret
= nand_do_read_ops(mtd
, from
, &ops
);
2225 *retlen
= ops
.retlen
;
2226 nand_release_device(mtd
);
2231 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
2232 * @mtd: mtd info structure
2233 * @chip: nand chip info structure
2234 * @page: page number to read
2236 int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
2238 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
2239 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2242 EXPORT_SYMBOL(nand_read_oob_std
);
2245 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
2247 * @mtd: mtd info structure
2248 * @chip: nand chip info structure
2249 * @page: page number to read
2251 int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2254 int length
= mtd
->oobsize
;
2255 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2256 int eccsize
= chip
->ecc
.size
;
2257 uint8_t *bufpoi
= chip
->oob_poi
;
2258 int i
, toread
, sndrnd
= 0, pos
;
2260 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
2261 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
2263 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2264 if (mtd
->writesize
> 512)
2265 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
2267 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
2270 toread
= min_t(int, length
, chunk
);
2271 chip
->read_buf(mtd
, bufpoi
, toread
);
2276 chip
->read_buf(mtd
, bufpoi
, length
);
2280 EXPORT_SYMBOL(nand_read_oob_syndrome
);
2283 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
2284 * @mtd: mtd info structure
2285 * @chip: nand chip info structure
2286 * @page: page number to write
2288 int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
, int page
)
2291 const uint8_t *buf
= chip
->oob_poi
;
2292 int length
= mtd
->oobsize
;
2294 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
2295 chip
->write_buf(mtd
, buf
, length
);
2296 /* Send command to program the OOB data */
2297 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2299 status
= chip
->waitfunc(mtd
, chip
);
2301 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2303 EXPORT_SYMBOL(nand_write_oob_std
);
2306 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
2307 * with syndrome - only for large page flash
2308 * @mtd: mtd info structure
2309 * @chip: nand chip info structure
2310 * @page: page number to write
2312 int nand_write_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2315 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
2316 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
2317 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
2318 const uint8_t *bufpoi
= chip
->oob_poi
;
2321 * data-ecc-data-ecc ... ecc-oob
2323 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2325 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
2326 pos
= steps
* (eccsize
+ chunk
);
2331 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
2332 for (i
= 0; i
< steps
; i
++) {
2334 if (mtd
->writesize
<= 512) {
2335 uint32_t fill
= 0xFFFFFFFF;
2339 int num
= min_t(int, len
, 4);
2340 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2345 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2346 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2350 len
= min_t(int, length
, chunk
);
2351 chip
->write_buf(mtd
, bufpoi
, len
);
2356 chip
->write_buf(mtd
, bufpoi
, length
);
2358 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2359 status
= chip
->waitfunc(mtd
, chip
);
2361 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2363 EXPORT_SYMBOL(nand_write_oob_syndrome
);
2366 * nand_do_read_oob - [INTERN] NAND read out-of-band
2367 * @mtd: MTD device structure
2368 * @from: offset to read from
2369 * @ops: oob operations description structure
2371 * NAND read out-of-band data from the spare area.
2373 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2374 struct mtd_oob_ops
*ops
)
2376 int page
, realpage
, chipnr
;
2377 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2378 struct mtd_ecc_stats stats
;
2379 int readlen
= ops
->ooblen
;
2381 uint8_t *buf
= ops
->oobbuf
;
2384 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2385 __func__
, (unsigned long long)from
, readlen
);
2387 stats
= mtd
->ecc_stats
;
2389 len
= mtd_oobavail(mtd
, ops
);
2391 if (unlikely(ops
->ooboffs
>= len
)) {
2392 pr_debug("%s: attempt to start read outside oob\n",
2397 /* Do not allow reads past end of device */
2398 if (unlikely(from
>= mtd
->size
||
2399 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2400 (from
>> chip
->page_shift
)) * len
)) {
2401 pr_debug("%s: attempt to read beyond end of device\n",
2406 chipnr
= (int)(from
>> chip
->chip_shift
);
2407 chip
->select_chip(mtd
, chipnr
);
2409 /* Shift to get page */
2410 realpage
= (int)(from
>> chip
->page_shift
);
2411 page
= realpage
& chip
->pagemask
;
2414 if (ops
->mode
== MTD_OPS_RAW
)
2415 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2417 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2422 len
= min(len
, readlen
);
2423 buf
= nand_transfer_oob(mtd
, buf
, ops
, len
);
2425 if (chip
->options
& NAND_NEED_READRDY
) {
2426 /* Apply delay or wait for ready/busy pin */
2427 if (!chip
->dev_ready
)
2428 udelay(chip
->chip_delay
);
2430 nand_wait_ready(mtd
);
2437 /* Increment page address */
2440 page
= realpage
& chip
->pagemask
;
2441 /* Check, if we cross a chip boundary */
2444 chip
->select_chip(mtd
, -1);
2445 chip
->select_chip(mtd
, chipnr
);
2448 chip
->select_chip(mtd
, -1);
2450 ops
->oobretlen
= ops
->ooblen
- readlen
;
2455 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2458 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2462 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2463 * @mtd: MTD device structure
2464 * @from: offset to read from
2465 * @ops: oob operation description structure
2467 * NAND read data and/or out-of-band data.
2469 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2470 struct mtd_oob_ops
*ops
)
2476 /* Do not allow reads past end of device */
2477 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2478 pr_debug("%s: attempt to read beyond end of device\n",
2483 if (ops
->mode
!= MTD_OPS_PLACE_OOB
&&
2484 ops
->mode
!= MTD_OPS_AUTO_OOB
&&
2485 ops
->mode
!= MTD_OPS_RAW
)
2488 nand_get_device(mtd
, FL_READING
);
2491 ret
= nand_do_read_oob(mtd
, from
, ops
);
2493 ret
= nand_do_read_ops(mtd
, from
, ops
);
2495 nand_release_device(mtd
);
2501 * nand_write_page_raw - [INTERN] raw page write function
2502 * @mtd: mtd info structure
2503 * @chip: nand chip info structure
2505 * @oob_required: must write chip->oob_poi to OOB
2506 * @page: page number to write
2508 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2510 int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2511 const uint8_t *buf
, int oob_required
, int page
)
2513 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2515 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2519 EXPORT_SYMBOL(nand_write_page_raw
);
2522 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2523 * @mtd: mtd info structure
2524 * @chip: nand chip info structure
2526 * @oob_required: must write chip->oob_poi to OOB
2527 * @page: page number to write
2529 * We need a special oob layout and handling even when ECC isn't checked.
2531 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2532 struct nand_chip
*chip
,
2533 const uint8_t *buf
, int oob_required
,
2536 int eccsize
= chip
->ecc
.size
;
2537 int eccbytes
= chip
->ecc
.bytes
;
2538 uint8_t *oob
= chip
->oob_poi
;
2541 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2542 chip
->write_buf(mtd
, buf
, eccsize
);
2545 if (chip
->ecc
.prepad
) {
2546 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2547 oob
+= chip
->ecc
.prepad
;
2550 chip
->write_buf(mtd
, oob
, eccbytes
);
2553 if (chip
->ecc
.postpad
) {
2554 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2555 oob
+= chip
->ecc
.postpad
;
2559 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2561 chip
->write_buf(mtd
, oob
, size
);
2566 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2567 * @mtd: mtd info structure
2568 * @chip: nand chip info structure
2570 * @oob_required: must write chip->oob_poi to OOB
2571 * @page: page number to write
2573 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2574 const uint8_t *buf
, int oob_required
,
2577 int i
, eccsize
= chip
->ecc
.size
, ret
;
2578 int eccbytes
= chip
->ecc
.bytes
;
2579 int eccsteps
= chip
->ecc
.steps
;
2580 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2581 const uint8_t *p
= buf
;
2583 /* Software ECC calculation */
2584 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2585 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2587 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2592 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2596 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2597 * @mtd: mtd info structure
2598 * @chip: nand chip info structure
2600 * @oob_required: must write chip->oob_poi to OOB
2601 * @page: page number to write
2603 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2604 const uint8_t *buf
, int oob_required
,
2607 int i
, eccsize
= chip
->ecc
.size
, ret
;
2608 int eccbytes
= chip
->ecc
.bytes
;
2609 int eccsteps
= chip
->ecc
.steps
;
2610 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2611 const uint8_t *p
= buf
;
2613 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2614 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2615 chip
->write_buf(mtd
, p
, eccsize
);
2616 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2619 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2624 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2631 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2632 * @mtd: mtd info structure
2633 * @chip: nand chip info structure
2634 * @offset: column address of subpage within the page
2635 * @data_len: data length
2637 * @oob_required: must write chip->oob_poi to OOB
2638 * @page: page number to write
2640 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2641 struct nand_chip
*chip
, uint32_t offset
,
2642 uint32_t data_len
, const uint8_t *buf
,
2643 int oob_required
, int page
)
2645 uint8_t *oob_buf
= chip
->oob_poi
;
2646 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2647 int ecc_size
= chip
->ecc
.size
;
2648 int ecc_bytes
= chip
->ecc
.bytes
;
2649 int ecc_steps
= chip
->ecc
.steps
;
2650 uint32_t start_step
= offset
/ ecc_size
;
2651 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2652 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2655 for (step
= 0; step
< ecc_steps
; step
++) {
2656 /* configure controller for WRITE access */
2657 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2659 /* write data (untouched subpages already masked by 0xFF) */
2660 chip
->write_buf(mtd
, buf
, ecc_size
);
2662 /* mask ECC of un-touched subpages by padding 0xFF */
2663 if ((step
< start_step
) || (step
> end_step
))
2664 memset(ecc_calc
, 0xff, ecc_bytes
);
2666 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2668 /* mask OOB of un-touched subpages by padding 0xFF */
2669 /* if oob_required, preserve OOB metadata of written subpage */
2670 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2671 memset(oob_buf
, 0xff, oob_bytes
);
2674 ecc_calc
+= ecc_bytes
;
2675 oob_buf
+= oob_bytes
;
2678 /* copy calculated ECC for whole page to chip->buffer->oob */
2679 /* this include masked-value(0xFF) for unwritten subpages */
2680 ecc_calc
= chip
->buffers
->ecccalc
;
2681 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
2686 /* write OOB buffer to NAND device */
2687 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2694 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2695 * @mtd: mtd info structure
2696 * @chip: nand chip info structure
2698 * @oob_required: must write chip->oob_poi to OOB
2699 * @page: page number to write
2701 * The hw generator calculates the error syndrome automatically. Therefore we
2702 * need a special oob layout and handling.
2704 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2705 struct nand_chip
*chip
,
2706 const uint8_t *buf
, int oob_required
,
2709 int i
, eccsize
= chip
->ecc
.size
;
2710 int eccbytes
= chip
->ecc
.bytes
;
2711 int eccsteps
= chip
->ecc
.steps
;
2712 const uint8_t *p
= buf
;
2713 uint8_t *oob
= chip
->oob_poi
;
2715 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2717 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2718 chip
->write_buf(mtd
, p
, eccsize
);
2720 if (chip
->ecc
.prepad
) {
2721 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2722 oob
+= chip
->ecc
.prepad
;
2725 chip
->ecc
.calculate(mtd
, p
, oob
);
2726 chip
->write_buf(mtd
, oob
, eccbytes
);
2729 if (chip
->ecc
.postpad
) {
2730 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2731 oob
+= chip
->ecc
.postpad
;
2735 /* Calculate remaining oob bytes */
2736 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2738 chip
->write_buf(mtd
, oob
, i
);
2744 * nand_write_page - write one page
2745 * @mtd: MTD device structure
2746 * @chip: NAND chip descriptor
2747 * @offset: address offset within the page
2748 * @data_len: length of actual data to be written
2749 * @buf: the data to write
2750 * @oob_required: must write chip->oob_poi to OOB
2751 * @page: page number to write
2752 * @raw: use _raw version of write_page
2754 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2755 uint32_t offset
, int data_len
, const uint8_t *buf
,
2756 int oob_required
, int page
, int raw
)
2758 int status
, subpage
;
2760 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2761 chip
->ecc
.write_subpage
)
2762 subpage
= offset
|| (data_len
< mtd
->writesize
);
2766 if (nand_standard_page_accessors(&chip
->ecc
))
2767 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2770 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2771 oob_required
, page
);
2773 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2774 buf
, oob_required
, page
);
2776 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2782 if (nand_standard_page_accessors(&chip
->ecc
)) {
2783 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2785 status
= chip
->waitfunc(mtd
, chip
);
2786 if (status
& NAND_STATUS_FAIL
)
2794 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2795 * @mtd: MTD device structure
2796 * @oob: oob data buffer
2797 * @len: oob data write length
2798 * @ops: oob ops structure
2800 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2801 struct mtd_oob_ops
*ops
)
2803 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2807 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2808 * data from a previous OOB read.
2810 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2812 switch (ops
->mode
) {
2814 case MTD_OPS_PLACE_OOB
:
2816 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2819 case MTD_OPS_AUTO_OOB
:
2820 ret
= mtd_ooblayout_set_databytes(mtd
, oob
, chip
->oob_poi
,
2831 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2834 * nand_do_write_ops - [INTERN] NAND write with ECC
2835 * @mtd: MTD device structure
2836 * @to: offset to write to
2837 * @ops: oob operations description structure
2839 * NAND write with ECC.
2841 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2842 struct mtd_oob_ops
*ops
)
2844 int chipnr
, realpage
, page
, blockmask
, column
;
2845 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2846 uint32_t writelen
= ops
->len
;
2848 uint32_t oobwritelen
= ops
->ooblen
;
2849 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2851 uint8_t *oob
= ops
->oobbuf
;
2852 uint8_t *buf
= ops
->datbuf
;
2854 int oob_required
= oob
? 1 : 0;
2860 /* Reject writes, which are not page aligned */
2861 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2862 pr_notice("%s: attempt to write non page aligned data\n",
2867 column
= to
& (mtd
->writesize
- 1);
2869 chipnr
= (int)(to
>> chip
->chip_shift
);
2870 chip
->select_chip(mtd
, chipnr
);
2872 /* Check, if it is write protected */
2873 if (nand_check_wp(mtd
)) {
2878 realpage
= (int)(to
>> chip
->page_shift
);
2879 page
= realpage
& chip
->pagemask
;
2880 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2882 /* Invalidate the page cache, when we write to the cached page */
2883 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2884 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2887 /* Don't allow multipage oob writes with offset */
2888 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2894 int bytes
= mtd
->writesize
;
2895 uint8_t *wbuf
= buf
;
2897 int part_pagewr
= (column
|| writelen
< mtd
->writesize
);
2901 else if (chip
->options
& NAND_USE_BOUNCE_BUFFER
)
2902 use_bufpoi
= !virt_addr_valid(buf
) ||
2903 !IS_ALIGNED((unsigned long)buf
,
2908 /* Partial page write?, or need to use bounce buffer */
2910 pr_debug("%s: using write bounce buffer for buf@%p\n",
2913 bytes
= min_t(int, bytes
- column
, writelen
);
2915 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2916 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2917 wbuf
= chip
->buffers
->databuf
;
2920 if (unlikely(oob
)) {
2921 size_t len
= min(oobwritelen
, oobmaxlen
);
2922 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2925 /* We still need to erase leftover OOB data */
2926 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2929 ret
= nand_write_page(mtd
, chip
, column
, bytes
, wbuf
,
2931 (ops
->mode
== MTD_OPS_RAW
));
2943 page
= realpage
& chip
->pagemask
;
2944 /* Check, if we cross a chip boundary */
2947 chip
->select_chip(mtd
, -1);
2948 chip
->select_chip(mtd
, chipnr
);
2952 ops
->retlen
= ops
->len
- writelen
;
2954 ops
->oobretlen
= ops
->ooblen
;
2957 chip
->select_chip(mtd
, -1);
2962 * panic_nand_write - [MTD Interface] NAND write with ECC
2963 * @mtd: MTD device structure
2964 * @to: offset to write to
2965 * @len: number of bytes to write
2966 * @retlen: pointer to variable to store the number of written bytes
2967 * @buf: the data to write
2969 * NAND write with ECC. Used when performing writes in interrupt context, this
2970 * may for example be called by mtdoops when writing an oops while in panic.
2972 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2973 size_t *retlen
, const uint8_t *buf
)
2975 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2976 struct mtd_oob_ops ops
;
2979 /* Wait for the device to get ready */
2980 panic_nand_wait(mtd
, chip
, 400);
2982 /* Grab the device */
2983 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2985 memset(&ops
, 0, sizeof(ops
));
2987 ops
.datbuf
= (uint8_t *)buf
;
2988 ops
.mode
= MTD_OPS_PLACE_OOB
;
2990 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2992 *retlen
= ops
.retlen
;
2997 * nand_write - [MTD Interface] NAND write with ECC
2998 * @mtd: MTD device structure
2999 * @to: offset to write to
3000 * @len: number of bytes to write
3001 * @retlen: pointer to variable to store the number of written bytes
3002 * @buf: the data to write
3004 * NAND write with ECC.
3006 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
3007 size_t *retlen
, const uint8_t *buf
)
3009 struct mtd_oob_ops ops
;
3012 nand_get_device(mtd
, FL_WRITING
);
3013 memset(&ops
, 0, sizeof(ops
));
3015 ops
.datbuf
= (uint8_t *)buf
;
3016 ops
.mode
= MTD_OPS_PLACE_OOB
;
3017 ret
= nand_do_write_ops(mtd
, to
, &ops
);
3018 *retlen
= ops
.retlen
;
3019 nand_release_device(mtd
);
3024 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
3025 * @mtd: MTD device structure
3026 * @to: offset to write to
3027 * @ops: oob operation description structure
3029 * NAND write out-of-band.
3031 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
3032 struct mtd_oob_ops
*ops
)
3034 int chipnr
, page
, status
, len
;
3035 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3037 pr_debug("%s: to = 0x%08x, len = %i\n",
3038 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
3040 len
= mtd_oobavail(mtd
, ops
);
3042 /* Do not allow write past end of page */
3043 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
3044 pr_debug("%s: attempt to write past end of page\n",
3049 if (unlikely(ops
->ooboffs
>= len
)) {
3050 pr_debug("%s: attempt to start write outside oob\n",
3055 /* Do not allow write past end of device */
3056 if (unlikely(to
>= mtd
->size
||
3057 ops
->ooboffs
+ ops
->ooblen
>
3058 ((mtd
->size
>> chip
->page_shift
) -
3059 (to
>> chip
->page_shift
)) * len
)) {
3060 pr_debug("%s: attempt to write beyond end of device\n",
3065 chipnr
= (int)(to
>> chip
->chip_shift
);
3068 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
3069 * of my DiskOnChip 2000 test units) will clear the whole data page too
3070 * if we don't do this. I have no clue why, but I seem to have 'fixed'
3071 * it in the doc2000 driver in August 1999. dwmw2.
3073 nand_reset(chip
, chipnr
);
3075 chip
->select_chip(mtd
, chipnr
);
3077 /* Shift to get page */
3078 page
= (int)(to
>> chip
->page_shift
);
3080 /* Check, if it is write protected */
3081 if (nand_check_wp(mtd
)) {
3082 chip
->select_chip(mtd
, -1);
3086 /* Invalidate the page cache, if we write to the cached page */
3087 if (page
== chip
->pagebuf
)
3090 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
3092 if (ops
->mode
== MTD_OPS_RAW
)
3093 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
3095 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
3097 chip
->select_chip(mtd
, -1);
3102 ops
->oobretlen
= ops
->ooblen
;
3108 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
3109 * @mtd: MTD device structure
3110 * @to: offset to write to
3111 * @ops: oob operation description structure
3113 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
3114 struct mtd_oob_ops
*ops
)
3116 int ret
= -ENOTSUPP
;
3120 /* Do not allow writes past end of device */
3121 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
3122 pr_debug("%s: attempt to write beyond end of device\n",
3127 nand_get_device(mtd
, FL_WRITING
);
3129 switch (ops
->mode
) {
3130 case MTD_OPS_PLACE_OOB
:
3131 case MTD_OPS_AUTO_OOB
:
3140 ret
= nand_do_write_oob(mtd
, to
, ops
);
3142 ret
= nand_do_write_ops(mtd
, to
, ops
);
3145 nand_release_device(mtd
);
3150 * single_erase - [GENERIC] NAND standard block erase command function
3151 * @mtd: MTD device structure
3152 * @page: the page address of the block which will be erased
3154 * Standard erase command for NAND chips. Returns NAND status.
3156 static int single_erase(struct mtd_info
*mtd
, int page
)
3158 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3159 /* Send commands to erase a block */
3160 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
3161 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
3163 return chip
->waitfunc(mtd
, chip
);
3167 * nand_erase - [MTD Interface] erase block(s)
3168 * @mtd: MTD device structure
3169 * @instr: erase instruction
3171 * Erase one ore more blocks.
3173 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
3175 return nand_erase_nand(mtd
, instr
, 0);
3179 * nand_erase_nand - [INTERN] erase block(s)
3180 * @mtd: MTD device structure
3181 * @instr: erase instruction
3182 * @allowbbt: allow erasing the bbt area
3184 * Erase one ore more blocks.
3186 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
3189 int page
, status
, pages_per_block
, ret
, chipnr
;
3190 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3193 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3194 __func__
, (unsigned long long)instr
->addr
,
3195 (unsigned long long)instr
->len
);
3197 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
3200 /* Grab the lock and see if the device is available */
3201 nand_get_device(mtd
, FL_ERASING
);
3203 /* Shift to get first page */
3204 page
= (int)(instr
->addr
>> chip
->page_shift
);
3205 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
3207 /* Calculate pages in each block */
3208 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
3210 /* Select the NAND device */
3211 chip
->select_chip(mtd
, chipnr
);
3213 /* Check, if it is write protected */
3214 if (nand_check_wp(mtd
)) {
3215 pr_debug("%s: device is write protected!\n",
3217 instr
->state
= MTD_ERASE_FAILED
;
3221 /* Loop through the pages */
3224 instr
->state
= MTD_ERASING
;
3227 /* Check if we have a bad block, we do not erase bad blocks! */
3228 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
3229 chip
->page_shift
, allowbbt
)) {
3230 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3232 instr
->state
= MTD_ERASE_FAILED
;
3237 * Invalidate the page cache, if we erase the block which
3238 * contains the current cached page.
3240 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
3241 (page
+ pages_per_block
))
3244 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
3246 /* See if block erase succeeded */
3247 if (status
& NAND_STATUS_FAIL
) {
3248 pr_debug("%s: failed erase, page 0x%08x\n",
3250 instr
->state
= MTD_ERASE_FAILED
;
3252 ((loff_t
)page
<< chip
->page_shift
);
3256 /* Increment page address and decrement length */
3257 len
-= (1ULL << chip
->phys_erase_shift
);
3258 page
+= pages_per_block
;
3260 /* Check, if we cross a chip boundary */
3261 if (len
&& !(page
& chip
->pagemask
)) {
3263 chip
->select_chip(mtd
, -1);
3264 chip
->select_chip(mtd
, chipnr
);
3267 instr
->state
= MTD_ERASE_DONE
;
3271 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
3273 /* Deselect and wake up anyone waiting on the device */
3274 chip
->select_chip(mtd
, -1);
3275 nand_release_device(mtd
);
3277 /* Do call back function */
3279 mtd_erase_callback(instr
);
3281 /* Return more or less happy */
3286 * nand_sync - [MTD Interface] sync
3287 * @mtd: MTD device structure
3289 * Sync is actually a wait for chip ready function.
3291 static void nand_sync(struct mtd_info
*mtd
)
3293 pr_debug("%s: called\n", __func__
);
3295 /* Grab the lock and see if the device is available */
3296 nand_get_device(mtd
, FL_SYNCING
);
3297 /* Release it and go back */
3298 nand_release_device(mtd
);
3302 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3303 * @mtd: MTD device structure
3304 * @offs: offset relative to mtd start
3306 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
3308 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3309 int chipnr
= (int)(offs
>> chip
->chip_shift
);
3312 /* Select the NAND device */
3313 nand_get_device(mtd
, FL_READING
);
3314 chip
->select_chip(mtd
, chipnr
);
3316 ret
= nand_block_checkbad(mtd
, offs
, 0);
3318 chip
->select_chip(mtd
, -1);
3319 nand_release_device(mtd
);
3325 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3326 * @mtd: MTD device structure
3327 * @ofs: offset relative to mtd start
3329 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3333 ret
= nand_block_isbad(mtd
, ofs
);
3335 /* If it was bad already, return success and do nothing */
3341 return nand_block_markbad_lowlevel(mtd
, ofs
);
3345 * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd
3346 * @mtd: MTD device structure
3347 * @ofs: offset relative to mtd start
3348 * @len: length of mtd
3350 static int nand_max_bad_blocks(struct mtd_info
*mtd
, loff_t ofs
, size_t len
)
3352 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3353 u32 part_start_block
;
3359 * max_bb_per_die and blocks_per_die used to determine
3360 * the maximum bad block count.
3362 if (!chip
->max_bb_per_die
|| !chip
->blocks_per_die
)
3365 /* Get the start and end of the partition in erase blocks. */
3366 part_start_block
= mtd_div_by_eb(ofs
, mtd
);
3367 part_end_block
= mtd_div_by_eb(len
, mtd
) + part_start_block
- 1;
3369 /* Get the start and end LUNs of the partition. */
3370 part_start_die
= part_start_block
/ chip
->blocks_per_die
;
3371 part_end_die
= part_end_block
/ chip
->blocks_per_die
;
3374 * Look up the bad blocks per unit and multiply by the number of units
3375 * that the partition spans.
3377 return chip
->max_bb_per_die
* (part_end_die
- part_start_die
+ 1);
3381 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3382 * @mtd: MTD device structure
3383 * @chip: nand chip info structure
3384 * @addr: feature address.
3385 * @subfeature_param: the subfeature parameters, a four bytes array.
3387 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3388 int addr
, uint8_t *subfeature_param
)
3393 if (!chip
->onfi_version
||
3394 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3395 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3398 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3399 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3400 chip
->write_byte(mtd
, subfeature_param
[i
]);
3402 status
= chip
->waitfunc(mtd
, chip
);
3403 if (status
& NAND_STATUS_FAIL
)
3409 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3410 * @mtd: MTD device structure
3411 * @chip: nand chip info structure
3412 * @addr: feature address.
3413 * @subfeature_param: the subfeature parameters, a four bytes array.
3415 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3416 int addr
, uint8_t *subfeature_param
)
3420 if (!chip
->onfi_version
||
3421 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3422 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3425 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3426 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3427 *subfeature_param
++ = chip
->read_byte(mtd
);
3432 * nand_onfi_get_set_features_notsupp - set/get features stub returning
3434 * @mtd: MTD device structure
3435 * @chip: nand chip info structure
3436 * @addr: feature address.
3437 * @subfeature_param: the subfeature parameters, a four bytes array.
3439 * Should be used by NAND controller drivers that do not support the SET/GET
3440 * FEATURES operations.
3442 int nand_onfi_get_set_features_notsupp(struct mtd_info
*mtd
,
3443 struct nand_chip
*chip
, int addr
,
3444 u8
*subfeature_param
)
3448 EXPORT_SYMBOL(nand_onfi_get_set_features_notsupp
);
3451 * nand_suspend - [MTD Interface] Suspend the NAND flash
3452 * @mtd: MTD device structure
3454 static int nand_suspend(struct mtd_info
*mtd
)
3456 return nand_get_device(mtd
, FL_PM_SUSPENDED
);
3460 * nand_resume - [MTD Interface] Resume the NAND flash
3461 * @mtd: MTD device structure
3463 static void nand_resume(struct mtd_info
*mtd
)
3465 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3467 if (chip
->state
== FL_PM_SUSPENDED
)
3468 nand_release_device(mtd
);
3470 pr_err("%s called for a chip which is not in suspended state\n",
3475 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3476 * prevent further operations
3477 * @mtd: MTD device structure
3479 static void nand_shutdown(struct mtd_info
*mtd
)
3481 nand_get_device(mtd
, FL_PM_SUSPENDED
);
3484 /* Set default functions */
3485 static void nand_set_defaults(struct nand_chip
*chip
)
3487 unsigned int busw
= chip
->options
& NAND_BUSWIDTH_16
;
3489 /* check for proper chip_delay setup, set 20us if not */
3490 if (!chip
->chip_delay
)
3491 chip
->chip_delay
= 20;
3493 /* check, if a user supplied command function given */
3494 if (chip
->cmdfunc
== NULL
)
3495 chip
->cmdfunc
= nand_command
;
3497 /* check, if a user supplied wait function given */
3498 if (chip
->waitfunc
== NULL
)
3499 chip
->waitfunc
= nand_wait
;
3501 if (!chip
->select_chip
)
3502 chip
->select_chip
= nand_select_chip
;
3504 /* set for ONFI nand */
3505 if (!chip
->onfi_set_features
)
3506 chip
->onfi_set_features
= nand_onfi_set_features
;
3507 if (!chip
->onfi_get_features
)
3508 chip
->onfi_get_features
= nand_onfi_get_features
;
3510 /* If called twice, pointers that depend on busw may need to be reset */
3511 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3512 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3513 if (!chip
->read_word
)
3514 chip
->read_word
= nand_read_word
;
3515 if (!chip
->block_bad
)
3516 chip
->block_bad
= nand_block_bad
;
3517 if (!chip
->block_markbad
)
3518 chip
->block_markbad
= nand_default_block_markbad
;
3519 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3520 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3521 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3522 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3523 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3524 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3525 if (!chip
->scan_bbt
)
3526 chip
->scan_bbt
= nand_default_bbt
;
3528 if (!chip
->controller
) {
3529 chip
->controller
= &chip
->hwcontrol
;
3530 nand_hw_control_init(chip
->controller
);
3533 if (!chip
->buf_align
)
3534 chip
->buf_align
= 1;
3537 /* Sanitize ONFI strings so we can safely print them */
3538 static void sanitize_string(uint8_t *s
, size_t len
)
3542 /* Null terminate */
3545 /* Remove non printable chars */
3546 for (i
= 0; i
< len
- 1; i
++) {
3547 if (s
[i
] < ' ' || s
[i
] > 127)
3551 /* Remove trailing spaces */
3555 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3560 for (i
= 0; i
< 8; i
++)
3561 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3567 /* Parse the Extended Parameter Page. */
3568 static int nand_flash_detect_ext_param_page(struct nand_chip
*chip
,
3569 struct nand_onfi_params
*p
)
3571 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3572 struct onfi_ext_param_page
*ep
;
3573 struct onfi_ext_section
*s
;
3574 struct onfi_ext_ecc_info
*ecc
;
3580 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3581 ep
= kmalloc(len
, GFP_KERNEL
);
3585 /* Send our own NAND_CMD_PARAM. */
3586 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3588 /* Use the Change Read Column command to skip the ONFI param pages. */
3589 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3590 sizeof(*p
) * p
->num_of_param_pages
, -1);
3592 /* Read out the Extended Parameter Page. */
3593 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3594 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3595 != le16_to_cpu(ep
->crc
))) {
3596 pr_debug("fail in the CRC.\n");
3601 * Check the signature.
3602 * Do not strictly follow the ONFI spec, maybe changed in future.
3604 if (strncmp(ep
->sig
, "EPPS", 4)) {
3605 pr_debug("The signature is invalid.\n");
3609 /* find the ECC section. */
3610 cursor
= (uint8_t *)(ep
+ 1);
3611 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3612 s
= ep
->sections
+ i
;
3613 if (s
->type
== ONFI_SECTION_TYPE_2
)
3615 cursor
+= s
->length
* 16;
3617 if (i
== ONFI_EXT_SECTION_MAX
) {
3618 pr_debug("We can not find the ECC section.\n");
3622 /* get the info we want. */
3623 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3625 if (!ecc
->codeword_size
) {
3626 pr_debug("Invalid codeword size\n");
3630 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3631 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3640 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3642 static int nand_flash_detect_onfi(struct nand_chip
*chip
)
3644 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3645 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3649 /* Try ONFI for unknown chip or LP */
3650 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3651 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3652 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3655 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3656 for (i
= 0; i
< 3; i
++) {
3657 for (j
= 0; j
< sizeof(*p
); j
++)
3658 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3659 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3660 le16_to_cpu(p
->crc
)) {
3666 pr_err("Could not find valid ONFI parameter page; aborting\n");
3671 val
= le16_to_cpu(p
->revision
);
3673 chip
->onfi_version
= 23;
3674 else if (val
& (1 << 4))
3675 chip
->onfi_version
= 22;
3676 else if (val
& (1 << 3))
3677 chip
->onfi_version
= 21;
3678 else if (val
& (1 << 2))
3679 chip
->onfi_version
= 20;
3680 else if (val
& (1 << 1))
3681 chip
->onfi_version
= 10;
3683 if (!chip
->onfi_version
) {
3684 pr_info("unsupported ONFI version: %d\n", val
);
3688 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3689 sanitize_string(p
->model
, sizeof(p
->model
));
3691 mtd
->name
= p
->model
;
3693 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3696 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3697 * (don't ask me who thought of this...). MTD assumes that these
3698 * dimensions will be power-of-2, so just truncate the remaining area.
3700 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3701 mtd
->erasesize
*= mtd
->writesize
;
3703 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3705 /* See erasesize comment */
3706 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3707 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3708 chip
->bits_per_cell
= p
->bits_per_cell
;
3710 chip
->max_bb_per_die
= le16_to_cpu(p
->bb_per_lun
);
3711 chip
->blocks_per_die
= le32_to_cpu(p
->blocks_per_lun
);
3713 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3714 chip
->options
|= NAND_BUSWIDTH_16
;
3716 if (p
->ecc_bits
!= 0xff) {
3717 chip
->ecc_strength_ds
= p
->ecc_bits
;
3718 chip
->ecc_step_ds
= 512;
3719 } else if (chip
->onfi_version
>= 21 &&
3720 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3723 * The nand_flash_detect_ext_param_page() uses the
3724 * Change Read Column command which maybe not supported
3725 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3726 * now. We do not replace user supplied command function.
3728 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3729 chip
->cmdfunc
= nand_command_lp
;
3731 /* The Extended Parameter Page is supported since ONFI 2.1. */
3732 if (nand_flash_detect_ext_param_page(chip
, p
))
3733 pr_warn("Failed to detect ONFI extended param page\n");
3735 pr_warn("Could not retrieve ONFI ECC requirements\n");
3742 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3744 static int nand_flash_detect_jedec(struct nand_chip
*chip
)
3746 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3747 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3748 struct jedec_ecc_info
*ecc
;
3752 /* Try JEDEC for unknown chip or LP */
3753 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3754 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3755 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3756 chip
->read_byte(mtd
) != 'C')
3759 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3760 for (i
= 0; i
< 3; i
++) {
3761 for (j
= 0; j
< sizeof(*p
); j
++)
3762 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3764 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3765 le16_to_cpu(p
->crc
))
3770 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3775 val
= le16_to_cpu(p
->revision
);
3777 chip
->jedec_version
= 10;
3778 else if (val
& (1 << 1))
3779 chip
->jedec_version
= 1; /* vendor specific version */
3781 if (!chip
->jedec_version
) {
3782 pr_info("unsupported JEDEC version: %d\n", val
);
3786 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3787 sanitize_string(p
->model
, sizeof(p
->model
));
3789 mtd
->name
= p
->model
;
3791 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3793 /* Please reference to the comment for nand_flash_detect_onfi. */
3794 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3795 mtd
->erasesize
*= mtd
->writesize
;
3797 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3799 /* Please reference to the comment for nand_flash_detect_onfi. */
3800 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3801 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3802 chip
->bits_per_cell
= p
->bits_per_cell
;
3804 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3805 chip
->options
|= NAND_BUSWIDTH_16
;
3808 ecc
= &p
->ecc_info
[0];
3810 if (ecc
->codeword_size
>= 9) {
3811 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3812 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3814 pr_warn("Invalid codeword size\n");
3821 * nand_id_has_period - Check if an ID string has a given wraparound period
3822 * @id_data: the ID string
3823 * @arrlen: the length of the @id_data array
3824 * @period: the period of repitition
3826 * Check if an ID string is repeated within a given sequence of bytes at
3827 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3828 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3829 * if the repetition has a period of @period; otherwise, returns zero.
3831 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3834 for (i
= 0; i
< period
; i
++)
3835 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3836 if (id_data
[i
] != id_data
[j
])
3842 * nand_id_len - Get the length of an ID string returned by CMD_READID
3843 * @id_data: the ID string
3844 * @arrlen: the length of the @id_data array
3846 * Returns the length of the ID string, according to known wraparound/trailing
3847 * zero patterns. If no pattern exists, returns the length of the array.
3849 static int nand_id_len(u8
*id_data
, int arrlen
)
3851 int last_nonzero
, period
;
3853 /* Find last non-zero byte */
3854 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3855 if (id_data
[last_nonzero
])
3859 if (last_nonzero
< 0)
3862 /* Calculate wraparound period */
3863 for (period
= 1; period
< arrlen
; period
++)
3864 if (nand_id_has_period(id_data
, arrlen
, period
))
3867 /* There's a repeated pattern */
3868 if (period
< arrlen
)
3871 /* There are trailing zeros */
3872 if (last_nonzero
< arrlen
- 1)
3873 return last_nonzero
+ 1;
3875 /* No pattern detected */
3879 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3880 static int nand_get_bits_per_cell(u8 cellinfo
)
3884 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3885 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3890 * Many new NAND share similar device ID codes, which represent the size of the
3891 * chip. The rest of the parameters must be decoded according to generic or
3892 * manufacturer-specific "extended ID" decoding patterns.
3894 void nand_decode_ext_id(struct nand_chip
*chip
)
3896 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3898 u8
*id_data
= chip
->id
.data
;
3899 /* The 3rd id byte holds MLC / multichip data */
3900 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3901 /* The 4th id byte is the important one */
3905 mtd
->writesize
= 1024 << (extid
& 0x03);
3908 mtd
->oobsize
= (8 << (extid
& 0x01)) * (mtd
->writesize
>> 9);
3910 /* Calc blocksize. Blocksize is multiples of 64KiB */
3911 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3913 /* Get buswidth information */
3915 chip
->options
|= NAND_BUSWIDTH_16
;
3917 EXPORT_SYMBOL_GPL(nand_decode_ext_id
);
3920 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3921 * decodes a matching ID table entry and assigns the MTD size parameters for
3924 static void nand_decode_id(struct nand_chip
*chip
, struct nand_flash_dev
*type
)
3926 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3928 mtd
->erasesize
= type
->erasesize
;
3929 mtd
->writesize
= type
->pagesize
;
3930 mtd
->oobsize
= mtd
->writesize
/ 32;
3932 /* All legacy ID NAND are small-page, SLC */
3933 chip
->bits_per_cell
= 1;
3937 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3938 * heuristic patterns using various detected parameters (e.g., manufacturer,
3939 * page size, cell-type information).
3941 static void nand_decode_bbm_options(struct nand_chip
*chip
)
3943 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3945 /* Set the bad block position */
3946 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3947 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3949 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3952 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3954 return type
->id_len
;
3957 static bool find_full_id_nand(struct nand_chip
*chip
,
3958 struct nand_flash_dev
*type
)
3960 struct mtd_info
*mtd
= nand_to_mtd(chip
);
3961 u8
*id_data
= chip
->id
.data
;
3963 if (!strncmp(type
->id
, id_data
, type
->id_len
)) {
3964 mtd
->writesize
= type
->pagesize
;
3965 mtd
->erasesize
= type
->erasesize
;
3966 mtd
->oobsize
= type
->oobsize
;
3968 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3969 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3970 chip
->options
|= type
->options
;
3971 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3972 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3973 chip
->onfi_timing_mode_default
=
3974 type
->onfi_timing_mode_default
;
3977 mtd
->name
= type
->name
;
3985 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
3986 * compliant and does not have a full-id or legacy-id entry in the nand_ids
3989 static void nand_manufacturer_detect(struct nand_chip
*chip
)
3992 * Try manufacturer detection if available and use
3993 * nand_decode_ext_id() otherwise.
3995 if (chip
->manufacturer
.desc
&& chip
->manufacturer
.desc
->ops
&&
3996 chip
->manufacturer
.desc
->ops
->detect
) {
3997 /* The 3rd id byte holds MLC / multichip data */
3998 chip
->bits_per_cell
= nand_get_bits_per_cell(chip
->id
.data
[2]);
3999 chip
->manufacturer
.desc
->ops
->detect(chip
);
4001 nand_decode_ext_id(chip
);
4006 * Manufacturer initialization. This function is called for all NANDs including
4007 * ONFI and JEDEC compliant ones.
4008 * Manufacturer drivers should put all their specific initialization code in
4009 * their ->init() hook.
4011 static int nand_manufacturer_init(struct nand_chip
*chip
)
4013 if (!chip
->manufacturer
.desc
|| !chip
->manufacturer
.desc
->ops
||
4014 !chip
->manufacturer
.desc
->ops
->init
)
4017 return chip
->manufacturer
.desc
->ops
->init(chip
);
4021 * Manufacturer cleanup. This function is called for all NANDs including
4022 * ONFI and JEDEC compliant ones.
4023 * Manufacturer drivers should put all their specific cleanup code in their
4026 static void nand_manufacturer_cleanup(struct nand_chip
*chip
)
4028 /* Release manufacturer private data */
4029 if (chip
->manufacturer
.desc
&& chip
->manufacturer
.desc
->ops
&&
4030 chip
->manufacturer
.desc
->ops
->cleanup
)
4031 chip
->manufacturer
.desc
->ops
->cleanup(chip
);
4035 * Get the flash and manufacturer id and lookup if the type is supported.
4037 static int nand_detect(struct nand_chip
*chip
, struct nand_flash_dev
*type
)
4039 const struct nand_manufacturer
*manufacturer
;
4040 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4043 u8
*id_data
= chip
->id
.data
;
4047 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
4050 nand_reset(chip
, 0);
4052 /* Select the device */
4053 chip
->select_chip(mtd
, 0);
4055 /* Send the command for reading device ID */
4056 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4058 /* Read manufacturer and device IDs */
4059 maf_id
= chip
->read_byte(mtd
);
4060 dev_id
= chip
->read_byte(mtd
);
4063 * Try again to make sure, as some systems the bus-hold or other
4064 * interface concerns can cause random data which looks like a
4065 * possibly credible NAND flash to appear. If the two results do
4066 * not match, ignore the device completely.
4069 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4071 /* Read entire ID string */
4072 for (i
= 0; i
< 8; i
++)
4073 id_data
[i
] = chip
->read_byte(mtd
);
4075 if (id_data
[0] != maf_id
|| id_data
[1] != dev_id
) {
4076 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4077 maf_id
, dev_id
, id_data
[0], id_data
[1]);
4081 chip
->id
.len
= nand_id_len(id_data
, 8);
4083 /* Try to identify manufacturer */
4084 manufacturer
= nand_get_manufacturer(maf_id
);
4085 chip
->manufacturer
.desc
= manufacturer
;
4088 type
= nand_flash_ids
;
4091 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
4093 * This is required to make sure initial NAND bus width set by the
4094 * NAND controller driver is coherent with the real NAND bus width
4095 * (extracted by auto-detection code).
4097 busw
= chip
->options
& NAND_BUSWIDTH_16
;
4100 * The flag is only set (never cleared), reset it to its default value
4101 * before starting auto-detection.
4103 chip
->options
&= ~NAND_BUSWIDTH_16
;
4105 for (; type
->name
!= NULL
; type
++) {
4106 if (is_full_id_nand(type
)) {
4107 if (find_full_id_nand(chip
, type
))
4109 } else if (dev_id
== type
->dev_id
) {
4114 chip
->onfi_version
= 0;
4115 if (!type
->name
|| !type
->pagesize
) {
4116 /* Check if the chip is ONFI compliant */
4117 if (nand_flash_detect_onfi(chip
))
4120 /* Check if the chip is JEDEC compliant */
4121 if (nand_flash_detect_jedec(chip
))
4129 mtd
->name
= type
->name
;
4131 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
4133 if (!type
->pagesize
)
4134 nand_manufacturer_detect(chip
);
4136 nand_decode_id(chip
, type
);
4138 /* Get chip options */
4139 chip
->options
|= type
->options
;
4143 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
4144 WARN_ON(busw
& NAND_BUSWIDTH_16
);
4145 nand_set_defaults(chip
);
4146 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
4148 * Check, if buswidth is correct. Hardware drivers should set
4151 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4153 pr_info("%s %s\n", nand_manufacturer_name(manufacturer
),
4155 pr_warn("bus width %d instead of %d bits\n", busw
? 16 : 8,
4156 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8);
4160 nand_decode_bbm_options(chip
);
4162 /* Calculate the address shift from the page size */
4163 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
4164 /* Convert chipsize to number of pages per chip -1 */
4165 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
4167 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
4168 ffs(mtd
->erasesize
) - 1;
4169 if (chip
->chipsize
& 0xffffffff)
4170 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
4172 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
4173 chip
->chip_shift
+= 32 - 1;
4176 chip
->badblockbits
= 8;
4177 chip
->erase
= single_erase
;
4179 /* Do not replace user supplied command function! */
4180 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
4181 chip
->cmdfunc
= nand_command_lp
;
4183 ret
= nand_manufacturer_init(chip
);
4187 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4190 if (chip
->onfi_version
)
4191 pr_info("%s %s\n", nand_manufacturer_name(manufacturer
),
4192 chip
->onfi_params
.model
);
4193 else if (chip
->jedec_version
)
4194 pr_info("%s %s\n", nand_manufacturer_name(manufacturer
),
4195 chip
->jedec_params
.model
);
4197 pr_info("%s %s\n", nand_manufacturer_name(manufacturer
),
4200 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4201 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
4202 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
4206 static const char * const nand_ecc_modes
[] = {
4207 [NAND_ECC_NONE
] = "none",
4208 [NAND_ECC_SOFT
] = "soft",
4209 [NAND_ECC_HW
] = "hw",
4210 [NAND_ECC_HW_SYNDROME
] = "hw_syndrome",
4211 [NAND_ECC_HW_OOB_FIRST
] = "hw_oob_first",
4212 [NAND_ECC_ON_DIE
] = "on-die",
4215 static int of_get_nand_ecc_mode(struct device_node
*np
)
4220 err
= of_property_read_string(np
, "nand-ecc-mode", &pm
);
4224 for (i
= 0; i
< ARRAY_SIZE(nand_ecc_modes
); i
++)
4225 if (!strcasecmp(pm
, nand_ecc_modes
[i
]))
4229 * For backward compatibility we support few obsoleted values that don't
4230 * have their mappings into nand_ecc_modes_t anymore (they were merged
4231 * with other enums).
4233 if (!strcasecmp(pm
, "soft_bch"))
4234 return NAND_ECC_SOFT
;
4239 static const char * const nand_ecc_algos
[] = {
4240 [NAND_ECC_HAMMING
] = "hamming",
4241 [NAND_ECC_BCH
] = "bch",
4244 static int of_get_nand_ecc_algo(struct device_node
*np
)
4249 err
= of_property_read_string(np
, "nand-ecc-algo", &pm
);
4251 for (i
= NAND_ECC_HAMMING
; i
< ARRAY_SIZE(nand_ecc_algos
); i
++)
4252 if (!strcasecmp(pm
, nand_ecc_algos
[i
]))
4258 * For backward compatibility we also read "nand-ecc-mode" checking
4259 * for some obsoleted values that were specifying ECC algorithm.
4261 err
= of_property_read_string(np
, "nand-ecc-mode", &pm
);
4265 if (!strcasecmp(pm
, "soft"))
4266 return NAND_ECC_HAMMING
;
4267 else if (!strcasecmp(pm
, "soft_bch"))
4268 return NAND_ECC_BCH
;
4273 static int of_get_nand_ecc_step_size(struct device_node
*np
)
4278 ret
= of_property_read_u32(np
, "nand-ecc-step-size", &val
);
4279 return ret
? ret
: val
;
4282 static int of_get_nand_ecc_strength(struct device_node
*np
)
4287 ret
= of_property_read_u32(np
, "nand-ecc-strength", &val
);
4288 return ret
? ret
: val
;
4291 static int of_get_nand_bus_width(struct device_node
*np
)
4295 if (of_property_read_u32(np
, "nand-bus-width", &val
))
4307 static bool of_get_nand_on_flash_bbt(struct device_node
*np
)
4309 return of_property_read_bool(np
, "nand-on-flash-bbt");
4312 static int nand_dt_init(struct nand_chip
*chip
)
4314 struct device_node
*dn
= nand_get_flash_node(chip
);
4315 int ecc_mode
, ecc_algo
, ecc_strength
, ecc_step
;
4320 if (of_get_nand_bus_width(dn
) == 16)
4321 chip
->options
|= NAND_BUSWIDTH_16
;
4323 if (of_get_nand_on_flash_bbt(dn
))
4324 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
4326 ecc_mode
= of_get_nand_ecc_mode(dn
);
4327 ecc_algo
= of_get_nand_ecc_algo(dn
);
4328 ecc_strength
= of_get_nand_ecc_strength(dn
);
4329 ecc_step
= of_get_nand_ecc_step_size(dn
);
4332 chip
->ecc
.mode
= ecc_mode
;
4335 chip
->ecc
.algo
= ecc_algo
;
4337 if (ecc_strength
>= 0)
4338 chip
->ecc
.strength
= ecc_strength
;
4341 chip
->ecc
.size
= ecc_step
;
4343 if (of_property_read_bool(dn
, "nand-ecc-maximize"))
4344 chip
->ecc
.options
|= NAND_ECC_MAXIMIZE
;
4350 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4351 * @mtd: MTD device structure
4352 * @maxchips: number of chips to scan for
4353 * @table: alternative NAND ID table
4355 * This is the first phase of the normal nand_scan() function. It reads the
4356 * flash ID and sets up MTD fields accordingly.
4359 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4360 struct nand_flash_dev
*table
)
4362 int i
, nand_maf_id
, nand_dev_id
;
4363 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4366 ret
= nand_dt_init(chip
);
4370 if (!mtd
->name
&& mtd
->dev
.parent
)
4371 mtd
->name
= dev_name(mtd
->dev
.parent
);
4373 if ((!chip
->cmdfunc
|| !chip
->select_chip
) && !chip
->cmd_ctrl
) {
4375 * Default functions assigned for chip_select() and
4376 * cmdfunc() both expect cmd_ctrl() to be populated,
4377 * so we need to check that that's the case
4379 pr_err("chip.cmd_ctrl() callback is not provided");
4382 /* Set the default functions */
4383 nand_set_defaults(chip
);
4385 /* Read the flash type */
4386 ret
= nand_detect(chip
, table
);
4388 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4389 pr_warn("No NAND device found\n");
4390 chip
->select_chip(mtd
, -1);
4394 /* Initialize the ->data_interface field. */
4395 ret
= nand_init_data_interface(chip
);
4400 * Setup the data interface correctly on the chip and controller side.
4401 * This explicit call to nand_setup_data_interface() is only required
4402 * for the first die, because nand_reset() has been called before
4403 * ->data_interface and ->default_onfi_timing_mode were set.
4404 * For the other dies, nand_reset() will automatically switch to the
4407 ret
= nand_setup_data_interface(chip
, 0);
4411 nand_maf_id
= chip
->id
.data
[0];
4412 nand_dev_id
= chip
->id
.data
[1];
4414 chip
->select_chip(mtd
, -1);
4416 /* Check for a chip array */
4417 for (i
= 1; i
< maxchips
; i
++) {
4418 /* See comment in nand_get_flash_type for reset */
4419 nand_reset(chip
, i
);
4421 chip
->select_chip(mtd
, i
);
4422 /* Send the command for reading device ID */
4423 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4424 /* Read manufacturer and device IDs */
4425 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4426 nand_dev_id
!= chip
->read_byte(mtd
)) {
4427 chip
->select_chip(mtd
, -1);
4430 chip
->select_chip(mtd
, -1);
4433 pr_info("%d chips detected\n", i
);
4435 /* Store the number of chips and calc total size for mtd */
4437 mtd
->size
= i
* chip
->chipsize
;
4442 /* Free manufacturer priv data. */
4443 nand_manufacturer_cleanup(chip
);
4447 EXPORT_SYMBOL(nand_scan_ident
);
4449 static int nand_set_ecc_soft_ops(struct mtd_info
*mtd
)
4451 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4452 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4454 if (WARN_ON(ecc
->mode
!= NAND_ECC_SOFT
))
4457 switch (ecc
->algo
) {
4458 case NAND_ECC_HAMMING
:
4459 ecc
->calculate
= nand_calculate_ecc
;
4460 ecc
->correct
= nand_correct_data
;
4461 ecc
->read_page
= nand_read_page_swecc
;
4462 ecc
->read_subpage
= nand_read_subpage
;
4463 ecc
->write_page
= nand_write_page_swecc
;
4464 ecc
->read_page_raw
= nand_read_page_raw
;
4465 ecc
->write_page_raw
= nand_write_page_raw
;
4466 ecc
->read_oob
= nand_read_oob_std
;
4467 ecc
->write_oob
= nand_write_oob_std
;
4474 if (!mtd_nand_has_bch()) {
4475 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4478 ecc
->calculate
= nand_bch_calculate_ecc
;
4479 ecc
->correct
= nand_bch_correct_data
;
4480 ecc
->read_page
= nand_read_page_swecc
;
4481 ecc
->read_subpage
= nand_read_subpage
;
4482 ecc
->write_page
= nand_write_page_swecc
;
4483 ecc
->read_page_raw
= nand_read_page_raw
;
4484 ecc
->write_page_raw
= nand_write_page_raw
;
4485 ecc
->read_oob
= nand_read_oob_std
;
4486 ecc
->write_oob
= nand_write_oob_std
;
4489 * Board driver should supply ecc.size and ecc.strength
4490 * values to select how many bits are correctable.
4491 * Otherwise, default to 4 bits for large page devices.
4493 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4499 * if no ecc placement scheme was provided pickup the default
4502 if (!mtd
->ooblayout
) {
4503 /* handle large page devices only */
4504 if (mtd
->oobsize
< 64) {
4505 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4509 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
4514 * We can only maximize ECC config when the default layout is
4515 * used, otherwise we don't know how many bytes can really be
4518 if (mtd
->ooblayout
== &nand_ooblayout_lp_ops
&&
4519 ecc
->options
& NAND_ECC_MAXIMIZE
) {
4522 /* Always prefer 1k blocks over 512bytes ones */
4524 steps
= mtd
->writesize
/ ecc
->size
;
4526 /* Reserve 2 bytes for the BBM */
4527 bytes
= (mtd
->oobsize
- 2) / steps
;
4528 ecc
->strength
= bytes
* 8 / fls(8 * ecc
->size
);
4531 /* See nand_bch_init() for details. */
4533 ecc
->priv
= nand_bch_init(mtd
);
4535 WARN(1, "BCH ECC initialization failed!\n");
4540 WARN(1, "Unsupported ECC algorithm!\n");
4546 * nand_check_ecc_caps - check the sanity of preset ECC settings
4547 * @chip: nand chip info structure
4548 * @caps: ECC caps info structure
4549 * @oobavail: OOB size that the ECC engine can use
4551 * When ECC step size and strength are already set, check if they are supported
4552 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4553 * On success, the calculated ECC bytes is set.
4555 int nand_check_ecc_caps(struct nand_chip
*chip
,
4556 const struct nand_ecc_caps
*caps
, int oobavail
)
4558 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4559 const struct nand_ecc_step_info
*stepinfo
;
4560 int preset_step
= chip
->ecc
.size
;
4561 int preset_strength
= chip
->ecc
.strength
;
4562 int nsteps
, ecc_bytes
;
4565 if (WARN_ON(oobavail
< 0))
4568 if (!preset_step
|| !preset_strength
)
4571 nsteps
= mtd
->writesize
/ preset_step
;
4573 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4574 stepinfo
= &caps
->stepinfos
[i
];
4576 if (stepinfo
->stepsize
!= preset_step
)
4579 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4580 if (stepinfo
->strengths
[j
] != preset_strength
)
4583 ecc_bytes
= caps
->calc_ecc_bytes(preset_step
,
4585 if (WARN_ON_ONCE(ecc_bytes
< 0))
4588 if (ecc_bytes
* nsteps
> oobavail
) {
4589 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4590 preset_step
, preset_strength
);
4594 chip
->ecc
.bytes
= ecc_bytes
;
4600 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4601 preset_step
, preset_strength
);
4605 EXPORT_SYMBOL_GPL(nand_check_ecc_caps
);
4608 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4609 * @chip: nand chip info structure
4610 * @caps: ECC engine caps info structure
4611 * @oobavail: OOB size that the ECC engine can use
4613 * If a chip's ECC requirement is provided, try to meet it with the least
4614 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4615 * On success, the chosen ECC settings are set.
4617 int nand_match_ecc_req(struct nand_chip
*chip
,
4618 const struct nand_ecc_caps
*caps
, int oobavail
)
4620 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4621 const struct nand_ecc_step_info
*stepinfo
;
4622 int req_step
= chip
->ecc_step_ds
;
4623 int req_strength
= chip
->ecc_strength_ds
;
4624 int req_corr
, step_size
, strength
, nsteps
, ecc_bytes
, ecc_bytes_total
;
4625 int best_step
, best_strength
, best_ecc_bytes
;
4626 int best_ecc_bytes_total
= INT_MAX
;
4629 if (WARN_ON(oobavail
< 0))
4632 /* No information provided by the NAND chip */
4633 if (!req_step
|| !req_strength
)
4636 /* number of correctable bits the chip requires in a page */
4637 req_corr
= mtd
->writesize
/ req_step
* req_strength
;
4639 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4640 stepinfo
= &caps
->stepinfos
[i
];
4641 step_size
= stepinfo
->stepsize
;
4643 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4644 strength
= stepinfo
->strengths
[j
];
4647 * If both step size and strength are smaller than the
4648 * chip's requirement, it is not easy to compare the
4649 * resulted reliability.
4651 if (step_size
< req_step
&& strength
< req_strength
)
4654 if (mtd
->writesize
% step_size
)
4657 nsteps
= mtd
->writesize
/ step_size
;
4659 ecc_bytes
= caps
->calc_ecc_bytes(step_size
, strength
);
4660 if (WARN_ON_ONCE(ecc_bytes
< 0))
4662 ecc_bytes_total
= ecc_bytes
* nsteps
;
4664 if (ecc_bytes_total
> oobavail
||
4665 strength
* nsteps
< req_corr
)
4669 * We assume the best is to meet the chip's requrement
4670 * with the least number of ECC bytes.
4672 if (ecc_bytes_total
< best_ecc_bytes_total
) {
4673 best_ecc_bytes_total
= ecc_bytes_total
;
4674 best_step
= step_size
;
4675 best_strength
= strength
;
4676 best_ecc_bytes
= ecc_bytes
;
4681 if (best_ecc_bytes_total
== INT_MAX
)
4684 chip
->ecc
.size
= best_step
;
4685 chip
->ecc
.strength
= best_strength
;
4686 chip
->ecc
.bytes
= best_ecc_bytes
;
4690 EXPORT_SYMBOL_GPL(nand_match_ecc_req
);
4693 * nand_maximize_ecc - choose the max ECC strength available
4694 * @chip: nand chip info structure
4695 * @caps: ECC engine caps info structure
4696 * @oobavail: OOB size that the ECC engine can use
4698 * Choose the max ECC strength that is supported on the controller, and can fit
4699 * within the chip's OOB. On success, the chosen ECC settings are set.
4701 int nand_maximize_ecc(struct nand_chip
*chip
,
4702 const struct nand_ecc_caps
*caps
, int oobavail
)
4704 struct mtd_info
*mtd
= nand_to_mtd(chip
);
4705 const struct nand_ecc_step_info
*stepinfo
;
4706 int step_size
, strength
, nsteps
, ecc_bytes
, corr
;
4709 int best_strength
, best_ecc_bytes
;
4712 if (WARN_ON(oobavail
< 0))
4715 for (i
= 0; i
< caps
->nstepinfos
; i
++) {
4716 stepinfo
= &caps
->stepinfos
[i
];
4717 step_size
= stepinfo
->stepsize
;
4719 /* If chip->ecc.size is already set, respect it */
4720 if (chip
->ecc
.size
&& step_size
!= chip
->ecc
.size
)
4723 for (j
= 0; j
< stepinfo
->nstrengths
; j
++) {
4724 strength
= stepinfo
->strengths
[j
];
4726 if (mtd
->writesize
% step_size
)
4729 nsteps
= mtd
->writesize
/ step_size
;
4731 ecc_bytes
= caps
->calc_ecc_bytes(step_size
, strength
);
4732 if (WARN_ON_ONCE(ecc_bytes
< 0))
4735 if (ecc_bytes
* nsteps
> oobavail
)
4738 corr
= strength
* nsteps
;
4741 * If the number of correctable bits is the same,
4742 * bigger step_size has more reliability.
4744 if (corr
> best_corr
||
4745 (corr
== best_corr
&& step_size
> best_step
)) {
4747 best_step
= step_size
;
4748 best_strength
= strength
;
4749 best_ecc_bytes
= ecc_bytes
;
4757 chip
->ecc
.size
= best_step
;
4758 chip
->ecc
.strength
= best_strength
;
4759 chip
->ecc
.bytes
= best_ecc_bytes
;
4763 EXPORT_SYMBOL_GPL(nand_maximize_ecc
);
4766 * Check if the chip configuration meet the datasheet requirements.
4768 * If our configuration corrects A bits per B bytes and the minimum
4769 * required correction level is X bits per Y bytes, then we must ensure
4770 * both of the following are true:
4772 * (1) A / B >= X / Y
4775 * Requirement (1) ensures we can correct for the required bitflip density.
4776 * Requirement (2) ensures we can correct even when all bitflips are clumped
4777 * in the same sector.
4779 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4781 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4782 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4785 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4786 /* Not enough information */
4790 * We get the number of corrected bits per page to compare
4791 * the correction density.
4793 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4794 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4796 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4799 static bool invalid_ecc_page_accessors(struct nand_chip
*chip
)
4801 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4803 if (nand_standard_page_accessors(ecc
))
4807 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4808 * controller driver implements all the page accessors because
4809 * default helpers are not suitable when the core does not
4810 * send the READ0/PAGEPROG commands.
4812 return (!ecc
->read_page
|| !ecc
->write_page
||
4813 !ecc
->read_page_raw
|| !ecc
->write_page_raw
||
4814 (NAND_HAS_SUBPAGE_READ(chip
) && !ecc
->read_subpage
) ||
4815 (NAND_HAS_SUBPAGE_WRITE(chip
) && !ecc
->write_subpage
&&
4816 ecc
->hwctl
&& ecc
->calculate
));
4820 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4821 * @mtd: MTD device structure
4823 * This is the second phase of the normal nand_scan() function. It fills out
4824 * all the uninitialized function pointers with the defaults and scans for a
4825 * bad block table if appropriate.
4827 int nand_scan_tail(struct mtd_info
*mtd
)
4829 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4830 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4831 struct nand_buffers
*nbuf
= NULL
;
4834 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4835 if (WARN_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4836 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
))) {
4841 if (invalid_ecc_page_accessors(chip
)) {
4842 pr_err("Invalid ECC page accessors setup\n");
4847 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4848 nbuf
= kzalloc(sizeof(*nbuf
), GFP_KERNEL
);
4854 nbuf
->ecccalc
= kmalloc(mtd
->oobsize
, GFP_KERNEL
);
4855 if (!nbuf
->ecccalc
) {
4860 nbuf
->ecccode
= kmalloc(mtd
->oobsize
, GFP_KERNEL
);
4861 if (!nbuf
->ecccode
) {
4866 nbuf
->databuf
= kmalloc(mtd
->writesize
+ mtd
->oobsize
,
4868 if (!nbuf
->databuf
) {
4873 chip
->buffers
= nbuf
;
4875 if (!chip
->buffers
) {
4881 /* Set the internal oob buffer location, just after the page data */
4882 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4885 * If no default placement scheme is given, select an appropriate one.
4887 if (!mtd
->ooblayout
&&
4888 !(ecc
->mode
== NAND_ECC_SOFT
&& ecc
->algo
== NAND_ECC_BCH
)) {
4889 switch (mtd
->oobsize
) {
4892 mtd_set_ooblayout(mtd
, &nand_ooblayout_sp_ops
);
4896 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_hamming_ops
);
4899 WARN(1, "No oob scheme defined for oobsize %d\n",
4907 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4908 * selected and we have 256 byte pagesize fallback to software ECC
4911 switch (ecc
->mode
) {
4912 case NAND_ECC_HW_OOB_FIRST
:
4913 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4914 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4915 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4919 if (!ecc
->read_page
)
4920 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4923 /* Use standard hwecc read page function? */
4924 if (!ecc
->read_page
)
4925 ecc
->read_page
= nand_read_page_hwecc
;
4926 if (!ecc
->write_page
)
4927 ecc
->write_page
= nand_write_page_hwecc
;
4928 if (!ecc
->read_page_raw
)
4929 ecc
->read_page_raw
= nand_read_page_raw
;
4930 if (!ecc
->write_page_raw
)
4931 ecc
->write_page_raw
= nand_write_page_raw
;
4933 ecc
->read_oob
= nand_read_oob_std
;
4934 if (!ecc
->write_oob
)
4935 ecc
->write_oob
= nand_write_oob_std
;
4936 if (!ecc
->read_subpage
)
4937 ecc
->read_subpage
= nand_read_subpage
;
4938 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4939 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4941 case NAND_ECC_HW_SYNDROME
:
4942 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4944 ecc
->read_page
== nand_read_page_hwecc
||
4946 ecc
->write_page
== nand_write_page_hwecc
)) {
4947 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4951 /* Use standard syndrome read/write page function? */
4952 if (!ecc
->read_page
)
4953 ecc
->read_page
= nand_read_page_syndrome
;
4954 if (!ecc
->write_page
)
4955 ecc
->write_page
= nand_write_page_syndrome
;
4956 if (!ecc
->read_page_raw
)
4957 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4958 if (!ecc
->write_page_raw
)
4959 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4961 ecc
->read_oob
= nand_read_oob_syndrome
;
4962 if (!ecc
->write_oob
)
4963 ecc
->write_oob
= nand_write_oob_syndrome
;
4965 if (mtd
->writesize
>= ecc
->size
) {
4966 if (!ecc
->strength
) {
4967 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4973 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4974 ecc
->size
, mtd
->writesize
);
4975 ecc
->mode
= NAND_ECC_SOFT
;
4976 ecc
->algo
= NAND_ECC_HAMMING
;
4979 ret
= nand_set_ecc_soft_ops(mtd
);
4986 case NAND_ECC_ON_DIE
:
4987 if (!ecc
->read_page
|| !ecc
->write_page
) {
4988 WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
4993 ecc
->read_oob
= nand_read_oob_std
;
4994 if (!ecc
->write_oob
)
4995 ecc
->write_oob
= nand_write_oob_std
;
4999 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
5000 ecc
->read_page
= nand_read_page_raw
;
5001 ecc
->write_page
= nand_write_page_raw
;
5002 ecc
->read_oob
= nand_read_oob_std
;
5003 ecc
->read_page_raw
= nand_read_page_raw
;
5004 ecc
->write_page_raw
= nand_write_page_raw
;
5005 ecc
->write_oob
= nand_write_oob_std
;
5006 ecc
->size
= mtd
->writesize
;
5012 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
5017 /* For many systems, the standard OOB write also works for raw */
5018 if (!ecc
->read_oob_raw
)
5019 ecc
->read_oob_raw
= ecc
->read_oob
;
5020 if (!ecc
->write_oob_raw
)
5021 ecc
->write_oob_raw
= ecc
->write_oob
;
5023 /* propagate ecc info to mtd_info */
5024 mtd
->ecc_strength
= ecc
->strength
;
5025 mtd
->ecc_step_size
= ecc
->size
;
5028 * Set the number of read / write steps for one page depending on ECC
5031 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
5032 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
5033 WARN(1, "Invalid ECC parameters\n");
5037 ecc
->total
= ecc
->steps
* ecc
->bytes
;
5038 if (ecc
->total
> mtd
->oobsize
) {
5039 WARN(1, "Total number of ECC bytes exceeded oobsize\n");
5045 * The number of bytes available for a client to place data into
5046 * the out of band area.
5048 ret
= mtd_ooblayout_count_freebytes(mtd
);
5052 mtd
->oobavail
= ret
;
5054 /* ECC sanity check: warn if it's too weak */
5055 if (!nand_ecc_strength_good(mtd
))
5056 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
5059 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
5060 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
5061 switch (ecc
->steps
) {
5063 mtd
->subpage_sft
= 1;
5068 mtd
->subpage_sft
= 2;
5072 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
5074 /* Initialize state */
5075 chip
->state
= FL_READY
;
5077 /* Invalidate the pagebuffer reference */
5080 /* Large page NAND with SOFT_ECC should support subpage reads */
5081 switch (ecc
->mode
) {
5083 if (chip
->page_shift
> 9)
5084 chip
->options
|= NAND_SUBPAGE_READ
;
5091 /* Fill in remaining MTD driver data */
5092 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
5093 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
5095 mtd
->_erase
= nand_erase
;
5097 mtd
->_unpoint
= NULL
;
5098 mtd
->_read
= nand_read
;
5099 mtd
->_write
= nand_write
;
5100 mtd
->_panic_write
= panic_nand_write
;
5101 mtd
->_read_oob
= nand_read_oob
;
5102 mtd
->_write_oob
= nand_write_oob
;
5103 mtd
->_sync
= nand_sync
;
5105 mtd
->_unlock
= NULL
;
5106 mtd
->_suspend
= nand_suspend
;
5107 mtd
->_resume
= nand_resume
;
5108 mtd
->_reboot
= nand_shutdown
;
5109 mtd
->_block_isreserved
= nand_block_isreserved
;
5110 mtd
->_block_isbad
= nand_block_isbad
;
5111 mtd
->_block_markbad
= nand_block_markbad
;
5112 mtd
->_max_bad_blocks
= nand_max_bad_blocks
;
5113 mtd
->writebufsize
= mtd
->writesize
;
5116 * Initialize bitflip_threshold to its default prior scan_bbt() call.
5117 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
5120 if (!mtd
->bitflip_threshold
)
5121 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
5123 /* Check, if we should skip the bad block table scan */
5124 if (chip
->options
& NAND_SKIP_BBTSCAN
)
5127 /* Build bad block table */
5128 ret
= chip
->scan_bbt(mtd
);
5135 kfree(nbuf
->databuf
);
5136 kfree(nbuf
->ecccode
);
5137 kfree(nbuf
->ecccalc
);
5142 /* Clean up nand_scan_ident(). */
5144 /* Free manufacturer priv data. */
5145 nand_manufacturer_cleanup(chip
);
5149 EXPORT_SYMBOL(nand_scan_tail
);
5152 * is_module_text_address() isn't exported, and it's mostly a pointless
5153 * test if this is a module _anyway_ -- they'd have to try _really_ hard
5154 * to call us from in-kernel code if the core NAND support is modular.
5157 #define caller_is_module() (1)
5159 #define caller_is_module() \
5160 is_module_text_address((unsigned long)__builtin_return_address(0))
5164 * nand_scan - [NAND Interface] Scan for the NAND device
5165 * @mtd: MTD device structure
5166 * @maxchips: number of chips to scan for
5168 * This fills out all the uninitialized function pointers with the defaults.
5169 * The flash ID is read and the mtd/chip structures are filled with the
5170 * appropriate values.
5172 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
5176 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
5178 ret
= nand_scan_tail(mtd
);
5181 EXPORT_SYMBOL(nand_scan
);
5184 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
5185 * @chip: NAND chip object
5187 void nand_cleanup(struct nand_chip
*chip
)
5189 if (chip
->ecc
.mode
== NAND_ECC_SOFT
&&
5190 chip
->ecc
.algo
== NAND_ECC_BCH
)
5191 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
5193 nand_release_data_interface(chip
);
5195 /* Free bad block table memory */
5197 if (!(chip
->options
& NAND_OWN_BUFFERS
) && chip
->buffers
) {
5198 kfree(chip
->buffers
->databuf
);
5199 kfree(chip
->buffers
->ecccode
);
5200 kfree(chip
->buffers
->ecccalc
);
5201 kfree(chip
->buffers
);
5204 /* Free bad block descriptor memory */
5205 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
5206 & NAND_BBT_DYNAMICSTRUCT
)
5207 kfree(chip
->badblock_pattern
);
5209 /* Free manufacturer priv data. */
5210 nand_manufacturer_cleanup(chip
);
5212 EXPORT_SYMBOL_GPL(nand_cleanup
);
5215 * nand_release - [NAND Interface] Unregister the MTD device and free resources
5216 * held by the NAND device
5217 * @mtd: MTD device structure
5219 void nand_release(struct mtd_info
*mtd
)
5221 mtd_device_unregister(mtd
);
5222 nand_cleanup(mtd_to_nand(mtd
));
5224 EXPORT_SYMBOL_GPL(nand_release
);
5226 MODULE_LICENSE("GPL");
5227 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
5228 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
5229 MODULE_DESCRIPTION("Generic NAND flash driver code");