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[mirror_ubuntu-focal-kernel.git] / drivers / mtd / nand / pxa3xx_nand.c
1 /*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * See Documentation/mtd/nand/pxa3xx-nand.txt for more details.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/dmaengine.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dma/pxa-dma.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/rawnand.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/io.h>
27 #include <linux/iopoll.h>
28 #include <linux/irq.h>
29 #include <linux/slab.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/platform_data/mtd-nand-pxa3xx.h>
33 #include <linux/mfd/syscon.h>
34 #include <linux/regmap.h>
35
36 #define CHIP_DELAY_TIMEOUT msecs_to_jiffies(200)
37 #define NAND_STOP_DELAY msecs_to_jiffies(40)
38 #define PAGE_CHUNK_SIZE (2048)
39
40 /*
41 * Define a buffer size for the initial command that detects the flash device:
42 * STATUS, READID and PARAM.
43 * ONFI param page is 256 bytes, and there are three redundant copies
44 * to be read. JEDEC param page is 512 bytes, and there are also three
45 * redundant copies to be read.
46 * Hence this buffer should be at least 512 x 3. Let's pick 2048.
47 */
48 #define INIT_BUFFER_SIZE 2048
49
50 /* System control register and bit to enable NAND on some SoCs */
51 #define GENCONF_SOC_DEVICE_MUX 0x208
52 #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
53
54 /* registers and bit definitions */
55 #define NDCR (0x00) /* Control register */
56 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
57 #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
58 #define NDSR (0x14) /* Status Register */
59 #define NDPCR (0x18) /* Page Count Register */
60 #define NDBDR0 (0x1C) /* Bad Block Register 0 */
61 #define NDBDR1 (0x20) /* Bad Block Register 1 */
62 #define NDECCCTRL (0x28) /* ECC control */
63 #define NDDB (0x40) /* Data Buffer */
64 #define NDCB0 (0x48) /* Command Buffer0 */
65 #define NDCB1 (0x4C) /* Command Buffer1 */
66 #define NDCB2 (0x50) /* Command Buffer2 */
67
68 #define NDCR_SPARE_EN (0x1 << 31)
69 #define NDCR_ECC_EN (0x1 << 30)
70 #define NDCR_DMA_EN (0x1 << 29)
71 #define NDCR_ND_RUN (0x1 << 28)
72 #define NDCR_DWIDTH_C (0x1 << 27)
73 #define NDCR_DWIDTH_M (0x1 << 26)
74 #define NDCR_PAGE_SZ (0x1 << 24)
75 #define NDCR_NCSX (0x1 << 23)
76 #define NDCR_ND_MODE (0x3 << 21)
77 #define NDCR_NAND_MODE (0x0)
78 #define NDCR_CLR_PG_CNT (0x1 << 20)
79 #define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
80 #define NFCV2_NDCR_STOP_ON_UNCOR (0x1 << 19)
81 #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
82 #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
83
84 #define NDCR_RA_START (0x1 << 15)
85 #define NDCR_PG_PER_BLK (0x1 << 14)
86 #define NDCR_ND_ARB_EN (0x1 << 12)
87 #define NDCR_INT_MASK (0xFFF)
88
89 #define NDSR_MASK (0xfff)
90 #define NDSR_ERR_CNT_OFF (16)
91 #define NDSR_ERR_CNT_MASK (0x1f)
92 #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
93 #define NDSR_RDY (0x1 << 12)
94 #define NDSR_FLASH_RDY (0x1 << 11)
95 #define NDSR_CS0_PAGED (0x1 << 10)
96 #define NDSR_CS1_PAGED (0x1 << 9)
97 #define NDSR_CS0_CMDD (0x1 << 8)
98 #define NDSR_CS1_CMDD (0x1 << 7)
99 #define NDSR_CS0_BBD (0x1 << 6)
100 #define NDSR_CS1_BBD (0x1 << 5)
101 #define NDSR_UNCORERR (0x1 << 4)
102 #define NDSR_CORERR (0x1 << 3)
103 #define NDSR_WRDREQ (0x1 << 2)
104 #define NDSR_RDDREQ (0x1 << 1)
105 #define NDSR_WRCMDREQ (0x1)
106
107 #define NDCB0_LEN_OVRD (0x1 << 28)
108 #define NDCB0_ST_ROW_EN (0x1 << 26)
109 #define NDCB0_AUTO_RS (0x1 << 25)
110 #define NDCB0_CSEL (0x1 << 24)
111 #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
112 #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
113 #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
114 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
115 #define NDCB0_NC (0x1 << 20)
116 #define NDCB0_DBC (0x1 << 19)
117 #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
118 #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
119 #define NDCB0_CMD2_MASK (0xff << 8)
120 #define NDCB0_CMD1_MASK (0xff)
121 #define NDCB0_ADDR_CYC_SHIFT (16)
122
123 #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
124 #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
125 #define EXT_CMD_TYPE_READ 4 /* Read */
126 #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
127 #define EXT_CMD_TYPE_FINAL 3 /* Final command */
128 #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
129 #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
130
131 /*
132 * This should be large enough to read 'ONFI' and 'JEDEC'.
133 * Let's use 7 bytes, which is the maximum ID count supported
134 * by the controller (see NDCR_RD_ID_CNT_MASK).
135 */
136 #define READ_ID_BYTES 7
137
138 /* macros for registers read/write */
139 #define nand_writel(info, off, val) \
140 do { \
141 dev_vdbg(&info->pdev->dev, \
142 "%s():%d nand_writel(0x%x, 0x%04x)\n", \
143 __func__, __LINE__, (val), (off)); \
144 writel_relaxed((val), (info)->mmio_base + (off)); \
145 } while (0)
146
147 #define nand_readl(info, off) \
148 ({ \
149 unsigned int _v; \
150 _v = readl_relaxed((info)->mmio_base + (off)); \
151 dev_vdbg(&info->pdev->dev, \
152 "%s():%d nand_readl(0x%04x) = 0x%x\n", \
153 __func__, __LINE__, (off), _v); \
154 _v; \
155 })
156
157 /* error code and state */
158 enum {
159 ERR_NONE = 0,
160 ERR_DMABUSERR = -1,
161 ERR_SENDCMD = -2,
162 ERR_UNCORERR = -3,
163 ERR_BBERR = -4,
164 ERR_CORERR = -5,
165 };
166
167 enum {
168 STATE_IDLE = 0,
169 STATE_PREPARED,
170 STATE_CMD_HANDLE,
171 STATE_DMA_READING,
172 STATE_DMA_WRITING,
173 STATE_DMA_DONE,
174 STATE_PIO_READING,
175 STATE_PIO_WRITING,
176 STATE_CMD_DONE,
177 STATE_READY,
178 };
179
180 enum pxa3xx_nand_variant {
181 PXA3XX_NAND_VARIANT_PXA,
182 PXA3XX_NAND_VARIANT_ARMADA370,
183 PXA3XX_NAND_VARIANT_ARMADA_8K,
184 };
185
186 struct pxa3xx_nand_host {
187 struct nand_chip chip;
188 void *info_data;
189
190 /* page size of attached chip */
191 int use_ecc;
192 int cs;
193
194 /* calculated from pxa3xx_nand_flash data */
195 unsigned int col_addr_cycles;
196 unsigned int row_addr_cycles;
197 };
198
199 struct pxa3xx_nand_info {
200 struct nand_hw_control controller;
201 struct platform_device *pdev;
202
203 struct clk *clk;
204 void __iomem *mmio_base;
205 unsigned long mmio_phys;
206 struct completion cmd_complete, dev_ready;
207
208 unsigned int buf_start;
209 unsigned int buf_count;
210 unsigned int buf_size;
211 unsigned int data_buff_pos;
212 unsigned int oob_buff_pos;
213
214 /* DMA information */
215 struct scatterlist sg;
216 enum dma_data_direction dma_dir;
217 struct dma_chan *dma_chan;
218 dma_cookie_t dma_cookie;
219 int drcmr_dat;
220
221 unsigned char *data_buff;
222 unsigned char *oob_buff;
223 dma_addr_t data_buff_phys;
224 int data_dma_ch;
225
226 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
227 unsigned int state;
228
229 /*
230 * This driver supports NFCv1 (as found in PXA SoC)
231 * and NFCv2 (as found in Armada 370/XP SoC).
232 */
233 enum pxa3xx_nand_variant variant;
234
235 int cs;
236 int use_ecc; /* use HW ECC ? */
237 int ecc_bch; /* using BCH ECC? */
238 int use_dma; /* use DMA ? */
239 int use_spare; /* use spare ? */
240 int need_wait;
241
242 /* Amount of real data per full chunk */
243 unsigned int chunk_size;
244
245 /* Amount of spare data per full chunk */
246 unsigned int spare_size;
247
248 /* Number of full chunks (i.e chunk_size + spare_size) */
249 unsigned int nfullchunks;
250
251 /*
252 * Total number of chunks. If equal to nfullchunks, then there
253 * are only full chunks. Otherwise, there is one last chunk of
254 * size (last_chunk_size + last_spare_size)
255 */
256 unsigned int ntotalchunks;
257
258 /* Amount of real data in the last chunk */
259 unsigned int last_chunk_size;
260
261 /* Amount of spare data in the last chunk */
262 unsigned int last_spare_size;
263
264 unsigned int ecc_size;
265 unsigned int ecc_err_cnt;
266 unsigned int max_bitflips;
267 int retcode;
268
269 /*
270 * Variables only valid during command
271 * execution. step_chunk_size and step_spare_size is the
272 * amount of real data and spare data in the current
273 * chunk. cur_chunk is the current chunk being
274 * read/programmed.
275 */
276 unsigned int step_chunk_size;
277 unsigned int step_spare_size;
278 unsigned int cur_chunk;
279
280 /* cached register value */
281 uint32_t reg_ndcr;
282 uint32_t ndtr0cs0;
283 uint32_t ndtr1cs0;
284
285 /* generated NDCBx register values */
286 uint32_t ndcb0;
287 uint32_t ndcb1;
288 uint32_t ndcb2;
289 uint32_t ndcb3;
290 };
291
292 static bool use_dma = 1;
293 module_param(use_dma, bool, 0444);
294 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
295
296 struct pxa3xx_nand_timing {
297 unsigned int tCH; /* Enable signal hold time */
298 unsigned int tCS; /* Enable signal setup time */
299 unsigned int tWH; /* ND_nWE high duration */
300 unsigned int tWP; /* ND_nWE pulse time */
301 unsigned int tRH; /* ND_nRE high duration */
302 unsigned int tRP; /* ND_nRE pulse width */
303 unsigned int tR; /* ND_nWE high to ND_nRE low for read */
304 unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
305 unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
306 };
307
308 struct pxa3xx_nand_flash {
309 uint32_t chip_id;
310 unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
311 unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
312 struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
313 };
314
315 static struct pxa3xx_nand_timing timing[] = {
316 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
317 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
318 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
319 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
320 };
321
322 static struct pxa3xx_nand_flash builtin_flash_types[] = {
323 { 0x46ec, 16, 16, &timing[1] },
324 { 0xdaec, 8, 8, &timing[1] },
325 { 0xd7ec, 8, 8, &timing[1] },
326 { 0xa12c, 8, 8, &timing[2] },
327 { 0xb12c, 16, 16, &timing[2] },
328 { 0xdc2c, 8, 8, &timing[2] },
329 { 0xcc2c, 16, 16, &timing[2] },
330 { 0xba20, 16, 16, &timing[3] },
331 };
332
333 static int pxa3xx_ooblayout_ecc(struct mtd_info *mtd, int section,
334 struct mtd_oob_region *oobregion)
335 {
336 struct nand_chip *chip = mtd_to_nand(mtd);
337 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
338 struct pxa3xx_nand_info *info = host->info_data;
339 int nchunks = mtd->writesize / info->chunk_size;
340
341 if (section >= nchunks)
342 return -ERANGE;
343
344 oobregion->offset = ((info->ecc_size + info->spare_size) * section) +
345 info->spare_size;
346 oobregion->length = info->ecc_size;
347
348 return 0;
349 }
350
351 static int pxa3xx_ooblayout_free(struct mtd_info *mtd, int section,
352 struct mtd_oob_region *oobregion)
353 {
354 struct nand_chip *chip = mtd_to_nand(mtd);
355 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
356 struct pxa3xx_nand_info *info = host->info_data;
357 int nchunks = mtd->writesize / info->chunk_size;
358
359 if (section >= nchunks)
360 return -ERANGE;
361
362 if (!info->spare_size)
363 return 0;
364
365 oobregion->offset = section * (info->ecc_size + info->spare_size);
366 oobregion->length = info->spare_size;
367 if (!section) {
368 /*
369 * Bootrom looks in bytes 0 & 5 for bad blocks for the
370 * 4KB page / 4bit BCH combination.
371 */
372 if (mtd->writesize == 4096 && info->chunk_size == 2048) {
373 oobregion->offset += 6;
374 oobregion->length -= 6;
375 } else {
376 oobregion->offset += 2;
377 oobregion->length -= 2;
378 }
379 }
380
381 return 0;
382 }
383
384 static const struct mtd_ooblayout_ops pxa3xx_ooblayout_ops = {
385 .ecc = pxa3xx_ooblayout_ecc,
386 .free = pxa3xx_ooblayout_free,
387 };
388
389 static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
390 static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
391
392 static struct nand_bbt_descr bbt_main_descr = {
393 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
394 | NAND_BBT_2BIT | NAND_BBT_VERSION,
395 .offs = 8,
396 .len = 6,
397 .veroffs = 14,
398 .maxblocks = 8, /* Last 8 blocks in each chip */
399 .pattern = bbt_pattern
400 };
401
402 static struct nand_bbt_descr bbt_mirror_descr = {
403 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
404 | NAND_BBT_2BIT | NAND_BBT_VERSION,
405 .offs = 8,
406 .len = 6,
407 .veroffs = 14,
408 .maxblocks = 8, /* Last 8 blocks in each chip */
409 .pattern = bbt_mirror_pattern
410 };
411
412 #define NDTR0_tCH(c) (min((c), 7) << 19)
413 #define NDTR0_tCS(c) (min((c), 7) << 16)
414 #define NDTR0_tWH(c) (min((c), 7) << 11)
415 #define NDTR0_tWP(c) (min((c), 7) << 8)
416 #define NDTR0_tRH(c) (min((c), 7) << 3)
417 #define NDTR0_tRP(c) (min((c), 7) << 0)
418
419 #define NDTR1_tR(c) (min((c), 65535) << 16)
420 #define NDTR1_tWHR(c) (min((c), 15) << 4)
421 #define NDTR1_tAR(c) (min((c), 15) << 0)
422
423 /* convert nano-seconds to nand flash controller clock cycles */
424 #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
425
426 static const struct of_device_id pxa3xx_nand_dt_ids[] = {
427 {
428 .compatible = "marvell,pxa3xx-nand",
429 .data = (void *)PXA3XX_NAND_VARIANT_PXA,
430 },
431 {
432 .compatible = "marvell,armada370-nand",
433 .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
434 },
435 {
436 .compatible = "marvell,armada-8k-nand",
437 .data = (void *)PXA3XX_NAND_VARIANT_ARMADA_8K,
438 },
439 {}
440 };
441 MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
442
443 static enum pxa3xx_nand_variant
444 pxa3xx_nand_get_variant(struct platform_device *pdev)
445 {
446 const struct of_device_id *of_id =
447 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
448 if (!of_id)
449 return PXA3XX_NAND_VARIANT_PXA;
450 return (enum pxa3xx_nand_variant)of_id->data;
451 }
452
453 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
454 const struct pxa3xx_nand_timing *t)
455 {
456 struct pxa3xx_nand_info *info = host->info_data;
457 unsigned long nand_clk = clk_get_rate(info->clk);
458 uint32_t ndtr0, ndtr1;
459
460 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
461 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
462 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
463 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
464 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
465 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
466
467 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
468 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
469 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
470
471 info->ndtr0cs0 = ndtr0;
472 info->ndtr1cs0 = ndtr1;
473 nand_writel(info, NDTR0CS0, ndtr0);
474 nand_writel(info, NDTR1CS0, ndtr1);
475 }
476
477 static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
478 const struct nand_sdr_timings *t)
479 {
480 struct pxa3xx_nand_info *info = host->info_data;
481 struct nand_chip *chip = &host->chip;
482 unsigned long nand_clk = clk_get_rate(info->clk);
483 uint32_t ndtr0, ndtr1;
484
485 u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
486 u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
487 u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
488 u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
489 u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
490 u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
491 u32 tR = chip->chip_delay * 1000;
492 u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
493 u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
494
495 /* fallback to a default value if tR = 0 */
496 if (!tR)
497 tR = 20000;
498
499 ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
500 NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
501 NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
502 NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
503 NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
504 NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
505
506 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
507 NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
508 NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
509
510 info->ndtr0cs0 = ndtr0;
511 info->ndtr1cs0 = ndtr1;
512 nand_writel(info, NDTR0CS0, ndtr0);
513 nand_writel(info, NDTR1CS0, ndtr1);
514 }
515
516 static int pxa3xx_nand_init_timings_compat(struct pxa3xx_nand_host *host,
517 unsigned int *flash_width,
518 unsigned int *dfc_width)
519 {
520 struct nand_chip *chip = &host->chip;
521 struct pxa3xx_nand_info *info = host->info_data;
522 const struct pxa3xx_nand_flash *f = NULL;
523 struct mtd_info *mtd = nand_to_mtd(&host->chip);
524 int i, id, ntypes;
525
526 ntypes = ARRAY_SIZE(builtin_flash_types);
527
528 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
529
530 id = chip->read_byte(mtd);
531 id |= chip->read_byte(mtd) << 0x8;
532
533 for (i = 0; i < ntypes; i++) {
534 f = &builtin_flash_types[i];
535
536 if (f->chip_id == id)
537 break;
538 }
539
540 if (i == ntypes) {
541 dev_err(&info->pdev->dev, "Error: timings not found\n");
542 return -EINVAL;
543 }
544
545 pxa3xx_nand_set_timing(host, f->timing);
546
547 *flash_width = f->flash_width;
548 *dfc_width = f->dfc_width;
549
550 return 0;
551 }
552
553 static int pxa3xx_nand_init_timings_onfi(struct pxa3xx_nand_host *host,
554 int mode)
555 {
556 const struct nand_sdr_timings *timings;
557
558 mode = fls(mode) - 1;
559 if (mode < 0)
560 mode = 0;
561
562 timings = onfi_async_timing_mode_to_sdr_timings(mode);
563 if (IS_ERR(timings))
564 return PTR_ERR(timings);
565
566 pxa3xx_nand_set_sdr_timing(host, timings);
567
568 return 0;
569 }
570
571 static int pxa3xx_nand_init(struct pxa3xx_nand_host *host)
572 {
573 struct nand_chip *chip = &host->chip;
574 struct pxa3xx_nand_info *info = host->info_data;
575 unsigned int flash_width = 0, dfc_width = 0;
576 int mode, err;
577
578 mode = onfi_get_async_timing_mode(chip);
579 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
580 err = pxa3xx_nand_init_timings_compat(host, &flash_width,
581 &dfc_width);
582 if (err)
583 return err;
584
585 if (flash_width == 16) {
586 info->reg_ndcr |= NDCR_DWIDTH_M;
587 chip->options |= NAND_BUSWIDTH_16;
588 }
589
590 info->reg_ndcr |= (dfc_width == 16) ? NDCR_DWIDTH_C : 0;
591 } else {
592 err = pxa3xx_nand_init_timings_onfi(host, mode);
593 if (err)
594 return err;
595 }
596
597 return 0;
598 }
599
600 /**
601 * NOTE: it is a must to set ND_RUN firstly, then write
602 * command buffer, otherwise, it does not work.
603 * We enable all the interrupt at the same time, and
604 * let pxa3xx_nand_irq to handle all logic.
605 */
606 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
607 {
608 uint32_t ndcr;
609
610 ndcr = info->reg_ndcr;
611
612 if (info->use_ecc) {
613 ndcr |= NDCR_ECC_EN;
614 if (info->ecc_bch)
615 nand_writel(info, NDECCCTRL, 0x1);
616 } else {
617 ndcr &= ~NDCR_ECC_EN;
618 if (info->ecc_bch)
619 nand_writel(info, NDECCCTRL, 0x0);
620 }
621
622 if (info->use_dma)
623 ndcr |= NDCR_DMA_EN;
624 else
625 ndcr &= ~NDCR_DMA_EN;
626
627 if (info->use_spare)
628 ndcr |= NDCR_SPARE_EN;
629 else
630 ndcr &= ~NDCR_SPARE_EN;
631
632 ndcr |= NDCR_ND_RUN;
633
634 /* clear status bits and run */
635 nand_writel(info, NDSR, NDSR_MASK);
636 nand_writel(info, NDCR, 0);
637 nand_writel(info, NDCR, ndcr);
638 }
639
640 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
641 {
642 uint32_t ndcr;
643 int timeout = NAND_STOP_DELAY;
644
645 /* wait RUN bit in NDCR become 0 */
646 ndcr = nand_readl(info, NDCR);
647 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
648 ndcr = nand_readl(info, NDCR);
649 udelay(1);
650 }
651
652 if (timeout <= 0) {
653 ndcr &= ~NDCR_ND_RUN;
654 nand_writel(info, NDCR, ndcr);
655 }
656 if (info->dma_chan)
657 dmaengine_terminate_all(info->dma_chan);
658
659 /* clear status bits */
660 nand_writel(info, NDSR, NDSR_MASK);
661 }
662
663 static void __maybe_unused
664 enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
665 {
666 uint32_t ndcr;
667
668 ndcr = nand_readl(info, NDCR);
669 nand_writel(info, NDCR, ndcr & ~int_mask);
670 }
671
672 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
673 {
674 uint32_t ndcr;
675
676 ndcr = nand_readl(info, NDCR);
677 nand_writel(info, NDCR, ndcr | int_mask);
678 }
679
680 static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
681 {
682 if (info->ecc_bch) {
683 u32 val;
684 int ret;
685
686 /*
687 * According to the datasheet, when reading from NDDB
688 * with BCH enabled, after each 32 bytes reads, we
689 * have to make sure that the NDSR.RDDREQ bit is set.
690 *
691 * Drain the FIFO 8 32 bits reads at a time, and skip
692 * the polling on the last read.
693 */
694 while (len > 8) {
695 ioread32_rep(info->mmio_base + NDDB, data, 8);
696
697 ret = readl_relaxed_poll_timeout(info->mmio_base + NDSR, val,
698 val & NDSR_RDDREQ, 1000, 5000);
699 if (ret) {
700 dev_err(&info->pdev->dev,
701 "Timeout on RDDREQ while draining the FIFO\n");
702 return;
703 }
704
705 data += 32;
706 len -= 8;
707 }
708 }
709
710 ioread32_rep(info->mmio_base + NDDB, data, len);
711 }
712
713 static void handle_data_pio(struct pxa3xx_nand_info *info)
714 {
715 switch (info->state) {
716 case STATE_PIO_WRITING:
717 if (info->step_chunk_size)
718 writesl(info->mmio_base + NDDB,
719 info->data_buff + info->data_buff_pos,
720 DIV_ROUND_UP(info->step_chunk_size, 4));
721
722 if (info->step_spare_size)
723 writesl(info->mmio_base + NDDB,
724 info->oob_buff + info->oob_buff_pos,
725 DIV_ROUND_UP(info->step_spare_size, 4));
726 break;
727 case STATE_PIO_READING:
728 if (info->step_chunk_size)
729 drain_fifo(info,
730 info->data_buff + info->data_buff_pos,
731 DIV_ROUND_UP(info->step_chunk_size, 4));
732
733 if (info->step_spare_size)
734 drain_fifo(info,
735 info->oob_buff + info->oob_buff_pos,
736 DIV_ROUND_UP(info->step_spare_size, 4));
737 break;
738 default:
739 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
740 info->state);
741 BUG();
742 }
743
744 /* Update buffer pointers for multi-page read/write */
745 info->data_buff_pos += info->step_chunk_size;
746 info->oob_buff_pos += info->step_spare_size;
747 }
748
749 static void pxa3xx_nand_data_dma_irq(void *data)
750 {
751 struct pxa3xx_nand_info *info = data;
752 struct dma_tx_state state;
753 enum dma_status status;
754
755 status = dmaengine_tx_status(info->dma_chan, info->dma_cookie, &state);
756 if (likely(status == DMA_COMPLETE)) {
757 info->state = STATE_DMA_DONE;
758 } else {
759 dev_err(&info->pdev->dev, "DMA error on data channel\n");
760 info->retcode = ERR_DMABUSERR;
761 }
762 dma_unmap_sg(info->dma_chan->device->dev, &info->sg, 1, info->dma_dir);
763
764 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
765 enable_int(info, NDCR_INT_MASK);
766 }
767
768 static void start_data_dma(struct pxa3xx_nand_info *info)
769 {
770 enum dma_transfer_direction direction;
771 struct dma_async_tx_descriptor *tx;
772
773 switch (info->state) {
774 case STATE_DMA_WRITING:
775 info->dma_dir = DMA_TO_DEVICE;
776 direction = DMA_MEM_TO_DEV;
777 break;
778 case STATE_DMA_READING:
779 info->dma_dir = DMA_FROM_DEVICE;
780 direction = DMA_DEV_TO_MEM;
781 break;
782 default:
783 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
784 info->state);
785 BUG();
786 }
787 info->sg.length = info->chunk_size;
788 if (info->use_spare)
789 info->sg.length += info->spare_size + info->ecc_size;
790 dma_map_sg(info->dma_chan->device->dev, &info->sg, 1, info->dma_dir);
791
792 tx = dmaengine_prep_slave_sg(info->dma_chan, &info->sg, 1, direction,
793 DMA_PREP_INTERRUPT);
794 if (!tx) {
795 dev_err(&info->pdev->dev, "prep_slave_sg() failed\n");
796 return;
797 }
798 tx->callback = pxa3xx_nand_data_dma_irq;
799 tx->callback_param = info;
800 info->dma_cookie = dmaengine_submit(tx);
801 dma_async_issue_pending(info->dma_chan);
802 dev_dbg(&info->pdev->dev, "%s(dir=%d cookie=%x size=%u)\n",
803 __func__, direction, info->dma_cookie, info->sg.length);
804 }
805
806 static irqreturn_t pxa3xx_nand_irq_thread(int irq, void *data)
807 {
808 struct pxa3xx_nand_info *info = data;
809
810 handle_data_pio(info);
811
812 info->state = STATE_CMD_DONE;
813 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
814
815 return IRQ_HANDLED;
816 }
817
818 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
819 {
820 struct pxa3xx_nand_info *info = devid;
821 unsigned int status, is_completed = 0, is_ready = 0;
822 unsigned int ready, cmd_done;
823 irqreturn_t ret = IRQ_HANDLED;
824
825 if (info->cs == 0) {
826 ready = NDSR_FLASH_RDY;
827 cmd_done = NDSR_CS0_CMDD;
828 } else {
829 ready = NDSR_RDY;
830 cmd_done = NDSR_CS1_CMDD;
831 }
832
833 status = nand_readl(info, NDSR);
834
835 if (status & NDSR_UNCORERR)
836 info->retcode = ERR_UNCORERR;
837 if (status & NDSR_CORERR) {
838 info->retcode = ERR_CORERR;
839 if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
840 info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) &&
841 info->ecc_bch)
842 info->ecc_err_cnt = NDSR_ERR_CNT(status);
843 else
844 info->ecc_err_cnt = 1;
845
846 /*
847 * Each chunk composing a page is corrected independently,
848 * and we need to store maximum number of corrected bitflips
849 * to return it to the MTD layer in ecc.read_page().
850 */
851 info->max_bitflips = max_t(unsigned int,
852 info->max_bitflips,
853 info->ecc_err_cnt);
854 }
855 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
856 /* whether use dma to transfer data */
857 if (info->use_dma) {
858 disable_int(info, NDCR_INT_MASK);
859 info->state = (status & NDSR_RDDREQ) ?
860 STATE_DMA_READING : STATE_DMA_WRITING;
861 start_data_dma(info);
862 goto NORMAL_IRQ_EXIT;
863 } else {
864 info->state = (status & NDSR_RDDREQ) ?
865 STATE_PIO_READING : STATE_PIO_WRITING;
866 ret = IRQ_WAKE_THREAD;
867 goto NORMAL_IRQ_EXIT;
868 }
869 }
870 if (status & cmd_done) {
871 info->state = STATE_CMD_DONE;
872 is_completed = 1;
873 }
874 if (status & ready) {
875 info->state = STATE_READY;
876 is_ready = 1;
877 }
878
879 /*
880 * Clear all status bit before issuing the next command, which
881 * can and will alter the status bits and will deserve a new
882 * interrupt on its own. This lets the controller exit the IRQ
883 */
884 nand_writel(info, NDSR, status);
885
886 if (status & NDSR_WRCMDREQ) {
887 status &= ~NDSR_WRCMDREQ;
888 info->state = STATE_CMD_HANDLE;
889
890 /*
891 * Command buffer registers NDCB{0-2} (and optionally NDCB3)
892 * must be loaded by writing directly either 12 or 16
893 * bytes directly to NDCB0, four bytes at a time.
894 *
895 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
896 * but each NDCBx register can be read.
897 */
898 nand_writel(info, NDCB0, info->ndcb0);
899 nand_writel(info, NDCB0, info->ndcb1);
900 nand_writel(info, NDCB0, info->ndcb2);
901
902 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
903 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
904 info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
905 nand_writel(info, NDCB0, info->ndcb3);
906 }
907
908 if (is_completed)
909 complete(&info->cmd_complete);
910 if (is_ready)
911 complete(&info->dev_ready);
912 NORMAL_IRQ_EXIT:
913 return ret;
914 }
915
916 static inline int is_buf_blank(uint8_t *buf, size_t len)
917 {
918 for (; len > 0; len--)
919 if (*buf++ != 0xff)
920 return 0;
921 return 1;
922 }
923
924 static void set_command_address(struct pxa3xx_nand_info *info,
925 unsigned int page_size, uint16_t column, int page_addr)
926 {
927 /* small page addr setting */
928 if (page_size < PAGE_CHUNK_SIZE) {
929 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
930 | (column & 0xFF);
931
932 info->ndcb2 = 0;
933 } else {
934 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
935 | (column & 0xFFFF);
936
937 if (page_addr & 0xFF0000)
938 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
939 else
940 info->ndcb2 = 0;
941 }
942 }
943
944 static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
945 {
946 struct pxa3xx_nand_host *host = info->host[info->cs];
947 struct mtd_info *mtd = nand_to_mtd(&host->chip);
948
949 /* reset data and oob column point to handle data */
950 info->buf_start = 0;
951 info->buf_count = 0;
952 info->data_buff_pos = 0;
953 info->oob_buff_pos = 0;
954 info->step_chunk_size = 0;
955 info->step_spare_size = 0;
956 info->cur_chunk = 0;
957 info->use_ecc = 0;
958 info->use_spare = 1;
959 info->retcode = ERR_NONE;
960 info->ecc_err_cnt = 0;
961 info->ndcb3 = 0;
962 info->need_wait = 0;
963
964 switch (command) {
965 case NAND_CMD_READ0:
966 case NAND_CMD_PAGEPROG:
967 info->use_ecc = 1;
968 break;
969 case NAND_CMD_PARAM:
970 info->use_spare = 0;
971 break;
972 default:
973 info->ndcb1 = 0;
974 info->ndcb2 = 0;
975 break;
976 }
977
978 /*
979 * If we are about to issue a read command, or about to set
980 * the write address, then clean the data buffer.
981 */
982 if (command == NAND_CMD_READ0 ||
983 command == NAND_CMD_READOOB ||
984 command == NAND_CMD_SEQIN) {
985
986 info->buf_count = mtd->writesize + mtd->oobsize;
987 memset(info->data_buff, 0xFF, info->buf_count);
988 }
989
990 }
991
992 static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
993 int ext_cmd_type, uint16_t column, int page_addr)
994 {
995 int addr_cycle, exec_cmd;
996 struct pxa3xx_nand_host *host;
997 struct mtd_info *mtd;
998
999 host = info->host[info->cs];
1000 mtd = nand_to_mtd(&host->chip);
1001 addr_cycle = 0;
1002 exec_cmd = 1;
1003
1004 if (info->cs != 0)
1005 info->ndcb0 = NDCB0_CSEL;
1006 else
1007 info->ndcb0 = 0;
1008
1009 if (command == NAND_CMD_SEQIN)
1010 exec_cmd = 0;
1011
1012 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
1013 + host->col_addr_cycles);
1014
1015 switch (command) {
1016 case NAND_CMD_READOOB:
1017 case NAND_CMD_READ0:
1018 info->buf_start = column;
1019 info->ndcb0 |= NDCB0_CMD_TYPE(0)
1020 | addr_cycle
1021 | NAND_CMD_READ0;
1022
1023 if (command == NAND_CMD_READOOB)
1024 info->buf_start += mtd->writesize;
1025
1026 if (info->cur_chunk < info->nfullchunks) {
1027 info->step_chunk_size = info->chunk_size;
1028 info->step_spare_size = info->spare_size;
1029 } else {
1030 info->step_chunk_size = info->last_chunk_size;
1031 info->step_spare_size = info->last_spare_size;
1032 }
1033
1034 /*
1035 * Multiple page read needs an 'extended command type' field,
1036 * which is either naked-read or last-read according to the
1037 * state.
1038 */
1039 if (mtd->writesize == PAGE_CHUNK_SIZE) {
1040 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
1041 } else if (mtd->writesize > PAGE_CHUNK_SIZE) {
1042 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
1043 | NDCB0_LEN_OVRD
1044 | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
1045 info->ndcb3 = info->step_chunk_size +
1046 info->step_spare_size;
1047 }
1048
1049 set_command_address(info, mtd->writesize, column, page_addr);
1050 break;
1051
1052 case NAND_CMD_SEQIN:
1053
1054 info->buf_start = column;
1055 set_command_address(info, mtd->writesize, 0, page_addr);
1056
1057 /*
1058 * Multiple page programming needs to execute the initial
1059 * SEQIN command that sets the page address.
1060 */
1061 if (mtd->writesize > PAGE_CHUNK_SIZE) {
1062 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
1063 | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
1064 | addr_cycle
1065 | command;
1066 exec_cmd = 1;
1067 }
1068 break;
1069
1070 case NAND_CMD_PAGEPROG:
1071 if (is_buf_blank(info->data_buff,
1072 (mtd->writesize + mtd->oobsize))) {
1073 exec_cmd = 0;
1074 break;
1075 }
1076
1077 if (info->cur_chunk < info->nfullchunks) {
1078 info->step_chunk_size = info->chunk_size;
1079 info->step_spare_size = info->spare_size;
1080 } else {
1081 info->step_chunk_size = info->last_chunk_size;
1082 info->step_spare_size = info->last_spare_size;
1083 }
1084
1085 /* Second command setting for large pages */
1086 if (mtd->writesize > PAGE_CHUNK_SIZE) {
1087 /*
1088 * Multiple page write uses the 'extended command'
1089 * field. This can be used to issue a command dispatch
1090 * or a naked-write depending on the current stage.
1091 */
1092 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
1093 | NDCB0_LEN_OVRD
1094 | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
1095 info->ndcb3 = info->step_chunk_size +
1096 info->step_spare_size;
1097
1098 /*
1099 * This is the command dispatch that completes a chunked
1100 * page program operation.
1101 */
1102 if (info->cur_chunk == info->ntotalchunks) {
1103 info->ndcb0 = NDCB0_CMD_TYPE(0x1)
1104 | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
1105 | command;
1106 info->ndcb1 = 0;
1107 info->ndcb2 = 0;
1108 info->ndcb3 = 0;
1109 }
1110 } else {
1111 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
1112 | NDCB0_AUTO_RS
1113 | NDCB0_ST_ROW_EN
1114 | NDCB0_DBC
1115 | (NAND_CMD_PAGEPROG << 8)
1116 | NAND_CMD_SEQIN
1117 | addr_cycle;
1118 }
1119 break;
1120
1121 case NAND_CMD_PARAM:
1122 info->buf_count = INIT_BUFFER_SIZE;
1123 info->ndcb0 |= NDCB0_CMD_TYPE(0)
1124 | NDCB0_ADDR_CYC(1)
1125 | NDCB0_LEN_OVRD
1126 | command;
1127 info->ndcb1 = (column & 0xFF);
1128 info->ndcb3 = INIT_BUFFER_SIZE;
1129 info->step_chunk_size = INIT_BUFFER_SIZE;
1130 break;
1131
1132 case NAND_CMD_READID:
1133 info->buf_count = READ_ID_BYTES;
1134 info->ndcb0 |= NDCB0_CMD_TYPE(3)
1135 | NDCB0_ADDR_CYC(1)
1136 | command;
1137 info->ndcb1 = (column & 0xFF);
1138
1139 info->step_chunk_size = 8;
1140 break;
1141 case NAND_CMD_STATUS:
1142 info->buf_count = 1;
1143 info->ndcb0 |= NDCB0_CMD_TYPE(4)
1144 | NDCB0_ADDR_CYC(1)
1145 | command;
1146
1147 info->step_chunk_size = 8;
1148 break;
1149
1150 case NAND_CMD_ERASE1:
1151 info->ndcb0 |= NDCB0_CMD_TYPE(2)
1152 | NDCB0_AUTO_RS
1153 | NDCB0_ADDR_CYC(3)
1154 | NDCB0_DBC
1155 | (NAND_CMD_ERASE2 << 8)
1156 | NAND_CMD_ERASE1;
1157 info->ndcb1 = page_addr;
1158 info->ndcb2 = 0;
1159
1160 break;
1161 case NAND_CMD_RESET:
1162 info->ndcb0 |= NDCB0_CMD_TYPE(5)
1163 | command;
1164
1165 break;
1166
1167 case NAND_CMD_ERASE2:
1168 exec_cmd = 0;
1169 break;
1170
1171 default:
1172 exec_cmd = 0;
1173 dev_err(&info->pdev->dev, "non-supported command %x\n",
1174 command);
1175 break;
1176 }
1177
1178 return exec_cmd;
1179 }
1180
1181 static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
1182 int column, int page_addr)
1183 {
1184 struct nand_chip *chip = mtd_to_nand(mtd);
1185 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1186 struct pxa3xx_nand_info *info = host->info_data;
1187 int exec_cmd;
1188
1189 /*
1190 * if this is a x16 device ,then convert the input
1191 * "byte" address into a "word" address appropriate
1192 * for indexing a word-oriented device
1193 */
1194 if (info->reg_ndcr & NDCR_DWIDTH_M)
1195 column /= 2;
1196
1197 /*
1198 * There may be different NAND chip hooked to
1199 * different chip select, so check whether
1200 * chip select has been changed, if yes, reset the timing
1201 */
1202 if (info->cs != host->cs) {
1203 info->cs = host->cs;
1204 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1205 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
1206 }
1207
1208 prepare_start_command(info, command);
1209
1210 info->state = STATE_PREPARED;
1211 exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
1212
1213 if (exec_cmd) {
1214 init_completion(&info->cmd_complete);
1215 init_completion(&info->dev_ready);
1216 info->need_wait = 1;
1217 pxa3xx_nand_start(info);
1218
1219 if (!wait_for_completion_timeout(&info->cmd_complete,
1220 CHIP_DELAY_TIMEOUT)) {
1221 dev_err(&info->pdev->dev, "Wait time out!!!\n");
1222 /* Stop State Machine for next command cycle */
1223 pxa3xx_nand_stop(info);
1224 }
1225 }
1226 info->state = STATE_IDLE;
1227 }
1228
1229 static void nand_cmdfunc_extended(struct mtd_info *mtd,
1230 const unsigned command,
1231 int column, int page_addr)
1232 {
1233 struct nand_chip *chip = mtd_to_nand(mtd);
1234 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1235 struct pxa3xx_nand_info *info = host->info_data;
1236 int exec_cmd, ext_cmd_type;
1237
1238 /*
1239 * if this is a x16 device then convert the input
1240 * "byte" address into a "word" address appropriate
1241 * for indexing a word-oriented device
1242 */
1243 if (info->reg_ndcr & NDCR_DWIDTH_M)
1244 column /= 2;
1245
1246 /*
1247 * There may be different NAND chip hooked to
1248 * different chip select, so check whether
1249 * chip select has been changed, if yes, reset the timing
1250 */
1251 if (info->cs != host->cs) {
1252 info->cs = host->cs;
1253 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1254 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
1255 }
1256
1257 /* Select the extended command for the first command */
1258 switch (command) {
1259 case NAND_CMD_READ0:
1260 case NAND_CMD_READOOB:
1261 ext_cmd_type = EXT_CMD_TYPE_MONO;
1262 break;
1263 case NAND_CMD_SEQIN:
1264 ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
1265 break;
1266 case NAND_CMD_PAGEPROG:
1267 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
1268 break;
1269 default:
1270 ext_cmd_type = 0;
1271 break;
1272 }
1273
1274 prepare_start_command(info, command);
1275
1276 /*
1277 * Prepare the "is ready" completion before starting a command
1278 * transaction sequence. If the command is not executed the
1279 * completion will be completed, see below.
1280 *
1281 * We can do that inside the loop because the command variable
1282 * is invariant and thus so is the exec_cmd.
1283 */
1284 info->need_wait = 1;
1285 init_completion(&info->dev_ready);
1286 do {
1287 info->state = STATE_PREPARED;
1288
1289 exec_cmd = prepare_set_command(info, command, ext_cmd_type,
1290 column, page_addr);
1291 if (!exec_cmd) {
1292 info->need_wait = 0;
1293 complete(&info->dev_ready);
1294 break;
1295 }
1296
1297 init_completion(&info->cmd_complete);
1298 pxa3xx_nand_start(info);
1299
1300 if (!wait_for_completion_timeout(&info->cmd_complete,
1301 CHIP_DELAY_TIMEOUT)) {
1302 dev_err(&info->pdev->dev, "Wait time out!!!\n");
1303 /* Stop State Machine for next command cycle */
1304 pxa3xx_nand_stop(info);
1305 break;
1306 }
1307
1308 /* Only a few commands need several steps */
1309 if (command != NAND_CMD_PAGEPROG &&
1310 command != NAND_CMD_READ0 &&
1311 command != NAND_CMD_READOOB)
1312 break;
1313
1314 info->cur_chunk++;
1315
1316 /* Check if the sequence is complete */
1317 if (info->cur_chunk == info->ntotalchunks && command != NAND_CMD_PAGEPROG)
1318 break;
1319
1320 /*
1321 * After a splitted program command sequence has issued
1322 * the command dispatch, the command sequence is complete.
1323 */
1324 if (info->cur_chunk == (info->ntotalchunks + 1) &&
1325 command == NAND_CMD_PAGEPROG &&
1326 ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
1327 break;
1328
1329 if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
1330 /* Last read: issue a 'last naked read' */
1331 if (info->cur_chunk == info->ntotalchunks - 1)
1332 ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
1333 else
1334 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
1335
1336 /*
1337 * If a splitted program command has no more data to transfer,
1338 * the command dispatch must be issued to complete.
1339 */
1340 } else if (command == NAND_CMD_PAGEPROG &&
1341 info->cur_chunk == info->ntotalchunks) {
1342 ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
1343 }
1344 } while (1);
1345
1346 info->state = STATE_IDLE;
1347 }
1348
1349 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
1350 struct nand_chip *chip, const uint8_t *buf, int oob_required,
1351 int page)
1352 {
1353 chip->write_buf(mtd, buf, mtd->writesize);
1354 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1355
1356 return 0;
1357 }
1358
1359 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
1360 struct nand_chip *chip, uint8_t *buf, int oob_required,
1361 int page)
1362 {
1363 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1364 struct pxa3xx_nand_info *info = host->info_data;
1365
1366 chip->read_buf(mtd, buf, mtd->writesize);
1367 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1368
1369 if (info->retcode == ERR_CORERR && info->use_ecc) {
1370 mtd->ecc_stats.corrected += info->ecc_err_cnt;
1371
1372 } else if (info->retcode == ERR_UNCORERR) {
1373 /*
1374 * for blank page (all 0xff), HW will calculate its ECC as
1375 * 0, which is different from the ECC information within
1376 * OOB, ignore such uncorrectable errors
1377 */
1378 if (is_buf_blank(buf, mtd->writesize))
1379 info->retcode = ERR_NONE;
1380 else
1381 mtd->ecc_stats.failed++;
1382 }
1383
1384 return info->max_bitflips;
1385 }
1386
1387 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
1388 {
1389 struct nand_chip *chip = mtd_to_nand(mtd);
1390 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1391 struct pxa3xx_nand_info *info = host->info_data;
1392 char retval = 0xFF;
1393
1394 if (info->buf_start < info->buf_count)
1395 /* Has just send a new command? */
1396 retval = info->data_buff[info->buf_start++];
1397
1398 return retval;
1399 }
1400
1401 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
1402 {
1403 struct nand_chip *chip = mtd_to_nand(mtd);
1404 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1405 struct pxa3xx_nand_info *info = host->info_data;
1406 u16 retval = 0xFFFF;
1407
1408 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
1409 retval = *((u16 *)(info->data_buff+info->buf_start));
1410 info->buf_start += 2;
1411 }
1412 return retval;
1413 }
1414
1415 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1416 {
1417 struct nand_chip *chip = mtd_to_nand(mtd);
1418 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1419 struct pxa3xx_nand_info *info = host->info_data;
1420 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
1421
1422 memcpy(buf, info->data_buff + info->buf_start, real_len);
1423 info->buf_start += real_len;
1424 }
1425
1426 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
1427 const uint8_t *buf, int len)
1428 {
1429 struct nand_chip *chip = mtd_to_nand(mtd);
1430 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1431 struct pxa3xx_nand_info *info = host->info_data;
1432 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
1433
1434 memcpy(info->data_buff + info->buf_start, buf, real_len);
1435 info->buf_start += real_len;
1436 }
1437
1438 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
1439 {
1440 return;
1441 }
1442
1443 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1444 {
1445 struct nand_chip *chip = mtd_to_nand(mtd);
1446 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1447 struct pxa3xx_nand_info *info = host->info_data;
1448
1449 if (info->need_wait) {
1450 info->need_wait = 0;
1451 if (!wait_for_completion_timeout(&info->dev_ready,
1452 CHIP_DELAY_TIMEOUT)) {
1453 dev_err(&info->pdev->dev, "Ready time out!!!\n");
1454 return NAND_STATUS_FAIL;
1455 }
1456 }
1457
1458 /* pxa3xx_nand_send_command has waited for command complete */
1459 if (this->state == FL_WRITING || this->state == FL_ERASING) {
1460 if (info->retcode == ERR_NONE)
1461 return 0;
1462 else
1463 return NAND_STATUS_FAIL;
1464 }
1465
1466 return NAND_STATUS_READY;
1467 }
1468
1469 static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
1470 {
1471 struct pxa3xx_nand_host *host = info->host[info->cs];
1472 struct platform_device *pdev = info->pdev;
1473 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
1474 const struct nand_sdr_timings *timings;
1475
1476 /* Configure default flash values */
1477 info->chunk_size = PAGE_CHUNK_SIZE;
1478 info->reg_ndcr = 0x0; /* enable all interrupts */
1479 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
1480 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
1481 info->reg_ndcr |= NDCR_SPARE_EN;
1482
1483 /* use the common timing to make a try */
1484 timings = onfi_async_timing_mode_to_sdr_timings(0);
1485 if (IS_ERR(timings))
1486 return PTR_ERR(timings);
1487
1488 pxa3xx_nand_set_sdr_timing(host, timings);
1489 return 0;
1490 }
1491
1492 static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
1493 {
1494 struct pxa3xx_nand_host *host = info->host[info->cs];
1495 struct nand_chip *chip = &host->chip;
1496 struct mtd_info *mtd = nand_to_mtd(chip);
1497
1498 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
1499 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
1500 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
1501 }
1502
1503 static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
1504 {
1505 struct platform_device *pdev = info->pdev;
1506 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
1507 uint32_t ndcr = nand_readl(info, NDCR);
1508
1509 /* Set an initial chunk size */
1510 info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
1511 info->reg_ndcr = ndcr &
1512 ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
1513 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
1514 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
1515 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
1516 }
1517
1518 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1519 {
1520 struct platform_device *pdev = info->pdev;
1521 struct dma_slave_config config;
1522 dma_cap_mask_t mask;
1523 struct pxad_param param;
1524 int ret;
1525
1526 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
1527 if (info->data_buff == NULL)
1528 return -ENOMEM;
1529 if (use_dma == 0)
1530 return 0;
1531
1532 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1533 if (ret)
1534 return ret;
1535
1536 sg_init_one(&info->sg, info->data_buff, info->buf_size);
1537 dma_cap_zero(mask);
1538 dma_cap_set(DMA_SLAVE, mask);
1539 param.prio = PXAD_PRIO_LOWEST;
1540 param.drcmr = info->drcmr_dat;
1541 info->dma_chan = dma_request_slave_channel_compat(mask, pxad_filter_fn,
1542 &param, &pdev->dev,
1543 "data");
1544 if (!info->dma_chan) {
1545 dev_err(&pdev->dev, "unable to request data dma channel\n");
1546 return -ENODEV;
1547 }
1548
1549 memset(&config, 0, sizeof(config));
1550 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1551 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1552 config.src_addr = info->mmio_phys + NDDB;
1553 config.dst_addr = info->mmio_phys + NDDB;
1554 config.src_maxburst = 32;
1555 config.dst_maxburst = 32;
1556 ret = dmaengine_slave_config(info->dma_chan, &config);
1557 if (ret < 0) {
1558 dev_err(&info->pdev->dev,
1559 "dma channel configuration failed: %d\n",
1560 ret);
1561 return ret;
1562 }
1563
1564 /*
1565 * Now that DMA buffers are allocated we turn on
1566 * DMA proper for I/O operations.
1567 */
1568 info->use_dma = 1;
1569 return 0;
1570 }
1571
1572 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
1573 {
1574 if (info->use_dma) {
1575 dmaengine_terminate_all(info->dma_chan);
1576 dma_release_channel(info->dma_chan);
1577 }
1578 kfree(info->data_buff);
1579 }
1580
1581 static int pxa_ecc_init(struct pxa3xx_nand_info *info,
1582 struct mtd_info *mtd,
1583 int strength, int ecc_stepsize, int page_size)
1584 {
1585 struct nand_chip *chip = mtd_to_nand(mtd);
1586 struct nand_ecc_ctrl *ecc = &chip->ecc;
1587
1588 if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
1589 info->nfullchunks = 1;
1590 info->ntotalchunks = 1;
1591 info->chunk_size = 2048;
1592 info->spare_size = 40;
1593 info->ecc_size = 24;
1594 ecc->mode = NAND_ECC_HW;
1595 ecc->size = 512;
1596 ecc->strength = 1;
1597
1598 } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
1599 info->nfullchunks = 1;
1600 info->ntotalchunks = 1;
1601 info->chunk_size = 512;
1602 info->spare_size = 8;
1603 info->ecc_size = 8;
1604 ecc->mode = NAND_ECC_HW;
1605 ecc->size = 512;
1606 ecc->strength = 1;
1607
1608 /*
1609 * Required ECC: 4-bit correction per 512 bytes
1610 * Select: 16-bit correction per 2048 bytes
1611 */
1612 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
1613 info->ecc_bch = 1;
1614 info->nfullchunks = 1;
1615 info->ntotalchunks = 1;
1616 info->chunk_size = 2048;
1617 info->spare_size = 32;
1618 info->ecc_size = 32;
1619 ecc->mode = NAND_ECC_HW;
1620 ecc->size = info->chunk_size;
1621 mtd_set_ooblayout(mtd, &pxa3xx_ooblayout_ops);
1622 ecc->strength = 16;
1623
1624 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
1625 info->ecc_bch = 1;
1626 info->nfullchunks = 2;
1627 info->ntotalchunks = 2;
1628 info->chunk_size = 2048;
1629 info->spare_size = 32;
1630 info->ecc_size = 32;
1631 ecc->mode = NAND_ECC_HW;
1632 ecc->size = info->chunk_size;
1633 mtd_set_ooblayout(mtd, &pxa3xx_ooblayout_ops);
1634 ecc->strength = 16;
1635
1636 /*
1637 * Required ECC: 8-bit correction per 512 bytes
1638 * Select: 16-bit correction per 1024 bytes
1639 */
1640 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
1641 info->ecc_bch = 1;
1642 info->nfullchunks = 4;
1643 info->ntotalchunks = 5;
1644 info->chunk_size = 1024;
1645 info->spare_size = 0;
1646 info->last_chunk_size = 0;
1647 info->last_spare_size = 64;
1648 info->ecc_size = 32;
1649 ecc->mode = NAND_ECC_HW;
1650 ecc->size = info->chunk_size;
1651 mtd_set_ooblayout(mtd, &pxa3xx_ooblayout_ops);
1652 ecc->strength = 16;
1653 } else {
1654 dev_err(&info->pdev->dev,
1655 "ECC strength %d at page size %d is not supported\n",
1656 strength, page_size);
1657 return -ENODEV;
1658 }
1659
1660 dev_info(&info->pdev->dev, "ECC strength %d, ECC step size %d\n",
1661 ecc->strength, ecc->size);
1662 return 0;
1663 }
1664
1665 static int pxa3xx_nand_scan(struct mtd_info *mtd)
1666 {
1667 struct nand_chip *chip = mtd_to_nand(mtd);
1668 struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
1669 struct pxa3xx_nand_info *info = host->info_data;
1670 struct platform_device *pdev = info->pdev;
1671 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
1672 int ret;
1673 uint16_t ecc_strength, ecc_step;
1674
1675 if (pdata->keep_config) {
1676 pxa3xx_nand_detect_config(info);
1677 } else {
1678 ret = pxa3xx_nand_config_ident(info);
1679 if (ret)
1680 return ret;
1681 }
1682
1683 if (info->reg_ndcr & NDCR_DWIDTH_M)
1684 chip->options |= NAND_BUSWIDTH_16;
1685
1686 /* Device detection must be done with ECC disabled */
1687 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
1688 info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K)
1689 nand_writel(info, NDECCCTRL, 0x0);
1690
1691 if (pdata->flash_bbt)
1692 chip->bbt_options |= NAND_BBT_USE_FLASH;
1693
1694 chip->ecc.strength = pdata->ecc_strength;
1695 chip->ecc.size = pdata->ecc_step_size;
1696
1697 ret = nand_scan_ident(mtd, 1, NULL);
1698 if (ret)
1699 return ret;
1700
1701 if (!pdata->keep_config) {
1702 ret = pxa3xx_nand_init(host);
1703 if (ret) {
1704 dev_err(&info->pdev->dev, "Failed to init nand: %d\n",
1705 ret);
1706 return ret;
1707 }
1708 }
1709
1710 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
1711 /*
1712 * We'll use a bad block table stored in-flash and don't
1713 * allow writing the bad block marker to the flash.
1714 */
1715 chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
1716 chip->bbt_td = &bbt_main_descr;
1717 chip->bbt_md = &bbt_mirror_descr;
1718 }
1719
1720 /*
1721 * If the page size is bigger than the FIFO size, let's check
1722 * we are given the right variant and then switch to the extended
1723 * (aka splitted) command handling,
1724 */
1725 if (mtd->writesize > PAGE_CHUNK_SIZE) {
1726 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
1727 info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) {
1728 chip->cmdfunc = nand_cmdfunc_extended;
1729 } else {
1730 dev_err(&info->pdev->dev,
1731 "unsupported page size on this variant\n");
1732 return -ENODEV;
1733 }
1734 }
1735
1736 ecc_strength = chip->ecc.strength;
1737 ecc_step = chip->ecc.size;
1738 if (!ecc_strength || !ecc_step) {
1739 ecc_strength = chip->ecc_strength_ds;
1740 ecc_step = chip->ecc_step_ds;
1741 }
1742
1743 /* Set default ECC strength requirements on non-ONFI devices */
1744 if (ecc_strength < 1 && ecc_step < 1) {
1745 ecc_strength = 1;
1746 ecc_step = 512;
1747 }
1748
1749 ret = pxa_ecc_init(info, mtd, ecc_strength,
1750 ecc_step, mtd->writesize);
1751 if (ret)
1752 return ret;
1753
1754 /* calculate addressing information */
1755 if (mtd->writesize >= 2048)
1756 host->col_addr_cycles = 2;
1757 else
1758 host->col_addr_cycles = 1;
1759
1760 /* release the initial buffer */
1761 kfree(info->data_buff);
1762
1763 /* allocate the real data + oob buffer */
1764 info->buf_size = mtd->writesize + mtd->oobsize;
1765 ret = pxa3xx_nand_init_buff(info);
1766 if (ret)
1767 return ret;
1768 info->oob_buff = info->data_buff + mtd->writesize;
1769
1770 if ((mtd->size >> chip->page_shift) > 65536)
1771 host->row_addr_cycles = 3;
1772 else
1773 host->row_addr_cycles = 2;
1774
1775 if (!pdata->keep_config)
1776 pxa3xx_nand_config_tail(info);
1777
1778 return nand_scan_tail(mtd);
1779 }
1780
1781 static int alloc_nand_resource(struct platform_device *pdev)
1782 {
1783 struct device_node *np = pdev->dev.of_node;
1784 struct pxa3xx_nand_platform_data *pdata;
1785 struct pxa3xx_nand_info *info;
1786 struct pxa3xx_nand_host *host;
1787 struct nand_chip *chip = NULL;
1788 struct mtd_info *mtd;
1789 struct resource *r;
1790 int ret, irq, cs;
1791
1792 pdata = dev_get_platdata(&pdev->dev);
1793 if (pdata->num_cs <= 0) {
1794 dev_err(&pdev->dev, "invalid number of chip selects\n");
1795 return -ENODEV;
1796 }
1797
1798 info = devm_kzalloc(&pdev->dev,
1799 sizeof(*info) + sizeof(*host) * pdata->num_cs,
1800 GFP_KERNEL);
1801 if (!info)
1802 return -ENOMEM;
1803
1804 info->pdev = pdev;
1805 info->variant = pxa3xx_nand_get_variant(pdev);
1806 for (cs = 0; cs < pdata->num_cs; cs++) {
1807 host = (void *)&info[1] + sizeof(*host) * cs;
1808 chip = &host->chip;
1809 nand_set_controller_data(chip, host);
1810 mtd = nand_to_mtd(chip);
1811 info->host[cs] = host;
1812 host->cs = cs;
1813 host->info_data = info;
1814 mtd->dev.parent = &pdev->dev;
1815 /* FIXME: all chips use the same device tree partitions */
1816 nand_set_flash_node(chip, np);
1817
1818 nand_set_controller_data(chip, host);
1819 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1820 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1821 chip->controller = &info->controller;
1822 chip->waitfunc = pxa3xx_nand_waitfunc;
1823 chip->select_chip = pxa3xx_nand_select_chip;
1824 chip->read_word = pxa3xx_nand_read_word;
1825 chip->read_byte = pxa3xx_nand_read_byte;
1826 chip->read_buf = pxa3xx_nand_read_buf;
1827 chip->write_buf = pxa3xx_nand_write_buf;
1828 chip->options |= NAND_NO_SUBPAGE_WRITE;
1829 chip->cmdfunc = nand_cmdfunc;
1830 chip->onfi_set_features = nand_onfi_get_set_features_notsupp;
1831 chip->onfi_get_features = nand_onfi_get_set_features_notsupp;
1832 }
1833
1834 nand_hw_control_init(chip->controller);
1835 info->clk = devm_clk_get(&pdev->dev, NULL);
1836 if (IS_ERR(info->clk)) {
1837 ret = PTR_ERR(info->clk);
1838 dev_err(&pdev->dev, "failed to get nand clock: %d\n", ret);
1839 return ret;
1840 }
1841 ret = clk_prepare_enable(info->clk);
1842 if (ret < 0)
1843 return ret;
1844
1845 if (!np && use_dma) {
1846 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1847 if (r == NULL) {
1848 dev_err(&pdev->dev,
1849 "no resource defined for data DMA\n");
1850 ret = -ENXIO;
1851 goto fail_disable_clk;
1852 }
1853 info->drcmr_dat = r->start;
1854 }
1855
1856 irq = platform_get_irq(pdev, 0);
1857 if (irq < 0) {
1858 dev_err(&pdev->dev, "no IRQ resource defined\n");
1859 ret = -ENXIO;
1860 goto fail_disable_clk;
1861 }
1862
1863 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1864 info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1865 if (IS_ERR(info->mmio_base)) {
1866 ret = PTR_ERR(info->mmio_base);
1867 dev_err(&pdev->dev, "failed to map register space: %d\n", ret);
1868 goto fail_disable_clk;
1869 }
1870 info->mmio_phys = r->start;
1871
1872 /* Allocate a buffer to allow flash detection */
1873 info->buf_size = INIT_BUFFER_SIZE;
1874 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
1875 if (info->data_buff == NULL) {
1876 ret = -ENOMEM;
1877 goto fail_disable_clk;
1878 }
1879
1880 /* initialize all interrupts to be disabled */
1881 disable_int(info, NDSR_MASK);
1882
1883 ret = request_threaded_irq(irq, pxa3xx_nand_irq,
1884 pxa3xx_nand_irq_thread, IRQF_ONESHOT,
1885 pdev->name, info);
1886 if (ret < 0) {
1887 dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
1888 goto fail_free_buf;
1889 }
1890
1891 platform_set_drvdata(pdev, info);
1892
1893 return 0;
1894
1895 fail_free_buf:
1896 free_irq(irq, info);
1897 kfree(info->data_buff);
1898 fail_disable_clk:
1899 clk_disable_unprepare(info->clk);
1900 return ret;
1901 }
1902
1903 static int pxa3xx_nand_remove(struct platform_device *pdev)
1904 {
1905 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1906 struct pxa3xx_nand_platform_data *pdata;
1907 int irq, cs;
1908
1909 if (!info)
1910 return 0;
1911
1912 pdata = dev_get_platdata(&pdev->dev);
1913
1914 irq = platform_get_irq(pdev, 0);
1915 if (irq >= 0)
1916 free_irq(irq, info);
1917 pxa3xx_nand_free_buff(info);
1918
1919 /*
1920 * In the pxa3xx case, the DFI bus is shared between the SMC and NFC.
1921 * In order to prevent a lockup of the system bus, the DFI bus
1922 * arbitration is granted to SMC upon driver removal. This is done by
1923 * setting the x_ARB_CNTL bit, which also prevents the NAND to have
1924 * access to the bus anymore.
1925 */
1926 nand_writel(info, NDCR,
1927 (nand_readl(info, NDCR) & ~NDCR_ND_ARB_EN) |
1928 NFCV1_NDCR_ARB_CNTL);
1929 clk_disable_unprepare(info->clk);
1930
1931 for (cs = 0; cs < pdata->num_cs; cs++)
1932 nand_release(nand_to_mtd(&info->host[cs]->chip));
1933 return 0;
1934 }
1935
1936 static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1937 {
1938 struct pxa3xx_nand_platform_data *pdata;
1939 struct device_node *np = pdev->dev.of_node;
1940 const struct of_device_id *of_id =
1941 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1942
1943 if (!of_id)
1944 return 0;
1945
1946 /*
1947 * Some SoCs like A7k/A8k need to enable manually the NAND
1948 * controller to avoid being bootloader dependent. This is done
1949 * through the use of a single bit in the System Functions registers.
1950 */
1951 if (pxa3xx_nand_get_variant(pdev) == PXA3XX_NAND_VARIANT_ARMADA_8K) {
1952 struct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle(
1953 pdev->dev.of_node, "marvell,system-controller");
1954 u32 reg;
1955
1956 if (IS_ERR(sysctrl_base))
1957 return PTR_ERR(sysctrl_base);
1958
1959 regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, &reg);
1960 reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN;
1961 regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
1962 }
1963
1964 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1965 if (!pdata)
1966 return -ENOMEM;
1967
1968 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1969 pdata->enable_arbiter = 1;
1970 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1971 pdata->keep_config = 1;
1972 of_property_read_u32(np, "num-cs", &pdata->num_cs);
1973
1974 pdev->dev.platform_data = pdata;
1975
1976 return 0;
1977 }
1978
1979 static int pxa3xx_nand_probe(struct platform_device *pdev)
1980 {
1981 struct pxa3xx_nand_platform_data *pdata;
1982 struct pxa3xx_nand_info *info;
1983 int ret, cs, probe_success, dma_available;
1984
1985 dma_available = IS_ENABLED(CONFIG_ARM) &&
1986 (IS_ENABLED(CONFIG_ARCH_PXA) || IS_ENABLED(CONFIG_ARCH_MMP));
1987 if (use_dma && !dma_available) {
1988 use_dma = 0;
1989 dev_warn(&pdev->dev,
1990 "This platform can't do DMA on this device\n");
1991 }
1992
1993 ret = pxa3xx_nand_probe_dt(pdev);
1994 if (ret)
1995 return ret;
1996
1997 pdata = dev_get_platdata(&pdev->dev);
1998 if (!pdata) {
1999 dev_err(&pdev->dev, "no platform data defined\n");
2000 return -ENODEV;
2001 }
2002
2003 ret = alloc_nand_resource(pdev);
2004 if (ret)
2005 return ret;
2006
2007 info = platform_get_drvdata(pdev);
2008 probe_success = 0;
2009 for (cs = 0; cs < pdata->num_cs; cs++) {
2010 struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
2011
2012 /*
2013 * The mtd name matches the one used in 'mtdparts' kernel
2014 * parameter. This name cannot be changed or otherwise
2015 * user's mtd partitions configuration would get broken.
2016 */
2017 mtd->name = "pxa3xx_nand-0";
2018 info->cs = cs;
2019 ret = pxa3xx_nand_scan(mtd);
2020 if (ret) {
2021 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
2022 cs);
2023 continue;
2024 }
2025
2026 ret = mtd_device_register(mtd, pdata->parts[cs],
2027 pdata->nr_parts[cs]);
2028 if (!ret)
2029 probe_success = 1;
2030 }
2031
2032 if (!probe_success) {
2033 pxa3xx_nand_remove(pdev);
2034 return -ENODEV;
2035 }
2036
2037 return 0;
2038 }
2039
2040 #ifdef CONFIG_PM
2041 static int pxa3xx_nand_suspend(struct device *dev)
2042 {
2043 struct pxa3xx_nand_info *info = dev_get_drvdata(dev);
2044
2045 if (info->state) {
2046 dev_err(dev, "driver busy, state = %d\n", info->state);
2047 return -EAGAIN;
2048 }
2049
2050 clk_disable(info->clk);
2051 return 0;
2052 }
2053
2054 static int pxa3xx_nand_resume(struct device *dev)
2055 {
2056 struct pxa3xx_nand_info *info = dev_get_drvdata(dev);
2057 int ret;
2058
2059 ret = clk_enable(info->clk);
2060 if (ret < 0)
2061 return ret;
2062
2063 /* We don't want to handle interrupt without calling mtd routine */
2064 disable_int(info, NDCR_INT_MASK);
2065
2066 /*
2067 * Directly set the chip select to a invalid value,
2068 * then the driver would reset the timing according
2069 * to current chip select at the beginning of cmdfunc
2070 */
2071 info->cs = 0xff;
2072
2073 /*
2074 * As the spec says, the NDSR would be updated to 0x1800 when
2075 * doing the nand_clk disable/enable.
2076 * To prevent it damaging state machine of the driver, clear
2077 * all status before resume
2078 */
2079 nand_writel(info, NDSR, NDSR_MASK);
2080
2081 return 0;
2082 }
2083 #else
2084 #define pxa3xx_nand_suspend NULL
2085 #define pxa3xx_nand_resume NULL
2086 #endif
2087
2088 static const struct dev_pm_ops pxa3xx_nand_pm_ops = {
2089 .suspend = pxa3xx_nand_suspend,
2090 .resume = pxa3xx_nand_resume,
2091 };
2092
2093 static struct platform_driver pxa3xx_nand_driver = {
2094 .driver = {
2095 .name = "pxa3xx-nand",
2096 .of_match_table = pxa3xx_nand_dt_ids,
2097 .pm = &pxa3xx_nand_pm_ops,
2098 },
2099 .probe = pxa3xx_nand_probe,
2100 .remove = pxa3xx_nand_remove,
2101 };
2102
2103 module_platform_driver(pxa3xx_nand_driver);
2104
2105 MODULE_LICENSE("GPL");
2106 MODULE_DESCRIPTION("PXA3xx NAND controller driver");
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