drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c

   1 /*
   2  * BCM47XX NAND flash driver
   3  *
   4  * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include "bcm47xxnflash.h"
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/slab.h>
  17 #include <linux/delay.h>
  18 #include <linux/bcma/bcma.h>
  19
  20 /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
  21  * shown ~1000 retries as maxiumum. */
  22 #define NFLASH_READY_RETRIES            10000
  23
  24 #define NFLASH_SECTOR_SIZE              512
  25
  26 #define NCTL_CMD0                       0x00010000
  27 #define NCTL_COL                        0x00020000      /* Update column with value from BCMA_CC_NFLASH_COL_ADDR */
  28 #define NCTL_ROW                        0x00040000      /* Update row (page) with value from BCMA_CC_NFLASH_ROW_ADDR */
  29 #define NCTL_CMD1W                      0x00080000
  30 #define NCTL_READ                       0x00100000
  31 #define NCTL_WRITE                      0x00200000
  32 #define NCTL_SPECADDR                   0x01000000
  33 #define NCTL_READY                      0x04000000
  34 #define NCTL_ERR                        0x08000000
  35 #define NCTL_CSA                        0x40000000
  36 #define NCTL_START                      0x80000000
  37
  38 /**************************************************
  39  * Various helpers
  40  **************************************************/
  41
  42 static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
  43 {
  44         return ((ns * 1000 * clock) / 1000000) + 1;
  45 }
  46
  47 static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
  48 {
  49         int i = 0;
  50
  51         bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code);
  52         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  53                 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) {
  54                         i = 0;
  55                         break;
  56                 }
  57         }
  58         if (i) {
  59                 pr_err("NFLASH control command not ready!\n");
  60                 return -EBUSY;
  61         }
  62         return 0;
  63 }
  64
  65 static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
  66 {
  67         int i;
  68
  69         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  70                 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) {
  71                         if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
  72                             BCMA_CC_NFLASH_CTL_ERR) {
  73                                 pr_err("Error on polling\n");
  74                                 return -EBUSY;
  75                         } else {
  76                                 return 0;
  77                         }
  78                 }
  79         }
  80
  81         pr_err("Polling timeout!\n");
  82         return -EBUSY;
  83 }
  84
  85 /**************************************************
  86  * R/W
  87  **************************************************/
  88
  89 static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
  90                                            int len)
  91 {
  92         struct nand_chip *nand_chip = mtd_to_nand(mtd);
  93         struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
  94
  95         u32 ctlcode;
  96         u32 *dest = (u32 *)buf;
  97         int i;
  98         int toread;
  99
 100         BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
 101         /* Don't validate column using nand_chip->page_shift, it may be bigger
 102          * when accessing OOB */
 103
 104         while (len) {
 105                 /* We can read maximum of 0x200 bytes at once */
 106                 toread = min(len, 0x200);
 107
 108                 /* Set page and column */
 109                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
 110                                 b47n->curr_column);
 111                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
 112                                 b47n->curr_page_addr);
 113
 114                 /* Prepare to read */
 115                 ctlcode = NCTL_CSA | NCTL_CMD1W | NCTL_ROW | NCTL_COL |
 116                           NCTL_CMD0;
 117                 ctlcode |= NAND_CMD_READSTART << 8;
 118                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
 119                         return;
 120                 if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
 121                         return;
 122
 123                 /* Eventually read some data :) */
 124                 for (i = 0; i < toread; i += 4, dest++) {
 125                         ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ;
 126                         if (i == toread - 4) /* Last read goes without that */
 127                                 ctlcode &= ~NCTL_CSA;
 128                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 129                                                               ctlcode))
 130                                 return;
 131                         *dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
 132                 }
 133
 134                 b47n->curr_column += toread;
 135                 len -= toread;
 136         }
 137 }
 138
 139 static void bcm47xxnflash_ops_bcm4706_write(struct mtd_info *mtd,
 140                                             const uint8_t *buf, int len)
 141 {
 142         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 143         struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 144         struct bcma_drv_cc *cc = b47n->cc;
 145
 146         u32 ctlcode;
 147         const u32 *data = (u32 *)buf;
 148         int i;
 149
 150         BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
 151         /* Don't validate column using nand_chip->page_shift, it may be bigger
 152          * when accessing OOB */
 153
 154         for (i = 0; i < len; i += 4, data++) {
 155                 bcma_cc_write32(cc, BCMA_CC_NFLASH_DATA, *data);
 156
 157                 ctlcode = NCTL_CSA | 0x30000000 | NCTL_WRITE;
 158                 if (i == len - 4) /* Last read goes without that */
 159                         ctlcode &= ~NCTL_CSA;
 160                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) {
 161                         pr_err("%s ctl_cmd didn't work!\n", __func__);
 162                         return;
 163                 }
 164         }
 165
 166         b47n->curr_column += len;
 167 }
 168
 169 /**************************************************
 170  * NAND chip ops
 171  **************************************************/
 172
 173 static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct nand_chip *nand_chip,
 174                                                int cmd, unsigned int ctrl)
 175 {
 176         struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 177         u32 code = 0;
 178
 179         if (cmd == NAND_CMD_NONE)
 180                 return;
 181
 182         if (cmd & NAND_CTRL_CLE)
 183                 code = cmd | NCTL_CMD0;
 184
 185         /* nCS is not needed for reset command */
 186         if (cmd != NAND_CMD_RESET)
 187                 code |= NCTL_CSA;
 188
 189         bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, code);
 190 }
 191
 192 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
 193 static void bcm47xxnflash_ops_bcm4706_select_chip(struct nand_chip *chip,
 194                                                   int cs)
 195 {
 196         return;
 197 }
 198
 199 static int bcm47xxnflash_ops_bcm4706_dev_ready(struct nand_chip *nand_chip)
 200 {
 201         struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 202
 203         return !!(bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_CTL) & NCTL_READY);
 204 }
 205
 206 /*
 207  * Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
 208  * For example, reading chip id is performed in a non-standard way.
 209  * Setting column and page is also handled differently, we use a special
 210  * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
 211  * standard commands would be much more complicated.
 212  */
 213 static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct nand_chip *nand_chip,
 214                                               unsigned command, int column,
 215                                               int page_addr)
 216 {
 217         struct mtd_info *mtd = nand_to_mtd(nand_chip);
 218         struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 219         struct bcma_drv_cc *cc = b47n->cc;
 220         u32 ctlcode;
 221         int i;
 222
 223         if (column != -1)
 224                 b47n->curr_column = column;
 225         if (page_addr != -1)
 226                 b47n->curr_page_addr = page_addr;
 227
 228         switch (command) {
 229         case NAND_CMD_RESET:
 230                 nand_chip->legacy.cmd_ctrl(nand_chip, command, NAND_CTRL_CLE);
 231
 232                 ndelay(100);
 233                 nand_wait_ready(nand_chip);
 234                 break;
 235         case NAND_CMD_READID:
 236                 ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
 237                 ctlcode |= NAND_CMD_READID;
 238                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
 239                         pr_err("READID error\n");
 240                         break;
 241                 }
 242
 243                 /*
 244                  * Reading is specific, last one has to go without NCTL_CSA
 245                  * bit. We don't know how many reads NAND subsystem is going
 246                  * to perform, so cache everything.
 247                  */
 248                 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
 249                         ctlcode = NCTL_CSA | NCTL_READ;
 250                         if (i == ARRAY_SIZE(b47n->id_data) - 1)
 251                                 ctlcode &= ~NCTL_CSA;
 252                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 253                                                               ctlcode)) {
 254                                 pr_err("READID error\n");
 255                                 break;
 256                         }
 257                         b47n->id_data[i] =
 258                                 bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA)
 259                                 & 0xFF;
 260                 }
 261
 262                 break;
 263         case NAND_CMD_STATUS:
 264                 ctlcode = NCTL_CSA | NCTL_CMD0 | NAND_CMD_STATUS;
 265                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 266                         pr_err("STATUS command error\n");
 267                 break;
 268         case NAND_CMD_READ0:
 269                 break;
 270         case NAND_CMD_READOOB:
 271                 if (page_addr != -1)
 272                         b47n->curr_column += mtd->writesize;
 273                 break;
 274         case NAND_CMD_ERASE1:
 275                 bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
 276                                 b47n->curr_page_addr);
 277                 ctlcode = NCTL_ROW | NCTL_CMD1W | NCTL_CMD0 |
 278                           NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8);
 279                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 280                         pr_err("ERASE1 failed\n");
 281                 break;
 282         case NAND_CMD_ERASE2:
 283                 break;
 284         case NAND_CMD_SEQIN:
 285                 /* Set page and column */
 286                 bcma_cc_write32(cc, BCMA_CC_NFLASH_COL_ADDR,
 287                                 b47n->curr_column);
 288                 bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
 289                                 b47n->curr_page_addr);
 290
 291                 /* Prepare to write */
 292                 ctlcode = 0x40000000 | NCTL_ROW | NCTL_COL | NCTL_CMD0;
 293                 ctlcode |= NAND_CMD_SEQIN;
 294                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 295                         pr_err("SEQIN failed\n");
 296                 break;
 297         case NAND_CMD_PAGEPROG:
 298                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_CMD0 |
 299                                                           NAND_CMD_PAGEPROG))
 300                         pr_err("PAGEPROG failed\n");
 301                 if (bcm47xxnflash_ops_bcm4706_poll(cc))
 302                         pr_err("PAGEPROG not ready\n");
 303                 break;
 304         default:
 305                 pr_err("Command 0x%X unsupported\n", command);
 306                 break;
 307         }
 308         b47n->curr_command = command;
 309 }
 310
 311 static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct nand_chip *nand_chip)
 312 {
 313         struct mtd_info *mtd = nand_to_mtd(nand_chip);
 314         struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 315         struct bcma_drv_cc *cc = b47n->cc;
 316         u32 tmp = 0;
 317
 318         switch (b47n->curr_command) {
 319         case NAND_CMD_READID:
 320                 if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
 321                         pr_err("Requested invalid id_data: %d\n",
 322                                b47n->curr_column);
 323                         return 0;
 324                 }
 325                 return b47n->id_data[b47n->curr_column++];
 326         case NAND_CMD_STATUS:
 327                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_READ))
 328                         return 0;
 329                 return bcma_cc_read32(cc, BCMA_CC_NFLASH_DATA) & 0xff;
 330         case NAND_CMD_READOOB:
 331                 bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
 332                 return tmp & 0xFF;
 333         }
 334
 335         pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
 336         return 0;
 337 }
 338
 339 static void bcm47xxnflash_ops_bcm4706_read_buf(struct nand_chip *nand_chip,
 340                                                uint8_t *buf, int len)
 341 {
 342         struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 343
 344         switch (b47n->curr_command) {
 345         case NAND_CMD_READ0:
 346         case NAND_CMD_READOOB:
 347                 bcm47xxnflash_ops_bcm4706_read(nand_to_mtd(nand_chip), buf,
 348                                                len);
 349                 return;
 350         }
 351
 352         pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
 353 }
 354
 355 static void bcm47xxnflash_ops_bcm4706_write_buf(struct nand_chip *nand_chip,
 356                                                 const uint8_t *buf, int len)
 357 {
 358         struct bcm47xxnflash *b47n = nand_get_controller_data(nand_chip);
 359
 360         switch (b47n->curr_command) {
 361         case NAND_CMD_SEQIN:
 362                 bcm47xxnflash_ops_bcm4706_write(nand_to_mtd(nand_chip), buf,
 363                                                 len);
 364                 return;
 365         }
 366
 367         pr_err("Invalid command for buf write: 0x%X\n", b47n->curr_command);
 368 }
 369
 370 /**************************************************
 371  * Init
 372  **************************************************/
 373
 374 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 375 {
 376         struct nand_chip *nand_chip = (struct nand_chip *)&b47n->nand_chip;
 377         int err;
 378         u32 freq;
 379         u16 clock;
 380         u8 w0, w1, w2, w3, w4;
 381
 382         unsigned long chipsize; /* MiB */
 383         u8 tbits, col_bits, col_size, row_bits, row_bsize;
 384         u32 val;
 385
 386         nand_chip->legacy.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
 387         nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
 388         nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
 389         b47n->nand_chip.legacy.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
 390         b47n->nand_chip.legacy.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
 391         b47n->nand_chip.legacy.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
 392         b47n->nand_chip.legacy.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
 393         b47n->nand_chip.legacy.set_features = nand_get_set_features_notsupp;
 394         b47n->nand_chip.legacy.get_features = nand_get_set_features_notsupp;
 395
 396         nand_chip->legacy.chip_delay = 50;
 397         b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
 398         b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
 399
 400         /* Enable NAND flash access */
 401         bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 402                       BCMA_CC_4706_FLASHSCFG_NF1);
 403
 404         /* Configure wait counters */
 405         if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
 406                 /* 400 MHz */
 407                 freq = 400000000 / 4;
 408         } else {
 409                 freq = bcma_chipco_pll_read(b47n->cc, 4);
 410                 freq = (freq & 0xFFF) >> 3;
 411                 /* Fixed reference clock 25 MHz and m = 2 */
 412                 freq = (freq * 25000000 / 2) / 4;
 413         }
 414         clock = freq / 1000000;
 415         w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
 416         w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
 417         w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 418         w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 419         w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
 420         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
 421                         (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
 422
 423         /* Scan NAND */
 424         err = nand_scan(&b47n->nand_chip, 1);
 425         if (err) {
 426                 pr_err("Could not scan NAND flash: %d\n", err);
 427                 goto exit;
 428         }
 429
 430         /* Configure FLASH */
 431         chipsize = b47n->nand_chip.chipsize >> 20;
 432         tbits = ffs(chipsize); /* find first bit set */
 433         if (!tbits || tbits != fls(chipsize)) {
 434                 pr_err("Invalid flash size: 0x%lX\n", chipsize);
 435                 err = -ENOTSUPP;
 436                 goto exit;
 437         }
 438         tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
 439
 440         col_bits = b47n->nand_chip.page_shift + 1;
 441         col_size = (col_bits + 7) / 8;
 442
 443         row_bits = tbits - col_bits + 1;
 444         row_bsize = (row_bits + 7) / 8;
 445
 446         val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
 447         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
 448
 449 exit:
 450         if (err)
 451                 bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 452                                ~BCMA_CC_4706_FLASHSCFG_NF1);
 453         return err;
 454 }