1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
5 * Copyright © 2006 Texas Instruments.
7 * Port to 2.6.23 Copyright © 2008 by:
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
9 * Troy Kisky <troy.kisky@boundarydevices.com>
10 * Dirk Behme <Dirk.Behme@gmail.com>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/err.h>
18 #include <linux/mtd/rawnand.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/slab.h>
21 #include <linux/of_device.h>
24 #include <linux/platform_data/mtd-davinci.h>
25 #include <linux/platform_data/mtd-davinci-aemif.h>
28 * This is a device driver for the NAND flash controller found on the
29 * various DaVinci family chips. It handles up to four SoC chipselects,
30 * and some flavors of secondary chipselect (e.g. based on A12) as used
31 * with multichip packages.
33 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
34 * available on chips like the DM355 and OMAP-L137 and needed with the
35 * more error-prone MLC NAND chips.
37 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
38 * outputs in a "wire-AND" configuration, with no per-chip signals.
40 struct davinci_nand_info
{
41 struct nand_chip chip
;
43 struct platform_device
*pdev
;
50 void __iomem
*current_cs
;
52 uint32_t mask_chipsel
;
56 uint32_t core_chipsel
;
58 struct davinci_aemif_timing
*timing
;
61 static DEFINE_SPINLOCK(davinci_nand_lock
);
62 static bool ecc4_busy
;
64 static inline struct davinci_nand_info
*to_davinci_nand(struct mtd_info
*mtd
)
66 return container_of(mtd_to_nand(mtd
), struct davinci_nand_info
, chip
);
69 static inline unsigned int davinci_nand_readl(struct davinci_nand_info
*info
,
72 return __raw_readl(info
->base
+ offset
);
75 static inline void davinci_nand_writel(struct davinci_nand_info
*info
,
76 int offset
, unsigned long value
)
78 __raw_writel(value
, info
->base
+ offset
);
81 /*----------------------------------------------------------------------*/
84 * Access to hardware control lines: ALE, CLE, secondary chipselect.
87 static void nand_davinci_hwcontrol(struct nand_chip
*nand
, int cmd
,
90 struct davinci_nand_info
*info
= to_davinci_nand(nand_to_mtd(nand
));
91 void __iomem
*addr
= info
->current_cs
;
93 /* Did the control lines change? */
94 if (ctrl
& NAND_CTRL_CHANGE
) {
95 if ((ctrl
& NAND_CTRL_CLE
) == NAND_CTRL_CLE
)
96 addr
+= info
->mask_cle
;
97 else if ((ctrl
& NAND_CTRL_ALE
) == NAND_CTRL_ALE
)
98 addr
+= info
->mask_ale
;
100 nand
->legacy
.IO_ADDR_W
= addr
;
103 if (cmd
!= NAND_CMD_NONE
)
104 iowrite8(cmd
, nand
->legacy
.IO_ADDR_W
);
107 static void nand_davinci_select_chip(struct nand_chip
*nand
, int chip
)
109 struct davinci_nand_info
*info
= to_davinci_nand(nand_to_mtd(nand
));
111 info
->current_cs
= info
->vaddr
;
113 /* maybe kick in a second chipselect */
115 info
->current_cs
+= info
->mask_chipsel
;
117 info
->chip
.legacy
.IO_ADDR_W
= info
->current_cs
;
118 info
->chip
.legacy
.IO_ADDR_R
= info
->chip
.legacy
.IO_ADDR_W
;
121 /*----------------------------------------------------------------------*/
124 * 1-bit hardware ECC ... context maintained for each core chipselect
127 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info
*mtd
)
129 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
131 return davinci_nand_readl(info
, NANDF1ECC_OFFSET
132 + 4 * info
->core_chipsel
);
135 static void nand_davinci_hwctl_1bit(struct nand_chip
*chip
, int mode
)
137 struct davinci_nand_info
*info
;
141 info
= to_davinci_nand(nand_to_mtd(chip
));
143 /* Reset ECC hardware */
144 nand_davinci_readecc_1bit(nand_to_mtd(chip
));
146 spin_lock_irqsave(&davinci_nand_lock
, flags
);
148 /* Restart ECC hardware */
149 nandcfr
= davinci_nand_readl(info
, NANDFCR_OFFSET
);
150 nandcfr
|= BIT(8 + info
->core_chipsel
);
151 davinci_nand_writel(info
, NANDFCR_OFFSET
, nandcfr
);
153 spin_unlock_irqrestore(&davinci_nand_lock
, flags
);
157 * Read hardware ECC value and pack into three bytes
159 static int nand_davinci_calculate_1bit(struct nand_chip
*chip
,
160 const u_char
*dat
, u_char
*ecc_code
)
162 unsigned int ecc_val
= nand_davinci_readecc_1bit(nand_to_mtd(chip
));
163 unsigned int ecc24
= (ecc_val
& 0x0fff) | ((ecc_val
& 0x0fff0000) >> 4);
165 /* invert so that erased block ecc is correct */
167 ecc_code
[0] = (u_char
)(ecc24
);
168 ecc_code
[1] = (u_char
)(ecc24
>> 8);
169 ecc_code
[2] = (u_char
)(ecc24
>> 16);
174 static int nand_davinci_correct_1bit(struct nand_chip
*chip
, u_char
*dat
,
175 u_char
*read_ecc
, u_char
*calc_ecc
)
177 uint32_t eccNand
= read_ecc
[0] | (read_ecc
[1] << 8) |
179 uint32_t eccCalc
= calc_ecc
[0] | (calc_ecc
[1] << 8) |
181 uint32_t diff
= eccCalc
^ eccNand
;
184 if ((((diff
>> 12) ^ diff
) & 0xfff) == 0xfff) {
185 /* Correctable error */
186 if ((diff
>> (12 + 3)) < chip
->ecc
.size
) {
187 dat
[diff
>> (12 + 3)] ^= BIT((diff
>> 12) & 7);
192 } else if (!(diff
& (diff
- 1))) {
193 /* Single bit ECC error in the ECC itself,
197 /* Uncorrectable error */
205 /*----------------------------------------------------------------------*/
208 * 4-bit hardware ECC ... context maintained over entire AEMIF
210 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
211 * since that forces use of a problematic "infix OOB" layout.
212 * Among other things, it trashes manufacturer bad block markers.
213 * Also, and specific to this hardware, it ECC-protects the "prepad"
214 * in the OOB ... while having ECC protection for parts of OOB would
215 * seem useful, the current MTD stack sometimes wants to update the
216 * OOB without recomputing ECC.
219 static void nand_davinci_hwctl_4bit(struct nand_chip
*chip
, int mode
)
221 struct davinci_nand_info
*info
= to_davinci_nand(nand_to_mtd(chip
));
225 /* Reset ECC hardware */
226 davinci_nand_readl(info
, NAND_4BIT_ECC1_OFFSET
);
228 spin_lock_irqsave(&davinci_nand_lock
, flags
);
230 /* Start 4-bit ECC calculation for read/write */
231 val
= davinci_nand_readl(info
, NANDFCR_OFFSET
);
233 val
|= (info
->core_chipsel
<< 4) | BIT(12);
234 davinci_nand_writel(info
, NANDFCR_OFFSET
, val
);
236 info
->is_readmode
= (mode
== NAND_ECC_READ
);
238 spin_unlock_irqrestore(&davinci_nand_lock
, flags
);
241 /* Read raw ECC code after writing to NAND. */
243 nand_davinci_readecc_4bit(struct davinci_nand_info
*info
, u32 code
[4])
245 const u32 mask
= 0x03ff03ff;
247 code
[0] = davinci_nand_readl(info
, NAND_4BIT_ECC1_OFFSET
) & mask
;
248 code
[1] = davinci_nand_readl(info
, NAND_4BIT_ECC2_OFFSET
) & mask
;
249 code
[2] = davinci_nand_readl(info
, NAND_4BIT_ECC3_OFFSET
) & mask
;
250 code
[3] = davinci_nand_readl(info
, NAND_4BIT_ECC4_OFFSET
) & mask
;
253 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
254 static int nand_davinci_calculate_4bit(struct nand_chip
*chip
,
255 const u_char
*dat
, u_char
*ecc_code
)
257 struct davinci_nand_info
*info
= to_davinci_nand(nand_to_mtd(chip
));
261 /* After a read, terminate ECC calculation by a dummy read
262 * of some 4-bit ECC register. ECC covers everything that
263 * was read; correct() just uses the hardware state, so
264 * ecc_code is not needed.
266 if (info
->is_readmode
) {
267 davinci_nand_readl(info
, NAND_4BIT_ECC1_OFFSET
);
271 /* Pack eight raw 10-bit ecc values into ten bytes, making
272 * two passes which each convert four values (in upper and
273 * lower halves of two 32-bit words) into five bytes. The
274 * ROM boot loader uses this same packing scheme.
276 nand_davinci_readecc_4bit(info
, raw_ecc
);
277 for (i
= 0, p
= raw_ecc
; i
< 2; i
++, p
+= 2) {
278 *ecc_code
++ = p
[0] & 0xff;
279 *ecc_code
++ = ((p
[0] >> 8) & 0x03) | ((p
[0] >> 14) & 0xfc);
280 *ecc_code
++ = ((p
[0] >> 22) & 0x0f) | ((p
[1] << 4) & 0xf0);
281 *ecc_code
++ = ((p
[1] >> 4) & 0x3f) | ((p
[1] >> 10) & 0xc0);
282 *ecc_code
++ = (p
[1] >> 18) & 0xff;
288 /* Correct up to 4 bits in data we just read, using state left in the
289 * hardware plus the ecc_code computed when it was first written.
291 static int nand_davinci_correct_4bit(struct nand_chip
*chip
, u_char
*data
,
292 u_char
*ecc_code
, u_char
*null
)
295 struct davinci_nand_info
*info
= to_davinci_nand(nand_to_mtd(chip
));
296 unsigned short ecc10
[8];
297 unsigned short *ecc16
;
300 unsigned num_errors
, corrected
;
303 /* Unpack ten bytes into eight 10 bit values. We know we're
304 * little-endian, and use type punning for less shifting/masking.
306 if (WARN_ON(0x01 & (uintptr_t)ecc_code
))
308 ecc16
= (unsigned short *)ecc_code
;
310 ecc10
[0] = (ecc16
[0] >> 0) & 0x3ff;
311 ecc10
[1] = ((ecc16
[0] >> 10) & 0x3f) | ((ecc16
[1] << 6) & 0x3c0);
312 ecc10
[2] = (ecc16
[1] >> 4) & 0x3ff;
313 ecc10
[3] = ((ecc16
[1] >> 14) & 0x3) | ((ecc16
[2] << 2) & 0x3fc);
314 ecc10
[4] = (ecc16
[2] >> 8) | ((ecc16
[3] << 8) & 0x300);
315 ecc10
[5] = (ecc16
[3] >> 2) & 0x3ff;
316 ecc10
[6] = ((ecc16
[3] >> 12) & 0xf) | ((ecc16
[4] << 4) & 0x3f0);
317 ecc10
[7] = (ecc16
[4] >> 6) & 0x3ff;
319 /* Tell ECC controller about the expected ECC codes. */
320 for (i
= 7; i
>= 0; i
--)
321 davinci_nand_writel(info
, NAND_4BIT_ECC_LOAD_OFFSET
, ecc10
[i
]);
323 /* Allow time for syndrome calculation ... then read it.
324 * A syndrome of all zeroes 0 means no detected errors.
326 davinci_nand_readl(info
, NANDFSR_OFFSET
);
327 nand_davinci_readecc_4bit(info
, syndrome
);
328 if (!(syndrome
[0] | syndrome
[1] | syndrome
[2] | syndrome
[3]))
332 * Clear any previous address calculation by doing a dummy read of an
333 * error address register.
335 davinci_nand_readl(info
, NAND_ERR_ADD1_OFFSET
);
337 /* Start address calculation, and wait for it to complete.
338 * We _could_ start reading more data while this is working,
339 * to speed up the overall page read.
341 davinci_nand_writel(info
, NANDFCR_OFFSET
,
342 davinci_nand_readl(info
, NANDFCR_OFFSET
) | BIT(13));
345 * ECC_STATE field reads 0x3 (Error correction complete) immediately
346 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
347 * begin trying to poll for the state, you may fall right out of your
348 * loop without any of the correction calculations having taken place.
349 * The recommendation from the hardware team is to initially delay as
350 * long as ECC_STATE reads less than 4. After that, ECC HW has entered
353 timeo
= jiffies
+ usecs_to_jiffies(100);
355 ecc_state
= (davinci_nand_readl(info
,
356 NANDFSR_OFFSET
) >> 8) & 0x0f;
358 } while ((ecc_state
< 4) && time_before(jiffies
, timeo
));
361 u32 fsr
= davinci_nand_readl(info
, NANDFSR_OFFSET
);
363 switch ((fsr
>> 8) & 0x0f) {
364 case 0: /* no error, should not happen */
365 davinci_nand_readl(info
, NAND_ERR_ERRVAL1_OFFSET
);
367 case 1: /* five or more errors detected */
368 davinci_nand_readl(info
, NAND_ERR_ERRVAL1_OFFSET
);
370 case 2: /* error addresses computed */
372 num_errors
= 1 + ((fsr
>> 16) & 0x03);
374 default: /* still working on it */
381 /* correct each error */
382 for (i
= 0, corrected
= 0; i
< num_errors
; i
++) {
383 int error_address
, error_value
;
386 error_address
= davinci_nand_readl(info
,
387 NAND_ERR_ADD2_OFFSET
);
388 error_value
= davinci_nand_readl(info
,
389 NAND_ERR_ERRVAL2_OFFSET
);
391 error_address
= davinci_nand_readl(info
,
392 NAND_ERR_ADD1_OFFSET
);
393 error_value
= davinci_nand_readl(info
,
394 NAND_ERR_ERRVAL1_OFFSET
);
398 error_address
>>= 16;
401 error_address
&= 0x3ff;
402 error_address
= (512 + 7) - error_address
;
404 if (error_address
< 512) {
405 data
[error_address
] ^= error_value
;
413 /*----------------------------------------------------------------------*/
416 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
417 * how these chips are normally wired. This translates to both 8 and 16
418 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
420 * For now we assume that configuration, or any other one which ignores
421 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
422 * and have that transparently morphed into multiple NAND operations.
424 static void nand_davinci_read_buf(struct nand_chip
*chip
, uint8_t *buf
,
427 if ((0x03 & ((uintptr_t)buf
)) == 0 && (0x03 & len
) == 0)
428 ioread32_rep(chip
->legacy
.IO_ADDR_R
, buf
, len
>> 2);
429 else if ((0x01 & ((uintptr_t)buf
)) == 0 && (0x01 & len
) == 0)
430 ioread16_rep(chip
->legacy
.IO_ADDR_R
, buf
, len
>> 1);
432 ioread8_rep(chip
->legacy
.IO_ADDR_R
, buf
, len
);
435 static void nand_davinci_write_buf(struct nand_chip
*chip
, const uint8_t *buf
,
438 if ((0x03 & ((uintptr_t)buf
)) == 0 && (0x03 & len
) == 0)
439 iowrite32_rep(chip
->legacy
.IO_ADDR_R
, buf
, len
>> 2);
440 else if ((0x01 & ((uintptr_t)buf
)) == 0 && (0x01 & len
) == 0)
441 iowrite16_rep(chip
->legacy
.IO_ADDR_R
, buf
, len
>> 1);
443 iowrite8_rep(chip
->legacy
.IO_ADDR_R
, buf
, len
);
447 * Check hardware register for wait status. Returns 1 if device is ready,
448 * 0 if it is still busy.
450 static int nand_davinci_dev_ready(struct nand_chip
*chip
)
452 struct davinci_nand_info
*info
= to_davinci_nand(nand_to_mtd(chip
));
454 return davinci_nand_readl(info
, NANDFSR_OFFSET
) & BIT(0);
457 /*----------------------------------------------------------------------*/
459 /* An ECC layout for using 4-bit ECC with small-page flash, storing
460 * ten ECC bytes plus the manufacturer's bad block marker byte, and
461 * and not overlapping the default BBT markers.
463 static int hwecc4_ooblayout_small_ecc(struct mtd_info
*mtd
, int section
,
464 struct mtd_oob_region
*oobregion
)
470 oobregion
->offset
= 0;
471 oobregion
->length
= 5;
472 } else if (section
== 1) {
473 oobregion
->offset
= 6;
474 oobregion
->length
= 2;
476 oobregion
->offset
= 13;
477 oobregion
->length
= 3;
483 static int hwecc4_ooblayout_small_free(struct mtd_info
*mtd
, int section
,
484 struct mtd_oob_region
*oobregion
)
490 oobregion
->offset
= 8;
491 oobregion
->length
= 5;
493 oobregion
->offset
= 16;
494 oobregion
->length
= mtd
->oobsize
- 16;
500 static const struct mtd_ooblayout_ops hwecc4_small_ooblayout_ops
= {
501 .ecc
= hwecc4_ooblayout_small_ecc
,
502 .free
= hwecc4_ooblayout_small_free
,
505 #if defined(CONFIG_OF)
506 static const struct of_device_id davinci_nand_of_match
[] = {
507 {.compatible
= "ti,davinci-nand", },
508 {.compatible
= "ti,keystone-nand", },
511 MODULE_DEVICE_TABLE(of
, davinci_nand_of_match
);
513 static struct davinci_nand_pdata
514 *nand_davinci_get_pdata(struct platform_device
*pdev
)
516 if (!dev_get_platdata(&pdev
->dev
) && pdev
->dev
.of_node
) {
517 struct davinci_nand_pdata
*pdata
;
521 pdata
= devm_kzalloc(&pdev
->dev
,
522 sizeof(struct davinci_nand_pdata
),
524 pdev
->dev
.platform_data
= pdata
;
526 return ERR_PTR(-ENOMEM
);
527 if (!of_property_read_u32(pdev
->dev
.of_node
,
528 "ti,davinci-chipselect", &prop
))
529 pdata
->core_chipsel
= prop
;
531 return ERR_PTR(-EINVAL
);
533 if (!of_property_read_u32(pdev
->dev
.of_node
,
534 "ti,davinci-mask-ale", &prop
))
535 pdata
->mask_ale
= prop
;
536 if (!of_property_read_u32(pdev
->dev
.of_node
,
537 "ti,davinci-mask-cle", &prop
))
538 pdata
->mask_cle
= prop
;
539 if (!of_property_read_u32(pdev
->dev
.of_node
,
540 "ti,davinci-mask-chipsel", &prop
))
541 pdata
->mask_chipsel
= prop
;
542 if (!of_property_read_string(pdev
->dev
.of_node
,
543 "ti,davinci-ecc-mode", &mode
)) {
544 if (!strncmp("none", mode
, 4))
545 pdata
->ecc_mode
= NAND_ECC_NONE
;
546 if (!strncmp("soft", mode
, 4))
547 pdata
->ecc_mode
= NAND_ECC_SOFT
;
548 if (!strncmp("hw", mode
, 2))
549 pdata
->ecc_mode
= NAND_ECC_HW
;
551 if (!of_property_read_u32(pdev
->dev
.of_node
,
552 "ti,davinci-ecc-bits", &prop
))
553 pdata
->ecc_bits
= prop
;
555 if (!of_property_read_u32(pdev
->dev
.of_node
,
556 "ti,davinci-nand-buswidth", &prop
) && prop
== 16)
557 pdata
->options
|= NAND_BUSWIDTH_16
;
559 if (of_property_read_bool(pdev
->dev
.of_node
,
560 "ti,davinci-nand-use-bbt"))
561 pdata
->bbt_options
= NAND_BBT_USE_FLASH
;
564 * Since kernel v4.8, this driver has been fixed to enable
565 * use of 4-bit hardware ECC with subpages and verified on
566 * TI's keystone EVMs (K2L, K2HK and K2E).
567 * However, in the interest of not breaking systems using
568 * existing UBI partitions, sub-page writes are not being
569 * (re)enabled. If you want to use subpage writes on Keystone
570 * platforms (i.e. do not have any existing UBI partitions),
571 * then use "ti,davinci-nand" as the compatible in your
574 if (of_device_is_compatible(pdev
->dev
.of_node
,
575 "ti,keystone-nand")) {
576 pdata
->options
|= NAND_NO_SUBPAGE_WRITE
;
580 return dev_get_platdata(&pdev
->dev
);
583 static struct davinci_nand_pdata
584 *nand_davinci_get_pdata(struct platform_device
*pdev
)
586 return dev_get_platdata(&pdev
->dev
);
590 static int davinci_nand_attach_chip(struct nand_chip
*chip
)
592 struct mtd_info
*mtd
= nand_to_mtd(chip
);
593 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
594 struct davinci_nand_pdata
*pdata
= nand_davinci_get_pdata(info
->pdev
);
598 return PTR_ERR(pdata
);
600 switch (info
->chip
.ecc
.mode
) {
607 * This driver expects Hamming based ECC when ecc_mode is set
608 * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
609 * avoid adding an extra ->ecc_algo field to
610 * davinci_nand_pdata.
612 info
->chip
.ecc
.algo
= NAND_ECC_HAMMING
;
615 if (pdata
->ecc_bits
== 4) {
617 * No sanity checks: CPUs must support this,
618 * and the chips may not use NAND_BUSWIDTH_16.
621 /* No sharing 4-bit hardware between chipselects yet */
622 spin_lock_irq(&davinci_nand_lock
);
627 spin_unlock_irq(&davinci_nand_lock
);
632 info
->chip
.ecc
.calculate
= nand_davinci_calculate_4bit
;
633 info
->chip
.ecc
.correct
= nand_davinci_correct_4bit
;
634 info
->chip
.ecc
.hwctl
= nand_davinci_hwctl_4bit
;
635 info
->chip
.ecc
.bytes
= 10;
636 info
->chip
.ecc
.options
= NAND_ECC_GENERIC_ERASED_CHECK
;
637 info
->chip
.ecc
.algo
= NAND_ECC_BCH
;
639 /* 1bit ecc hamming */
640 info
->chip
.ecc
.calculate
= nand_davinci_calculate_1bit
;
641 info
->chip
.ecc
.correct
= nand_davinci_correct_1bit
;
642 info
->chip
.ecc
.hwctl
= nand_davinci_hwctl_1bit
;
643 info
->chip
.ecc
.bytes
= 3;
644 info
->chip
.ecc
.algo
= NAND_ECC_HAMMING
;
646 info
->chip
.ecc
.size
= 512;
647 info
->chip
.ecc
.strength
= pdata
->ecc_bits
;
654 * Update ECC layout if needed ... for 1-bit HW ECC, the default
655 * is OK, but it allocates 6 bytes when only 3 are needed (for
656 * each 512 bytes). For the 4-bit HW ECC, that default is not
657 * usable: 10 bytes are needed, not 6.
659 if (pdata
->ecc_bits
== 4) {
660 int chunks
= mtd
->writesize
/ 512;
662 if (!chunks
|| mtd
->oobsize
< 16) {
663 dev_dbg(&info
->pdev
->dev
, "too small\n");
667 /* For small page chips, preserve the manufacturer's
668 * badblock marking data ... and make sure a flash BBT
669 * table marker fits in the free bytes.
672 mtd_set_ooblayout(mtd
, &hwecc4_small_ooblayout_ops
);
673 } else if (chunks
== 4 || chunks
== 8) {
674 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
675 info
->chip
.ecc
.mode
= NAND_ECC_HW_OOB_FIRST
;
684 static const struct nand_controller_ops davinci_nand_controller_ops
= {
685 .attach_chip
= davinci_nand_attach_chip
,
688 static int nand_davinci_probe(struct platform_device
*pdev
)
690 struct davinci_nand_pdata
*pdata
;
691 struct davinci_nand_info
*info
;
692 struct resource
*res1
;
693 struct resource
*res2
;
698 struct mtd_info
*mtd
;
700 pdata
= nand_davinci_get_pdata(pdev
);
702 return PTR_ERR(pdata
);
704 /* insist on board-specific configuration */
708 /* which external chipselect will we be managing? */
709 if (pdata
->core_chipsel
< 0 || pdata
->core_chipsel
> 3)
712 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
716 platform_set_drvdata(pdev
, info
);
718 res1
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
719 res2
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
720 if (!res1
|| !res2
) {
721 dev_err(&pdev
->dev
, "resource missing\n");
725 vaddr
= devm_ioremap_resource(&pdev
->dev
, res1
);
727 return PTR_ERR(vaddr
);
730 * This registers range is used to setup NAND settings. In case with
731 * TI AEMIF driver, the same memory address range is requested already
732 * by AEMIF, so we cannot request it twice, just ioremap.
733 * The AEMIF and NAND drivers not use the same registers in this range.
735 base
= devm_ioremap(&pdev
->dev
, res2
->start
, resource_size(res2
));
737 dev_err(&pdev
->dev
, "ioremap failed for resource %pR\n", res2
);
738 return -EADDRNOTAVAIL
;
745 mtd
= nand_to_mtd(&info
->chip
);
746 mtd
->dev
.parent
= &pdev
->dev
;
747 nand_set_flash_node(&info
->chip
, pdev
->dev
.of_node
);
749 info
->chip
.legacy
.IO_ADDR_R
= vaddr
;
750 info
->chip
.legacy
.IO_ADDR_W
= vaddr
;
751 info
->chip
.legacy
.chip_delay
= 0;
752 info
->chip
.legacy
.select_chip
= nand_davinci_select_chip
;
754 /* options such as NAND_BBT_USE_FLASH */
755 info
->chip
.bbt_options
= pdata
->bbt_options
;
756 /* options such as 16-bit widths */
757 info
->chip
.options
= pdata
->options
;
758 info
->chip
.bbt_td
= pdata
->bbt_td
;
759 info
->chip
.bbt_md
= pdata
->bbt_md
;
760 info
->timing
= pdata
->timing
;
762 info
->current_cs
= info
->vaddr
;
763 info
->core_chipsel
= pdata
->core_chipsel
;
764 info
->mask_chipsel
= pdata
->mask_chipsel
;
766 /* use nandboot-capable ALE/CLE masks by default */
767 info
->mask_ale
= pdata
->mask_ale
? : MASK_ALE
;
768 info
->mask_cle
= pdata
->mask_cle
? : MASK_CLE
;
770 /* Set address of hardware control function */
771 info
->chip
.legacy
.cmd_ctrl
= nand_davinci_hwcontrol
;
772 info
->chip
.legacy
.dev_ready
= nand_davinci_dev_ready
;
774 /* Speed up buffer I/O */
775 info
->chip
.legacy
.read_buf
= nand_davinci_read_buf
;
776 info
->chip
.legacy
.write_buf
= nand_davinci_write_buf
;
778 /* Use board-specific ECC config */
779 info
->chip
.ecc
.mode
= pdata
->ecc_mode
;
781 spin_lock_irq(&davinci_nand_lock
);
783 /* put CSxNAND into NAND mode */
784 val
= davinci_nand_readl(info
, NANDFCR_OFFSET
);
785 val
|= BIT(info
->core_chipsel
);
786 davinci_nand_writel(info
, NANDFCR_OFFSET
, val
);
788 spin_unlock_irq(&davinci_nand_lock
);
790 /* Scan to find existence of the device(s) */
791 info
->chip
.legacy
.dummy_controller
.ops
= &davinci_nand_controller_ops
;
792 ret
= nand_scan(&info
->chip
, pdata
->mask_chipsel
? 2 : 1);
794 dev_dbg(&pdev
->dev
, "no NAND chip(s) found\n");
799 ret
= mtd_device_register(mtd
, pdata
->parts
, pdata
->nr_parts
);
801 ret
= mtd_device_register(mtd
, NULL
, 0);
803 goto err_cleanup_nand
;
805 val
= davinci_nand_readl(info
, NRCSR_OFFSET
);
806 dev_info(&pdev
->dev
, "controller rev. %d.%d\n",
807 (val
>> 8) & 0xff, val
& 0xff);
812 nand_cleanup(&info
->chip
);
817 static int nand_davinci_remove(struct platform_device
*pdev
)
819 struct davinci_nand_info
*info
= platform_get_drvdata(pdev
);
821 spin_lock_irq(&davinci_nand_lock
);
822 if (info
->chip
.ecc
.mode
== NAND_ECC_HW_SYNDROME
)
824 spin_unlock_irq(&davinci_nand_lock
);
826 nand_release(&info
->chip
);
831 static struct platform_driver nand_davinci_driver
= {
832 .probe
= nand_davinci_probe
,
833 .remove
= nand_davinci_remove
,
835 .name
= "davinci_nand",
836 .of_match_table
= of_match_ptr(davinci_nand_of_match
),
839 MODULE_ALIAS("platform:davinci_nand");
841 module_platform_driver(nand_davinci_driver
);
843 MODULE_LICENSE("GPL");
844 MODULE_AUTHOR("Texas Instruments");
845 MODULE_DESCRIPTION("Davinci NAND flash driver");