1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Freescale Enhanced Local Bus Controller NAND driver
4 * Copyright © 2006-2007, 2010 Freescale Semiconductor
6 * Authors: Nick Spence <nick.spence@freescale.com>,
7 * Scott Wood <scottwood@freescale.com>
8 * Jack Lan <jack.lan@freescale.com>
9 * Roy Zang <tie-fei.zang@freescale.com>
12 #include <linux/module.h>
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <linux/string.h>
16 #include <linux/ioport.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/interrupt.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/rawnand.h>
25 #include <linux/mtd/nand_ecc.h>
26 #include <linux/mtd/partitions.h>
29 #include <asm/fsl_lbc.h>
32 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
33 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
35 /* mtd information per set */
38 struct nand_chip chip
;
39 struct fsl_lbc_ctrl
*ctrl
;
42 int bank
; /* Chip select bank number */
43 u8 __iomem
*vbase
; /* Chip select base virtual address */
44 int page_size
; /* NAND page size (0=512, 1=2048) */
45 unsigned int fmr
; /* FCM Flash Mode Register value */
48 /* Freescale eLBC FCM controller information */
50 struct fsl_elbc_fcm_ctrl
{
51 struct nand_controller controller
;
52 struct fsl_elbc_mtd
*chips
[MAX_BANKS
];
54 u8 __iomem
*addr
; /* Address of assigned FCM buffer */
55 unsigned int page
; /* Last page written to / read from */
56 unsigned int read_bytes
; /* Number of bytes read during command */
57 unsigned int column
; /* Saved column from SEQIN */
58 unsigned int index
; /* Pointer to next byte to 'read' */
59 unsigned int status
; /* status read from LTESR after last op */
60 unsigned int mdr
; /* UPM/FCM Data Register value */
61 unsigned int use_mdr
; /* Non zero if the MDR is to be set */
62 unsigned int oob
; /* Non zero if operating on OOB data */
63 unsigned int counter
; /* counter for the initializations */
64 unsigned int max_bitflips
; /* Saved during READ0 cmd */
67 /* These map to the positions used by the FCM hardware ECC generator */
69 static int fsl_elbc_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
70 struct mtd_oob_region
*oobregion
)
72 struct nand_chip
*chip
= mtd_to_nand(mtd
);
73 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
75 if (section
>= chip
->ecc
.steps
)
78 oobregion
->offset
= (16 * section
) + 6;
79 if (priv
->fmr
& FMR_ECCM
)
80 oobregion
->offset
+= 2;
82 oobregion
->length
= chip
->ecc
.bytes
;
87 static int fsl_elbc_ooblayout_free(struct mtd_info
*mtd
, int section
,
88 struct mtd_oob_region
*oobregion
)
90 struct nand_chip
*chip
= mtd_to_nand(mtd
);
91 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
93 if (section
> chip
->ecc
.steps
)
97 oobregion
->offset
= 0;
98 if (mtd
->writesize
> 512)
100 oobregion
->length
= (priv
->fmr
& FMR_ECCM
) ? 7 : 5;
102 oobregion
->offset
= (16 * section
) -
103 ((priv
->fmr
& FMR_ECCM
) ? 5 : 7);
104 if (section
< chip
->ecc
.steps
)
105 oobregion
->length
= 13;
107 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
113 static const struct mtd_ooblayout_ops fsl_elbc_ooblayout_ops
= {
114 .ecc
= fsl_elbc_ooblayout_ecc
,
115 .free
= fsl_elbc_ooblayout_free
,
119 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
120 * interfere with ECC positions, that's why we implement our own descriptors.
121 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
123 static u8 bbt_pattern
[] = {'B', 'b', 't', '0' };
124 static u8 mirror_pattern
[] = {'1', 't', 'b', 'B' };
126 static struct nand_bbt_descr bbt_main_descr
= {
127 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
|
128 NAND_BBT_2BIT
| NAND_BBT_VERSION
,
133 .pattern
= bbt_pattern
,
136 static struct nand_bbt_descr bbt_mirror_descr
= {
137 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
|
138 NAND_BBT_2BIT
| NAND_BBT_VERSION
,
143 .pattern
= mirror_pattern
,
146 /*=================================*/
149 * Set up the FCM hardware block and page address fields, and the fcm
150 * structure addr field to point to the correct FCM buffer in memory
152 static void set_addr(struct mtd_info
*mtd
, int column
, int page_addr
, int oob
)
154 struct nand_chip
*chip
= mtd_to_nand(mtd
);
155 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
156 struct fsl_lbc_ctrl
*ctrl
= priv
->ctrl
;
157 struct fsl_lbc_regs __iomem
*lbc
= ctrl
->regs
;
158 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= ctrl
->nand
;
161 elbc_fcm_ctrl
->page
= page_addr
;
163 if (priv
->page_size
) {
165 * large page size chip : FPAR[PI] save the lowest 6 bits,
166 * FBAR[BLK] save the other bits.
168 out_be32(&lbc
->fbar
, page_addr
>> 6);
170 ((page_addr
<< FPAR_LP_PI_SHIFT
) & FPAR_LP_PI
) |
171 (oob
? FPAR_LP_MS
: 0) | column
);
172 buf_num
= (page_addr
& 1) << 2;
175 * small page size chip : FPAR[PI] save the lowest 5 bits,
176 * FBAR[BLK] save the other bits.
178 out_be32(&lbc
->fbar
, page_addr
>> 5);
180 ((page_addr
<< FPAR_SP_PI_SHIFT
) & FPAR_SP_PI
) |
181 (oob
? FPAR_SP_MS
: 0) | column
);
182 buf_num
= page_addr
& 7;
185 elbc_fcm_ctrl
->addr
= priv
->vbase
+ buf_num
* 1024;
186 elbc_fcm_ctrl
->index
= column
;
188 /* for OOB data point to the second half of the buffer */
190 elbc_fcm_ctrl
->index
+= priv
->page_size
? 2048 : 512;
192 dev_vdbg(priv
->dev
, "set_addr: bank=%d, "
193 "elbc_fcm_ctrl->addr=0x%p (0x%p), "
194 "index %x, pes %d ps %d\n",
195 buf_num
, elbc_fcm_ctrl
->addr
, priv
->vbase
,
196 elbc_fcm_ctrl
->index
,
197 chip
->phys_erase_shift
, chip
->page_shift
);
201 * execute FCM command and wait for it to complete
203 static int fsl_elbc_run_command(struct mtd_info
*mtd
)
205 struct nand_chip
*chip
= mtd_to_nand(mtd
);
206 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
207 struct fsl_lbc_ctrl
*ctrl
= priv
->ctrl
;
208 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= ctrl
->nand
;
209 struct fsl_lbc_regs __iomem
*lbc
= ctrl
->regs
;
211 /* Setup the FMR[OP] to execute without write protection */
212 out_be32(&lbc
->fmr
, priv
->fmr
| 3);
213 if (elbc_fcm_ctrl
->use_mdr
)
214 out_be32(&lbc
->mdr
, elbc_fcm_ctrl
->mdr
);
217 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
218 in_be32(&lbc
->fmr
), in_be32(&lbc
->fir
), in_be32(&lbc
->fcr
));
220 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
221 "fbcr=%08x bank=%d\n",
222 in_be32(&lbc
->fbar
), in_be32(&lbc
->fpar
),
223 in_be32(&lbc
->fbcr
), priv
->bank
);
225 ctrl
->irq_status
= 0;
226 /* execute special operation */
227 out_be32(&lbc
->lsor
, priv
->bank
);
229 /* wait for FCM complete flag or timeout */
230 wait_event_timeout(ctrl
->irq_wait
, ctrl
->irq_status
,
231 FCM_TIMEOUT_MSECS
* HZ
/1000);
232 elbc_fcm_ctrl
->status
= ctrl
->irq_status
;
233 /* store mdr value in case it was needed */
234 if (elbc_fcm_ctrl
->use_mdr
)
235 elbc_fcm_ctrl
->mdr
= in_be32(&lbc
->mdr
);
237 elbc_fcm_ctrl
->use_mdr
= 0;
239 if (elbc_fcm_ctrl
->status
!= LTESR_CC
) {
241 "command failed: fir %x fcr %x status %x mdr %x\n",
242 in_be32(&lbc
->fir
), in_be32(&lbc
->fcr
),
243 elbc_fcm_ctrl
->status
, elbc_fcm_ctrl
->mdr
);
247 if (chip
->ecc
.mode
!= NAND_ECC_HW
)
250 elbc_fcm_ctrl
->max_bitflips
= 0;
252 if (elbc_fcm_ctrl
->read_bytes
== mtd
->writesize
+ mtd
->oobsize
) {
253 uint32_t lteccr
= in_be32(&lbc
->lteccr
);
255 * if command was a full page read and the ELBC
256 * has the LTECCR register, then bits 12-15 (ppc order) of
257 * LTECCR indicates which 512 byte sub-pages had fixed errors.
258 * bits 28-31 are uncorrectable errors, marked elsewhere.
259 * for small page nand only 1 bit is used.
260 * if the ELBC doesn't have the lteccr register it reads 0
261 * FIXME: 4 bits can be corrected on NANDs with 2k pages, so
262 * count the number of sub-pages with bitflips and update
263 * ecc_stats.corrected accordingly.
265 if (lteccr
& 0x000F000F)
266 out_be32(&lbc
->lteccr
, 0x000F000F); /* clear lteccr */
267 if (lteccr
& 0x000F0000) {
268 mtd
->ecc_stats
.corrected
++;
269 elbc_fcm_ctrl
->max_bitflips
= 1;
276 static void fsl_elbc_do_read(struct nand_chip
*chip
, int oob
)
278 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
279 struct fsl_lbc_ctrl
*ctrl
= priv
->ctrl
;
280 struct fsl_lbc_regs __iomem
*lbc
= ctrl
->regs
;
282 if (priv
->page_size
) {
284 (FIR_OP_CM0
<< FIR_OP0_SHIFT
) |
285 (FIR_OP_CA
<< FIR_OP1_SHIFT
) |
286 (FIR_OP_PA
<< FIR_OP2_SHIFT
) |
287 (FIR_OP_CM1
<< FIR_OP3_SHIFT
) |
288 (FIR_OP_RBW
<< FIR_OP4_SHIFT
));
290 out_be32(&lbc
->fcr
, (NAND_CMD_READ0
<< FCR_CMD0_SHIFT
) |
291 (NAND_CMD_READSTART
<< FCR_CMD1_SHIFT
));
294 (FIR_OP_CM0
<< FIR_OP0_SHIFT
) |
295 (FIR_OP_CA
<< FIR_OP1_SHIFT
) |
296 (FIR_OP_PA
<< FIR_OP2_SHIFT
) |
297 (FIR_OP_RBW
<< FIR_OP3_SHIFT
));
300 out_be32(&lbc
->fcr
, NAND_CMD_READOOB
<< FCR_CMD0_SHIFT
);
302 out_be32(&lbc
->fcr
, NAND_CMD_READ0
<< FCR_CMD0_SHIFT
);
306 /* cmdfunc send commands to the FCM */
307 static void fsl_elbc_cmdfunc(struct nand_chip
*chip
, unsigned int command
,
308 int column
, int page_addr
)
310 struct mtd_info
*mtd
= nand_to_mtd(chip
);
311 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
312 struct fsl_lbc_ctrl
*ctrl
= priv
->ctrl
;
313 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= ctrl
->nand
;
314 struct fsl_lbc_regs __iomem
*lbc
= ctrl
->regs
;
316 elbc_fcm_ctrl
->use_mdr
= 0;
318 /* clear the read buffer */
319 elbc_fcm_ctrl
->read_bytes
= 0;
320 if (command
!= NAND_CMD_PAGEPROG
)
321 elbc_fcm_ctrl
->index
= 0;
324 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
331 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
332 " 0x%x, column: 0x%x.\n", page_addr
, column
);
335 out_be32(&lbc
->fbcr
, 0); /* read entire page to enable ECC */
336 set_addr(mtd
, 0, page_addr
, 0);
338 elbc_fcm_ctrl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
;
339 elbc_fcm_ctrl
->index
+= column
;
341 fsl_elbc_do_read(chip
, 0);
342 fsl_elbc_run_command(mtd
);
345 /* RNDOUT moves the pointer inside the page */
346 case NAND_CMD_RNDOUT
:
348 "fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n",
351 elbc_fcm_ctrl
->index
= column
;
354 /* READOOB reads only the OOB because no ECC is performed. */
355 case NAND_CMD_READOOB
:
357 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
358 " 0x%x, column: 0x%x.\n", page_addr
, column
);
360 out_be32(&lbc
->fbcr
, mtd
->oobsize
- column
);
361 set_addr(mtd
, column
, page_addr
, 1);
363 elbc_fcm_ctrl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
;
365 fsl_elbc_do_read(chip
, 1);
366 fsl_elbc_run_command(mtd
);
369 case NAND_CMD_READID
:
371 dev_vdbg(priv
->dev
, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command
);
373 out_be32(&lbc
->fir
, (FIR_OP_CM0
<< FIR_OP0_SHIFT
) |
374 (FIR_OP_UA
<< FIR_OP1_SHIFT
) |
375 (FIR_OP_RBW
<< FIR_OP2_SHIFT
));
376 out_be32(&lbc
->fcr
, command
<< FCR_CMD0_SHIFT
);
378 * although currently it's 8 bytes for READID, we always read
379 * the maximum 256 bytes(for PARAM)
381 out_be32(&lbc
->fbcr
, 256);
382 elbc_fcm_ctrl
->read_bytes
= 256;
383 elbc_fcm_ctrl
->use_mdr
= 1;
384 elbc_fcm_ctrl
->mdr
= column
;
385 set_addr(mtd
, 0, 0, 0);
386 fsl_elbc_run_command(mtd
);
389 /* ERASE1 stores the block and page address */
390 case NAND_CMD_ERASE1
:
392 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
393 "page_addr: 0x%x.\n", page_addr
);
394 set_addr(mtd
, 0, page_addr
, 0);
397 /* ERASE2 uses the block and page address from ERASE1 */
398 case NAND_CMD_ERASE2
:
399 dev_vdbg(priv
->dev
, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
402 (FIR_OP_CM0
<< FIR_OP0_SHIFT
) |
403 (FIR_OP_PA
<< FIR_OP1_SHIFT
) |
404 (FIR_OP_CM2
<< FIR_OP2_SHIFT
) |
405 (FIR_OP_CW1
<< FIR_OP3_SHIFT
) |
406 (FIR_OP_RS
<< FIR_OP4_SHIFT
));
409 (NAND_CMD_ERASE1
<< FCR_CMD0_SHIFT
) |
410 (NAND_CMD_STATUS
<< FCR_CMD1_SHIFT
) |
411 (NAND_CMD_ERASE2
<< FCR_CMD2_SHIFT
));
413 out_be32(&lbc
->fbcr
, 0);
414 elbc_fcm_ctrl
->read_bytes
= 0;
415 elbc_fcm_ctrl
->use_mdr
= 1;
417 fsl_elbc_run_command(mtd
);
420 /* SEQIN sets up the addr buffer and all registers except the length */
421 case NAND_CMD_SEQIN
: {
424 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
425 "page_addr: 0x%x, column: 0x%x.\n",
428 elbc_fcm_ctrl
->column
= column
;
429 elbc_fcm_ctrl
->use_mdr
= 1;
431 if (column
>= mtd
->writesize
) {
433 column
-= mtd
->writesize
;
434 elbc_fcm_ctrl
->oob
= 1;
436 WARN_ON(column
!= 0);
437 elbc_fcm_ctrl
->oob
= 0;
440 fcr
= (NAND_CMD_STATUS
<< FCR_CMD1_SHIFT
) |
441 (NAND_CMD_SEQIN
<< FCR_CMD2_SHIFT
) |
442 (NAND_CMD_PAGEPROG
<< FCR_CMD3_SHIFT
);
444 if (priv
->page_size
) {
446 (FIR_OP_CM2
<< FIR_OP0_SHIFT
) |
447 (FIR_OP_CA
<< FIR_OP1_SHIFT
) |
448 (FIR_OP_PA
<< FIR_OP2_SHIFT
) |
449 (FIR_OP_WB
<< FIR_OP3_SHIFT
) |
450 (FIR_OP_CM3
<< FIR_OP4_SHIFT
) |
451 (FIR_OP_CW1
<< FIR_OP5_SHIFT
) |
452 (FIR_OP_RS
<< FIR_OP6_SHIFT
));
455 (FIR_OP_CM0
<< FIR_OP0_SHIFT
) |
456 (FIR_OP_CM2
<< FIR_OP1_SHIFT
) |
457 (FIR_OP_CA
<< FIR_OP2_SHIFT
) |
458 (FIR_OP_PA
<< FIR_OP3_SHIFT
) |
459 (FIR_OP_WB
<< FIR_OP4_SHIFT
) |
460 (FIR_OP_CM3
<< FIR_OP5_SHIFT
) |
461 (FIR_OP_CW1
<< FIR_OP6_SHIFT
) |
462 (FIR_OP_RS
<< FIR_OP7_SHIFT
));
464 if (elbc_fcm_ctrl
->oob
)
465 /* OOB area --> READOOB */
466 fcr
|= NAND_CMD_READOOB
<< FCR_CMD0_SHIFT
;
468 /* First 256 bytes --> READ0 */
469 fcr
|= NAND_CMD_READ0
<< FCR_CMD0_SHIFT
;
472 out_be32(&lbc
->fcr
, fcr
);
473 set_addr(mtd
, column
, page_addr
, elbc_fcm_ctrl
->oob
);
477 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
478 case NAND_CMD_PAGEPROG
: {
480 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
481 "writing %d bytes.\n", elbc_fcm_ctrl
->index
);
483 /* if the write did not start at 0 or is not a full page
484 * then set the exact length, otherwise use a full page
485 * write so the HW generates the ECC.
487 if (elbc_fcm_ctrl
->oob
|| elbc_fcm_ctrl
->column
!= 0 ||
488 elbc_fcm_ctrl
->index
!= mtd
->writesize
+ mtd
->oobsize
)
490 elbc_fcm_ctrl
->index
- elbc_fcm_ctrl
->column
);
492 out_be32(&lbc
->fbcr
, 0);
494 fsl_elbc_run_command(mtd
);
498 /* CMD_STATUS must read the status byte while CEB is active */
499 /* Note - it does not wait for the ready line */
500 case NAND_CMD_STATUS
:
502 (FIR_OP_CM0
<< FIR_OP0_SHIFT
) |
503 (FIR_OP_RBW
<< FIR_OP1_SHIFT
));
504 out_be32(&lbc
->fcr
, NAND_CMD_STATUS
<< FCR_CMD0_SHIFT
);
505 out_be32(&lbc
->fbcr
, 1);
506 set_addr(mtd
, 0, 0, 0);
507 elbc_fcm_ctrl
->read_bytes
= 1;
509 fsl_elbc_run_command(mtd
);
511 /* The chip always seems to report that it is
512 * write-protected, even when it is not.
514 setbits8(elbc_fcm_ctrl
->addr
, NAND_STATUS_WP
);
517 /* RESET without waiting for the ready line */
519 dev_dbg(priv
->dev
, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
520 out_be32(&lbc
->fir
, FIR_OP_CM0
<< FIR_OP0_SHIFT
);
521 out_be32(&lbc
->fcr
, NAND_CMD_RESET
<< FCR_CMD0_SHIFT
);
522 fsl_elbc_run_command(mtd
);
527 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
532 static void fsl_elbc_select_chip(struct nand_chip
*chip
, int cs
)
534 /* The hardware does not seem to support multiple
540 * Write buf to the FCM Controller Data Buffer
542 static void fsl_elbc_write_buf(struct nand_chip
*chip
, const u8
*buf
, int len
)
544 struct mtd_info
*mtd
= nand_to_mtd(chip
);
545 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
546 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= priv
->ctrl
->nand
;
547 unsigned int bufsize
= mtd
->writesize
+ mtd
->oobsize
;
550 dev_err(priv
->dev
, "write_buf of %d bytes", len
);
551 elbc_fcm_ctrl
->status
= 0;
555 if ((unsigned int)len
> bufsize
- elbc_fcm_ctrl
->index
) {
557 "write_buf beyond end of buffer "
558 "(%d requested, %u available)\n",
559 len
, bufsize
- elbc_fcm_ctrl
->index
);
560 len
= bufsize
- elbc_fcm_ctrl
->index
;
563 memcpy_toio(&elbc_fcm_ctrl
->addr
[elbc_fcm_ctrl
->index
], buf
, len
);
565 * This is workaround for the weird elbc hangs during nand write,
566 * Scott Wood says: "...perhaps difference in how long it takes a
567 * write to make it through the localbus compared to a write to IMMR
568 * is causing problems, and sync isn't helping for some reason."
569 * Reading back the last byte helps though.
571 in_8(&elbc_fcm_ctrl
->addr
[elbc_fcm_ctrl
->index
] + len
- 1);
573 elbc_fcm_ctrl
->index
+= len
;
577 * read a byte from either the FCM hardware buffer if it has any data left
578 * otherwise issue a command to read a single byte.
580 static u8
fsl_elbc_read_byte(struct nand_chip
*chip
)
582 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
583 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= priv
->ctrl
->nand
;
585 /* If there are still bytes in the FCM, then use the next byte. */
586 if (elbc_fcm_ctrl
->index
< elbc_fcm_ctrl
->read_bytes
)
587 return in_8(&elbc_fcm_ctrl
->addr
[elbc_fcm_ctrl
->index
++]);
589 dev_err(priv
->dev
, "read_byte beyond end of buffer\n");
594 * Read from the FCM Controller Data Buffer
596 static void fsl_elbc_read_buf(struct nand_chip
*chip
, u8
*buf
, int len
)
598 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
599 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= priv
->ctrl
->nand
;
605 avail
= min((unsigned int)len
,
606 elbc_fcm_ctrl
->read_bytes
- elbc_fcm_ctrl
->index
);
607 memcpy_fromio(buf
, &elbc_fcm_ctrl
->addr
[elbc_fcm_ctrl
->index
], avail
);
608 elbc_fcm_ctrl
->index
+= avail
;
612 "read_buf beyond end of buffer "
613 "(%d requested, %d available)\n",
617 /* This function is called after Program and Erase Operations to
618 * check for success or failure.
620 static int fsl_elbc_wait(struct nand_chip
*chip
)
622 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
623 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= priv
->ctrl
->nand
;
625 if (elbc_fcm_ctrl
->status
!= LTESR_CC
)
626 return NAND_STATUS_FAIL
;
628 /* The chip always seems to report that it is
629 * write-protected, even when it is not.
631 return (elbc_fcm_ctrl
->mdr
& 0xff) | NAND_STATUS_WP
;
634 static int fsl_elbc_read_page(struct nand_chip
*chip
, uint8_t *buf
,
635 int oob_required
, int page
)
637 struct mtd_info
*mtd
= nand_to_mtd(chip
);
638 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
639 struct fsl_lbc_ctrl
*ctrl
= priv
->ctrl
;
640 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= ctrl
->nand
;
642 nand_read_page_op(chip
, page
, 0, buf
, mtd
->writesize
);
644 fsl_elbc_read_buf(chip
, chip
->oob_poi
, mtd
->oobsize
);
646 if (fsl_elbc_wait(chip
) & NAND_STATUS_FAIL
)
647 mtd
->ecc_stats
.failed
++;
649 return elbc_fcm_ctrl
->max_bitflips
;
652 /* ECC will be calculated automatically, and errors will be detected in
655 static int fsl_elbc_write_page(struct nand_chip
*chip
, const uint8_t *buf
,
656 int oob_required
, int page
)
658 struct mtd_info
*mtd
= nand_to_mtd(chip
);
660 nand_prog_page_begin_op(chip
, page
, 0, buf
, mtd
->writesize
);
661 fsl_elbc_write_buf(chip
, chip
->oob_poi
, mtd
->oobsize
);
663 return nand_prog_page_end_op(chip
);
666 /* ECC will be calculated automatically, and errors will be detected in
669 static int fsl_elbc_write_subpage(struct nand_chip
*chip
, uint32_t offset
,
670 uint32_t data_len
, const uint8_t *buf
,
671 int oob_required
, int page
)
673 struct mtd_info
*mtd
= nand_to_mtd(chip
);
675 nand_prog_page_begin_op(chip
, page
, 0, NULL
, 0);
676 fsl_elbc_write_buf(chip
, buf
, mtd
->writesize
);
677 fsl_elbc_write_buf(chip
, chip
->oob_poi
, mtd
->oobsize
);
678 return nand_prog_page_end_op(chip
);
681 static int fsl_elbc_chip_init(struct fsl_elbc_mtd
*priv
)
683 struct fsl_lbc_ctrl
*ctrl
= priv
->ctrl
;
684 struct fsl_lbc_regs __iomem
*lbc
= ctrl
->regs
;
685 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= ctrl
->nand
;
686 struct nand_chip
*chip
= &priv
->chip
;
687 struct mtd_info
*mtd
= nand_to_mtd(chip
);
689 dev_dbg(priv
->dev
, "eLBC Set Information for bank %d\n", priv
->bank
);
691 /* Fill in fsl_elbc_mtd structure */
692 mtd
->dev
.parent
= priv
->dev
;
693 nand_set_flash_node(chip
, priv
->dev
->of_node
);
695 /* set timeout to maximum */
696 priv
->fmr
= 15 << FMR_CWTO_SHIFT
;
697 if (in_be32(&lbc
->bank
[priv
->bank
].or) & OR_FCM_PGS
)
698 priv
->fmr
|= FMR_ECCM
;
700 /* fill in nand_chip structure */
701 /* set up function call table */
702 chip
->legacy
.read_byte
= fsl_elbc_read_byte
;
703 chip
->legacy
.write_buf
= fsl_elbc_write_buf
;
704 chip
->legacy
.read_buf
= fsl_elbc_read_buf
;
705 chip
->legacy
.select_chip
= fsl_elbc_select_chip
;
706 chip
->legacy
.cmdfunc
= fsl_elbc_cmdfunc
;
707 chip
->legacy
.waitfunc
= fsl_elbc_wait
;
708 chip
->legacy
.set_features
= nand_get_set_features_notsupp
;
709 chip
->legacy
.get_features
= nand_get_set_features_notsupp
;
711 chip
->bbt_td
= &bbt_main_descr
;
712 chip
->bbt_md
= &bbt_mirror_descr
;
714 /* set up nand options */
715 chip
->bbt_options
= NAND_BBT_USE_FLASH
;
717 chip
->controller
= &elbc_fcm_ctrl
->controller
;
718 nand_set_controller_data(chip
, priv
);
723 static int fsl_elbc_attach_chip(struct nand_chip
*chip
)
725 struct mtd_info
*mtd
= nand_to_mtd(chip
);
726 struct fsl_elbc_mtd
*priv
= nand_get_controller_data(chip
);
727 struct fsl_lbc_ctrl
*ctrl
= priv
->ctrl
;
728 struct fsl_lbc_regs __iomem
*lbc
= ctrl
->regs
;
731 switch (chip
->ecc
.mode
) {
733 * if ECC was not chosen in DT, decide whether to use HW or SW ECC from
737 /* If CS Base Register selects full hardware ECC then use it */
738 if ((in_be32(&lbc
->bank
[priv
->bank
].br
) & BR_DECC
) ==
740 chip
->ecc
.read_page
= fsl_elbc_read_page
;
741 chip
->ecc
.write_page
= fsl_elbc_write_page
;
742 chip
->ecc
.write_subpage
= fsl_elbc_write_subpage
;
744 chip
->ecc
.mode
= NAND_ECC_HW
;
745 mtd_set_ooblayout(mtd
, &fsl_elbc_ooblayout_ops
);
746 chip
->ecc
.size
= 512;
748 chip
->ecc
.strength
= 1;
750 /* otherwise fall back to default software ECC */
751 chip
->ecc
.mode
= NAND_ECC_SOFT
;
752 chip
->ecc
.algo
= NAND_ECC_HAMMING
;
756 /* if SW ECC was chosen in DT, we do not need to set anything here */
760 /* should we also implement NAND_ECC_HW to do as the code above? */
765 /* calculate FMR Address Length field */
767 if (chip
->pagemask
& 0xffff0000)
769 if (chip
->pagemask
& 0xff000000)
772 priv
->fmr
|= al
<< FMR_AL_SHIFT
;
774 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->numchips = %d\n",
775 nanddev_ntargets(&chip
->base
));
776 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->chipsize = %lld\n",
777 nanddev_target_size(&chip
->base
));
778 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->pagemask = %8x\n",
780 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->legacy.chip_delay = %d\n",
781 chip
->legacy
.chip_delay
);
782 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->badblockpos = %d\n",
784 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->chip_shift = %d\n",
786 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->page_shift = %d\n",
788 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
789 chip
->phys_erase_shift
);
790 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->ecc.mode = %d\n",
792 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->ecc.steps = %d\n",
794 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->ecc.bytes = %d\n",
796 dev_dbg(priv
->dev
, "fsl_elbc_init: nand->ecc.total = %d\n",
798 dev_dbg(priv
->dev
, "fsl_elbc_init: mtd->ooblayout = %p\n",
800 dev_dbg(priv
->dev
, "fsl_elbc_init: mtd->flags = %08x\n", mtd
->flags
);
801 dev_dbg(priv
->dev
, "fsl_elbc_init: mtd->size = %lld\n", mtd
->size
);
802 dev_dbg(priv
->dev
, "fsl_elbc_init: mtd->erasesize = %d\n",
804 dev_dbg(priv
->dev
, "fsl_elbc_init: mtd->writesize = %d\n",
806 dev_dbg(priv
->dev
, "fsl_elbc_init: mtd->oobsize = %d\n",
809 /* adjust Option Register and ECC to match Flash page size */
810 if (mtd
->writesize
== 512) {
812 clrbits32(&lbc
->bank
[priv
->bank
].or, OR_FCM_PGS
);
813 } else if (mtd
->writesize
== 2048) {
815 setbits32(&lbc
->bank
[priv
->bank
].or, OR_FCM_PGS
);
818 "fsl_elbc_init: page size %d is not supported\n",
826 static const struct nand_controller_ops fsl_elbc_controller_ops
= {
827 .attach_chip
= fsl_elbc_attach_chip
,
830 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd
*priv
)
832 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= priv
->ctrl
->nand
;
833 struct mtd_info
*mtd
= nand_to_mtd(&priv
->chip
);
838 iounmap(priv
->vbase
);
840 elbc_fcm_ctrl
->chips
[priv
->bank
] = NULL
;
845 static DEFINE_MUTEX(fsl_elbc_nand_mutex
);
847 static int fsl_elbc_nand_probe(struct platform_device
*pdev
)
849 struct fsl_lbc_regs __iomem
*lbc
;
850 struct fsl_elbc_mtd
*priv
;
852 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
;
853 static const char *part_probe_types
[]
854 = { "cmdlinepart", "RedBoot", "ofpart", NULL
};
858 struct device_node
*node
= pdev
->dev
.of_node
;
859 struct mtd_info
*mtd
;
861 if (!fsl_lbc_ctrl_dev
|| !fsl_lbc_ctrl_dev
->regs
)
863 lbc
= fsl_lbc_ctrl_dev
->regs
;
864 dev
= fsl_lbc_ctrl_dev
->dev
;
866 /* get, allocate and map the memory resource */
867 ret
= of_address_to_resource(node
, 0, &res
);
869 dev_err(dev
, "failed to get resource\n");
873 /* find which chip select it is connected to */
874 for (bank
= 0; bank
< MAX_BANKS
; bank
++)
875 if ((in_be32(&lbc
->bank
[bank
].br
) & BR_V
) &&
876 (in_be32(&lbc
->bank
[bank
].br
) & BR_MSEL
) == BR_MS_FCM
&&
877 (in_be32(&lbc
->bank
[bank
].br
) &
878 in_be32(&lbc
->bank
[bank
].or) & BR_BA
)
879 == fsl_lbc_addr(res
.start
))
882 if (bank
>= MAX_BANKS
) {
883 dev_err(dev
, "address did not match any chip selects\n");
887 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
891 mutex_lock(&fsl_elbc_nand_mutex
);
892 if (!fsl_lbc_ctrl_dev
->nand
) {
893 elbc_fcm_ctrl
= kzalloc(sizeof(*elbc_fcm_ctrl
), GFP_KERNEL
);
894 if (!elbc_fcm_ctrl
) {
895 mutex_unlock(&fsl_elbc_nand_mutex
);
899 elbc_fcm_ctrl
->counter
++;
901 nand_controller_init(&elbc_fcm_ctrl
->controller
);
902 fsl_lbc_ctrl_dev
->nand
= elbc_fcm_ctrl
;
904 elbc_fcm_ctrl
= fsl_lbc_ctrl_dev
->nand
;
906 mutex_unlock(&fsl_elbc_nand_mutex
);
908 elbc_fcm_ctrl
->chips
[bank
] = priv
;
910 priv
->ctrl
= fsl_lbc_ctrl_dev
;
911 priv
->dev
= &pdev
->dev
;
912 dev_set_drvdata(priv
->dev
, priv
);
914 priv
->vbase
= ioremap(res
.start
, resource_size(&res
));
916 dev_err(dev
, "failed to map chip region\n");
921 mtd
= nand_to_mtd(&priv
->chip
);
922 mtd
->name
= kasprintf(GFP_KERNEL
, "%llx.flash", (u64
)res
.start
);
923 if (!nand_to_mtd(&priv
->chip
)->name
) {
928 ret
= fsl_elbc_chip_init(priv
);
932 priv
->chip
.controller
->ops
= &fsl_elbc_controller_ops
;
933 ret
= nand_scan(&priv
->chip
, 1);
937 /* First look for RedBoot table or partitions on the command
938 * line, these take precedence over device tree information */
939 ret
= mtd_device_parse_register(mtd
, part_probe_types
, NULL
, NULL
, 0);
943 pr_info("eLBC NAND device at 0x%llx, bank %d\n",
944 (unsigned long long)res
.start
, priv
->bank
);
949 nand_cleanup(&priv
->chip
);
951 fsl_elbc_chip_remove(priv
);
956 static int fsl_elbc_nand_remove(struct platform_device
*pdev
)
958 struct fsl_elbc_fcm_ctrl
*elbc_fcm_ctrl
= fsl_lbc_ctrl_dev
->nand
;
959 struct fsl_elbc_mtd
*priv
= dev_get_drvdata(&pdev
->dev
);
961 nand_release(&priv
->chip
);
962 fsl_elbc_chip_remove(priv
);
964 mutex_lock(&fsl_elbc_nand_mutex
);
965 elbc_fcm_ctrl
->counter
--;
966 if (!elbc_fcm_ctrl
->counter
) {
967 fsl_lbc_ctrl_dev
->nand
= NULL
;
968 kfree(elbc_fcm_ctrl
);
970 mutex_unlock(&fsl_elbc_nand_mutex
);
976 static const struct of_device_id fsl_elbc_nand_match
[] = {
977 { .compatible
= "fsl,elbc-fcm-nand", },
980 MODULE_DEVICE_TABLE(of
, fsl_elbc_nand_match
);
982 static struct platform_driver fsl_elbc_nand_driver
= {
984 .name
= "fsl,elbc-fcm-nand",
985 .of_match_table
= fsl_elbc_nand_match
,
987 .probe
= fsl_elbc_nand_probe
,
988 .remove
= fsl_elbc_nand_remove
,
991 module_platform_driver(fsl_elbc_nand_driver
);
993 MODULE_LICENSE("GPL");
994 MODULE_AUTHOR("Freescale");
995 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");