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Merge tag 'for-linus-5.0-rc6-tag' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-hirsute-kernel.git] / drivers / mtd / nand / raw / lpc32xx_mlc.c
1 /*
2 * Driver for NAND MLC Controller in LPC32xx
3 *
4 * Author: Roland Stigge <stigge@antcom.de>
5 *
6 * Copyright © 2011 WORK Microwave GmbH
7 * Copyright © 2011, 2012 Roland Stigge
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 *
20 * NAND Flash Controller Operation:
21 * - Read: Auto Decode
22 * - Write: Auto Encode
23 * - Tested Page Sizes: 2048, 4096
24 */
25
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/rawnand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/clk.h>
33 #include <linux/err.h>
34 #include <linux/delay.h>
35 #include <linux/completion.h>
36 #include <linux/interrupt.h>
37 #include <linux/of.h>
38 #include <linux/of_gpio.h>
39 #include <linux/mtd/lpc32xx_mlc.h>
40 #include <linux/io.h>
41 #include <linux/mm.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/dmaengine.h>
44 #include <linux/mtd/nand_ecc.h>
45
46 #define DRV_NAME "lpc32xx_mlc"
47
48 /**********************************************************************
49 * MLC NAND controller register offsets
50 **********************************************************************/
51
52 #define MLC_BUFF(x) (x + 0x00000)
53 #define MLC_DATA(x) (x + 0x08000)
54 #define MLC_CMD(x) (x + 0x10000)
55 #define MLC_ADDR(x) (x + 0x10004)
56 #define MLC_ECC_ENC_REG(x) (x + 0x10008)
57 #define MLC_ECC_DEC_REG(x) (x + 0x1000C)
58 #define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010)
59 #define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014)
60 #define MLC_RPR(x) (x + 0x10018)
61 #define MLC_WPR(x) (x + 0x1001C)
62 #define MLC_RUBP(x) (x + 0x10020)
63 #define MLC_ROBP(x) (x + 0x10024)
64 #define MLC_SW_WP_ADD_LOW(x) (x + 0x10028)
65 #define MLC_SW_WP_ADD_HIG(x) (x + 0x1002C)
66 #define MLC_ICR(x) (x + 0x10030)
67 #define MLC_TIME_REG(x) (x + 0x10034)
68 #define MLC_IRQ_MR(x) (x + 0x10038)
69 #define MLC_IRQ_SR(x) (x + 0x1003C)
70 #define MLC_LOCK_PR(x) (x + 0x10044)
71 #define MLC_ISR(x) (x + 0x10048)
72 #define MLC_CEH(x) (x + 0x1004C)
73
74 /**********************************************************************
75 * MLC_CMD bit definitions
76 **********************************************************************/
77 #define MLCCMD_RESET 0xFF
78
79 /**********************************************************************
80 * MLC_ICR bit definitions
81 **********************************************************************/
82 #define MLCICR_WPROT (1 << 3)
83 #define MLCICR_LARGEBLOCK (1 << 2)
84 #define MLCICR_LONGADDR (1 << 1)
85 #define MLCICR_16BIT (1 << 0) /* unsupported by LPC32x0! */
86
87 /**********************************************************************
88 * MLC_TIME_REG bit definitions
89 **********************************************************************/
90 #define MLCTIMEREG_TCEA_DELAY(n) (((n) & 0x03) << 24)
91 #define MLCTIMEREG_BUSY_DELAY(n) (((n) & 0x1F) << 19)
92 #define MLCTIMEREG_NAND_TA(n) (((n) & 0x07) << 16)
93 #define MLCTIMEREG_RD_HIGH(n) (((n) & 0x0F) << 12)
94 #define MLCTIMEREG_RD_LOW(n) (((n) & 0x0F) << 8)
95 #define MLCTIMEREG_WR_HIGH(n) (((n) & 0x0F) << 4)
96 #define MLCTIMEREG_WR_LOW(n) (((n) & 0x0F) << 0)
97
98 /**********************************************************************
99 * MLC_IRQ_MR and MLC_IRQ_SR bit definitions
100 **********************************************************************/
101 #define MLCIRQ_NAND_READY (1 << 5)
102 #define MLCIRQ_CONTROLLER_READY (1 << 4)
103 #define MLCIRQ_DECODE_FAILURE (1 << 3)
104 #define MLCIRQ_DECODE_ERROR (1 << 2)
105 #define MLCIRQ_ECC_READY (1 << 1)
106 #define MLCIRQ_WRPROT_FAULT (1 << 0)
107
108 /**********************************************************************
109 * MLC_LOCK_PR bit definitions
110 **********************************************************************/
111 #define MLCLOCKPR_MAGIC 0xA25E
112
113 /**********************************************************************
114 * MLC_ISR bit definitions
115 **********************************************************************/
116 #define MLCISR_DECODER_FAILURE (1 << 6)
117 #define MLCISR_ERRORS ((1 << 4) | (1 << 5))
118 #define MLCISR_ERRORS_DETECTED (1 << 3)
119 #define MLCISR_ECC_READY (1 << 2)
120 #define MLCISR_CONTROLLER_READY (1 << 1)
121 #define MLCISR_NAND_READY (1 << 0)
122
123 /**********************************************************************
124 * MLC_CEH bit definitions
125 **********************************************************************/
126 #define MLCCEH_NORMAL (1 << 0)
127
128 struct lpc32xx_nand_cfg_mlc {
129 uint32_t tcea_delay;
130 uint32_t busy_delay;
131 uint32_t nand_ta;
132 uint32_t rd_high;
133 uint32_t rd_low;
134 uint32_t wr_high;
135 uint32_t wr_low;
136 int wp_gpio;
137 struct mtd_partition *parts;
138 unsigned num_parts;
139 };
140
141 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
142 struct mtd_oob_region *oobregion)
143 {
144 struct nand_chip *nand_chip = mtd_to_nand(mtd);
145
146 if (section >= nand_chip->ecc.steps)
147 return -ERANGE;
148
149 oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes;
150 oobregion->length = nand_chip->ecc.bytes;
151
152 return 0;
153 }
154
155 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
156 struct mtd_oob_region *oobregion)
157 {
158 struct nand_chip *nand_chip = mtd_to_nand(mtd);
159
160 if (section >= nand_chip->ecc.steps)
161 return -ERANGE;
162
163 oobregion->offset = 16 * section;
164 oobregion->length = 16 - nand_chip->ecc.bytes;
165
166 return 0;
167 }
168
169 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
170 .ecc = lpc32xx_ooblayout_ecc,
171 .free = lpc32xx_ooblayout_free,
172 };
173
174 static struct nand_bbt_descr lpc32xx_nand_bbt = {
175 .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
176 NAND_BBT_WRITE,
177 .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 },
178 };
179
180 static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = {
181 .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
182 NAND_BBT_WRITE,
183 .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 },
184 };
185
186 struct lpc32xx_nand_host {
187 struct platform_device *pdev;
188 struct nand_chip nand_chip;
189 struct lpc32xx_mlc_platform_data *pdata;
190 struct clk *clk;
191 void __iomem *io_base;
192 int irq;
193 struct lpc32xx_nand_cfg_mlc *ncfg;
194 struct completion comp_nand;
195 struct completion comp_controller;
196 uint32_t llptr;
197 /*
198 * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer
199 */
200 dma_addr_t oob_buf_phy;
201 /*
202 * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer
203 */
204 uint8_t *oob_buf;
205 /* Physical address of DMA base address */
206 dma_addr_t io_base_phy;
207
208 struct completion comp_dma;
209 struct dma_chan *dma_chan;
210 struct dma_slave_config dma_slave_config;
211 struct scatterlist sgl;
212 uint8_t *dma_buf;
213 uint8_t *dummy_buf;
214 int mlcsubpages; /* number of 512bytes-subpages */
215 };
216
217 /*
218 * Activate/Deactivate DMA Operation:
219 *
220 * Using the PL080 DMA Controller for transferring the 512 byte subpages
221 * instead of doing readl() / writel() in a loop slows it down significantly.
222 * Measurements via getnstimeofday() upon 512 byte subpage reads reveal:
223 *
224 * - readl() of 128 x 32 bits in a loop: ~20us
225 * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us
226 * - DMA read of 512 bytes (32 bit, no bursts): ~100us
227 *
228 * This applies to the transfer itself. In the DMA case: only the
229 * wait_for_completion() (DMA setup _not_ included).
230 *
231 * Note that the 512 bytes subpage transfer is done directly from/to a
232 * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a
233 * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND
234 * controller transferring data between its internal buffer to/from the NAND
235 * chip.)
236 *
237 * Therefore, using the PL080 DMA is disabled by default, for now.
238 *
239 */
240 static int use_dma;
241
242 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
243 {
244 uint32_t clkrate, tmp;
245
246 /* Reset MLC controller */
247 writel(MLCCMD_RESET, MLC_CMD(host->io_base));
248 udelay(1000);
249
250 /* Get base clock for MLC block */
251 clkrate = clk_get_rate(host->clk);
252 if (clkrate == 0)
253 clkrate = 104000000;
254
255 /* Unlock MLC_ICR
256 * (among others, will be locked again automatically) */
257 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
258
259 /* Configure MLC Controller: Large Block, 5 Byte Address */
260 tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR;
261 writel(tmp, MLC_ICR(host->io_base));
262
263 /* Unlock MLC_TIME_REG
264 * (among others, will be locked again automatically) */
265 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
266
267 /* Compute clock setup values, see LPC and NAND manual */
268 tmp = 0;
269 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
270 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
271 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
272 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
273 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
274 tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
275 tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
276 writel(tmp, MLC_TIME_REG(host->io_base));
277
278 /* Enable IRQ for CONTROLLER_READY and NAND_READY */
279 writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY,
280 MLC_IRQ_MR(host->io_base));
281
282 /* Normal nCE operation: nCE controlled by controller */
283 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
284 }
285
286 /*
287 * Hardware specific access to control lines
288 */
289 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
290 unsigned int ctrl)
291 {
292 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
293
294 if (cmd != NAND_CMD_NONE) {
295 if (ctrl & NAND_CLE)
296 writel(cmd, MLC_CMD(host->io_base));
297 else
298 writel(cmd, MLC_ADDR(host->io_base));
299 }
300 }
301
302 /*
303 * Read Device Ready (NAND device _and_ controller ready)
304 */
305 static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip)
306 {
307 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
308
309 if ((readb(MLC_ISR(host->io_base)) &
310 (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) ==
311 (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY))
312 return 1;
313
314 return 0;
315 }
316
317 static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host)
318 {
319 uint8_t sr;
320
321 /* Clear interrupt flag by reading status */
322 sr = readb(MLC_IRQ_SR(host->io_base));
323 if (sr & MLCIRQ_NAND_READY)
324 complete(&host->comp_nand);
325 if (sr & MLCIRQ_CONTROLLER_READY)
326 complete(&host->comp_controller);
327
328 return IRQ_HANDLED;
329 }
330
331 static int lpc32xx_waitfunc_nand(struct nand_chip *chip)
332 {
333 struct mtd_info *mtd = nand_to_mtd(chip);
334 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
335
336 if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
337 goto exit;
338
339 wait_for_completion(&host->comp_nand);
340
341 while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
342 /* Seems to be delayed sometimes by controller */
343 dev_dbg(&mtd->dev, "Warning: NAND not ready.\n");
344 cpu_relax();
345 }
346
347 exit:
348 return NAND_STATUS_READY;
349 }
350
351 static int lpc32xx_waitfunc_controller(struct nand_chip *chip)
352 {
353 struct mtd_info *mtd = nand_to_mtd(chip);
354 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
355
356 if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
357 goto exit;
358
359 wait_for_completion(&host->comp_controller);
360
361 while (!(readb(MLC_ISR(host->io_base)) &
362 MLCISR_CONTROLLER_READY)) {
363 dev_dbg(&mtd->dev, "Warning: Controller not ready.\n");
364 cpu_relax();
365 }
366
367 exit:
368 return NAND_STATUS_READY;
369 }
370
371 static int lpc32xx_waitfunc(struct nand_chip *chip)
372 {
373 lpc32xx_waitfunc_nand(chip);
374 lpc32xx_waitfunc_controller(chip);
375
376 return NAND_STATUS_READY;
377 }
378
379 /*
380 * Enable NAND write protect
381 */
382 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
383 {
384 if (gpio_is_valid(host->ncfg->wp_gpio))
385 gpio_set_value(host->ncfg->wp_gpio, 0);
386 }
387
388 /*
389 * Disable NAND write protect
390 */
391 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
392 {
393 if (gpio_is_valid(host->ncfg->wp_gpio))
394 gpio_set_value(host->ncfg->wp_gpio, 1);
395 }
396
397 static void lpc32xx_dma_complete_func(void *completion)
398 {
399 complete(completion);
400 }
401
402 static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
403 enum dma_transfer_direction dir)
404 {
405 struct nand_chip *chip = mtd_to_nand(mtd);
406 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
407 struct dma_async_tx_descriptor *desc;
408 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
409 int res;
410
411 sg_init_one(&host->sgl, mem, len);
412
413 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
414 DMA_BIDIRECTIONAL);
415 if (res != 1) {
416 dev_err(mtd->dev.parent, "Failed to map sg list\n");
417 return -ENXIO;
418 }
419 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
420 flags);
421 if (!desc) {
422 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
423 goto out1;
424 }
425
426 init_completion(&host->comp_dma);
427 desc->callback = lpc32xx_dma_complete_func;
428 desc->callback_param = &host->comp_dma;
429
430 dmaengine_submit(desc);
431 dma_async_issue_pending(host->dma_chan);
432
433 wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
434
435 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
436 DMA_BIDIRECTIONAL);
437 return 0;
438 out1:
439 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
440 DMA_BIDIRECTIONAL);
441 return -ENXIO;
442 }
443
444 static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,
445 int oob_required, int page)
446 {
447 struct mtd_info *mtd = nand_to_mtd(chip);
448 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
449 int i, j;
450 uint8_t *oobbuf = chip->oob_poi;
451 uint32_t mlc_isr;
452 int res;
453 uint8_t *dma_buf;
454 bool dma_mapped;
455
456 if ((void *)buf <= high_memory) {
457 dma_buf = buf;
458 dma_mapped = true;
459 } else {
460 dma_buf = host->dma_buf;
461 dma_mapped = false;
462 }
463
464 /* Writing Command and Address */
465 nand_read_page_op(chip, page, 0, NULL, 0);
466
467 /* For all sub-pages */
468 for (i = 0; i < host->mlcsubpages; i++) {
469 /* Start Auto Decode Command */
470 writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
471
472 /* Wait for Controller Ready */
473 lpc32xx_waitfunc_controller(chip);
474
475 /* Check ECC Error status */
476 mlc_isr = readl(MLC_ISR(host->io_base));
477 if (mlc_isr & MLCISR_DECODER_FAILURE) {
478 mtd->ecc_stats.failed++;
479 dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__);
480 } else if (mlc_isr & MLCISR_ERRORS_DETECTED) {
481 mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1;
482 }
483
484 /* Read 512 + 16 Bytes */
485 if (use_dma) {
486 res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
487 DMA_DEV_TO_MEM);
488 if (res)
489 return res;
490 } else {
491 for (j = 0; j < (512 >> 2); j++) {
492 *((uint32_t *)(buf)) =
493 readl(MLC_BUFF(host->io_base));
494 buf += 4;
495 }
496 }
497 for (j = 0; j < (16 >> 2); j++) {
498 *((uint32_t *)(oobbuf)) =
499 readl(MLC_BUFF(host->io_base));
500 oobbuf += 4;
501 }
502 }
503
504 if (use_dma && !dma_mapped)
505 memcpy(buf, dma_buf, mtd->writesize);
506
507 return 0;
508 }
509
510 static int lpc32xx_write_page_lowlevel(struct nand_chip *chip,
511 const uint8_t *buf, int oob_required,
512 int page)
513 {
514 struct mtd_info *mtd = nand_to_mtd(chip);
515 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
516 const uint8_t *oobbuf = chip->oob_poi;
517 uint8_t *dma_buf = (uint8_t *)buf;
518 int res;
519 int i, j;
520
521 if (use_dma && (void *)buf >= high_memory) {
522 dma_buf = host->dma_buf;
523 memcpy(dma_buf, buf, mtd->writesize);
524 }
525
526 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
527
528 for (i = 0; i < host->mlcsubpages; i++) {
529 /* Start Encode */
530 writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
531
532 /* Write 512 + 6 Bytes to Buffer */
533 if (use_dma) {
534 res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
535 DMA_MEM_TO_DEV);
536 if (res)
537 return res;
538 } else {
539 for (j = 0; j < (512 >> 2); j++) {
540 writel(*((uint32_t *)(buf)),
541 MLC_BUFF(host->io_base));
542 buf += 4;
543 }
544 }
545 writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
546 oobbuf += 4;
547 writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
548 oobbuf += 12;
549
550 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */
551 writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
552
553 /* Wait for Controller Ready */
554 lpc32xx_waitfunc_controller(chip);
555 }
556
557 return nand_prog_page_end_op(chip);
558 }
559
560 static int lpc32xx_read_oob(struct nand_chip *chip, int page)
561 {
562 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
563
564 /* Read whole page - necessary with MLC controller! */
565 lpc32xx_read_page(chip, host->dummy_buf, 1, page);
566
567 return 0;
568 }
569
570 static int lpc32xx_write_oob(struct nand_chip *chip, int page)
571 {
572 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */
573 return 0;
574 }
575
576 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
577 static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode)
578 {
579 /* Always enabled! */
580 }
581
582 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
583 {
584 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
585 dma_cap_mask_t mask;
586
587 if (!host->pdata || !host->pdata->dma_filter) {
588 dev_err(mtd->dev.parent, "no DMA platform data\n");
589 return -ENOENT;
590 }
591
592 dma_cap_zero(mask);
593 dma_cap_set(DMA_SLAVE, mask);
594 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
595 "nand-mlc");
596 if (!host->dma_chan) {
597 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
598 return -EBUSY;
599 }
600
601 /*
602 * Set direction to a sensible value even if the dmaengine driver
603 * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x
604 * driver criticizes it as "alien transfer direction".
605 */
606 host->dma_slave_config.direction = DMA_DEV_TO_MEM;
607 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
608 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
609 host->dma_slave_config.src_maxburst = 128;
610 host->dma_slave_config.dst_maxburst = 128;
611 /* DMA controller does flow control: */
612 host->dma_slave_config.device_fc = false;
613 host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
614 host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
615 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
616 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
617 goto out1;
618 }
619
620 return 0;
621 out1:
622 dma_release_channel(host->dma_chan);
623 return -ENXIO;
624 }
625
626 static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
627 {
628 struct lpc32xx_nand_cfg_mlc *ncfg;
629 struct device_node *np = dev->of_node;
630
631 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
632 if (!ncfg)
633 return NULL;
634
635 of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay);
636 of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay);
637 of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta);
638 of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high);
639 of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low);
640 of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high);
641 of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low);
642
643 if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta ||
644 !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high ||
645 !ncfg->wr_low) {
646 dev_err(dev, "chip parameters not specified correctly\n");
647 return NULL;
648 }
649
650 ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
651
652 return ncfg;
653 }
654
655 static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
656 {
657 struct mtd_info *mtd = nand_to_mtd(chip);
658 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
659 struct device *dev = &host->pdev->dev;
660
661 host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
662 if (!host->dma_buf)
663 return -ENOMEM;
664
665 host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
666 if (!host->dummy_buf)
667 return -ENOMEM;
668
669 chip->ecc.mode = NAND_ECC_HW;
670 chip->ecc.size = 512;
671 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
672 host->mlcsubpages = mtd->writesize / 512;
673
674 return 0;
675 }
676
677 static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
678 .attach_chip = lpc32xx_nand_attach_chip,
679 };
680
681 /*
682 * Probe for NAND controller
683 */
684 static int lpc32xx_nand_probe(struct platform_device *pdev)
685 {
686 struct lpc32xx_nand_host *host;
687 struct mtd_info *mtd;
688 struct nand_chip *nand_chip;
689 struct resource *rc;
690 int res;
691
692 /* Allocate memory for the device structure (and zero it) */
693 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
694 if (!host)
695 return -ENOMEM;
696
697 host->pdev = pdev;
698
699 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
700 host->io_base = devm_ioremap_resource(&pdev->dev, rc);
701 if (IS_ERR(host->io_base))
702 return PTR_ERR(host->io_base);
703
704 host->io_base_phy = rc->start;
705
706 nand_chip = &host->nand_chip;
707 mtd = nand_to_mtd(nand_chip);
708 if (pdev->dev.of_node)
709 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
710 if (!host->ncfg) {
711 dev_err(&pdev->dev,
712 "Missing or bad NAND config from device tree\n");
713 return -ENOENT;
714 }
715 if (host->ncfg->wp_gpio == -EPROBE_DEFER)
716 return -EPROBE_DEFER;
717 if (gpio_is_valid(host->ncfg->wp_gpio) &&
718 gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
719 dev_err(&pdev->dev, "GPIO not available\n");
720 return -EBUSY;
721 }
722 lpc32xx_wp_disable(host);
723
724 host->pdata = dev_get_platdata(&pdev->dev);
725
726 /* link the private data structures */
727 nand_set_controller_data(nand_chip, host);
728 nand_set_flash_node(nand_chip, pdev->dev.of_node);
729 mtd->dev.parent = &pdev->dev;
730
731 /* Get NAND clock */
732 host->clk = clk_get(&pdev->dev, NULL);
733 if (IS_ERR(host->clk)) {
734 dev_err(&pdev->dev, "Clock initialization failure\n");
735 res = -ENOENT;
736 goto free_gpio;
737 }
738 res = clk_prepare_enable(host->clk);
739 if (res)
740 goto put_clk;
741
742 nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
743 nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
744 nand_chip->legacy.chip_delay = 25; /* us */
745 nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
746 nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
747
748 /* Init NAND controller */
749 lpc32xx_nand_setup(host);
750
751 platform_set_drvdata(pdev, host);
752
753 /* Initialize function pointers */
754 nand_chip->ecc.hwctl = lpc32xx_ecc_enable;
755 nand_chip->ecc.read_page_raw = lpc32xx_read_page;
756 nand_chip->ecc.read_page = lpc32xx_read_page;
757 nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
758 nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel;
759 nand_chip->ecc.write_oob = lpc32xx_write_oob;
760 nand_chip->ecc.read_oob = lpc32xx_read_oob;
761 nand_chip->ecc.strength = 4;
762 nand_chip->ecc.bytes = 10;
763 nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
764
765 nand_chip->options = NAND_NO_SUBPAGE_WRITE;
766 nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
767 nand_chip->bbt_td = &lpc32xx_nand_bbt;
768 nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
769
770 if (use_dma) {
771 res = lpc32xx_dma_setup(host);
772 if (res) {
773 res = -EIO;
774 goto unprepare_clk;
775 }
776 }
777
778 /* initially clear interrupt status */
779 readb(MLC_IRQ_SR(host->io_base));
780
781 init_completion(&host->comp_nand);
782 init_completion(&host->comp_controller);
783
784 host->irq = platform_get_irq(pdev, 0);
785 if (host->irq < 0) {
786 dev_err(&pdev->dev, "failed to get platform irq\n");
787 res = -EINVAL;
788 goto release_dma_chan;
789 }
790
791 if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq,
792 IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
793 dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
794 res = -ENXIO;
795 goto release_dma_chan;
796 }
797
798 /*
799 * Scan to find existence of the device and get the type of NAND device:
800 * SMALL block or LARGE block.
801 */
802 nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
803 res = nand_scan(nand_chip, 1);
804 if (res)
805 goto free_irq;
806
807 mtd->name = DRV_NAME;
808
809 res = mtd_device_register(mtd, host->ncfg->parts,
810 host->ncfg->num_parts);
811 if (res)
812 goto cleanup_nand;
813
814 return 0;
815
816 cleanup_nand:
817 nand_cleanup(nand_chip);
818 free_irq:
819 free_irq(host->irq, host);
820 release_dma_chan:
821 if (use_dma)
822 dma_release_channel(host->dma_chan);
823 unprepare_clk:
824 clk_disable_unprepare(host->clk);
825 put_clk:
826 clk_put(host->clk);
827 free_gpio:
828 lpc32xx_wp_enable(host);
829 gpio_free(host->ncfg->wp_gpio);
830
831 return res;
832 }
833
834 /*
835 * Remove NAND device
836 */
837 static int lpc32xx_nand_remove(struct platform_device *pdev)
838 {
839 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
840
841 nand_release(&host->nand_chip);
842 free_irq(host->irq, host);
843 if (use_dma)
844 dma_release_channel(host->dma_chan);
845
846 clk_disable_unprepare(host->clk);
847 clk_put(host->clk);
848
849 lpc32xx_wp_enable(host);
850 gpio_free(host->ncfg->wp_gpio);
851
852 return 0;
853 }
854
855 #ifdef CONFIG_PM
856 static int lpc32xx_nand_resume(struct platform_device *pdev)
857 {
858 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
859 int ret;
860
861 /* Re-enable NAND clock */
862 ret = clk_prepare_enable(host->clk);
863 if (ret)
864 return ret;
865
866 /* Fresh init of NAND controller */
867 lpc32xx_nand_setup(host);
868
869 /* Disable write protect */
870 lpc32xx_wp_disable(host);
871
872 return 0;
873 }
874
875 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
876 {
877 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
878
879 /* Enable write protect for safety */
880 lpc32xx_wp_enable(host);
881
882 /* Disable clock */
883 clk_disable_unprepare(host->clk);
884 return 0;
885 }
886
887 #else
888 #define lpc32xx_nand_resume NULL
889 #define lpc32xx_nand_suspend NULL
890 #endif
891
892 static const struct of_device_id lpc32xx_nand_match[] = {
893 { .compatible = "nxp,lpc3220-mlc" },
894 { /* sentinel */ },
895 };
896 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
897
898 static struct platform_driver lpc32xx_nand_driver = {
899 .probe = lpc32xx_nand_probe,
900 .remove = lpc32xx_nand_remove,
901 .resume = lpc32xx_nand_resume,
902 .suspend = lpc32xx_nand_suspend,
903 .driver = {
904 .name = DRV_NAME,
905 .of_match_table = lpc32xx_nand_match,
906 },
907 };
908
909 module_platform_driver(lpc32xx_nand_driver);
910
911 MODULE_LICENSE("GPL");
912 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
913 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller");
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