drivers/mtd/nand/raw/nand_amd.c

   1 /*
   2  * Copyright (C) 2017 Free Electrons
   3  * Copyright (C) 2017 NextThing Co
   4  *
   5  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include "internals.h"
  19
  20 static void amd_nand_decode_id(struct nand_chip *chip)
  21 {
  22         struct mtd_info *mtd = nand_to_mtd(chip);
  23         struct nand_memory_organization *memorg;
  24
  25         memorg = nanddev_get_memorg(&chip->base);
  26
  27         nand_decode_ext_id(chip);
  28
  29         /*
  30          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
  31          * some Spansion chips have erasesize that conflicts with size
  32          * listed in nand_ids table.
  33          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
  34          */
  35         if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 &&
  36             chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 &&
  37             memorg->pagesize == 512) {
  38                 memorg->pages_per_eraseblock = 256;
  39                 memorg->pages_per_eraseblock <<= ((chip->id.data[3] & 0x03) << 1);
  40                 mtd->erasesize = memorg->pages_per_eraseblock *
  41                                  memorg->pagesize;
  42         }
  43 }
  44
  45 static int amd_nand_init(struct nand_chip *chip)
  46 {
  47         if (nand_is_slc(chip))
  48                 /*
  49                  * According to the datasheet of some Cypress SLC NANDs,
  50                  * the bad block markers can be in the first, second or last
  51                  * page of a block. So let's check all three locations.
  52                  */
  53                 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE |
  54                                  NAND_BBM_LASTPAGE;
  55
  56         return 0;
  57 }
  58
  59 const struct nand_manufacturer_ops amd_nand_manuf_ops = {
  60         .detect = amd_nand_decode_id,
  61         .init = amd_nand_init,
  62 };