2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/jiffies.h>
19 #include <linux/sched.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/rawnand.h>
22 #include <linux/mtd/partitions.h>
23 #include <linux/omap-dma.h>
25 #include <linux/slab.h>
27 #include <linux/of_device.h>
29 #include <linux/mtd/nand_bch.h>
30 #include <linux/platform_data/elm.h>
32 #include <linux/omap-gpmc.h>
33 #include <linux/platform_data/mtd-nand-omap2.h>
35 #define DRIVER_NAME "omap2-nand"
36 #define OMAP_NAND_TIMEOUT_MS 5000
38 #define NAND_Ecc_P1e (1 << 0)
39 #define NAND_Ecc_P2e (1 << 1)
40 #define NAND_Ecc_P4e (1 << 2)
41 #define NAND_Ecc_P8e (1 << 3)
42 #define NAND_Ecc_P16e (1 << 4)
43 #define NAND_Ecc_P32e (1 << 5)
44 #define NAND_Ecc_P64e (1 << 6)
45 #define NAND_Ecc_P128e (1 << 7)
46 #define NAND_Ecc_P256e (1 << 8)
47 #define NAND_Ecc_P512e (1 << 9)
48 #define NAND_Ecc_P1024e (1 << 10)
49 #define NAND_Ecc_P2048e (1 << 11)
51 #define NAND_Ecc_P1o (1 << 16)
52 #define NAND_Ecc_P2o (1 << 17)
53 #define NAND_Ecc_P4o (1 << 18)
54 #define NAND_Ecc_P8o (1 << 19)
55 #define NAND_Ecc_P16o (1 << 20)
56 #define NAND_Ecc_P32o (1 << 21)
57 #define NAND_Ecc_P64o (1 << 22)
58 #define NAND_Ecc_P128o (1 << 23)
59 #define NAND_Ecc_P256o (1 << 24)
60 #define NAND_Ecc_P512o (1 << 25)
61 #define NAND_Ecc_P1024o (1 << 26)
62 #define NAND_Ecc_P2048o (1 << 27)
64 #define TF(value) (value ? 1 : 0)
66 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
67 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
68 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
69 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
70 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
71 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
72 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
73 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
75 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
76 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
77 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
78 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
79 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
80 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
81 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
82 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
84 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
85 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
86 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
87 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
88 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
89 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
90 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
91 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
93 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
94 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
95 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
96 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
97 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
98 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
99 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
100 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
102 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
103 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
105 #define PREFETCH_CONFIG1_CS_SHIFT 24
106 #define ECC_CONFIG_CS_SHIFT 1
108 #define ENABLE_PREFETCH (0x1 << 7)
109 #define DMA_MPU_MODE_SHIFT 2
110 #define ECCSIZE0_SHIFT 12
111 #define ECCSIZE1_SHIFT 22
112 #define ECC1RESULTSIZE 0x1
113 #define ECCCLEAR 0x100
115 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
116 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
117 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
118 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
119 #define STATUS_BUFF_EMPTY 0x00000001
121 #define SECTOR_BYTES 512
122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
123 #define BCH4_BIT_PAD 4
125 /* GPMC ecc engine settings for read */
126 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
127 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
128 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
129 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
130 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
132 /* GPMC ecc engine settings for write */
133 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
134 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
135 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
137 #define BADBLOCK_MARKER_LENGTH 2
139 static u_char bch16_vector
[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
140 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
141 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
143 static u_char bch8_vector
[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
144 0xac, 0x6b, 0xff, 0x99, 0x7b};
145 static u_char bch4_vector
[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
147 struct omap_nand_info
{
148 struct nand_chip nand
;
149 struct platform_device
*pdev
;
153 enum nand_io xfer_type
;
155 enum omap_ecc ecc_opt
;
156 struct device_node
*elm_of_node
;
158 unsigned long phys_base
;
159 struct completion comp
;
160 struct dma_chan
*dma
;
164 OMAP_NAND_IO_READ
= 0, /* read */
165 OMAP_NAND_IO_WRITE
, /* write */
169 /* Interface to GPMC */
170 struct gpmc_nand_regs reg
;
171 struct gpmc_nand_ops
*ops
;
173 /* fields specific for BCHx_HW ECC scheme */
174 struct device
*elm_dev
;
175 /* NAND ready gpio */
176 struct gpio_desc
*ready_gpiod
;
179 static inline struct omap_nand_info
*mtd_to_omap(struct mtd_info
*mtd
)
181 return container_of(mtd_to_nand(mtd
), struct omap_nand_info
, nand
);
185 * omap_prefetch_enable - configures and starts prefetch transfer
186 * @cs: cs (chip select) number
187 * @fifo_th: fifo threshold to be used for read/ write
188 * @dma_mode: dma mode enable (1) or disable (0)
189 * @u32_count: number of bytes to be transferred
190 * @is_write: prefetch read(0) or write post(1) mode
192 static int omap_prefetch_enable(int cs
, int fifo_th
, int dma_mode
,
193 unsigned int u32_count
, int is_write
, struct omap_nand_info
*info
)
197 if (fifo_th
> PREFETCH_FIFOTHRESHOLD_MAX
)
200 if (readl(info
->reg
.gpmc_prefetch_control
))
203 /* Set the amount of bytes to be prefetched */
204 writel(u32_count
, info
->reg
.gpmc_prefetch_config2
);
206 /* Set dma/mpu mode, the prefetch read / post write and
207 * enable the engine. Set which cs is has requested for.
209 val
= ((cs
<< PREFETCH_CONFIG1_CS_SHIFT
) |
210 PREFETCH_FIFOTHRESHOLD(fifo_th
) | ENABLE_PREFETCH
|
211 (dma_mode
<< DMA_MPU_MODE_SHIFT
) | (is_write
& 0x1));
212 writel(val
, info
->reg
.gpmc_prefetch_config1
);
214 /* Start the prefetch engine */
215 writel(0x1, info
->reg
.gpmc_prefetch_control
);
221 * omap_prefetch_reset - disables and stops the prefetch engine
223 static int omap_prefetch_reset(int cs
, struct omap_nand_info
*info
)
227 /* check if the same module/cs is trying to reset */
228 config1
= readl(info
->reg
.gpmc_prefetch_config1
);
229 if (((config1
>> PREFETCH_CONFIG1_CS_SHIFT
) & CS_MASK
) != cs
)
232 /* Stop the PFPW engine */
233 writel(0x0, info
->reg
.gpmc_prefetch_control
);
235 /* Reset/disable the PFPW engine */
236 writel(0x0, info
->reg
.gpmc_prefetch_config1
);
242 * omap_hwcontrol - hardware specific access to control-lines
243 * @chip: NAND chip object
244 * @cmd: command to device
246 * NAND_NCE: bit 0 -> don't care
247 * NAND_CLE: bit 1 -> Command Latch
248 * NAND_ALE: bit 2 -> Address Latch
250 * NOTE: boards may use different bits for these!!
252 static void omap_hwcontrol(struct nand_chip
*chip
, int cmd
, unsigned int ctrl
)
254 struct omap_nand_info
*info
= mtd_to_omap(nand_to_mtd(chip
));
256 if (cmd
!= NAND_CMD_NONE
) {
258 writeb(cmd
, info
->reg
.gpmc_nand_command
);
260 else if (ctrl
& NAND_ALE
)
261 writeb(cmd
, info
->reg
.gpmc_nand_address
);
264 writeb(cmd
, info
->reg
.gpmc_nand_data
);
269 * omap_read_buf8 - read data from NAND controller into buffer
270 * @mtd: MTD device structure
271 * @buf: buffer to store date
272 * @len: number of bytes to read
274 static void omap_read_buf8(struct mtd_info
*mtd
, u_char
*buf
, int len
)
276 struct nand_chip
*nand
= mtd_to_nand(mtd
);
278 ioread8_rep(nand
->legacy
.IO_ADDR_R
, buf
, len
);
282 * omap_write_buf8 - write buffer to NAND controller
283 * @mtd: MTD device structure
285 * @len: number of bytes to write
287 static void omap_write_buf8(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
289 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
290 u_char
*p
= (u_char
*)buf
;
294 iowrite8(*p
++, info
->nand
.legacy
.IO_ADDR_W
);
295 /* wait until buffer is available for write */
297 status
= info
->ops
->nand_writebuffer_empty();
303 * omap_read_buf16 - read data from NAND controller into buffer
304 * @mtd: MTD device structure
305 * @buf: buffer to store date
306 * @len: number of bytes to read
308 static void omap_read_buf16(struct mtd_info
*mtd
, u_char
*buf
, int len
)
310 struct nand_chip
*nand
= mtd_to_nand(mtd
);
312 ioread16_rep(nand
->legacy
.IO_ADDR_R
, buf
, len
/ 2);
316 * omap_write_buf16 - write buffer to NAND controller
317 * @mtd: MTD device structure
319 * @len: number of bytes to write
321 static void omap_write_buf16(struct mtd_info
*mtd
, const u_char
* buf
, int len
)
323 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
324 u16
*p
= (u16
*) buf
;
326 /* FIXME try bursts of writesw() or DMA ... */
330 iowrite16(*p
++, info
->nand
.legacy
.IO_ADDR_W
);
331 /* wait until buffer is available for write */
333 status
= info
->ops
->nand_writebuffer_empty();
339 * omap_read_buf_pref - read data from NAND controller into buffer
340 * @chip: NAND chip object
341 * @buf: buffer to store date
342 * @len: number of bytes to read
344 static void omap_read_buf_pref(struct nand_chip
*chip
, u_char
*buf
, int len
)
346 struct mtd_info
*mtd
= nand_to_mtd(chip
);
347 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
348 uint32_t r_count
= 0;
352 /* take care of subpage reads */
354 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
355 omap_read_buf16(mtd
, buf
, len
% 4);
357 omap_read_buf8(mtd
, buf
, len
% 4);
358 p
= (u32
*) (buf
+ len
% 4);
362 /* configure and start prefetch transfer */
363 ret
= omap_prefetch_enable(info
->gpmc_cs
,
364 PREFETCH_FIFOTHRESHOLD_MAX
, 0x0, len
, 0x0, info
);
366 /* PFPW engine is busy, use cpu copy method */
367 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
368 omap_read_buf16(mtd
, (u_char
*)p
, len
);
370 omap_read_buf8(mtd
, (u_char
*)p
, len
);
373 r_count
= readl(info
->reg
.gpmc_prefetch_status
);
374 r_count
= PREFETCH_STATUS_FIFO_CNT(r_count
);
375 r_count
= r_count
>> 2;
376 ioread32_rep(info
->nand
.legacy
.IO_ADDR_R
, p
, r_count
);
380 /* disable and stop the PFPW engine */
381 omap_prefetch_reset(info
->gpmc_cs
, info
);
386 * omap_write_buf_pref - write buffer to NAND controller
387 * @chip: NAND chip object
389 * @len: number of bytes to write
391 static void omap_write_buf_pref(struct nand_chip
*chip
, const u_char
*buf
,
394 struct mtd_info
*mtd
= nand_to_mtd(chip
);
395 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
396 uint32_t w_count
= 0;
399 unsigned long tim
, limit
;
402 /* take care of subpage writes */
404 writeb(*buf
, info
->nand
.legacy
.IO_ADDR_W
);
405 p
= (u16
*)(buf
+ 1);
409 /* configure and start prefetch transfer */
410 ret
= omap_prefetch_enable(info
->gpmc_cs
,
411 PREFETCH_FIFOTHRESHOLD_MAX
, 0x0, len
, 0x1, info
);
413 /* PFPW engine is busy, use cpu copy method */
414 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
415 omap_write_buf16(mtd
, (u_char
*)p
, len
);
417 omap_write_buf8(mtd
, (u_char
*)p
, len
);
420 w_count
= readl(info
->reg
.gpmc_prefetch_status
);
421 w_count
= PREFETCH_STATUS_FIFO_CNT(w_count
);
422 w_count
= w_count
>> 1;
423 for (i
= 0; (i
< w_count
) && len
; i
++, len
-= 2)
424 iowrite16(*p
++, info
->nand
.legacy
.IO_ADDR_W
);
426 /* wait for data to flushed-out before reset the prefetch */
428 limit
= (loops_per_jiffy
*
429 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
432 val
= readl(info
->reg
.gpmc_prefetch_status
);
433 val
= PREFETCH_STATUS_COUNT(val
);
434 } while (val
&& (tim
++ < limit
));
436 /* disable and stop the PFPW engine */
437 omap_prefetch_reset(info
->gpmc_cs
, info
);
442 * omap_nand_dma_callback: callback on the completion of dma transfer
443 * @data: pointer to completion data structure
445 static void omap_nand_dma_callback(void *data
)
447 complete((struct completion
*) data
);
451 * omap_nand_dma_transfer: configure and start dma transfer
452 * @mtd: MTD device structure
453 * @addr: virtual address in RAM of source/destination
454 * @len: number of data bytes to be transferred
455 * @is_write: flag for read/write operation
457 static inline int omap_nand_dma_transfer(struct mtd_info
*mtd
, void *addr
,
458 unsigned int len
, int is_write
)
460 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
461 struct dma_async_tx_descriptor
*tx
;
462 enum dma_data_direction dir
= is_write
? DMA_TO_DEVICE
:
464 struct scatterlist sg
;
465 unsigned long tim
, limit
;
470 if (!virt_addr_valid(addr
))
473 sg_init_one(&sg
, addr
, len
);
474 n
= dma_map_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
476 dev_err(&info
->pdev
->dev
,
477 "Couldn't DMA map a %d byte buffer\n", len
);
481 tx
= dmaengine_prep_slave_sg(info
->dma
, &sg
, n
,
482 is_write
? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
483 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
487 tx
->callback
= omap_nand_dma_callback
;
488 tx
->callback_param
= &info
->comp
;
489 dmaengine_submit(tx
);
491 init_completion(&info
->comp
);
493 /* setup and start DMA using dma_addr */
494 dma_async_issue_pending(info
->dma
);
496 /* configure and start prefetch transfer */
497 ret
= omap_prefetch_enable(info
->gpmc_cs
,
498 PREFETCH_FIFOTHRESHOLD_MAX
, 0x1, len
, is_write
, info
);
500 /* PFPW engine is busy, use cpu copy method */
503 wait_for_completion(&info
->comp
);
505 limit
= (loops_per_jiffy
* msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
509 val
= readl(info
->reg
.gpmc_prefetch_status
);
510 val
= PREFETCH_STATUS_COUNT(val
);
511 } while (val
&& (tim
++ < limit
));
513 /* disable and stop the PFPW engine */
514 omap_prefetch_reset(info
->gpmc_cs
, info
);
516 dma_unmap_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
520 dma_unmap_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
522 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
523 is_write
== 0 ? omap_read_buf16(mtd
, (u_char
*) addr
, len
)
524 : omap_write_buf16(mtd
, (u_char
*) addr
, len
);
526 is_write
== 0 ? omap_read_buf8(mtd
, (u_char
*) addr
, len
)
527 : omap_write_buf8(mtd
, (u_char
*) addr
, len
);
532 * omap_read_buf_dma_pref - read data from NAND controller into buffer
533 * @chip: NAND chip object
534 * @buf: buffer to store date
535 * @len: number of bytes to read
537 static void omap_read_buf_dma_pref(struct nand_chip
*chip
, u_char
*buf
,
540 struct mtd_info
*mtd
= nand_to_mtd(chip
);
542 if (len
<= mtd
->oobsize
)
543 omap_read_buf_pref(chip
, buf
, len
);
545 /* start transfer in DMA mode */
546 omap_nand_dma_transfer(mtd
, buf
, len
, 0x0);
550 * omap_write_buf_dma_pref - write buffer to NAND controller
551 * @chip: NAND chip object
553 * @len: number of bytes to write
555 static void omap_write_buf_dma_pref(struct nand_chip
*chip
, const u_char
*buf
,
558 struct mtd_info
*mtd
= nand_to_mtd(chip
);
560 if (len
<= mtd
->oobsize
)
561 omap_write_buf_pref(chip
, buf
, len
);
563 /* start transfer in DMA mode */
564 omap_nand_dma_transfer(mtd
, (u_char
*)buf
, len
, 0x1);
568 * omap_nand_irq - GPMC irq handler
569 * @this_irq: gpmc irq number
570 * @dev: omap_nand_info structure pointer is passed here
572 static irqreturn_t
omap_nand_irq(int this_irq
, void *dev
)
574 struct omap_nand_info
*info
= (struct omap_nand_info
*) dev
;
577 bytes
= readl(info
->reg
.gpmc_prefetch_status
);
578 bytes
= PREFETCH_STATUS_FIFO_CNT(bytes
);
579 bytes
= bytes
& 0xFFFC; /* io in multiple of 4 bytes */
580 if (info
->iomode
== OMAP_NAND_IO_WRITE
) { /* checks for write io */
581 if (this_irq
== info
->gpmc_irq_count
)
584 if (info
->buf_len
&& (info
->buf_len
< bytes
))
585 bytes
= info
->buf_len
;
586 else if (!info
->buf_len
)
588 iowrite32_rep(info
->nand
.legacy
.IO_ADDR_W
, (u32
*)info
->buf
,
590 info
->buf
= info
->buf
+ bytes
;
591 info
->buf_len
-= bytes
;
594 ioread32_rep(info
->nand
.legacy
.IO_ADDR_R
, (u32
*)info
->buf
,
596 info
->buf
= info
->buf
+ bytes
;
598 if (this_irq
== info
->gpmc_irq_count
)
605 complete(&info
->comp
);
607 disable_irq_nosync(info
->gpmc_irq_fifo
);
608 disable_irq_nosync(info
->gpmc_irq_count
);
614 * omap_read_buf_irq_pref - read data from NAND controller into buffer
615 * @chip: NAND chip object
616 * @buf: buffer to store date
617 * @len: number of bytes to read
619 static void omap_read_buf_irq_pref(struct nand_chip
*chip
, u_char
*buf
,
622 struct mtd_info
*mtd
= nand_to_mtd(chip
);
623 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
626 if (len
<= mtd
->oobsize
) {
627 omap_read_buf_pref(chip
, buf
, len
);
631 info
->iomode
= OMAP_NAND_IO_READ
;
633 init_completion(&info
->comp
);
635 /* configure and start prefetch transfer */
636 ret
= omap_prefetch_enable(info
->gpmc_cs
,
637 PREFETCH_FIFOTHRESHOLD_MAX
/2, 0x0, len
, 0x0, info
);
639 /* PFPW engine is busy, use cpu copy method */
644 enable_irq(info
->gpmc_irq_count
);
645 enable_irq(info
->gpmc_irq_fifo
);
647 /* waiting for read to complete */
648 wait_for_completion(&info
->comp
);
650 /* disable and stop the PFPW engine */
651 omap_prefetch_reset(info
->gpmc_cs
, info
);
655 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
656 omap_read_buf16(mtd
, buf
, len
);
658 omap_read_buf8(mtd
, buf
, len
);
662 * omap_write_buf_irq_pref - write buffer to NAND controller
663 * @chip: NAND chip object
665 * @len: number of bytes to write
667 static void omap_write_buf_irq_pref(struct nand_chip
*chip
, const u_char
*buf
,
670 struct mtd_info
*mtd
= nand_to_mtd(chip
);
671 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
673 unsigned long tim
, limit
;
676 if (len
<= mtd
->oobsize
) {
677 omap_write_buf_pref(chip
, buf
, len
);
681 info
->iomode
= OMAP_NAND_IO_WRITE
;
682 info
->buf
= (u_char
*) buf
;
683 init_completion(&info
->comp
);
685 /* configure and start prefetch transfer : size=24 */
686 ret
= omap_prefetch_enable(info
->gpmc_cs
,
687 (PREFETCH_FIFOTHRESHOLD_MAX
* 3) / 8, 0x0, len
, 0x1, info
);
689 /* PFPW engine is busy, use cpu copy method */
694 enable_irq(info
->gpmc_irq_count
);
695 enable_irq(info
->gpmc_irq_fifo
);
697 /* waiting for write to complete */
698 wait_for_completion(&info
->comp
);
700 /* wait for data to flushed-out before reset the prefetch */
702 limit
= (loops_per_jiffy
* msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
704 val
= readl(info
->reg
.gpmc_prefetch_status
);
705 val
= PREFETCH_STATUS_COUNT(val
);
707 } while (val
&& (tim
++ < limit
));
709 /* disable and stop the PFPW engine */
710 omap_prefetch_reset(info
->gpmc_cs
, info
);
714 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
715 omap_write_buf16(mtd
, buf
, len
);
717 omap_write_buf8(mtd
, buf
, len
);
721 * gen_true_ecc - This function will generate true ECC value
722 * @ecc_buf: buffer to store ecc code
724 * This generated true ECC value can be used when correcting
725 * data read from NAND flash memory core
727 static void gen_true_ecc(u8
*ecc_buf
)
729 u32 tmp
= ecc_buf
[0] | (ecc_buf
[1] << 16) |
730 ((ecc_buf
[2] & 0xF0) << 20) | ((ecc_buf
[2] & 0x0F) << 8);
732 ecc_buf
[0] = ~(P64o(tmp
) | P64e(tmp
) | P32o(tmp
) | P32e(tmp
) |
733 P16o(tmp
) | P16e(tmp
) | P8o(tmp
) | P8e(tmp
));
734 ecc_buf
[1] = ~(P1024o(tmp
) | P1024e(tmp
) | P512o(tmp
) | P512e(tmp
) |
735 P256o(tmp
) | P256e(tmp
) | P128o(tmp
) | P128e(tmp
));
736 ecc_buf
[2] = ~(P4o(tmp
) | P4e(tmp
) | P2o(tmp
) | P2e(tmp
) | P1o(tmp
) |
737 P1e(tmp
) | P2048o(tmp
) | P2048e(tmp
));
741 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
742 * @ecc_data1: ecc code from nand spare area
743 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
744 * @page_data: page data
746 * This function compares two ECC's and indicates if there is an error.
747 * If the error can be corrected it will be corrected to the buffer.
748 * If there is no error, %0 is returned. If there is an error but it
749 * was corrected, %1 is returned. Otherwise, %-1 is returned.
751 static int omap_compare_ecc(u8
*ecc_data1
, /* read from NAND memory */
752 u8
*ecc_data2
, /* read from register */
756 u8 tmp0_bit
[8], tmp1_bit
[8], tmp2_bit
[8];
757 u8 comp0_bit
[8], comp1_bit
[8], comp2_bit
[8];
764 isEccFF
= ((*(u32
*)ecc_data1
& 0xFFFFFF) == 0xFFFFFF);
766 gen_true_ecc(ecc_data1
);
767 gen_true_ecc(ecc_data2
);
769 for (i
= 0; i
<= 2; i
++) {
770 *(ecc_data1
+ i
) = ~(*(ecc_data1
+ i
));
771 *(ecc_data2
+ i
) = ~(*(ecc_data2
+ i
));
774 for (i
= 0; i
< 8; i
++) {
775 tmp0_bit
[i
] = *ecc_data1
% 2;
776 *ecc_data1
= *ecc_data1
/ 2;
779 for (i
= 0; i
< 8; i
++) {
780 tmp1_bit
[i
] = *(ecc_data1
+ 1) % 2;
781 *(ecc_data1
+ 1) = *(ecc_data1
+ 1) / 2;
784 for (i
= 0; i
< 8; i
++) {
785 tmp2_bit
[i
] = *(ecc_data1
+ 2) % 2;
786 *(ecc_data1
+ 2) = *(ecc_data1
+ 2) / 2;
789 for (i
= 0; i
< 8; i
++) {
790 comp0_bit
[i
] = *ecc_data2
% 2;
791 *ecc_data2
= *ecc_data2
/ 2;
794 for (i
= 0; i
< 8; i
++) {
795 comp1_bit
[i
] = *(ecc_data2
+ 1) % 2;
796 *(ecc_data2
+ 1) = *(ecc_data2
+ 1) / 2;
799 for (i
= 0; i
< 8; i
++) {
800 comp2_bit
[i
] = *(ecc_data2
+ 2) % 2;
801 *(ecc_data2
+ 2) = *(ecc_data2
+ 2) / 2;
804 for (i
= 0; i
< 6; i
++)
805 ecc_bit
[i
] = tmp2_bit
[i
+ 2] ^ comp2_bit
[i
+ 2];
807 for (i
= 0; i
< 8; i
++)
808 ecc_bit
[i
+ 6] = tmp0_bit
[i
] ^ comp0_bit
[i
];
810 for (i
= 0; i
< 8; i
++)
811 ecc_bit
[i
+ 14] = tmp1_bit
[i
] ^ comp1_bit
[i
];
813 ecc_bit
[22] = tmp2_bit
[0] ^ comp2_bit
[0];
814 ecc_bit
[23] = tmp2_bit
[1] ^ comp2_bit
[1];
816 for (i
= 0; i
< 24; i
++)
817 ecc_sum
+= ecc_bit
[i
];
821 /* Not reached because this function is not called if
822 * ECC values are equal
827 /* Uncorrectable error */
828 pr_debug("ECC UNCORRECTED_ERROR 1\n");
832 /* UN-Correctable error */
833 pr_debug("ECC UNCORRECTED_ERROR B\n");
837 /* Correctable error */
838 find_byte
= (ecc_bit
[23] << 8) +
848 find_bit
= (ecc_bit
[5] << 2) + (ecc_bit
[3] << 1) + ecc_bit
[1];
850 pr_debug("Correcting single bit ECC error at offset: "
851 "%d, bit: %d\n", find_byte
, find_bit
);
853 page_data
[find_byte
] ^= (1 << find_bit
);
858 if (ecc_data2
[0] == 0 &&
863 pr_debug("UNCORRECTED_ERROR default\n");
869 * omap_correct_data - Compares the ECC read with HW generated ECC
870 * @chip: NAND chip object
872 * @read_ecc: ecc read from nand flash
873 * @calc_ecc: ecc read from HW ECC registers
875 * Compares the ecc read from nand spare area with ECC registers values
876 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
877 * detection and correction. If there are no errors, %0 is returned. If
878 * there were errors and all of the errors were corrected, the number of
879 * corrected errors is returned. If uncorrectable errors exist, %-1 is
882 static int omap_correct_data(struct nand_chip
*chip
, u_char
*dat
,
883 u_char
*read_ecc
, u_char
*calc_ecc
)
885 struct omap_nand_info
*info
= mtd_to_omap(nand_to_mtd(chip
));
886 int blockCnt
= 0, i
= 0, ret
= 0;
889 /* Ex NAND_ECC_HW12_2048 */
890 if ((info
->nand
.ecc
.mode
== NAND_ECC_HW
) &&
891 (info
->nand
.ecc
.size
== 2048))
896 for (i
= 0; i
< blockCnt
; i
++) {
897 if (memcmp(read_ecc
, calc_ecc
, 3) != 0) {
898 ret
= omap_compare_ecc(read_ecc
, calc_ecc
, dat
);
901 /* keep track of the number of corrected errors */
912 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
913 * @chip: NAND chip object
914 * @dat: The pointer to data on which ecc is computed
915 * @ecc_code: The ecc_code buffer
917 * Using noninverted ECC can be considered ugly since writing a blank
918 * page ie. padding will clear the ECC bytes. This is no problem as long
919 * nobody is trying to write data on the seemingly unused page. Reading
920 * an erased page will produce an ECC mismatch between generated and read
921 * ECC bytes that has to be dealt with separately.
923 static int omap_calculate_ecc(struct nand_chip
*chip
, const u_char
*dat
,
926 struct omap_nand_info
*info
= mtd_to_omap(nand_to_mtd(chip
));
929 val
= readl(info
->reg
.gpmc_ecc_config
);
930 if (((val
>> ECC_CONFIG_CS_SHIFT
) & CS_MASK
) != info
->gpmc_cs
)
933 /* read ecc result */
934 val
= readl(info
->reg
.gpmc_ecc1_result
);
935 *ecc_code
++ = val
; /* P128e, ..., P1e */
936 *ecc_code
++ = val
>> 16; /* P128o, ..., P1o */
937 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
938 *ecc_code
++ = ((val
>> 8) & 0x0f) | ((val
>> 20) & 0xf0);
944 * omap_enable_hwecc - This function enables the hardware ecc functionality
945 * @mtd: MTD device structure
946 * @mode: Read/Write mode
948 static void omap_enable_hwecc(struct nand_chip
*chip
, int mode
)
950 struct omap_nand_info
*info
= mtd_to_omap(nand_to_mtd(chip
));
951 unsigned int dev_width
= (chip
->options
& NAND_BUSWIDTH_16
) ? 1 : 0;
954 /* clear ecc and enable bits */
955 val
= ECCCLEAR
| ECC1
;
956 writel(val
, info
->reg
.gpmc_ecc_control
);
958 /* program ecc and result sizes */
959 val
= ((((info
->nand
.ecc
.size
>> 1) - 1) << ECCSIZE1_SHIFT
) |
961 writel(val
, info
->reg
.gpmc_ecc_size_config
);
966 writel(ECCCLEAR
| ECC1
, info
->reg
.gpmc_ecc_control
);
968 case NAND_ECC_READSYN
:
969 writel(ECCCLEAR
, info
->reg
.gpmc_ecc_control
);
972 dev_info(&info
->pdev
->dev
,
973 "error: unrecognized Mode[%d]!\n", mode
);
977 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
978 val
= (dev_width
<< 7) | (info
->gpmc_cs
<< 1) | (0x1);
979 writel(val
, info
->reg
.gpmc_ecc_config
);
983 * omap_wait - wait until the command is done
984 * @this: NAND Chip structure
986 * Wait function is called during Program and erase operations and
987 * the way it is called from MTD layer, we should wait till the NAND
988 * chip is ready after the programming/erase operation has completed.
990 * Erase can take up to 400ms and program up to 20ms according to
991 * general NAND and SmartMedia specs
993 static int omap_wait(struct nand_chip
*this)
995 struct omap_nand_info
*info
= mtd_to_omap(nand_to_mtd(this));
996 unsigned long timeo
= jiffies
;
999 timeo
+= msecs_to_jiffies(400);
1001 writeb(NAND_CMD_STATUS
& 0xFF, info
->reg
.gpmc_nand_command
);
1002 while (time_before(jiffies
, timeo
)) {
1003 status
= readb(info
->reg
.gpmc_nand_data
);
1004 if (status
& NAND_STATUS_READY
)
1009 status
= readb(info
->reg
.gpmc_nand_data
);
1014 * omap_dev_ready - checks the NAND Ready GPIO line
1015 * @mtd: MTD device structure
1017 * Returns true if ready and false if busy.
1019 static int omap_dev_ready(struct nand_chip
*chip
)
1021 struct omap_nand_info
*info
= mtd_to_omap(nand_to_mtd(chip
));
1023 return gpiod_get_value(info
->ready_gpiod
);
1027 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1028 * @mtd: MTD device structure
1029 * @mode: Read/Write mode
1031 * When using BCH with SW correction (i.e. no ELM), sector size is set
1032 * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
1033 * for both reading and writing with:
1034 * eccsize0 = 0 (no additional protected byte in spare area)
1035 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1037 static void __maybe_unused
omap_enable_hwecc_bch(struct nand_chip
*chip
,
1040 unsigned int bch_type
;
1041 unsigned int dev_width
, nsectors
;
1042 struct omap_nand_info
*info
= mtd_to_omap(nand_to_mtd(chip
));
1043 enum omap_ecc ecc_opt
= info
->ecc_opt
;
1045 unsigned int ecc_size1
, ecc_size0
;
1047 /* GPMC configurations for calculating ECC */
1049 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
:
1052 wr_mode
= BCH_WRAPMODE_6
;
1053 ecc_size0
= BCH_ECC_SIZE0
;
1054 ecc_size1
= BCH_ECC_SIZE1
;
1056 case OMAP_ECC_BCH4_CODE_HW
:
1058 nsectors
= chip
->ecc
.steps
;
1059 if (mode
== NAND_ECC_READ
) {
1060 wr_mode
= BCH_WRAPMODE_1
;
1061 ecc_size0
= BCH4R_ECC_SIZE0
;
1062 ecc_size1
= BCH4R_ECC_SIZE1
;
1064 wr_mode
= BCH_WRAPMODE_6
;
1065 ecc_size0
= BCH_ECC_SIZE0
;
1066 ecc_size1
= BCH_ECC_SIZE1
;
1069 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
1072 wr_mode
= BCH_WRAPMODE_6
;
1073 ecc_size0
= BCH_ECC_SIZE0
;
1074 ecc_size1
= BCH_ECC_SIZE1
;
1076 case OMAP_ECC_BCH8_CODE_HW
:
1078 nsectors
= chip
->ecc
.steps
;
1079 if (mode
== NAND_ECC_READ
) {
1080 wr_mode
= BCH_WRAPMODE_1
;
1081 ecc_size0
= BCH8R_ECC_SIZE0
;
1082 ecc_size1
= BCH8R_ECC_SIZE1
;
1084 wr_mode
= BCH_WRAPMODE_6
;
1085 ecc_size0
= BCH_ECC_SIZE0
;
1086 ecc_size1
= BCH_ECC_SIZE1
;
1089 case OMAP_ECC_BCH16_CODE_HW
:
1091 nsectors
= chip
->ecc
.steps
;
1092 if (mode
== NAND_ECC_READ
) {
1094 ecc_size0
= 52; /* ECC bits in nibbles per sector */
1095 ecc_size1
= 0; /* non-ECC bits in nibbles per sector */
1098 ecc_size0
= 0; /* extra bits in nibbles per sector */
1099 ecc_size1
= 52; /* OOB bits in nibbles per sector */
1106 writel(ECC1
, info
->reg
.gpmc_ecc_control
);
1108 /* Configure ecc size for BCH */
1109 val
= (ecc_size1
<< ECCSIZE1_SHIFT
) | (ecc_size0
<< ECCSIZE0_SHIFT
);
1110 writel(val
, info
->reg
.gpmc_ecc_size_config
);
1112 dev_width
= (chip
->options
& NAND_BUSWIDTH_16
) ? 1 : 0;
1114 /* BCH configuration */
1115 val
= ((1 << 16) | /* enable BCH */
1116 (bch_type
<< 12) | /* BCH4/BCH8/BCH16 */
1117 (wr_mode
<< 8) | /* wrap mode */
1118 (dev_width
<< 7) | /* bus width */
1119 (((nsectors
-1) & 0x7) << 4) | /* number of sectors */
1120 (info
->gpmc_cs
<< 1) | /* ECC CS */
1121 (0x1)); /* enable ECC */
1123 writel(val
, info
->reg
.gpmc_ecc_config
);
1125 /* Clear ecc and enable bits */
1126 writel(ECCCLEAR
| ECC1
, info
->reg
.gpmc_ecc_control
);
1129 static u8 bch4_polynomial
[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1130 static u8 bch8_polynomial
[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1131 0x97, 0x79, 0xe5, 0x24, 0xb5};
1134 * _omap_calculate_ecc_bch - Generate ECC bytes for one sector
1135 * @mtd: MTD device structure
1136 * @dat: The pointer to data on which ecc is computed
1137 * @ecc_code: The ecc_code buffer
1138 * @i: The sector number (for a multi sector page)
1140 * Support calculating of BCH4/8/16 ECC vectors for one sector
1141 * within a page. Sector number is in @i.
1143 static int _omap_calculate_ecc_bch(struct mtd_info
*mtd
,
1144 const u_char
*dat
, u_char
*ecc_calc
, int i
)
1146 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
1147 int eccbytes
= info
->nand
.ecc
.bytes
;
1148 struct gpmc_nand_regs
*gpmc_regs
= &info
->reg
;
1150 unsigned long bch_val1
, bch_val2
, bch_val3
, bch_val4
;
1154 ecc_code
= ecc_calc
;
1155 switch (info
->ecc_opt
) {
1156 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
1157 case OMAP_ECC_BCH8_CODE_HW
:
1158 bch_val1
= readl(gpmc_regs
->gpmc_bch_result0
[i
]);
1159 bch_val2
= readl(gpmc_regs
->gpmc_bch_result1
[i
]);
1160 bch_val3
= readl(gpmc_regs
->gpmc_bch_result2
[i
]);
1161 bch_val4
= readl(gpmc_regs
->gpmc_bch_result3
[i
]);
1162 *ecc_code
++ = (bch_val4
& 0xFF);
1163 *ecc_code
++ = ((bch_val3
>> 24) & 0xFF);
1164 *ecc_code
++ = ((bch_val3
>> 16) & 0xFF);
1165 *ecc_code
++ = ((bch_val3
>> 8) & 0xFF);
1166 *ecc_code
++ = (bch_val3
& 0xFF);
1167 *ecc_code
++ = ((bch_val2
>> 24) & 0xFF);
1168 *ecc_code
++ = ((bch_val2
>> 16) & 0xFF);
1169 *ecc_code
++ = ((bch_val2
>> 8) & 0xFF);
1170 *ecc_code
++ = (bch_val2
& 0xFF);
1171 *ecc_code
++ = ((bch_val1
>> 24) & 0xFF);
1172 *ecc_code
++ = ((bch_val1
>> 16) & 0xFF);
1173 *ecc_code
++ = ((bch_val1
>> 8) & 0xFF);
1174 *ecc_code
++ = (bch_val1
& 0xFF);
1176 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
:
1177 case OMAP_ECC_BCH4_CODE_HW
:
1178 bch_val1
= readl(gpmc_regs
->gpmc_bch_result0
[i
]);
1179 bch_val2
= readl(gpmc_regs
->gpmc_bch_result1
[i
]);
1180 *ecc_code
++ = ((bch_val2
>> 12) & 0xFF);
1181 *ecc_code
++ = ((bch_val2
>> 4) & 0xFF);
1182 *ecc_code
++ = ((bch_val2
& 0xF) << 4) |
1183 ((bch_val1
>> 28) & 0xF);
1184 *ecc_code
++ = ((bch_val1
>> 20) & 0xFF);
1185 *ecc_code
++ = ((bch_val1
>> 12) & 0xFF);
1186 *ecc_code
++ = ((bch_val1
>> 4) & 0xFF);
1187 *ecc_code
++ = ((bch_val1
& 0xF) << 4);
1189 case OMAP_ECC_BCH16_CODE_HW
:
1190 val
= readl(gpmc_regs
->gpmc_bch_result6
[i
]);
1191 ecc_code
[0] = ((val
>> 8) & 0xFF);
1192 ecc_code
[1] = ((val
>> 0) & 0xFF);
1193 val
= readl(gpmc_regs
->gpmc_bch_result5
[i
]);
1194 ecc_code
[2] = ((val
>> 24) & 0xFF);
1195 ecc_code
[3] = ((val
>> 16) & 0xFF);
1196 ecc_code
[4] = ((val
>> 8) & 0xFF);
1197 ecc_code
[5] = ((val
>> 0) & 0xFF);
1198 val
= readl(gpmc_regs
->gpmc_bch_result4
[i
]);
1199 ecc_code
[6] = ((val
>> 24) & 0xFF);
1200 ecc_code
[7] = ((val
>> 16) & 0xFF);
1201 ecc_code
[8] = ((val
>> 8) & 0xFF);
1202 ecc_code
[9] = ((val
>> 0) & 0xFF);
1203 val
= readl(gpmc_regs
->gpmc_bch_result3
[i
]);
1204 ecc_code
[10] = ((val
>> 24) & 0xFF);
1205 ecc_code
[11] = ((val
>> 16) & 0xFF);
1206 ecc_code
[12] = ((val
>> 8) & 0xFF);
1207 ecc_code
[13] = ((val
>> 0) & 0xFF);
1208 val
= readl(gpmc_regs
->gpmc_bch_result2
[i
]);
1209 ecc_code
[14] = ((val
>> 24) & 0xFF);
1210 ecc_code
[15] = ((val
>> 16) & 0xFF);
1211 ecc_code
[16] = ((val
>> 8) & 0xFF);
1212 ecc_code
[17] = ((val
>> 0) & 0xFF);
1213 val
= readl(gpmc_regs
->gpmc_bch_result1
[i
]);
1214 ecc_code
[18] = ((val
>> 24) & 0xFF);
1215 ecc_code
[19] = ((val
>> 16) & 0xFF);
1216 ecc_code
[20] = ((val
>> 8) & 0xFF);
1217 ecc_code
[21] = ((val
>> 0) & 0xFF);
1218 val
= readl(gpmc_regs
->gpmc_bch_result0
[i
]);
1219 ecc_code
[22] = ((val
>> 24) & 0xFF);
1220 ecc_code
[23] = ((val
>> 16) & 0xFF);
1221 ecc_code
[24] = ((val
>> 8) & 0xFF);
1222 ecc_code
[25] = ((val
>> 0) & 0xFF);
1228 /* ECC scheme specific syndrome customizations */
1229 switch (info
->ecc_opt
) {
1230 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
:
1231 /* Add constant polynomial to remainder, so that
1232 * ECC of blank pages results in 0x0 on reading back
1234 for (j
= 0; j
< eccbytes
; j
++)
1235 ecc_calc
[j
] ^= bch4_polynomial
[j
];
1237 case OMAP_ECC_BCH4_CODE_HW
:
1238 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1239 ecc_calc
[eccbytes
- 1] = 0x0;
1241 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
1242 /* Add constant polynomial to remainder, so that
1243 * ECC of blank pages results in 0x0 on reading back
1245 for (j
= 0; j
< eccbytes
; j
++)
1246 ecc_calc
[j
] ^= bch8_polynomial
[j
];
1248 case OMAP_ECC_BCH8_CODE_HW
:
1249 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1250 ecc_calc
[eccbytes
- 1] = 0x0;
1252 case OMAP_ECC_BCH16_CODE_HW
:
1262 * omap_calculate_ecc_bch_sw - ECC generator for sector for SW based correction
1263 * @chip: NAND chip object
1264 * @dat: The pointer to data on which ecc is computed
1265 * @ecc_code: The ecc_code buffer
1267 * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
1268 * when SW based correction is required as ECC is required for one sector
1271 static int omap_calculate_ecc_bch_sw(struct nand_chip
*chip
,
1272 const u_char
*dat
, u_char
*ecc_calc
)
1274 return _omap_calculate_ecc_bch(nand_to_mtd(chip
), dat
, ecc_calc
, 0);
1278 * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
1279 * @mtd: MTD device structure
1280 * @dat: The pointer to data on which ecc is computed
1281 * @ecc_code: The ecc_code buffer
1283 * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
1285 static int omap_calculate_ecc_bch_multi(struct mtd_info
*mtd
,
1286 const u_char
*dat
, u_char
*ecc_calc
)
1288 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
1289 int eccbytes
= info
->nand
.ecc
.bytes
;
1290 unsigned long nsectors
;
1293 nsectors
= ((readl(info
->reg
.gpmc_ecc_config
) >> 4) & 0x7) + 1;
1294 for (i
= 0; i
< nsectors
; i
++) {
1295 ret
= _omap_calculate_ecc_bch(mtd
, dat
, ecc_calc
, i
);
1299 ecc_calc
+= eccbytes
;
1306 * erased_sector_bitflips - count bit flips
1307 * @data: data sector buffer
1309 * @info: omap_nand_info
1311 * Check the bit flips in erased page falls below correctable level.
1312 * If falls below, report the page as erased with correctable bit
1313 * flip, else report as uncorrectable page.
1315 static int erased_sector_bitflips(u_char
*data
, u_char
*oob
,
1316 struct omap_nand_info
*info
)
1318 int flip_bits
= 0, i
;
1320 for (i
= 0; i
< info
->nand
.ecc
.size
; i
++) {
1321 flip_bits
+= hweight8(~data
[i
]);
1322 if (flip_bits
> info
->nand
.ecc
.strength
)
1326 for (i
= 0; i
< info
->nand
.ecc
.bytes
- 1; i
++) {
1327 flip_bits
+= hweight8(~oob
[i
]);
1328 if (flip_bits
> info
->nand
.ecc
.strength
)
1333 * Bit flips falls in correctable level.
1334 * Fill data area with 0xFF
1337 memset(data
, 0xFF, info
->nand
.ecc
.size
);
1338 memset(oob
, 0xFF, info
->nand
.ecc
.bytes
);
1345 * omap_elm_correct_data - corrects page data area in case error reported
1346 * @chip: NAND chip object
1348 * @read_ecc: ecc read from nand flash
1349 * @calc_ecc: ecc read from HW ECC registers
1351 * Calculated ecc vector reported as zero in case of non-error pages.
1352 * In case of non-zero ecc vector, first filter out erased-pages, and
1353 * then process data via ELM to detect bit-flips.
1355 static int omap_elm_correct_data(struct nand_chip
*chip
, u_char
*data
,
1356 u_char
*read_ecc
, u_char
*calc_ecc
)
1358 struct omap_nand_info
*info
= mtd_to_omap(nand_to_mtd(chip
));
1359 struct nand_ecc_ctrl
*ecc
= &info
->nand
.ecc
;
1360 int eccsteps
= info
->nand
.ecc
.steps
;
1361 int i
, j
, stat
= 0;
1362 int eccflag
, actual_eccbytes
;
1363 struct elm_errorvec err_vec
[ERROR_VECTOR_MAX
];
1364 u_char
*ecc_vec
= calc_ecc
;
1365 u_char
*spare_ecc
= read_ecc
;
1366 u_char
*erased_ecc_vec
;
1369 bool is_error_reported
= false;
1370 u32 bit_pos
, byte_pos
, error_max
, pos
;
1373 switch (info
->ecc_opt
) {
1374 case OMAP_ECC_BCH4_CODE_HW
:
1375 /* omit 7th ECC byte reserved for ROM code compatibility */
1376 actual_eccbytes
= ecc
->bytes
- 1;
1377 erased_ecc_vec
= bch4_vector
;
1379 case OMAP_ECC_BCH8_CODE_HW
:
1380 /* omit 14th ECC byte reserved for ROM code compatibility */
1381 actual_eccbytes
= ecc
->bytes
- 1;
1382 erased_ecc_vec
= bch8_vector
;
1384 case OMAP_ECC_BCH16_CODE_HW
:
1385 actual_eccbytes
= ecc
->bytes
;
1386 erased_ecc_vec
= bch16_vector
;
1389 dev_err(&info
->pdev
->dev
, "invalid driver configuration\n");
1393 /* Initialize elm error vector to zero */
1394 memset(err_vec
, 0, sizeof(err_vec
));
1396 for (i
= 0; i
< eccsteps
; i
++) {
1397 eccflag
= 0; /* initialize eccflag */
1400 * Check any error reported,
1401 * In case of error, non zero ecc reported.
1403 for (j
= 0; j
< actual_eccbytes
; j
++) {
1404 if (calc_ecc
[j
] != 0) {
1405 eccflag
= 1; /* non zero ecc, error present */
1411 if (memcmp(calc_ecc
, erased_ecc_vec
,
1412 actual_eccbytes
) == 0) {
1414 * calc_ecc[] matches pattern for ECC(all 0xff)
1415 * so this is definitely an erased-page
1418 buf
= &data
[info
->nand
.ecc
.size
* i
];
1420 * count number of 0-bits in read_buf.
1421 * This check can be removed once a similar
1422 * check is introduced in generic NAND driver
1424 bitflip_count
= erased_sector_bitflips(
1425 buf
, read_ecc
, info
);
1426 if (bitflip_count
) {
1428 * number of 0-bits within ECC limits
1429 * So this may be an erased-page
1431 stat
+= bitflip_count
;
1434 * Too many 0-bits. It may be a
1435 * - programmed-page, OR
1436 * - erased-page with many bit-flips
1437 * So this page requires check by ELM
1439 err_vec
[i
].error_reported
= true;
1440 is_error_reported
= true;
1445 /* Update the ecc vector */
1446 calc_ecc
+= ecc
->bytes
;
1447 read_ecc
+= ecc
->bytes
;
1450 /* Check if any error reported */
1451 if (!is_error_reported
)
1454 /* Decode BCH error using ELM module */
1455 elm_decode_bch_error_page(info
->elm_dev
, ecc_vec
, err_vec
);
1458 for (i
= 0; i
< eccsteps
; i
++) {
1459 if (err_vec
[i
].error_uncorrectable
) {
1460 dev_err(&info
->pdev
->dev
,
1461 "uncorrectable bit-flips found\n");
1463 } else if (err_vec
[i
].error_reported
) {
1464 for (j
= 0; j
< err_vec
[i
].error_count
; j
++) {
1465 switch (info
->ecc_opt
) {
1466 case OMAP_ECC_BCH4_CODE_HW
:
1467 /* Add 4 bits to take care of padding */
1468 pos
= err_vec
[i
].error_loc
[j
] +
1471 case OMAP_ECC_BCH8_CODE_HW
:
1472 case OMAP_ECC_BCH16_CODE_HW
:
1473 pos
= err_vec
[i
].error_loc
[j
];
1478 error_max
= (ecc
->size
+ actual_eccbytes
) * 8;
1479 /* Calculate bit position of error */
1482 /* Calculate byte position of error */
1483 byte_pos
= (error_max
- pos
- 1) / 8;
1485 if (pos
< error_max
) {
1486 if (byte_pos
< 512) {
1487 pr_debug("bitflip@dat[%d]=%x\n",
1488 byte_pos
, data
[byte_pos
]);
1489 data
[byte_pos
] ^= 1 << bit_pos
;
1491 pr_debug("bitflip@oob[%d]=%x\n",
1493 spare_ecc
[byte_pos
- 512]);
1494 spare_ecc
[byte_pos
- 512] ^=
1498 dev_err(&info
->pdev
->dev
,
1499 "invalid bit-flip @ %d:%d\n",
1506 /* Update number of correctable errors */
1507 stat
+= err_vec
[i
].error_count
;
1509 /* Update page data with sector size */
1511 spare_ecc
+= ecc
->bytes
;
1514 return (err
) ? err
: stat
;
1518 * omap_write_page_bch - BCH ecc based write page function for entire page
1519 * @chip: nand chip info structure
1521 * @oob_required: must write chip->oob_poi to OOB
1524 * Custom write page method evolved to support multi sector writing in one shot
1526 static int omap_write_page_bch(struct nand_chip
*chip
, const uint8_t *buf
,
1527 int oob_required
, int page
)
1529 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1531 uint8_t *ecc_calc
= chip
->ecc
.calc_buf
;
1533 nand_prog_page_begin_op(chip
, page
, 0, NULL
, 0);
1535 /* Enable GPMC ecc engine */
1536 chip
->ecc
.hwctl(chip
, NAND_ECC_WRITE
);
1539 chip
->legacy
.write_buf(chip
, buf
, mtd
->writesize
);
1541 /* Update ecc vector from GPMC result registers */
1542 omap_calculate_ecc_bch_multi(mtd
, buf
, &ecc_calc
[0]);
1544 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
1549 /* Write ecc vector to OOB area */
1550 chip
->legacy
.write_buf(chip
, chip
->oob_poi
, mtd
->oobsize
);
1552 return nand_prog_page_end_op(chip
);
1556 * omap_write_subpage_bch - BCH hardware ECC based subpage write
1557 * @chip: nand chip info structure
1558 * @offset: column address of subpage within the page
1559 * @data_len: data length
1561 * @oob_required: must write chip->oob_poi to OOB
1562 * @page: page number to write
1564 * OMAP optimized subpage write method.
1566 static int omap_write_subpage_bch(struct nand_chip
*chip
, u32 offset
,
1567 u32 data_len
, const u8
*buf
,
1568 int oob_required
, int page
)
1570 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1571 u8
*ecc_calc
= chip
->ecc
.calc_buf
;
1572 int ecc_size
= chip
->ecc
.size
;
1573 int ecc_bytes
= chip
->ecc
.bytes
;
1574 int ecc_steps
= chip
->ecc
.steps
;
1575 u32 start_step
= offset
/ ecc_size
;
1576 u32 end_step
= (offset
+ data_len
- 1) / ecc_size
;
1580 * Write entire page at one go as it would be optimal
1581 * as ECC is calculated by hardware.
1582 * ECC is calculated for all subpages but we choose
1583 * only what we want.
1585 nand_prog_page_begin_op(chip
, page
, 0, NULL
, 0);
1587 /* Enable GPMC ECC engine */
1588 chip
->ecc
.hwctl(chip
, NAND_ECC_WRITE
);
1591 chip
->legacy
.write_buf(chip
, buf
, mtd
->writesize
);
1593 for (step
= 0; step
< ecc_steps
; step
++) {
1594 /* mask ECC of un-touched subpages by padding 0xFF */
1595 if (step
< start_step
|| step
> end_step
)
1596 memset(ecc_calc
, 0xff, ecc_bytes
);
1598 ret
= _omap_calculate_ecc_bch(mtd
, buf
, ecc_calc
, step
);
1604 ecc_calc
+= ecc_bytes
;
1607 /* copy calculated ECC for whole page to chip->buffer->oob */
1608 /* this include masked-value(0xFF) for unwritten subpages */
1609 ecc_calc
= chip
->ecc
.calc_buf
;
1610 ret
= mtd_ooblayout_set_eccbytes(mtd
, ecc_calc
, chip
->oob_poi
, 0,
1615 /* write OOB buffer to NAND device */
1616 chip
->legacy
.write_buf(chip
, chip
->oob_poi
, mtd
->oobsize
);
1618 return nand_prog_page_end_op(chip
);
1622 * omap_read_page_bch - BCH ecc based page read function for entire page
1623 * @chip: nand chip info structure
1624 * @buf: buffer to store read data
1625 * @oob_required: caller requires OOB data read to chip->oob_poi
1626 * @page: page number to read
1628 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1629 * used for error correction.
1630 * Custom method evolved to support ELM error correction & multi sector
1631 * reading. On reading page data area is read along with OOB data with
1632 * ecc engine enabled. ecc vector updated after read of OOB data.
1633 * For non error pages ecc vector reported as zero.
1635 static int omap_read_page_bch(struct nand_chip
*chip
, uint8_t *buf
,
1636 int oob_required
, int page
)
1638 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1639 uint8_t *ecc_calc
= chip
->ecc
.calc_buf
;
1640 uint8_t *ecc_code
= chip
->ecc
.code_buf
;
1642 unsigned int max_bitflips
= 0;
1644 nand_read_page_op(chip
, page
, 0, NULL
, 0);
1646 /* Enable GPMC ecc engine */
1647 chip
->ecc
.hwctl(chip
, NAND_ECC_READ
);
1650 chip
->legacy
.read_buf(chip
, buf
, mtd
->writesize
);
1652 /* Read oob bytes */
1653 nand_change_read_column_op(chip
,
1654 mtd
->writesize
+ BADBLOCK_MARKER_LENGTH
,
1655 chip
->oob_poi
+ BADBLOCK_MARKER_LENGTH
,
1656 chip
->ecc
.total
, false);
1658 /* Calculate ecc bytes */
1659 omap_calculate_ecc_bch_multi(mtd
, buf
, ecc_calc
);
1661 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
1666 stat
= chip
->ecc
.correct(chip
, buf
, ecc_code
, ecc_calc
);
1669 mtd
->ecc_stats
.failed
++;
1671 mtd
->ecc_stats
.corrected
+= stat
;
1672 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1675 return max_bitflips
;
1679 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1680 * @omap_nand_info: NAND device structure containing platform data
1682 static bool is_elm_present(struct omap_nand_info
*info
,
1683 struct device_node
*elm_node
)
1685 struct platform_device
*pdev
;
1687 /* check whether elm-id is passed via DT */
1689 dev_err(&info
->pdev
->dev
, "ELM devicetree node not found\n");
1692 pdev
= of_find_device_by_node(elm_node
);
1693 /* check whether ELM device is registered */
1695 dev_err(&info
->pdev
->dev
, "ELM device not found\n");
1698 /* ELM module available, now configure it */
1699 info
->elm_dev
= &pdev
->dev
;
1703 static bool omap2_nand_ecc_check(struct omap_nand_info
*info
)
1705 bool ecc_needs_bch
, ecc_needs_omap_bch
, ecc_needs_elm
;
1707 switch (info
->ecc_opt
) {
1708 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
:
1709 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
1710 ecc_needs_omap_bch
= false;
1711 ecc_needs_bch
= true;
1712 ecc_needs_elm
= false;
1714 case OMAP_ECC_BCH4_CODE_HW
:
1715 case OMAP_ECC_BCH8_CODE_HW
:
1716 case OMAP_ECC_BCH16_CODE_HW
:
1717 ecc_needs_omap_bch
= true;
1718 ecc_needs_bch
= false;
1719 ecc_needs_elm
= true;
1722 ecc_needs_omap_bch
= false;
1723 ecc_needs_bch
= false;
1724 ecc_needs_elm
= false;
1728 if (ecc_needs_bch
&& !IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH
)) {
1729 dev_err(&info
->pdev
->dev
,
1730 "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
1733 if (ecc_needs_omap_bch
&& !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH
)) {
1734 dev_err(&info
->pdev
->dev
,
1735 "CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1738 if (ecc_needs_elm
&& !is_elm_present(info
, info
->elm_of_node
)) {
1739 dev_err(&info
->pdev
->dev
, "ELM not available\n");
1746 static const char * const nand_xfer_types
[] = {
1747 [NAND_OMAP_PREFETCH_POLLED
] = "prefetch-polled",
1748 [NAND_OMAP_POLLED
] = "polled",
1749 [NAND_OMAP_PREFETCH_DMA
] = "prefetch-dma",
1750 [NAND_OMAP_PREFETCH_IRQ
] = "prefetch-irq",
1753 static int omap_get_dt_info(struct device
*dev
, struct omap_nand_info
*info
)
1755 struct device_node
*child
= dev
->of_node
;
1760 if (of_property_read_u32(child
, "reg", &cs
) < 0) {
1761 dev_err(dev
, "reg not found in DT\n");
1767 /* detect availability of ELM module. Won't be present pre-OMAP4 */
1768 info
->elm_of_node
= of_parse_phandle(child
, "ti,elm-id", 0);
1769 if (!info
->elm_of_node
) {
1770 info
->elm_of_node
= of_parse_phandle(child
, "elm_id", 0);
1771 if (!info
->elm_of_node
)
1772 dev_dbg(dev
, "ti,elm-id not in DT\n");
1775 /* select ecc-scheme for NAND */
1776 if (of_property_read_string(child
, "ti,nand-ecc-opt", &s
)) {
1777 dev_err(dev
, "ti,nand-ecc-opt not found\n");
1781 if (!strcmp(s
, "sw")) {
1782 info
->ecc_opt
= OMAP_ECC_HAM1_CODE_SW
;
1783 } else if (!strcmp(s
, "ham1") ||
1784 !strcmp(s
, "hw") || !strcmp(s
, "hw-romcode")) {
1785 info
->ecc_opt
= OMAP_ECC_HAM1_CODE_HW
;
1786 } else if (!strcmp(s
, "bch4")) {
1787 if (info
->elm_of_node
)
1788 info
->ecc_opt
= OMAP_ECC_BCH4_CODE_HW
;
1790 info
->ecc_opt
= OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
;
1791 } else if (!strcmp(s
, "bch8")) {
1792 if (info
->elm_of_node
)
1793 info
->ecc_opt
= OMAP_ECC_BCH8_CODE_HW
;
1795 info
->ecc_opt
= OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
;
1796 } else if (!strcmp(s
, "bch16")) {
1797 info
->ecc_opt
= OMAP_ECC_BCH16_CODE_HW
;
1799 dev_err(dev
, "unrecognized value for ti,nand-ecc-opt\n");
1803 /* select data transfer mode */
1804 if (!of_property_read_string(child
, "ti,nand-xfer-type", &s
)) {
1805 for (i
= 0; i
< ARRAY_SIZE(nand_xfer_types
); i
++) {
1806 if (!strcasecmp(s
, nand_xfer_types
[i
])) {
1807 info
->xfer_type
= i
;
1812 dev_err(dev
, "unrecognized value for ti,nand-xfer-type\n");
1819 static int omap_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1820 struct mtd_oob_region
*oobregion
)
1822 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
1823 struct nand_chip
*chip
= &info
->nand
;
1824 int off
= BADBLOCK_MARKER_LENGTH
;
1826 if (info
->ecc_opt
== OMAP_ECC_HAM1_CODE_HW
&&
1827 !(chip
->options
& NAND_BUSWIDTH_16
))
1833 oobregion
->offset
= off
;
1834 oobregion
->length
= chip
->ecc
.total
;
1839 static int omap_ooblayout_free(struct mtd_info
*mtd
, int section
,
1840 struct mtd_oob_region
*oobregion
)
1842 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
1843 struct nand_chip
*chip
= &info
->nand
;
1844 int off
= BADBLOCK_MARKER_LENGTH
;
1846 if (info
->ecc_opt
== OMAP_ECC_HAM1_CODE_HW
&&
1847 !(chip
->options
& NAND_BUSWIDTH_16
))
1853 off
+= chip
->ecc
.total
;
1854 if (off
>= mtd
->oobsize
)
1857 oobregion
->offset
= off
;
1858 oobregion
->length
= mtd
->oobsize
- off
;
1863 static const struct mtd_ooblayout_ops omap_ooblayout_ops
= {
1864 .ecc
= omap_ooblayout_ecc
,
1865 .free
= omap_ooblayout_free
,
1868 static int omap_sw_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1869 struct mtd_oob_region
*oobregion
)
1871 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1872 int off
= BADBLOCK_MARKER_LENGTH
;
1874 if (section
>= chip
->ecc
.steps
)
1878 * When SW correction is employed, one OMAP specific marker byte is
1879 * reserved after each ECC step.
1881 oobregion
->offset
= off
+ (section
* (chip
->ecc
.bytes
+ 1));
1882 oobregion
->length
= chip
->ecc
.bytes
;
1887 static int omap_sw_ooblayout_free(struct mtd_info
*mtd
, int section
,
1888 struct mtd_oob_region
*oobregion
)
1890 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1891 int off
= BADBLOCK_MARKER_LENGTH
;
1897 * When SW correction is employed, one OMAP specific marker byte is
1898 * reserved after each ECC step.
1900 off
+= ((chip
->ecc
.bytes
+ 1) * chip
->ecc
.steps
);
1901 if (off
>= mtd
->oobsize
)
1904 oobregion
->offset
= off
;
1905 oobregion
->length
= mtd
->oobsize
- off
;
1910 static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops
= {
1911 .ecc
= omap_sw_ooblayout_ecc
,
1912 .free
= omap_sw_ooblayout_free
,
1915 static int omap_nand_attach_chip(struct nand_chip
*chip
)
1917 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1918 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
1919 struct device
*dev
= &info
->pdev
->dev
;
1920 int min_oobbytes
= BADBLOCK_MARKER_LENGTH
;
1921 int oobbytes_per_step
;
1922 dma_cap_mask_t mask
;
1925 if (chip
->bbt_options
& NAND_BBT_USE_FLASH
)
1926 chip
->bbt_options
|= NAND_BBT_NO_OOB
;
1928 chip
->options
|= NAND_SKIP_BBTSCAN
;
1930 /* Re-populate low-level callbacks based on xfer modes */
1931 switch (info
->xfer_type
) {
1932 case NAND_OMAP_PREFETCH_POLLED
:
1933 chip
->legacy
.read_buf
= omap_read_buf_pref
;
1934 chip
->legacy
.write_buf
= omap_write_buf_pref
;
1937 case NAND_OMAP_POLLED
:
1938 /* Use nand_base defaults for {read,write}_buf */
1941 case NAND_OMAP_PREFETCH_DMA
:
1943 dma_cap_set(DMA_SLAVE
, mask
);
1944 info
->dma
= dma_request_chan(dev
->parent
, "rxtx");
1946 if (IS_ERR(info
->dma
)) {
1947 dev_err(dev
, "DMA engine request failed\n");
1948 return PTR_ERR(info
->dma
);
1950 struct dma_slave_config cfg
;
1952 memset(&cfg
, 0, sizeof(cfg
));
1953 cfg
.src_addr
= info
->phys_base
;
1954 cfg
.dst_addr
= info
->phys_base
;
1955 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1956 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1957 cfg
.src_maxburst
= 16;
1958 cfg
.dst_maxburst
= 16;
1959 err
= dmaengine_slave_config(info
->dma
, &cfg
);
1962 "DMA engine slave config failed: %d\n",
1966 chip
->legacy
.read_buf
= omap_read_buf_dma_pref
;
1967 chip
->legacy
.write_buf
= omap_write_buf_dma_pref
;
1971 case NAND_OMAP_PREFETCH_IRQ
:
1972 info
->gpmc_irq_fifo
= platform_get_irq(info
->pdev
, 0);
1973 if (info
->gpmc_irq_fifo
<= 0) {
1974 dev_err(dev
, "Error getting fifo IRQ\n");
1977 err
= devm_request_irq(dev
, info
->gpmc_irq_fifo
,
1978 omap_nand_irq
, IRQF_SHARED
,
1979 "gpmc-nand-fifo", info
);
1981 dev_err(dev
, "Requesting IRQ %d, error %d\n",
1982 info
->gpmc_irq_fifo
, err
);
1983 info
->gpmc_irq_fifo
= 0;
1987 info
->gpmc_irq_count
= platform_get_irq(info
->pdev
, 1);
1988 if (info
->gpmc_irq_count
<= 0) {
1989 dev_err(dev
, "Error getting IRQ count\n");
1992 err
= devm_request_irq(dev
, info
->gpmc_irq_count
,
1993 omap_nand_irq
, IRQF_SHARED
,
1994 "gpmc-nand-count", info
);
1996 dev_err(dev
, "Requesting IRQ %d, error %d\n",
1997 info
->gpmc_irq_count
, err
);
1998 info
->gpmc_irq_count
= 0;
2002 chip
->legacy
.read_buf
= omap_read_buf_irq_pref
;
2003 chip
->legacy
.write_buf
= omap_write_buf_irq_pref
;
2008 dev_err(dev
, "xfer_type %d not supported!\n", info
->xfer_type
);
2012 if (!omap2_nand_ecc_check(info
))
2016 * Bail out earlier to let NAND_ECC_SOFT code create its own
2017 * ooblayout instead of using ours.
2019 if (info
->ecc_opt
== OMAP_ECC_HAM1_CODE_SW
) {
2020 chip
->ecc
.mode
= NAND_ECC_SOFT
;
2021 chip
->ecc
.algo
= NAND_ECC_HAMMING
;
2025 /* Populate MTD interface based on ECC scheme */
2026 switch (info
->ecc_opt
) {
2027 case OMAP_ECC_HAM1_CODE_HW
:
2028 dev_info(dev
, "nand: using OMAP_ECC_HAM1_CODE_HW\n");
2029 chip
->ecc
.mode
= NAND_ECC_HW
;
2030 chip
->ecc
.bytes
= 3;
2031 chip
->ecc
.size
= 512;
2032 chip
->ecc
.strength
= 1;
2033 chip
->ecc
.calculate
= omap_calculate_ecc
;
2034 chip
->ecc
.hwctl
= omap_enable_hwecc
;
2035 chip
->ecc
.correct
= omap_correct_data
;
2036 mtd_set_ooblayout(mtd
, &omap_ooblayout_ops
);
2037 oobbytes_per_step
= chip
->ecc
.bytes
;
2039 if (!(chip
->options
& NAND_BUSWIDTH_16
))
2044 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
:
2045 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
2046 chip
->ecc
.mode
= NAND_ECC_HW
;
2047 chip
->ecc
.size
= 512;
2048 chip
->ecc
.bytes
= 7;
2049 chip
->ecc
.strength
= 4;
2050 chip
->ecc
.hwctl
= omap_enable_hwecc_bch
;
2051 chip
->ecc
.correct
= nand_bch_correct_data
;
2052 chip
->ecc
.calculate
= omap_calculate_ecc_bch_sw
;
2053 mtd_set_ooblayout(mtd
, &omap_sw_ooblayout_ops
);
2054 /* Reserve one byte for the OMAP marker */
2055 oobbytes_per_step
= chip
->ecc
.bytes
+ 1;
2056 /* Software BCH library is used for locating errors */
2057 chip
->ecc
.priv
= nand_bch_init(mtd
);
2058 if (!chip
->ecc
.priv
) {
2059 dev_err(dev
, "Unable to use BCH library\n");
2064 case OMAP_ECC_BCH4_CODE_HW
:
2065 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
2066 chip
->ecc
.mode
= NAND_ECC_HW
;
2067 chip
->ecc
.size
= 512;
2068 /* 14th bit is kept reserved for ROM-code compatibility */
2069 chip
->ecc
.bytes
= 7 + 1;
2070 chip
->ecc
.strength
= 4;
2071 chip
->ecc
.hwctl
= omap_enable_hwecc_bch
;
2072 chip
->ecc
.correct
= omap_elm_correct_data
;
2073 chip
->ecc
.read_page
= omap_read_page_bch
;
2074 chip
->ecc
.write_page
= omap_write_page_bch
;
2075 chip
->ecc
.write_subpage
= omap_write_subpage_bch
;
2076 mtd_set_ooblayout(mtd
, &omap_ooblayout_ops
);
2077 oobbytes_per_step
= chip
->ecc
.bytes
;
2079 err
= elm_config(info
->elm_dev
, BCH4_ECC
,
2080 mtd
->writesize
/ chip
->ecc
.size
,
2081 chip
->ecc
.size
, chip
->ecc
.bytes
);
2086 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
:
2087 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
2088 chip
->ecc
.mode
= NAND_ECC_HW
;
2089 chip
->ecc
.size
= 512;
2090 chip
->ecc
.bytes
= 13;
2091 chip
->ecc
.strength
= 8;
2092 chip
->ecc
.hwctl
= omap_enable_hwecc_bch
;
2093 chip
->ecc
.correct
= nand_bch_correct_data
;
2094 chip
->ecc
.calculate
= omap_calculate_ecc_bch_sw
;
2095 mtd_set_ooblayout(mtd
, &omap_sw_ooblayout_ops
);
2096 /* Reserve one byte for the OMAP marker */
2097 oobbytes_per_step
= chip
->ecc
.bytes
+ 1;
2098 /* Software BCH library is used for locating errors */
2099 chip
->ecc
.priv
= nand_bch_init(mtd
);
2100 if (!chip
->ecc
.priv
) {
2101 dev_err(dev
, "unable to use BCH library\n");
2106 case OMAP_ECC_BCH8_CODE_HW
:
2107 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
2108 chip
->ecc
.mode
= NAND_ECC_HW
;
2109 chip
->ecc
.size
= 512;
2110 /* 14th bit is kept reserved for ROM-code compatibility */
2111 chip
->ecc
.bytes
= 13 + 1;
2112 chip
->ecc
.strength
= 8;
2113 chip
->ecc
.hwctl
= omap_enable_hwecc_bch
;
2114 chip
->ecc
.correct
= omap_elm_correct_data
;
2115 chip
->ecc
.read_page
= omap_read_page_bch
;
2116 chip
->ecc
.write_page
= omap_write_page_bch
;
2117 chip
->ecc
.write_subpage
= omap_write_subpage_bch
;
2118 mtd_set_ooblayout(mtd
, &omap_ooblayout_ops
);
2119 oobbytes_per_step
= chip
->ecc
.bytes
;
2121 err
= elm_config(info
->elm_dev
, BCH8_ECC
,
2122 mtd
->writesize
/ chip
->ecc
.size
,
2123 chip
->ecc
.size
, chip
->ecc
.bytes
);
2129 case OMAP_ECC_BCH16_CODE_HW
:
2130 pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
2131 chip
->ecc
.mode
= NAND_ECC_HW
;
2132 chip
->ecc
.size
= 512;
2133 chip
->ecc
.bytes
= 26;
2134 chip
->ecc
.strength
= 16;
2135 chip
->ecc
.hwctl
= omap_enable_hwecc_bch
;
2136 chip
->ecc
.correct
= omap_elm_correct_data
;
2137 chip
->ecc
.read_page
= omap_read_page_bch
;
2138 chip
->ecc
.write_page
= omap_write_page_bch
;
2139 chip
->ecc
.write_subpage
= omap_write_subpage_bch
;
2140 mtd_set_ooblayout(mtd
, &omap_ooblayout_ops
);
2141 oobbytes_per_step
= chip
->ecc
.bytes
;
2143 err
= elm_config(info
->elm_dev
, BCH16_ECC
,
2144 mtd
->writesize
/ chip
->ecc
.size
,
2145 chip
->ecc
.size
, chip
->ecc
.bytes
);
2151 dev_err(dev
, "Invalid or unsupported ECC scheme\n");
2155 /* Check if NAND device's OOB is enough to store ECC signatures */
2156 min_oobbytes
+= (oobbytes_per_step
*
2157 (mtd
->writesize
/ chip
->ecc
.size
));
2158 if (mtd
->oobsize
< min_oobbytes
) {
2160 "Not enough OOB bytes: required = %d, available=%d\n",
2161 min_oobbytes
, mtd
->oobsize
);
2168 static const struct nand_controller_ops omap_nand_controller_ops
= {
2169 .attach_chip
= omap_nand_attach_chip
,
2172 /* Shared among all NAND instances to synchronize access to the ECC Engine */
2173 static struct nand_controller omap_gpmc_controller
;
2174 static bool omap_gpmc_controller_initialized
;
2176 static int omap_nand_probe(struct platform_device
*pdev
)
2178 struct omap_nand_info
*info
;
2179 struct mtd_info
*mtd
;
2180 struct nand_chip
*nand_chip
;
2182 struct resource
*res
;
2183 struct device
*dev
= &pdev
->dev
;
2185 info
= devm_kzalloc(&pdev
->dev
, sizeof(struct omap_nand_info
),
2192 err
= omap_get_dt_info(dev
, info
);
2196 info
->ops
= gpmc_omap_get_nand_ops(&info
->reg
, info
->gpmc_cs
);
2198 dev_err(&pdev
->dev
, "Failed to get GPMC->NAND interface\n");
2202 nand_chip
= &info
->nand
;
2203 mtd
= nand_to_mtd(nand_chip
);
2204 mtd
->dev
.parent
= &pdev
->dev
;
2205 nand_chip
->ecc
.priv
= NULL
;
2206 nand_set_flash_node(nand_chip
, dev
->of_node
);
2209 mtd
->name
= devm_kasprintf(&pdev
->dev
, GFP_KERNEL
,
2210 "omap2-nand.%d", info
->gpmc_cs
);
2212 dev_err(&pdev
->dev
, "Failed to set MTD name\n");
2217 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2218 nand_chip
->legacy
.IO_ADDR_R
= devm_ioremap_resource(&pdev
->dev
, res
);
2219 if (IS_ERR(nand_chip
->legacy
.IO_ADDR_R
))
2220 return PTR_ERR(nand_chip
->legacy
.IO_ADDR_R
);
2222 info
->phys_base
= res
->start
;
2224 if (!omap_gpmc_controller_initialized
) {
2225 omap_gpmc_controller
.ops
= &omap_nand_controller_ops
;
2226 nand_controller_init(&omap_gpmc_controller
);
2227 omap_gpmc_controller_initialized
= true;
2230 nand_chip
->controller
= &omap_gpmc_controller
;
2232 nand_chip
->legacy
.IO_ADDR_W
= nand_chip
->legacy
.IO_ADDR_R
;
2233 nand_chip
->legacy
.cmd_ctrl
= omap_hwcontrol
;
2235 info
->ready_gpiod
= devm_gpiod_get_optional(&pdev
->dev
, "rb",
2237 if (IS_ERR(info
->ready_gpiod
)) {
2238 dev_err(dev
, "failed to get ready gpio\n");
2239 return PTR_ERR(info
->ready_gpiod
);
2243 * If RDY/BSY line is connected to OMAP then use the omap ready
2244 * function and the generic nand_wait function which reads the status
2245 * register after monitoring the RDY/BSY line. Otherwise use a standard
2246 * chip delay which is slightly more than tR (AC Timing) of the NAND
2247 * device and read status register until you get a failure or success
2249 if (info
->ready_gpiod
) {
2250 nand_chip
->legacy
.dev_ready
= omap_dev_ready
;
2251 nand_chip
->legacy
.chip_delay
= 0;
2253 nand_chip
->legacy
.waitfunc
= omap_wait
;
2254 nand_chip
->legacy
.chip_delay
= 50;
2257 if (info
->flash_bbt
)
2258 nand_chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
2260 /* scan NAND device connected to chip controller */
2261 nand_chip
->options
|= info
->devsize
& NAND_BUSWIDTH_16
;
2263 err
= nand_scan(nand_chip
, 1);
2267 err
= mtd_device_register(mtd
, NULL
, 0);
2271 platform_set_drvdata(pdev
, mtd
);
2276 nand_cleanup(nand_chip
);
2279 if (!IS_ERR_OR_NULL(info
->dma
))
2280 dma_release_channel(info
->dma
);
2281 if (nand_chip
->ecc
.priv
) {
2282 nand_bch_free(nand_chip
->ecc
.priv
);
2283 nand_chip
->ecc
.priv
= NULL
;
2288 static int omap_nand_remove(struct platform_device
*pdev
)
2290 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
2291 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
2292 struct omap_nand_info
*info
= mtd_to_omap(mtd
);
2293 if (nand_chip
->ecc
.priv
) {
2294 nand_bch_free(nand_chip
->ecc
.priv
);
2295 nand_chip
->ecc
.priv
= NULL
;
2298 dma_release_channel(info
->dma
);
2299 nand_release(nand_chip
);
2303 static const struct of_device_id omap_nand_ids
[] = {
2304 { .compatible
= "ti,omap2-nand", },
2307 MODULE_DEVICE_TABLE(of
, omap_nand_ids
);
2309 static struct platform_driver omap_nand_driver
= {
2310 .probe
= omap_nand_probe
,
2311 .remove
= omap_nand_remove
,
2313 .name
= DRIVER_NAME
,
2314 .of_match_table
= of_match_ptr(omap_nand_ids
),
2318 module_platform_driver(omap_nand_driver
);
2320 MODULE_ALIAS("platform:" DRIVER_NAME
);
2321 MODULE_LICENSE("GPL");
2322 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");