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[mirror_ubuntu-zesty-kernel.git] / drivers / mtd / nand / sunxi_nand.c
1 /*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
3 *
4 * Derived from:
5 * https://github.com/yuq/sunxi-nfc-mtd
6 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
7 *
8 * https://github.com/hno/Allwinner-Info
9 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
10 *
11 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
12 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/platform_device.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mtd.h>
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/nand.h>
36 #include <linux/mtd/partitions.h>
37 #include <linux/clk.h>
38 #include <linux/delay.h>
39 #include <linux/dmaengine.h>
40 #include <linux/gpio.h>
41 #include <linux/interrupt.h>
42 #include <linux/io.h>
43
44 #define NFC_REG_CTL 0x0000
45 #define NFC_REG_ST 0x0004
46 #define NFC_REG_INT 0x0008
47 #define NFC_REG_TIMING_CTL 0x000C
48 #define NFC_REG_TIMING_CFG 0x0010
49 #define NFC_REG_ADDR_LOW 0x0014
50 #define NFC_REG_ADDR_HIGH 0x0018
51 #define NFC_REG_SECTOR_NUM 0x001C
52 #define NFC_REG_CNT 0x0020
53 #define NFC_REG_CMD 0x0024
54 #define NFC_REG_RCMD_SET 0x0028
55 #define NFC_REG_WCMD_SET 0x002C
56 #define NFC_REG_IO_DATA 0x0030
57 #define NFC_REG_ECC_CTL 0x0034
58 #define NFC_REG_ECC_ST 0x0038
59 #define NFC_REG_DEBUG 0x003C
60 #define NFC_REG_ECC_CNT0 0x0040
61 #define NFC_REG_ECC_CNT1 0x0044
62 #define NFC_REG_ECC_CNT2 0x0048
63 #define NFC_REG_ECC_CNT3 0x004c
64 #define NFC_REG_USER_DATA_BASE 0x0050
65 #define NFC_REG_SPARE_AREA 0x00A0
66 #define NFC_RAM0_BASE 0x0400
67 #define NFC_RAM1_BASE 0x0800
68
69 /* define bit use in NFC_CTL */
70 #define NFC_EN BIT(0)
71 #define NFC_RESET BIT(1)
72 #define NFC_BUS_WIDYH BIT(2)
73 #define NFC_RB_SEL BIT(3)
74 #define NFC_CE_SEL GENMASK(26, 24)
75 #define NFC_CE_CTL BIT(6)
76 #define NFC_CE_CTL1 BIT(7)
77 #define NFC_PAGE_SIZE GENMASK(11, 8)
78 #define NFC_SAM BIT(12)
79 #define NFC_RAM_METHOD BIT(14)
80 #define NFC_DEBUG_CTL BIT(31)
81
82 /* define bit use in NFC_ST */
83 #define NFC_RB_B2R BIT(0)
84 #define NFC_CMD_INT_FLAG BIT(1)
85 #define NFC_DMA_INT_FLAG BIT(2)
86 #define NFC_CMD_FIFO_STATUS BIT(3)
87 #define NFC_STA BIT(4)
88 #define NFC_NATCH_INT_FLAG BIT(5)
89 #define NFC_RB_STATE0 BIT(8)
90 #define NFC_RB_STATE1 BIT(9)
91 #define NFC_RB_STATE2 BIT(10)
92 #define NFC_RB_STATE3 BIT(11)
93
94 /* define bit use in NFC_INT */
95 #define NFC_B2R_INT_ENABLE BIT(0)
96 #define NFC_CMD_INT_ENABLE BIT(1)
97 #define NFC_DMA_INT_ENABLE BIT(2)
98 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
99 NFC_CMD_INT_ENABLE | \
100 NFC_DMA_INT_ENABLE)
101
102 /* define bit use in NFC_TIMING_CTL */
103 #define NFC_TIMING_CTL_EDO BIT(8)
104
105 /* define NFC_TIMING_CFG register layout */
106 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
107 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
108 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
109 (((tCAD) & 0x7) << 8))
110
111 /* define bit use in NFC_CMD */
112 #define NFC_CMD_LOW_BYTE GENMASK(7, 0)
113 #define NFC_CMD_HIGH_BYTE GENMASK(15, 8)
114 #define NFC_ADR_NUM GENMASK(18, 16)
115 #define NFC_SEND_ADR BIT(19)
116 #define NFC_ACCESS_DIR BIT(20)
117 #define NFC_DATA_TRANS BIT(21)
118 #define NFC_SEND_CMD1 BIT(22)
119 #define NFC_WAIT_FLAG BIT(23)
120 #define NFC_SEND_CMD2 BIT(24)
121 #define NFC_SEQ BIT(25)
122 #define NFC_DATA_SWAP_METHOD BIT(26)
123 #define NFC_ROW_AUTO_INC BIT(27)
124 #define NFC_SEND_CMD3 BIT(28)
125 #define NFC_SEND_CMD4 BIT(29)
126 #define NFC_CMD_TYPE GENMASK(31, 30)
127
128 /* define bit use in NFC_RCMD_SET */
129 #define NFC_READ_CMD GENMASK(7, 0)
130 #define NFC_RANDOM_READ_CMD0 GENMASK(15, 8)
131 #define NFC_RANDOM_READ_CMD1 GENMASK(23, 16)
132
133 /* define bit use in NFC_WCMD_SET */
134 #define NFC_PROGRAM_CMD GENMASK(7, 0)
135 #define NFC_RANDOM_WRITE_CMD GENMASK(15, 8)
136 #define NFC_READ_CMD0 GENMASK(23, 16)
137 #define NFC_READ_CMD1 GENMASK(31, 24)
138
139 /* define bit use in NFC_ECC_CTL */
140 #define NFC_ECC_EN BIT(0)
141 #define NFC_ECC_PIPELINE BIT(3)
142 #define NFC_ECC_EXCEPTION BIT(4)
143 #define NFC_ECC_BLOCK_SIZE BIT(5)
144 #define NFC_RANDOM_EN BIT(9)
145 #define NFC_RANDOM_DIRECTION BIT(10)
146 #define NFC_ECC_MODE_SHIFT 12
147 #define NFC_ECC_MODE GENMASK(15, 12)
148 #define NFC_RANDOM_SEED GENMASK(30, 16)
149
150 /* NFC_USER_DATA helper macros */
151 #define NFC_BUF_TO_USER_DATA(buf) ((buf)[0] | ((buf)[1] << 8) | \
152 ((buf)[2] << 16) | ((buf)[3] << 24))
153
154 #define NFC_DEFAULT_TIMEOUT_MS 1000
155
156 #define NFC_SRAM_SIZE 1024
157
158 #define NFC_MAX_CS 7
159
160 /*
161 * Ready/Busy detection type: describes the Ready/Busy detection modes
162 *
163 * @RB_NONE: no external detection available, rely on STATUS command
164 * and software timeouts
165 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
166 * pin of the NAND flash chip must be connected to one of the
167 * native NAND R/B pins (those which can be muxed to the NAND
168 * Controller)
169 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
170 * pin of the NAND flash chip must be connected to a GPIO capable
171 * pin.
172 */
173 enum sunxi_nand_rb_type {
174 RB_NONE,
175 RB_NATIVE,
176 RB_GPIO,
177 };
178
179 /*
180 * Ready/Busy structure: stores information related to Ready/Busy detection
181 *
182 * @type: the Ready/Busy detection mode
183 * @info: information related to the R/B detection mode. Either a gpio
184 * id or a native R/B id (those supported by the NAND controller).
185 */
186 struct sunxi_nand_rb {
187 enum sunxi_nand_rb_type type;
188 union {
189 int gpio;
190 int nativeid;
191 } info;
192 };
193
194 /*
195 * Chip Select structure: stores information related to NAND Chip Select
196 *
197 * @cs: the NAND CS id used to communicate with a NAND Chip
198 * @rb: the Ready/Busy description
199 */
200 struct sunxi_nand_chip_sel {
201 u8 cs;
202 struct sunxi_nand_rb rb;
203 };
204
205 /*
206 * sunxi HW ECC infos: stores information related to HW ECC support
207 *
208 * @mode: the sunxi ECC mode field deduced from ECC requirements
209 * @layout: the OOB layout depending on the ECC requirements and the
210 * selected ECC mode
211 */
212 struct sunxi_nand_hw_ecc {
213 int mode;
214 struct nand_ecclayout layout;
215 };
216
217 /*
218 * NAND chip structure: stores NAND chip device related information
219 *
220 * @node: used to store NAND chips into a list
221 * @nand: base NAND chip structure
222 * @mtd: base MTD structure
223 * @clk_rate: clk_rate required for this NAND chip
224 * @timing_cfg TIMING_CFG register value for this NAND chip
225 * @selected: current active CS
226 * @nsels: number of CS lines required by the NAND chip
227 * @sels: array of CS lines descriptions
228 */
229 struct sunxi_nand_chip {
230 struct list_head node;
231 struct nand_chip nand;
232 struct mtd_info mtd;
233 unsigned long clk_rate;
234 u32 timing_cfg;
235 u32 timing_ctl;
236 int selected;
237 int nsels;
238 struct sunxi_nand_chip_sel sels[0];
239 };
240
241 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
242 {
243 return container_of(nand, struct sunxi_nand_chip, nand);
244 }
245
246 /*
247 * NAND Controller structure: stores sunxi NAND controller information
248 *
249 * @controller: base controller structure
250 * @dev: parent device (used to print error messages)
251 * @regs: NAND controller registers
252 * @ahb_clk: NAND Controller AHB clock
253 * @mod_clk: NAND Controller mod clock
254 * @assigned_cs: bitmask describing already assigned CS lines
255 * @clk_rate: NAND controller current clock rate
256 * @chips: a list containing all the NAND chips attached to
257 * this NAND controller
258 * @complete: a completion object used to wait for NAND
259 * controller events
260 */
261 struct sunxi_nfc {
262 struct nand_hw_control controller;
263 struct device *dev;
264 void __iomem *regs;
265 struct clk *ahb_clk;
266 struct clk *mod_clk;
267 unsigned long assigned_cs;
268 unsigned long clk_rate;
269 struct list_head chips;
270 struct completion complete;
271 };
272
273 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
274 {
275 return container_of(ctrl, struct sunxi_nfc, controller);
276 }
277
278 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
279 {
280 struct sunxi_nfc *nfc = dev_id;
281 u32 st = readl(nfc->regs + NFC_REG_ST);
282 u32 ien = readl(nfc->regs + NFC_REG_INT);
283
284 if (!(ien & st))
285 return IRQ_NONE;
286
287 if ((ien & st) == ien)
288 complete(&nfc->complete);
289
290 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
291 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
292
293 return IRQ_HANDLED;
294 }
295
296 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
297 unsigned int timeout_ms)
298 {
299 init_completion(&nfc->complete);
300
301 writel(flags, nfc->regs + NFC_REG_INT);
302
303 if (!timeout_ms)
304 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
305
306 if (!wait_for_completion_timeout(&nfc->complete,
307 msecs_to_jiffies(timeout_ms))) {
308 dev_err(nfc->dev, "wait interrupt timedout\n");
309 return -ETIMEDOUT;
310 }
311
312 return 0;
313 }
314
315 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
316 {
317 unsigned long timeout = jiffies +
318 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
319
320 do {
321 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
322 return 0;
323 } while (time_before(jiffies, timeout));
324
325 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
326 return -ETIMEDOUT;
327 }
328
329 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
330 {
331 unsigned long timeout = jiffies +
332 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
333
334 writel(0, nfc->regs + NFC_REG_ECC_CTL);
335 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
336
337 do {
338 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
339 return 0;
340 } while (time_before(jiffies, timeout));
341
342 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
343 return -ETIMEDOUT;
344 }
345
346 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
347 {
348 struct nand_chip *nand = mtd->priv;
349 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
350 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
351 struct sunxi_nand_rb *rb;
352 unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
353 int ret;
354
355 if (sunxi_nand->selected < 0)
356 return 0;
357
358 rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
359
360 switch (rb->type) {
361 case RB_NATIVE:
362 ret = !!(readl(nfc->regs + NFC_REG_ST) &
363 (NFC_RB_STATE0 << rb->info.nativeid));
364 if (ret)
365 break;
366
367 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
368 ret = !!(readl(nfc->regs + NFC_REG_ST) &
369 (NFC_RB_STATE0 << rb->info.nativeid));
370 break;
371 case RB_GPIO:
372 ret = gpio_get_value(rb->info.gpio);
373 break;
374 case RB_NONE:
375 default:
376 ret = 0;
377 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
378 break;
379 }
380
381 return ret;
382 }
383
384 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
385 {
386 struct nand_chip *nand = mtd->priv;
387 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
388 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
389 struct sunxi_nand_chip_sel *sel;
390 u32 ctl;
391
392 if (chip > 0 && chip >= sunxi_nand->nsels)
393 return;
394
395 if (chip == sunxi_nand->selected)
396 return;
397
398 ctl = readl(nfc->regs + NFC_REG_CTL) &
399 ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN);
400
401 if (chip >= 0) {
402 sel = &sunxi_nand->sels[chip];
403
404 ctl |= (sel->cs << 24) | NFC_EN |
405 (((nand->page_shift - 10) & 0xf) << 8);
406 if (sel->rb.type == RB_NONE) {
407 nand->dev_ready = NULL;
408 } else {
409 nand->dev_ready = sunxi_nfc_dev_ready;
410 if (sel->rb.type == RB_NATIVE)
411 ctl |= (sel->rb.info.nativeid << 3);
412 }
413
414 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
415
416 if (nfc->clk_rate != sunxi_nand->clk_rate) {
417 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
418 nfc->clk_rate = sunxi_nand->clk_rate;
419 }
420 }
421
422 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
423 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
424 writel(ctl, nfc->regs + NFC_REG_CTL);
425
426 sunxi_nand->selected = chip;
427 }
428
429 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
430 {
431 struct nand_chip *nand = mtd->priv;
432 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
433 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
434 int ret;
435 int cnt;
436 int offs = 0;
437 u32 tmp;
438
439 while (len > offs) {
440 cnt = min(len - offs, NFC_SRAM_SIZE);
441
442 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
443 if (ret)
444 break;
445
446 writel(cnt, nfc->regs + NFC_REG_CNT);
447 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
448 writel(tmp, nfc->regs + NFC_REG_CMD);
449
450 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
451 if (ret)
452 break;
453
454 if (buf)
455 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
456 cnt);
457 offs += cnt;
458 }
459 }
460
461 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
462 int len)
463 {
464 struct nand_chip *nand = mtd->priv;
465 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
466 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
467 int ret;
468 int cnt;
469 int offs = 0;
470 u32 tmp;
471
472 while (len > offs) {
473 cnt = min(len - offs, NFC_SRAM_SIZE);
474
475 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
476 if (ret)
477 break;
478
479 writel(cnt, nfc->regs + NFC_REG_CNT);
480 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
481 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
482 NFC_ACCESS_DIR;
483 writel(tmp, nfc->regs + NFC_REG_CMD);
484
485 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
486 if (ret)
487 break;
488
489 offs += cnt;
490 }
491 }
492
493 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
494 {
495 uint8_t ret;
496
497 sunxi_nfc_read_buf(mtd, &ret, 1);
498
499 return ret;
500 }
501
502 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
503 unsigned int ctrl)
504 {
505 struct nand_chip *nand = mtd->priv;
506 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
507 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
508 int ret;
509 u32 tmp;
510
511 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
512 if (ret)
513 return;
514
515 if (ctrl & NAND_CTRL_CHANGE) {
516 tmp = readl(nfc->regs + NFC_REG_CTL);
517 if (ctrl & NAND_NCE)
518 tmp |= NFC_CE_CTL;
519 else
520 tmp &= ~NFC_CE_CTL;
521 writel(tmp, nfc->regs + NFC_REG_CTL);
522 }
523
524 if (dat == NAND_CMD_NONE)
525 return;
526
527 if (ctrl & NAND_CLE) {
528 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
529 } else {
530 writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
531 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
532 }
533
534 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
535 }
536
537 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
538 struct nand_chip *chip, uint8_t *buf,
539 int oob_required, int page)
540 {
541 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
542 struct nand_ecc_ctrl *ecc = &chip->ecc;
543 struct nand_ecclayout *layout = ecc->layout;
544 struct sunxi_nand_hw_ecc *data = ecc->priv;
545 unsigned int max_bitflips = 0;
546 int offset;
547 int ret;
548 u32 tmp;
549 int i;
550 int cnt;
551
552 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
553 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
554 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
555 NFC_ECC_EXCEPTION;
556
557 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
558
559 for (i = 0; i < ecc->steps; i++) {
560 if (i)
561 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i * ecc->size, -1);
562
563 offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4;
564
565 chip->read_buf(mtd, NULL, ecc->size);
566
567 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
568
569 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
570 if (ret)
571 return ret;
572
573 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
574 writel(tmp, nfc->regs + NFC_REG_CMD);
575
576 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
577 if (ret)
578 return ret;
579
580 memcpy_fromio(buf + (i * ecc->size),
581 nfc->regs + NFC_RAM0_BASE, ecc->size);
582
583 if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
584 mtd->ecc_stats.failed++;
585 } else {
586 tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
587 mtd->ecc_stats.corrected += tmp;
588 max_bitflips = max_t(unsigned int, max_bitflips, tmp);
589 }
590
591 if (oob_required) {
592 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
593
594 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
595 if (ret)
596 return ret;
597
598 offset -= mtd->writesize;
599 chip->read_buf(mtd, chip->oob_poi + offset,
600 ecc->bytes + 4);
601 }
602 }
603
604 if (oob_required) {
605 cnt = ecc->layout->oobfree[ecc->steps].length;
606 if (cnt > 0) {
607 offset = mtd->writesize +
608 ecc->layout->oobfree[ecc->steps].offset;
609 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
610 offset -= mtd->writesize;
611 chip->read_buf(mtd, chip->oob_poi + offset, cnt);
612 }
613 }
614
615 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
616 tmp &= ~NFC_ECC_EN;
617
618 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
619
620 return max_bitflips;
621 }
622
623 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
624 struct nand_chip *chip,
625 const uint8_t *buf, int oob_required)
626 {
627 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
628 struct nand_ecc_ctrl *ecc = &chip->ecc;
629 struct nand_ecclayout *layout = ecc->layout;
630 struct sunxi_nand_hw_ecc *data = ecc->priv;
631 int offset;
632 int ret;
633 u32 tmp;
634 int i;
635 int cnt;
636
637 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
638 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
639 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
640 NFC_ECC_EXCEPTION;
641
642 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
643
644 for (i = 0; i < ecc->steps; i++) {
645 if (i)
646 chip->cmdfunc(mtd, NAND_CMD_RNDIN, i * ecc->size, -1);
647
648 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
649
650 offset = layout->eccpos[i * ecc->bytes] - 4 + mtd->writesize;
651
652 /* Fill OOB data in */
653 writel(NFC_BUF_TO_USER_DATA(chip->oob_poi +
654 layout->oobfree[i].offset),
655 nfc->regs + NFC_REG_USER_DATA_BASE);
656
657 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
658
659 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
660 if (ret)
661 return ret;
662
663 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
664 (1 << 30);
665 writel(tmp, nfc->regs + NFC_REG_CMD);
666 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
667 if (ret)
668 return ret;
669 }
670
671 if (oob_required) {
672 cnt = ecc->layout->oobfree[i].length;
673 if (cnt > 0) {
674 offset = mtd->writesize +
675 ecc->layout->oobfree[i].offset;
676 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
677 offset -= mtd->writesize;
678 chip->write_buf(mtd, chip->oob_poi + offset, cnt);
679 }
680 }
681
682 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
683 tmp &= ~NFC_ECC_EN;
684
685 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
686
687 return 0;
688 }
689
690 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
691 struct nand_chip *chip,
692 uint8_t *buf, int oob_required,
693 int page)
694 {
695 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
696 struct nand_ecc_ctrl *ecc = &chip->ecc;
697 struct sunxi_nand_hw_ecc *data = ecc->priv;
698 unsigned int max_bitflips = 0;
699 uint8_t *oob = chip->oob_poi;
700 int offset = 0;
701 int ret;
702 int cnt;
703 u32 tmp;
704 int i;
705
706 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
707 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
708 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
709 NFC_ECC_EXCEPTION;
710
711 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
712
713 for (i = 0; i < ecc->steps; i++) {
714 chip->read_buf(mtd, NULL, ecc->size);
715
716 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
717 writel(tmp, nfc->regs + NFC_REG_CMD);
718
719 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
720 if (ret)
721 return ret;
722
723 memcpy_fromio(buf, nfc->regs + NFC_RAM0_BASE, ecc->size);
724 buf += ecc->size;
725 offset += ecc->size;
726
727 if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
728 mtd->ecc_stats.failed++;
729 } else {
730 tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
731 mtd->ecc_stats.corrected += tmp;
732 max_bitflips = max_t(unsigned int, max_bitflips, tmp);
733 }
734
735 if (oob_required) {
736 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
737 chip->read_buf(mtd, oob, ecc->bytes + ecc->prepad);
738 oob += ecc->bytes + ecc->prepad;
739 }
740
741 offset += ecc->bytes + ecc->prepad;
742 }
743
744 if (oob_required) {
745 cnt = mtd->oobsize - (oob - chip->oob_poi);
746 if (cnt > 0) {
747 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
748 chip->read_buf(mtd, oob, cnt);
749 }
750 }
751
752 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
753 nfc->regs + NFC_REG_ECC_CTL);
754
755 return max_bitflips;
756 }
757
758 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
759 struct nand_chip *chip,
760 const uint8_t *buf,
761 int oob_required)
762 {
763 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
764 struct nand_ecc_ctrl *ecc = &chip->ecc;
765 struct sunxi_nand_hw_ecc *data = ecc->priv;
766 uint8_t *oob = chip->oob_poi;
767 int offset = 0;
768 int ret;
769 int cnt;
770 u32 tmp;
771 int i;
772
773 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
774 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
775 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
776 NFC_ECC_EXCEPTION;
777
778 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
779
780 for (i = 0; i < ecc->steps; i++) {
781 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
782 offset += ecc->size;
783
784 /* Fill OOB data in */
785 writel(NFC_BUF_TO_USER_DATA(oob),
786 nfc->regs + NFC_REG_USER_DATA_BASE);
787
788 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
789 (1 << 30);
790 writel(tmp, nfc->regs + NFC_REG_CMD);
791
792 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
793 if (ret)
794 return ret;
795
796 offset += ecc->bytes + ecc->prepad;
797 oob += ecc->bytes + ecc->prepad;
798 }
799
800 if (oob_required) {
801 cnt = mtd->oobsize - (oob - chip->oob_poi);
802 if (cnt > 0) {
803 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
804 chip->write_buf(mtd, oob, cnt);
805 }
806 }
807
808 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
809 tmp &= ~NFC_ECC_EN;
810
811 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
812
813 return 0;
814 }
815
816 static const s32 tWB_lut[] = {6, 12, 16, 20};
817 static const s32 tRHW_lut[] = {4, 8, 12, 20};
818
819 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
820 u32 clk_period)
821 {
822 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
823 int i;
824
825 for (i = 0; i < lut_size; i++) {
826 if (clk_cycles <= lut[i])
827 return i;
828 }
829
830 /* Doesn't fit */
831 return -EINVAL;
832 }
833
834 #define sunxi_nand_lookup_timing(l, p, c) \
835 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
836
837 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
838 const struct nand_sdr_timings *timings)
839 {
840 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
841 u32 min_clk_period = 0;
842 s32 tWB, tADL, tWHR, tRHW, tCAD;
843
844 /* T1 <=> tCLS */
845 if (timings->tCLS_min > min_clk_period)
846 min_clk_period = timings->tCLS_min;
847
848 /* T2 <=> tCLH */
849 if (timings->tCLH_min > min_clk_period)
850 min_clk_period = timings->tCLH_min;
851
852 /* T3 <=> tCS */
853 if (timings->tCS_min > min_clk_period)
854 min_clk_period = timings->tCS_min;
855
856 /* T4 <=> tCH */
857 if (timings->tCH_min > min_clk_period)
858 min_clk_period = timings->tCH_min;
859
860 /* T5 <=> tWP */
861 if (timings->tWP_min > min_clk_period)
862 min_clk_period = timings->tWP_min;
863
864 /* T6 <=> tWH */
865 if (timings->tWH_min > min_clk_period)
866 min_clk_period = timings->tWH_min;
867
868 /* T7 <=> tALS */
869 if (timings->tALS_min > min_clk_period)
870 min_clk_period = timings->tALS_min;
871
872 /* T8 <=> tDS */
873 if (timings->tDS_min > min_clk_period)
874 min_clk_period = timings->tDS_min;
875
876 /* T9 <=> tDH */
877 if (timings->tDH_min > min_clk_period)
878 min_clk_period = timings->tDH_min;
879
880 /* T10 <=> tRR */
881 if (timings->tRR_min > (min_clk_period * 3))
882 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
883
884 /* T11 <=> tALH */
885 if (timings->tALH_min > min_clk_period)
886 min_clk_period = timings->tALH_min;
887
888 /* T12 <=> tRP */
889 if (timings->tRP_min > min_clk_period)
890 min_clk_period = timings->tRP_min;
891
892 /* T13 <=> tREH */
893 if (timings->tREH_min > min_clk_period)
894 min_clk_period = timings->tREH_min;
895
896 /* T14 <=> tRC */
897 if (timings->tRC_min > (min_clk_period * 2))
898 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
899
900 /* T15 <=> tWC */
901 if (timings->tWC_min > (min_clk_period * 2))
902 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
903
904 /* T16 - T19 + tCAD */
905 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
906 min_clk_period);
907 if (tWB < 0) {
908 dev_err(nfc->dev, "unsupported tWB\n");
909 return tWB;
910 }
911
912 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
913 if (tADL > 3) {
914 dev_err(nfc->dev, "unsupported tADL\n");
915 return -EINVAL;
916 }
917
918 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
919 if (tWHR > 3) {
920 dev_err(nfc->dev, "unsupported tWHR\n");
921 return -EINVAL;
922 }
923
924 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
925 min_clk_period);
926 if (tRHW < 0) {
927 dev_err(nfc->dev, "unsupported tRHW\n");
928 return tRHW;
929 }
930
931 /*
932 * TODO: according to ONFI specs this value only applies for DDR NAND,
933 * but Allwinner seems to set this to 0x7. Mimic them for now.
934 */
935 tCAD = 0x7;
936
937 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
938 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
939
940 /*
941 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
942 * output cycle timings shall be used if the host drives tRC less than
943 * 30 ns.
944 */
945 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
946
947 /* Convert min_clk_period from picoseconds to nanoseconds */
948 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
949
950 /*
951 * Convert min_clk_period into a clk frequency, then get the
952 * appropriate rate for the NAND controller IP given this formula
953 * (specified in the datasheet):
954 * nand clk_rate = 2 * min_clk_rate
955 */
956 chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
957
958 return 0;
959 }
960
961 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
962 struct device_node *np)
963 {
964 const struct nand_sdr_timings *timings;
965 int ret;
966 int mode;
967
968 mode = onfi_get_async_timing_mode(&chip->nand);
969 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
970 mode = chip->nand.onfi_timing_mode_default;
971 } else {
972 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
973
974 mode = fls(mode) - 1;
975 if (mode < 0)
976 mode = 0;
977
978 feature[0] = mode;
979 ret = chip->nand.onfi_set_features(&chip->mtd, &chip->nand,
980 ONFI_FEATURE_ADDR_TIMING_MODE,
981 feature);
982 if (ret)
983 return ret;
984 }
985
986 timings = onfi_async_timing_mode_to_sdr_timings(mode);
987 if (IS_ERR(timings))
988 return PTR_ERR(timings);
989
990 return sunxi_nand_chip_set_timings(chip, timings);
991 }
992
993 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
994 struct nand_ecc_ctrl *ecc,
995 struct device_node *np)
996 {
997 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
998 struct nand_chip *nand = mtd->priv;
999 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1000 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1001 struct sunxi_nand_hw_ecc *data;
1002 struct nand_ecclayout *layout;
1003 int nsectors;
1004 int ret;
1005 int i;
1006
1007 data = kzalloc(sizeof(*data), GFP_KERNEL);
1008 if (!data)
1009 return -ENOMEM;
1010
1011 /* Add ECC info retrieval from DT */
1012 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1013 if (ecc->strength <= strengths[i])
1014 break;
1015 }
1016
1017 if (i >= ARRAY_SIZE(strengths)) {
1018 dev_err(nfc->dev, "unsupported strength\n");
1019 ret = -ENOTSUPP;
1020 goto err;
1021 }
1022
1023 data->mode = i;
1024
1025 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1026 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1027
1028 /* HW ECC always work with even numbers of ECC bytes */
1029 ecc->bytes = ALIGN(ecc->bytes, 2);
1030
1031 layout = &data->layout;
1032 nsectors = mtd->writesize / ecc->size;
1033
1034 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1035 ret = -EINVAL;
1036 goto err;
1037 }
1038
1039 layout->eccbytes = (ecc->bytes * nsectors);
1040
1041 ecc->layout = layout;
1042 ecc->priv = data;
1043
1044 return 0;
1045
1046 err:
1047 kfree(data);
1048
1049 return ret;
1050 }
1051
1052 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1053 {
1054 kfree(ecc->priv);
1055 }
1056
1057 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1058 struct nand_ecc_ctrl *ecc,
1059 struct device_node *np)
1060 {
1061 struct nand_ecclayout *layout;
1062 int nsectors;
1063 int i, j;
1064 int ret;
1065
1066 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1067 if (ret)
1068 return ret;
1069
1070 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1071 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1072 layout = ecc->layout;
1073 nsectors = mtd->writesize / ecc->size;
1074
1075 for (i = 0; i < nsectors; i++) {
1076 if (i) {
1077 layout->oobfree[i].offset =
1078 layout->oobfree[i - 1].offset +
1079 layout->oobfree[i - 1].length +
1080 ecc->bytes;
1081 layout->oobfree[i].length = 4;
1082 } else {
1083 /*
1084 * The first 2 bytes are used for BB markers, hence we
1085 * only have 2 bytes available in the first user data
1086 * section.
1087 */
1088 layout->oobfree[i].length = 2;
1089 layout->oobfree[i].offset = 2;
1090 }
1091
1092 for (j = 0; j < ecc->bytes; j++)
1093 layout->eccpos[(ecc->bytes * i) + j] =
1094 layout->oobfree[i].offset +
1095 layout->oobfree[i].length + j;
1096 }
1097
1098 if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1099 layout->oobfree[nsectors].offset =
1100 layout->oobfree[nsectors - 1].offset +
1101 layout->oobfree[nsectors - 1].length +
1102 ecc->bytes;
1103 layout->oobfree[nsectors].length = mtd->oobsize -
1104 ((ecc->bytes + 4) * nsectors);
1105 }
1106
1107 return 0;
1108 }
1109
1110 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1111 struct nand_ecc_ctrl *ecc,
1112 struct device_node *np)
1113 {
1114 struct nand_ecclayout *layout;
1115 int nsectors;
1116 int i;
1117 int ret;
1118
1119 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1120 if (ret)
1121 return ret;
1122
1123 ecc->prepad = 4;
1124 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1125 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1126
1127 layout = ecc->layout;
1128 nsectors = mtd->writesize / ecc->size;
1129
1130 for (i = 0; i < (ecc->bytes * nsectors); i++)
1131 layout->eccpos[i] = i;
1132
1133 layout->oobfree[0].length = mtd->oobsize - i;
1134 layout->oobfree[0].offset = i;
1135
1136 return 0;
1137 }
1138
1139 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1140 {
1141 switch (ecc->mode) {
1142 case NAND_ECC_HW:
1143 case NAND_ECC_HW_SYNDROME:
1144 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1145 break;
1146 case NAND_ECC_NONE:
1147 kfree(ecc->layout);
1148 default:
1149 break;
1150 }
1151 }
1152
1153 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1154 struct device_node *np)
1155 {
1156 struct nand_chip *nand = mtd->priv;
1157 int strength;
1158 int blk_size;
1159 int ret;
1160
1161 blk_size = of_get_nand_ecc_step_size(np);
1162 strength = of_get_nand_ecc_strength(np);
1163 if (blk_size > 0 && strength > 0) {
1164 ecc->size = blk_size;
1165 ecc->strength = strength;
1166 } else {
1167 ecc->size = nand->ecc_step_ds;
1168 ecc->strength = nand->ecc_strength_ds;
1169 }
1170
1171 if (!ecc->size || !ecc->strength)
1172 return -EINVAL;
1173
1174 ecc->mode = NAND_ECC_HW;
1175
1176 ret = of_get_nand_ecc_mode(np);
1177 if (ret >= 0)
1178 ecc->mode = ret;
1179
1180 switch (ecc->mode) {
1181 case NAND_ECC_SOFT_BCH:
1182 break;
1183 case NAND_ECC_HW:
1184 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1185 if (ret)
1186 return ret;
1187 break;
1188 case NAND_ECC_HW_SYNDROME:
1189 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1190 if (ret)
1191 return ret;
1192 break;
1193 case NAND_ECC_NONE:
1194 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1195 if (!ecc->layout)
1196 return -ENOMEM;
1197 ecc->layout->oobfree[0].length = mtd->oobsize;
1198 case NAND_ECC_SOFT:
1199 break;
1200 default:
1201 return -EINVAL;
1202 }
1203
1204 return 0;
1205 }
1206
1207 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1208 struct device_node *np)
1209 {
1210 const struct nand_sdr_timings *timings;
1211 struct sunxi_nand_chip *chip;
1212 struct mtd_part_parser_data ppdata;
1213 struct mtd_info *mtd;
1214 struct nand_chip *nand;
1215 int nsels;
1216 int ret;
1217 int i;
1218 u32 tmp;
1219
1220 if (!of_get_property(np, "reg", &nsels))
1221 return -EINVAL;
1222
1223 nsels /= sizeof(u32);
1224 if (!nsels) {
1225 dev_err(dev, "invalid reg property size\n");
1226 return -EINVAL;
1227 }
1228
1229 chip = devm_kzalloc(dev,
1230 sizeof(*chip) +
1231 (nsels * sizeof(struct sunxi_nand_chip_sel)),
1232 GFP_KERNEL);
1233 if (!chip) {
1234 dev_err(dev, "could not allocate chip\n");
1235 return -ENOMEM;
1236 }
1237
1238 chip->nsels = nsels;
1239 chip->selected = -1;
1240
1241 for (i = 0; i < nsels; i++) {
1242 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1243 if (ret) {
1244 dev_err(dev, "could not retrieve reg property: %d\n",
1245 ret);
1246 return ret;
1247 }
1248
1249 if (tmp > NFC_MAX_CS) {
1250 dev_err(dev,
1251 "invalid reg value: %u (max CS = 7)\n",
1252 tmp);
1253 return -EINVAL;
1254 }
1255
1256 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1257 dev_err(dev, "CS %d already assigned\n", tmp);
1258 return -EINVAL;
1259 }
1260
1261 chip->sels[i].cs = tmp;
1262
1263 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1264 tmp < 2) {
1265 chip->sels[i].rb.type = RB_NATIVE;
1266 chip->sels[i].rb.info.nativeid = tmp;
1267 } else {
1268 ret = of_get_named_gpio(np, "rb-gpios", i);
1269 if (ret >= 0) {
1270 tmp = ret;
1271 chip->sels[i].rb.type = RB_GPIO;
1272 chip->sels[i].rb.info.gpio = tmp;
1273 ret = devm_gpio_request(dev, tmp, "nand-rb");
1274 if (ret)
1275 return ret;
1276
1277 ret = gpio_direction_input(tmp);
1278 if (ret)
1279 return ret;
1280 } else {
1281 chip->sels[i].rb.type = RB_NONE;
1282 }
1283 }
1284 }
1285
1286 timings = onfi_async_timing_mode_to_sdr_timings(0);
1287 if (IS_ERR(timings)) {
1288 ret = PTR_ERR(timings);
1289 dev_err(dev,
1290 "could not retrieve timings for ONFI mode 0: %d\n",
1291 ret);
1292 return ret;
1293 }
1294
1295 ret = sunxi_nand_chip_set_timings(chip, timings);
1296 if (ret) {
1297 dev_err(dev, "could not configure chip timings: %d\n", ret);
1298 return ret;
1299 }
1300
1301 nand = &chip->nand;
1302 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1303 nand->chip_delay = 200;
1304 nand->controller = &nfc->controller;
1305 nand->select_chip = sunxi_nfc_select_chip;
1306 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1307 nand->read_buf = sunxi_nfc_read_buf;
1308 nand->write_buf = sunxi_nfc_write_buf;
1309 nand->read_byte = sunxi_nfc_read_byte;
1310
1311 if (of_get_nand_on_flash_bbt(np))
1312 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1313
1314 mtd = &chip->mtd;
1315 mtd->dev.parent = dev;
1316 mtd->priv = nand;
1317 mtd->owner = THIS_MODULE;
1318
1319 ret = nand_scan_ident(mtd, nsels, NULL);
1320 if (ret)
1321 return ret;
1322
1323 ret = sunxi_nand_chip_init_timings(chip, np);
1324 if (ret) {
1325 dev_err(dev, "could not configure chip timings: %d\n", ret);
1326 return ret;
1327 }
1328
1329 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1330 if (ret) {
1331 dev_err(dev, "ECC init failed: %d\n", ret);
1332 return ret;
1333 }
1334
1335 ret = nand_scan_tail(mtd);
1336 if (ret) {
1337 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1338 return ret;
1339 }
1340
1341 ppdata.of_node = np;
1342 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1343 if (ret) {
1344 dev_err(dev, "failed to register mtd device: %d\n", ret);
1345 nand_release(mtd);
1346 return ret;
1347 }
1348
1349 list_add_tail(&chip->node, &nfc->chips);
1350
1351 return 0;
1352 }
1353
1354 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1355 {
1356 struct device_node *np = dev->of_node;
1357 struct device_node *nand_np;
1358 int nchips = of_get_child_count(np);
1359 int ret;
1360
1361 if (nchips > 8) {
1362 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1363 return -EINVAL;
1364 }
1365
1366 for_each_child_of_node(np, nand_np) {
1367 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1368 if (ret)
1369 return ret;
1370 }
1371
1372 return 0;
1373 }
1374
1375 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1376 {
1377 struct sunxi_nand_chip *chip;
1378
1379 while (!list_empty(&nfc->chips)) {
1380 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1381 node);
1382 nand_release(&chip->mtd);
1383 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1384 list_del(&chip->node);
1385 }
1386 }
1387
1388 static int sunxi_nfc_probe(struct platform_device *pdev)
1389 {
1390 struct device *dev = &pdev->dev;
1391 struct resource *r;
1392 struct sunxi_nfc *nfc;
1393 int irq;
1394 int ret;
1395
1396 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1397 if (!nfc)
1398 return -ENOMEM;
1399
1400 nfc->dev = dev;
1401 spin_lock_init(&nfc->controller.lock);
1402 init_waitqueue_head(&nfc->controller.wq);
1403 INIT_LIST_HEAD(&nfc->chips);
1404
1405 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1406 nfc->regs = devm_ioremap_resource(dev, r);
1407 if (IS_ERR(nfc->regs))
1408 return PTR_ERR(nfc->regs);
1409
1410 irq = platform_get_irq(pdev, 0);
1411 if (irq < 0) {
1412 dev_err(dev, "failed to retrieve irq\n");
1413 return irq;
1414 }
1415
1416 nfc->ahb_clk = devm_clk_get(dev, "ahb");
1417 if (IS_ERR(nfc->ahb_clk)) {
1418 dev_err(dev, "failed to retrieve ahb clk\n");
1419 return PTR_ERR(nfc->ahb_clk);
1420 }
1421
1422 ret = clk_prepare_enable(nfc->ahb_clk);
1423 if (ret)
1424 return ret;
1425
1426 nfc->mod_clk = devm_clk_get(dev, "mod");
1427 if (IS_ERR(nfc->mod_clk)) {
1428 dev_err(dev, "failed to retrieve mod clk\n");
1429 ret = PTR_ERR(nfc->mod_clk);
1430 goto out_ahb_clk_unprepare;
1431 }
1432
1433 ret = clk_prepare_enable(nfc->mod_clk);
1434 if (ret)
1435 goto out_ahb_clk_unprepare;
1436
1437 ret = sunxi_nfc_rst(nfc);
1438 if (ret)
1439 goto out_mod_clk_unprepare;
1440
1441 writel(0, nfc->regs + NFC_REG_INT);
1442 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1443 0, "sunxi-nand", nfc);
1444 if (ret)
1445 goto out_mod_clk_unprepare;
1446
1447 platform_set_drvdata(pdev, nfc);
1448
1449 ret = sunxi_nand_chips_init(dev, nfc);
1450 if (ret) {
1451 dev_err(dev, "failed to init nand chips\n");
1452 goto out_mod_clk_unprepare;
1453 }
1454
1455 return 0;
1456
1457 out_mod_clk_unprepare:
1458 clk_disable_unprepare(nfc->mod_clk);
1459 out_ahb_clk_unprepare:
1460 clk_disable_unprepare(nfc->ahb_clk);
1461
1462 return ret;
1463 }
1464
1465 static int sunxi_nfc_remove(struct platform_device *pdev)
1466 {
1467 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1468
1469 sunxi_nand_chips_cleanup(nfc);
1470
1471 return 0;
1472 }
1473
1474 static const struct of_device_id sunxi_nfc_ids[] = {
1475 { .compatible = "allwinner,sun4i-a10-nand" },
1476 { /* sentinel */ }
1477 };
1478 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1479
1480 static struct platform_driver sunxi_nfc_driver = {
1481 .driver = {
1482 .name = "sunxi_nand",
1483 .of_match_table = sunxi_nfc_ids,
1484 },
1485 .probe = sunxi_nfc_probe,
1486 .remove = sunxi_nfc_remove,
1487 };
1488 module_platform_driver(sunxi_nfc_driver);
1489
1490 MODULE_LICENSE("GPL v2");
1491 MODULE_AUTHOR("Boris BREZILLON");
1492 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1493 MODULE_ALIAS("platform:sunxi_nand");
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