drivers/mtd/nand/txx9ndfmc.c

   1 /*
   2  * TXx9 NAND flash memory controller driver
   3  * Based on RBTX49xx patch from CELF patch archive.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * (C) Copyright TOSHIBA CORPORATION 2004-2007
  10  * All Rights Reserved.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/nand_ecc.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/io.h>
  22 #include <asm/txx9/ndfmc.h>
  23
  24 /* TXX9 NDFMC Registers */
  25 #define TXX9_NDFDTR     0x00
  26 #define TXX9_NDFMCR     0x04
  27 #define TXX9_NDFSR      0x08
  28 #define TXX9_NDFISR     0x0c
  29 #define TXX9_NDFIMR     0x10
  30 #define TXX9_NDFSPR     0x14
  31 #define TXX9_NDFRSTR    0x18    /* not TX4939 */
  32
  33 /* NDFMCR : NDFMC Mode Control */
  34 #define TXX9_NDFMCR_WE  0x80
  35 #define TXX9_NDFMCR_ECC_ALL     0x60
  36 #define TXX9_NDFMCR_ECC_RESET   0x60
  37 #define TXX9_NDFMCR_ECC_READ    0x40
  38 #define TXX9_NDFMCR_ECC_ON      0x20
  39 #define TXX9_NDFMCR_ECC_OFF     0x00
  40 #define TXX9_NDFMCR_CE  0x10
  41 #define TXX9_NDFMCR_BSPRT       0x04    /* TX4925/TX4926 only */
  42 #define TXX9_NDFMCR_ALE 0x02
  43 #define TXX9_NDFMCR_CLE 0x01
  44 /* TX4939 only */
  45 #define TXX9_NDFMCR_X16 0x0400
  46 #define TXX9_NDFMCR_DMAREQ_MASK 0x0300
  47 #define TXX9_NDFMCR_DMAREQ_NODMA        0x0000
  48 #define TXX9_NDFMCR_DMAREQ_128  0x0100
  49 #define TXX9_NDFMCR_DMAREQ_256  0x0200
  50 #define TXX9_NDFMCR_DMAREQ_512  0x0300
  51 #define TXX9_NDFMCR_CS_MASK     0x0c
  52 #define TXX9_NDFMCR_CS(ch)      ((ch) << 2)
  53
  54 /* NDFMCR : NDFMC Status */
  55 #define TXX9_NDFSR_BUSY 0x80
  56 /* TX4939 only */
  57 #define TXX9_NDFSR_DMARUN       0x40
  58
  59 /* NDFMCR : NDFMC Reset */
  60 #define TXX9_NDFRSTR_RST        0x01
  61
  62 struct txx9ndfmc_priv {
  63         struct platform_device *dev;
  64         struct nand_chip chip;
  65         struct mtd_info mtd;
  66         int cs;
  67         const char *mtdname;
  68 };
  69
  70 #define MAX_TXX9NDFMC_DEV       4
  71 struct txx9ndfmc_drvdata {
  72         struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
  73         void __iomem *base;
  74         unsigned char hold;     /* in gbusclock */
  75         unsigned char spw;      /* in gbusclock */
  76         struct nand_hw_control hw_control;
  77         struct mtd_partition *parts[MAX_TXX9NDFMC_DEV];
  78 };
  79
  80 static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
  81 {
  82         struct nand_chip *chip = mtd->priv;
  83         struct txx9ndfmc_priv *txx9_priv = chip->priv;
  84         return txx9_priv->dev;
  85 }
  86
  87 static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
  88 {
  89         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
  90         struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
  91
  92         return drvdata->base + (reg << plat->shift);
  93 }
  94
  95 static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
  96 {
  97         return __raw_readl(ndregaddr(dev, reg));
  98 }
  99
 100 static void txx9ndfmc_write(struct platform_device *dev,
 101                             u32 val, unsigned int reg)
 102 {
 103         __raw_writel(val, ndregaddr(dev, reg));
 104 }
 105
 106 static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
 107 {
 108         struct platform_device *dev = mtd_to_platdev(mtd);
 109
 110         return txx9ndfmc_read(dev, TXX9_NDFDTR);
 111 }
 112
 113 static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 114                                 int len)
 115 {
 116         struct platform_device *dev = mtd_to_platdev(mtd);
 117         void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
 118         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
 119
 120         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
 121         while (len--)
 122                 __raw_writel(*buf++, ndfdtr);
 123         txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
 124 }
 125
 126 static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 127 {
 128         struct platform_device *dev = mtd_to_platdev(mtd);
 129         void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
 130
 131         while (len--)
 132                 *buf++ = __raw_readl(ndfdtr);
 133 }
 134
 135 static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
 136                                 int len)
 137 {
 138         struct platform_device *dev = mtd_to_platdev(mtd);
 139         void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
 140
 141         while (len--)
 142                 if (*buf++ != (uint8_t)__raw_readl(ndfdtr))
 143                         return -EFAULT;
 144         return 0;
 145 }
 146
 147 static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
 148                                unsigned int ctrl)
 149 {
 150         struct nand_chip *chip = mtd->priv;
 151         struct txx9ndfmc_priv *txx9_priv = chip->priv;
 152         struct platform_device *dev = txx9_priv->dev;
 153         struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
 154
 155         if (ctrl & NAND_CTRL_CHANGE) {
 156                 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
 157
 158                 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
 159                 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
 160                 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
 161                 /* TXX9_NDFMCR_CE bit is 0:high 1:low */
 162                 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
 163                 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
 164                         mcr &= ~TXX9_NDFMCR_CS_MASK;
 165                         mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
 166                 }
 167                 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
 168         }
 169         if (cmd != NAND_CMD_NONE)
 170                 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
 171         if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
 172                 /* dummy write to update external latch */
 173                 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
 174                         txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
 175         }
 176         mmiowb();
 177 }
 178
 179 static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
 180 {
 181         struct platform_device *dev = mtd_to_platdev(mtd);
 182
 183         return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
 184 }
 185
 186 static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 187                                    uint8_t *ecc_code)
 188 {
 189         struct platform_device *dev = mtd_to_platdev(mtd);
 190         struct nand_chip *chip = mtd->priv;
 191         int eccbytes;
 192         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
 193
 194         mcr &= ~TXX9_NDFMCR_ECC_ALL;
 195         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
 196         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
 197         for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
 198                 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
 199                 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
 200                 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
 201                 ecc_code += 3;
 202         }
 203         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
 204         return 0;
 205 }
 206
 207 static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
 208                 unsigned char *read_ecc, unsigned char *calc_ecc)
 209 {
 210         struct nand_chip *chip = mtd->priv;
 211         int eccsize;
 212         int corrected = 0;
 213         int stat;
 214
 215         for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
 216                 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
 217                 if (stat < 0)
 218                         return stat;
 219                 corrected += stat;
 220                 buf += 256;
 221                 read_ecc += 3;
 222                 calc_ecc += 3;
 223         }
 224         return corrected;
 225 }
 226
 227 static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
 228 {
 229         struct platform_device *dev = mtd_to_platdev(mtd);
 230         u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
 231
 232         mcr &= ~TXX9_NDFMCR_ECC_ALL;
 233         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
 234         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
 235         txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
 236 }
 237
 238 static void txx9ndfmc_initialize(struct platform_device *dev)
 239 {
 240         struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
 241         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
 242         int tmout = 100;
 243
 244         if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
 245                 ; /* no NDFRSTR.  Write to NDFSPR resets the NDFMC. */
 246         else {
 247                 /* reset NDFMC */
 248                 txx9ndfmc_write(dev,
 249                                 txx9ndfmc_read(dev, TXX9_NDFRSTR) |
 250                                 TXX9_NDFRSTR_RST,
 251                                 TXX9_NDFRSTR);
 252                 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
 253                         if (--tmout == 0) {
 254                                 dev_err(&dev->dev, "reset failed.\n");
 255                                 break;
 256                         }
 257                         udelay(1);
 258                 }
 259         }
 260         /* setup Hold Time, Strobe Pulse Width */
 261         txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
 262         txx9ndfmc_write(dev,
 263                         (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
 264                         TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
 265 }
 266
 267 #define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
 268         DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
 269
 270 static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
 271 {
 272         struct nand_chip *chip = mtd->priv;
 273         int ret;
 274
 275         ret = nand_scan_ident(mtd, 1, NULL);
 276         if (!ret) {
 277                 if (mtd->writesize >= 512) {
 278                         /* Hardware ECC 6 byte ECC per 512 Byte data */
 279                         chip->ecc.size = 512;
 280                         chip->ecc.bytes = 6;
 281                 }
 282                 ret = nand_scan_tail(mtd);
 283         }
 284         return ret;
 285 }
 286
 287 static int __init txx9ndfmc_probe(struct platform_device *dev)
 288 {
 289         struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
 290         static const char *probes[] = { "cmdlinepart", NULL };
 291         int hold, spw;
 292         int i;
 293         struct txx9ndfmc_drvdata *drvdata;
 294         unsigned long gbusclk = plat->gbus_clock;
 295         struct resource *res;
 296
 297         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 298         if (!res)
 299                 return -ENODEV;
 300         drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
 301         if (!drvdata)
 302                 return -ENOMEM;
 303         if (!devm_request_mem_region(&dev->dev, res->start,
 304                                      resource_size(res), dev_name(&dev->dev)))
 305                 return -EBUSY;
 306         drvdata->base = devm_ioremap(&dev->dev, res->start,
 307                                      resource_size(res));
 308         if (!drvdata->base)
 309                 return -EBUSY;
 310
 311         hold = plat->hold ?: 20; /* tDH */
 312         spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
 313
 314         hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
 315         spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
 316         if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
 317                 hold -= 2;      /* actual hold time : (HOLD + 2) BUSCLK */
 318         spw -= 1;       /* actual wait time : (SPW + 1) BUSCLK */
 319         hold = clamp(hold, 1, 15);
 320         drvdata->hold = hold;
 321         spw = clamp(spw, 1, 15);
 322         drvdata->spw = spw;
 323         dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
 324                  (gbusclk + 500000) / 1000000, hold, spw);
 325
 326         spin_lock_init(&drvdata->hw_control.lock);
 327         init_waitqueue_head(&drvdata->hw_control.wq);
 328
 329         platform_set_drvdata(dev, drvdata);
 330         txx9ndfmc_initialize(dev);
 331
 332         for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
 333                 struct txx9ndfmc_priv *txx9_priv;
 334                 struct nand_chip *chip;
 335                 struct mtd_info *mtd;
 336                 int nr_parts;
 337
 338                 if (!(plat->ch_mask & (1 << i)))
 339                         continue;
 340                 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
 341                                     GFP_KERNEL);
 342                 if (!txx9_priv) {
 343                         dev_err(&dev->dev, "Unable to allocate "
 344                                 "TXx9 NDFMC MTD device structure.\n");
 345                         continue;
 346                 }
 347                 chip = &txx9_priv->chip;
 348                 mtd = &txx9_priv->mtd;
 349                 mtd->owner = THIS_MODULE;
 350
 351                 mtd->priv = chip;
 352
 353                 chip->read_byte = txx9ndfmc_read_byte;
 354                 chip->read_buf = txx9ndfmc_read_buf;
 355                 chip->write_buf = txx9ndfmc_write_buf;
 356                 chip->verify_buf = txx9ndfmc_verify_buf;
 357                 chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
 358                 chip->dev_ready = txx9ndfmc_dev_ready;
 359                 chip->ecc.calculate = txx9ndfmc_calculate_ecc;
 360                 chip->ecc.correct = txx9ndfmc_correct_data;
 361                 chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
 362                 chip->ecc.mode = NAND_ECC_HW;
 363                 /* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
 364                 chip->ecc.size = 256;
 365                 chip->ecc.bytes = 3;
 366                 chip->chip_delay = 100;
 367                 chip->controller = &drvdata->hw_control;
 368
 369                 chip->priv = txx9_priv;
 370                 txx9_priv->dev = dev;
 371
 372                 if (plat->ch_mask != 1) {
 373                         txx9_priv->cs = i;
 374                         txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
 375                                                        dev_name(&dev->dev), i);
 376                 } else {
 377                         txx9_priv->cs = -1;
 378                         txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
 379                                                      GFP_KERNEL);
 380                 }
 381                 if (!txx9_priv->mtdname) {
 382                         kfree(txx9_priv);
 383                         dev_err(&dev->dev, "Unable to allocate MTD name.\n");
 384                         continue;
 385                 }
 386                 if (plat->wide_mask & (1 << i))
 387                         chip->options |= NAND_BUSWIDTH_16;
 388
 389                 if (txx9ndfmc_nand_scan(mtd)) {
 390                         kfree(txx9_priv->mtdname);
 391                         kfree(txx9_priv);
 392                         continue;
 393                 }
 394                 mtd->name = txx9_priv->mtdname;
 395
 396                 nr_parts = parse_mtd_partitions(mtd, probes,
 397                                                 &drvdata->parts[i], 0);
 398                 mtd_device_register(mtd, drvdata->parts[i], nr_parts);
 399                 drvdata->mtds[i] = mtd;
 400         }
 401
 402         return 0;
 403 }
 404
 405 static int __exit txx9ndfmc_remove(struct platform_device *dev)
 406 {
 407         struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
 408         int i;
 409
 410         platform_set_drvdata(dev, NULL);
 411         if (!drvdata)
 412                 return 0;
 413         for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
 414                 struct mtd_info *mtd = drvdata->mtds[i];
 415                 struct nand_chip *chip;
 416                 struct txx9ndfmc_priv *txx9_priv;
 417
 418                 if (!mtd)
 419                         continue;
 420                 chip = mtd->priv;
 421                 txx9_priv = chip->priv;
 422
 423                 nand_release(mtd);
 424                 kfree(drvdata->parts[i]);
 425                 kfree(txx9_priv->mtdname);
 426                 kfree(txx9_priv);
 427         }
 428         return 0;
 429 }
 430
 431 #ifdef CONFIG_PM
 432 static int txx9ndfmc_resume(struct platform_device *dev)
 433 {
 434         if (platform_get_drvdata(dev))
 435                 txx9ndfmc_initialize(dev);
 436         return 0;
 437 }
 438 #else
 439 #define txx9ndfmc_resume NULL
 440 #endif
 441
 442 static struct platform_driver txx9ndfmc_driver = {
 443         .remove         = __exit_p(txx9ndfmc_remove),
 444         .resume         = txx9ndfmc_resume,
 445         .driver         = {
 446                 .name   = "txx9ndfmc",
 447                 .owner  = THIS_MODULE,
 448         },
 449 };
 450
 451 static int __init txx9ndfmc_init(void)
 452 {
 453         return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe);
 454 }
 455
 456 static void __exit txx9ndfmc_exit(void)
 457 {
 458         platform_driver_unregister(&txx9ndfmc_driver);
 459 }
 460
 461 module_init(txx9ndfmc_init);
 462 module_exit(txx9ndfmc_exit);
 463
 464 MODULE_LICENSE("GPL");
 465 MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
 466 MODULE_ALIAS("platform:txx9ndfmc");