2 * linux/drivers/mtd/onenand/omap2.c
4 * OneNAND driver for OMAP2 / OMAP3
6 * Copyright © 2005-2006 Nokia Corporation
8 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
9 * IRQ and DMA support written by Timo Teras
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; see the file COPYING. If not, write to the Free Software
22 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/onenand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/dma-mapping.h>
37 #include <linux/slab.h>
38 #include <linux/regulator/consumer.h>
40 #include <asm/mach/flash.h>
41 #include <plat/gpmc.h>
42 #include <plat/onenand.h>
43 #include <mach/gpio.h>
47 #include <plat/board.h>
49 #define DRIVER_NAME "omap2-onenand"
51 #define ONENAND_IO_SIZE SZ_128K
52 #define ONENAND_BUFRAM_SIZE (1024 * 5)
54 struct omap2_onenand
{
55 struct platform_device
*pdev
;
57 unsigned long phys_base
;
60 struct mtd_partition
*parts
;
61 struct onenand_chip onenand
;
62 struct completion irq_done
;
63 struct completion dma_done
;
66 int (*setup
)(void __iomem
*base
, int *freq_ptr
);
67 struct regulator
*regulator
;
70 #ifdef CONFIG_MTD_PARTITIONS
71 static const char *part_probes
[] = { "cmdlinepart", NULL
, };
74 static void omap2_onenand_dma_cb(int lch
, u16 ch_status
, void *data
)
76 struct omap2_onenand
*c
= data
;
78 complete(&c
->dma_done
);
81 static irqreturn_t
omap2_onenand_interrupt(int irq
, void *dev_id
)
83 struct omap2_onenand
*c
= dev_id
;
85 complete(&c
->irq_done
);
90 static inline unsigned short read_reg(struct omap2_onenand
*c
, int reg
)
92 return readw(c
->onenand
.base
+ reg
);
95 static inline void write_reg(struct omap2_onenand
*c
, unsigned short value
,
98 writew(value
, c
->onenand
.base
+ reg
);
101 static void wait_err(char *msg
, int state
, unsigned int ctrl
, unsigned int intr
)
103 printk(KERN_ERR
"onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
104 msg
, state
, ctrl
, intr
);
107 static void wait_warn(char *msg
, int state
, unsigned int ctrl
,
110 printk(KERN_WARNING
"onenand_wait: %s! state %d ctrl 0x%04x "
111 "intr 0x%04x\n", msg
, state
, ctrl
, intr
);
114 static int omap2_onenand_wait(struct mtd_info
*mtd
, int state
)
116 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
117 struct onenand_chip
*this = mtd
->priv
;
118 unsigned int intr
= 0;
119 unsigned int ctrl
, ctrl_mask
;
120 unsigned long timeout
;
123 if (state
== FL_RESETING
|| state
== FL_PREPARING_ERASE
||
124 state
== FL_VERIFYING_ERASE
) {
126 unsigned int intr_flags
= ONENAND_INT_MASTER
;
130 intr_flags
|= ONENAND_INT_RESET
;
132 case FL_PREPARING_ERASE
:
133 intr_flags
|= ONENAND_INT_ERASE
;
135 case FL_VERIFYING_ERASE
:
142 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
143 if (intr
& ONENAND_INT_MASTER
)
146 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
147 if (ctrl
& ONENAND_CTRL_ERROR
) {
148 wait_err("controller error", state
, ctrl
, intr
);
151 if ((intr
& intr_flags
) == intr_flags
)
153 /* Continue in wait for interrupt branch */
156 if (state
!= FL_READING
) {
159 /* Turn interrupts on */
160 syscfg
= read_reg(c
, ONENAND_REG_SYS_CFG1
);
161 if (!(syscfg
& ONENAND_SYS_CFG1_IOBE
)) {
162 syscfg
|= ONENAND_SYS_CFG1_IOBE
;
163 write_reg(c
, syscfg
, ONENAND_REG_SYS_CFG1
);
164 if (cpu_is_omap34xx())
165 /* Add a delay to let GPIO settle */
166 syscfg
= read_reg(c
, ONENAND_REG_SYS_CFG1
);
169 INIT_COMPLETION(c
->irq_done
);
171 result
= gpio_get_value(c
->gpio_irq
);
173 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
174 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
175 wait_err("gpio error", state
, ctrl
, intr
);
183 result
= wait_for_completion_timeout(&c
->irq_done
,
184 msecs_to_jiffies(20));
186 /* Timeout after 20ms */
187 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
188 if (ctrl
& ONENAND_CTRL_ONGO
&&
191 * The operation seems to be still going
192 * so give it some more time.
198 ONENAND_REG_INTERRUPT
);
199 wait_err("timeout", state
, ctrl
, intr
);
202 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
203 if ((intr
& ONENAND_INT_MASTER
) == 0)
204 wait_warn("timeout", state
, ctrl
, intr
);
210 /* Turn interrupts off */
211 syscfg
= read_reg(c
, ONENAND_REG_SYS_CFG1
);
212 syscfg
&= ~ONENAND_SYS_CFG1_IOBE
;
213 write_reg(c
, syscfg
, ONENAND_REG_SYS_CFG1
);
215 timeout
= jiffies
+ msecs_to_jiffies(20);
217 if (time_before(jiffies
, timeout
)) {
218 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
219 if (intr
& ONENAND_INT_MASTER
)
222 /* Timeout after 20ms */
223 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
224 if (ctrl
& ONENAND_CTRL_ONGO
) {
226 * The operation seems to be still going
227 * so give it some more time.
232 msecs_to_jiffies(20);
241 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
242 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
244 if (intr
& ONENAND_INT_READ
) {
245 int ecc
= read_reg(c
, ONENAND_REG_ECC_STATUS
);
248 unsigned int addr1
, addr8
;
250 addr1
= read_reg(c
, ONENAND_REG_START_ADDRESS1
);
251 addr8
= read_reg(c
, ONENAND_REG_START_ADDRESS8
);
252 if (ecc
& ONENAND_ECC_2BIT_ALL
) {
253 printk(KERN_ERR
"onenand_wait: ECC error = "
254 "0x%04x, addr1 %#x, addr8 %#x\n",
256 mtd
->ecc_stats
.failed
++;
258 } else if (ecc
& ONENAND_ECC_1BIT_ALL
) {
259 printk(KERN_NOTICE
"onenand_wait: correctable "
260 "ECC error = 0x%04x, addr1 %#x, "
261 "addr8 %#x\n", ecc
, addr1
, addr8
);
262 mtd
->ecc_stats
.corrected
++;
265 } else if (state
== FL_READING
) {
266 wait_err("timeout", state
, ctrl
, intr
);
270 if (ctrl
& ONENAND_CTRL_ERROR
) {
271 wait_err("controller error", state
, ctrl
, intr
);
272 if (ctrl
& ONENAND_CTRL_LOCK
)
273 printk(KERN_ERR
"onenand_wait: "
274 "Device is write protected!!!\n");
280 ctrl_mask
&= ~0x8000;
282 if (ctrl
& ctrl_mask
)
283 wait_warn("unexpected controller status", state
, ctrl
, intr
);
288 static inline int omap2_onenand_bufferram_offset(struct mtd_info
*mtd
, int area
)
290 struct onenand_chip
*this = mtd
->priv
;
292 if (ONENAND_CURRENT_BUFFERRAM(this)) {
293 if (area
== ONENAND_DATARAM
)
294 return this->writesize
;
295 if (area
== ONENAND_SPARERAM
)
302 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
304 static int omap3_onenand_read_bufferram(struct mtd_info
*mtd
, int area
,
305 unsigned char *buffer
, int offset
,
308 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
309 struct onenand_chip
*this = mtd
->priv
;
310 dma_addr_t dma_src
, dma_dst
;
312 unsigned long timeout
;
313 void *buf
= (void *)buffer
;
315 volatile unsigned *done
;
317 bram_offset
= omap2_onenand_bufferram_offset(mtd
, area
) + area
+ offset
;
318 if (bram_offset
& 3 || (size_t)buf
& 3 || count
< 384)
321 /* panic_write() may be in an interrupt context */
322 if (in_interrupt() || oops_in_progress
)
325 if (buf
>= high_memory
) {
328 if (((size_t)buf
& PAGE_MASK
) !=
329 ((size_t)(buf
+ count
- 1) & PAGE_MASK
))
331 p1
= vmalloc_to_page(buf
);
334 buf
= page_address(p1
) + ((size_t)buf
& ~PAGE_MASK
);
340 memcpy(buf
+ count
, this->base
+ bram_offset
+ count
, xtra
);
343 dma_src
= c
->phys_base
+ bram_offset
;
344 dma_dst
= dma_map_single(&c
->pdev
->dev
, buf
, count
, DMA_FROM_DEVICE
);
345 if (dma_mapping_error(&c
->pdev
->dev
, dma_dst
)) {
346 dev_err(&c
->pdev
->dev
,
347 "Couldn't DMA map a %d byte buffer\n",
352 omap_set_dma_transfer_params(c
->dma_channel
, OMAP_DMA_DATA_TYPE_S32
,
353 count
>> 2, 1, 0, 0, 0);
354 omap_set_dma_src_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
356 omap_set_dma_dest_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
359 INIT_COMPLETION(c
->dma_done
);
360 omap_start_dma(c
->dma_channel
);
362 timeout
= jiffies
+ msecs_to_jiffies(20);
363 done
= &c
->dma_done
.done
;
364 while (time_before(jiffies
, timeout
))
368 dma_unmap_single(&c
->pdev
->dev
, dma_dst
, count
, DMA_FROM_DEVICE
);
371 dev_err(&c
->pdev
->dev
, "timeout waiting for DMA\n");
378 memcpy(buf
, this->base
+ bram_offset
, count
);
382 static int omap3_onenand_write_bufferram(struct mtd_info
*mtd
, int area
,
383 const unsigned char *buffer
,
384 int offset
, size_t count
)
386 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
387 struct onenand_chip
*this = mtd
->priv
;
388 dma_addr_t dma_src
, dma_dst
;
390 unsigned long timeout
;
391 void *buf
= (void *)buffer
;
392 volatile unsigned *done
;
394 bram_offset
= omap2_onenand_bufferram_offset(mtd
, area
) + area
+ offset
;
395 if (bram_offset
& 3 || (size_t)buf
& 3 || count
< 384)
398 /* panic_write() may be in an interrupt context */
399 if (in_interrupt() || oops_in_progress
)
402 if (buf
>= high_memory
) {
405 if (((size_t)buf
& PAGE_MASK
) !=
406 ((size_t)(buf
+ count
- 1) & PAGE_MASK
))
408 p1
= vmalloc_to_page(buf
);
411 buf
= page_address(p1
) + ((size_t)buf
& ~PAGE_MASK
);
414 dma_src
= dma_map_single(&c
->pdev
->dev
, buf
, count
, DMA_TO_DEVICE
);
415 dma_dst
= c
->phys_base
+ bram_offset
;
416 if (dma_mapping_error(&c
->pdev
->dev
, dma_src
)) {
417 dev_err(&c
->pdev
->dev
,
418 "Couldn't DMA map a %d byte buffer\n",
423 omap_set_dma_transfer_params(c
->dma_channel
, OMAP_DMA_DATA_TYPE_S32
,
424 count
>> 2, 1, 0, 0, 0);
425 omap_set_dma_src_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
427 omap_set_dma_dest_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
430 INIT_COMPLETION(c
->dma_done
);
431 omap_start_dma(c
->dma_channel
);
433 timeout
= jiffies
+ msecs_to_jiffies(20);
434 done
= &c
->dma_done
.done
;
435 while (time_before(jiffies
, timeout
))
439 dma_unmap_single(&c
->pdev
->dev
, dma_src
, count
, DMA_TO_DEVICE
);
442 dev_err(&c
->pdev
->dev
, "timeout waiting for DMA\n");
449 memcpy(this->base
+ bram_offset
, buf
, count
);
455 int omap3_onenand_read_bufferram(struct mtd_info
*mtd
, int area
,
456 unsigned char *buffer
, int offset
,
459 int omap3_onenand_write_bufferram(struct mtd_info
*mtd
, int area
,
460 const unsigned char *buffer
,
461 int offset
, size_t count
);
465 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
467 static int omap2_onenand_read_bufferram(struct mtd_info
*mtd
, int area
,
468 unsigned char *buffer
, int offset
,
471 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
472 struct onenand_chip
*this = mtd
->priv
;
473 dma_addr_t dma_src
, dma_dst
;
476 bram_offset
= omap2_onenand_bufferram_offset(mtd
, area
) + area
+ offset
;
477 /* DMA is not used. Revisit PM requirements before enabling it. */
478 if (1 || (c
->dma_channel
< 0) ||
479 ((void *) buffer
>= (void *) high_memory
) || (bram_offset
& 3) ||
480 (((unsigned int) buffer
) & 3) || (count
< 1024) || (count
& 3)) {
481 memcpy(buffer
, (__force
void *)(this->base
+ bram_offset
),
486 dma_src
= c
->phys_base
+ bram_offset
;
487 dma_dst
= dma_map_single(&c
->pdev
->dev
, buffer
, count
,
489 if (dma_mapping_error(&c
->pdev
->dev
, dma_dst
)) {
490 dev_err(&c
->pdev
->dev
,
491 "Couldn't DMA map a %d byte buffer\n",
496 omap_set_dma_transfer_params(c
->dma_channel
, OMAP_DMA_DATA_TYPE_S32
,
497 count
/ 4, 1, 0, 0, 0);
498 omap_set_dma_src_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
500 omap_set_dma_dest_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
503 INIT_COMPLETION(c
->dma_done
);
504 omap_start_dma(c
->dma_channel
);
505 wait_for_completion(&c
->dma_done
);
507 dma_unmap_single(&c
->pdev
->dev
, dma_dst
, count
, DMA_FROM_DEVICE
);
512 static int omap2_onenand_write_bufferram(struct mtd_info
*mtd
, int area
,
513 const unsigned char *buffer
,
514 int offset
, size_t count
)
516 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
517 struct onenand_chip
*this = mtd
->priv
;
518 dma_addr_t dma_src
, dma_dst
;
521 bram_offset
= omap2_onenand_bufferram_offset(mtd
, area
) + area
+ offset
;
522 /* DMA is not used. Revisit PM requirements before enabling it. */
523 if (1 || (c
->dma_channel
< 0) ||
524 ((void *) buffer
>= (void *) high_memory
) || (bram_offset
& 3) ||
525 (((unsigned int) buffer
) & 3) || (count
< 1024) || (count
& 3)) {
526 memcpy((__force
void *)(this->base
+ bram_offset
), buffer
,
531 dma_src
= dma_map_single(&c
->pdev
->dev
, (void *) buffer
, count
,
533 dma_dst
= c
->phys_base
+ bram_offset
;
534 if (dma_mapping_error(&c
->pdev
->dev
, dma_src
)) {
535 dev_err(&c
->pdev
->dev
,
536 "Couldn't DMA map a %d byte buffer\n",
541 omap_set_dma_transfer_params(c
->dma_channel
, OMAP_DMA_DATA_TYPE_S16
,
542 count
/ 2, 1, 0, 0, 0);
543 omap_set_dma_src_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
545 omap_set_dma_dest_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
548 INIT_COMPLETION(c
->dma_done
);
549 omap_start_dma(c
->dma_channel
);
550 wait_for_completion(&c
->dma_done
);
552 dma_unmap_single(&c
->pdev
->dev
, dma_src
, count
, DMA_TO_DEVICE
);
559 int omap2_onenand_read_bufferram(struct mtd_info
*mtd
, int area
,
560 unsigned char *buffer
, int offset
,
563 int omap2_onenand_write_bufferram(struct mtd_info
*mtd
, int area
,
564 const unsigned char *buffer
,
565 int offset
, size_t count
);
569 static struct platform_driver omap2_onenand_driver
;
571 static int __adjust_timing(struct device
*dev
, void *data
)
574 struct omap2_onenand
*c
;
576 c
= dev_get_drvdata(dev
);
578 BUG_ON(c
->setup
== NULL
);
580 /* DMA is not in use so this is all that is needed */
581 /* Revisit for OMAP3! */
582 ret
= c
->setup(c
->onenand
.base
, &c
->freq
);
587 int omap2_onenand_rephase(void)
589 return driver_for_each_device(&omap2_onenand_driver
.driver
, NULL
,
590 NULL
, __adjust_timing
);
593 static void omap2_onenand_shutdown(struct platform_device
*pdev
)
595 struct omap2_onenand
*c
= dev_get_drvdata(&pdev
->dev
);
597 /* With certain content in the buffer RAM, the OMAP boot ROM code
598 * can recognize the flash chip incorrectly. Zero it out before
601 memset((__force
void *)c
->onenand
.base
, 0, ONENAND_BUFRAM_SIZE
);
604 static int omap2_onenand_enable(struct mtd_info
*mtd
)
607 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
609 ret
= regulator_enable(c
->regulator
);
611 dev_err(&c
->pdev
->dev
, "can't enable regulator\n");
616 static int omap2_onenand_disable(struct mtd_info
*mtd
)
619 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
621 ret
= regulator_disable(c
->regulator
);
623 dev_err(&c
->pdev
->dev
, "can't disable regulator\n");
628 static int __devinit
omap2_onenand_probe(struct platform_device
*pdev
)
630 struct omap_onenand_platform_data
*pdata
;
631 struct omap2_onenand
*c
;
632 struct onenand_chip
*this;
635 pdata
= pdev
->dev
.platform_data
;
637 dev_err(&pdev
->dev
, "platform data missing\n");
641 c
= kzalloc(sizeof(struct omap2_onenand
), GFP_KERNEL
);
645 init_completion(&c
->irq_done
);
646 init_completion(&c
->dma_done
);
647 c
->gpmc_cs
= pdata
->cs
;
648 c
->gpio_irq
= pdata
->gpio_irq
;
649 c
->dma_channel
= pdata
->dma_channel
;
650 if (c
->dma_channel
< 0) {
651 /* if -1, don't use DMA */
655 r
= gpmc_cs_request(c
->gpmc_cs
, ONENAND_IO_SIZE
, &c
->phys_base
);
657 dev_err(&pdev
->dev
, "Cannot request GPMC CS\n");
661 if (request_mem_region(c
->phys_base
, ONENAND_IO_SIZE
,
662 pdev
->dev
.driver
->name
) == NULL
) {
663 dev_err(&pdev
->dev
, "Cannot reserve memory region at 0x%08lx, "
664 "size: 0x%x\n", c
->phys_base
, ONENAND_IO_SIZE
);
668 c
->onenand
.base
= ioremap(c
->phys_base
, ONENAND_IO_SIZE
);
669 if (c
->onenand
.base
== NULL
) {
671 goto err_release_mem_region
;
674 if (pdata
->onenand_setup
!= NULL
) {
675 r
= pdata
->onenand_setup(c
->onenand
.base
, &c
->freq
);
677 dev_err(&pdev
->dev
, "Onenand platform setup failed: "
681 c
->setup
= pdata
->onenand_setup
;
685 if ((r
= gpio_request(c
->gpio_irq
, "OneNAND irq")) < 0) {
686 dev_err(&pdev
->dev
, "Failed to request GPIO%d for "
687 "OneNAND\n", c
->gpio_irq
);
690 gpio_direction_input(c
->gpio_irq
);
692 if ((r
= request_irq(gpio_to_irq(c
->gpio_irq
),
693 omap2_onenand_interrupt
, IRQF_TRIGGER_RISING
,
694 pdev
->dev
.driver
->name
, c
)) < 0)
695 goto err_release_gpio
;
698 if (c
->dma_channel
>= 0) {
699 r
= omap_request_dma(0, pdev
->dev
.driver
->name
,
700 omap2_onenand_dma_cb
, (void *) c
,
703 omap_set_dma_write_mode(c
->dma_channel
,
704 OMAP_DMA_WRITE_NON_POSTED
);
705 omap_set_dma_src_data_pack(c
->dma_channel
, 1);
706 omap_set_dma_src_burst_mode(c
->dma_channel
,
707 OMAP_DMA_DATA_BURST_8
);
708 omap_set_dma_dest_data_pack(c
->dma_channel
, 1);
709 omap_set_dma_dest_burst_mode(c
->dma_channel
,
710 OMAP_DMA_DATA_BURST_8
);
713 "failed to allocate DMA for OneNAND, "
714 "using PIO instead\n");
719 dev_info(&pdev
->dev
, "initializing on CS%d, phys base 0x%08lx, virtual "
720 "base %p, freq %d MHz\n", c
->gpmc_cs
, c
->phys_base
,
721 c
->onenand
.base
, c
->freq
);
724 c
->mtd
.name
= dev_name(&pdev
->dev
);
725 c
->mtd
.priv
= &c
->onenand
;
726 c
->mtd
.owner
= THIS_MODULE
;
728 c
->mtd
.dev
.parent
= &pdev
->dev
;
731 if (c
->dma_channel
>= 0) {
732 this->wait
= omap2_onenand_wait
;
733 if (cpu_is_omap34xx()) {
734 this->read_bufferram
= omap3_onenand_read_bufferram
;
735 this->write_bufferram
= omap3_onenand_write_bufferram
;
737 this->read_bufferram
= omap2_onenand_read_bufferram
;
738 this->write_bufferram
= omap2_onenand_write_bufferram
;
742 if (pdata
->regulator_can_sleep
) {
743 c
->regulator
= regulator_get(&pdev
->dev
, "vonenand");
744 if (IS_ERR(c
->regulator
)) {
745 dev_err(&pdev
->dev
, "Failed to get regulator\n");
746 goto err_release_dma
;
748 c
->onenand
.enable
= omap2_onenand_enable
;
749 c
->onenand
.disable
= omap2_onenand_disable
;
752 if (pdata
->skip_initial_unlocking
)
753 this->options
|= ONENAND_SKIP_INITIAL_UNLOCKING
;
755 if ((r
= onenand_scan(&c
->mtd
, 1)) < 0)
756 goto err_release_regulator
;
758 #ifdef CONFIG_MTD_PARTITIONS
759 r
= parse_mtd_partitions(&c
->mtd
, part_probes
, &c
->parts
, 0);
761 r
= add_mtd_partitions(&c
->mtd
, c
->parts
, r
);
762 else if (pdata
->parts
!= NULL
)
763 r
= add_mtd_partitions(&c
->mtd
, pdata
->parts
, pdata
->nr_parts
);
766 r
= add_mtd_device(&c
->mtd
);
768 goto err_release_onenand
;
770 platform_set_drvdata(pdev
, c
);
775 onenand_release(&c
->mtd
);
776 err_release_regulator
:
777 regulator_put(c
->regulator
);
779 if (c
->dma_channel
!= -1)
780 omap_free_dma(c
->dma_channel
);
782 free_irq(gpio_to_irq(c
->gpio_irq
), c
);
785 gpio_free(c
->gpio_irq
);
787 iounmap(c
->onenand
.base
);
788 err_release_mem_region
:
789 release_mem_region(c
->phys_base
, ONENAND_IO_SIZE
);
791 gpmc_cs_free(c
->gpmc_cs
);
799 static int __devexit
omap2_onenand_remove(struct platform_device
*pdev
)
801 struct omap2_onenand
*c
= dev_get_drvdata(&pdev
->dev
);
803 onenand_release(&c
->mtd
);
804 regulator_put(c
->regulator
);
805 if (c
->dma_channel
!= -1)
806 omap_free_dma(c
->dma_channel
);
807 omap2_onenand_shutdown(pdev
);
808 platform_set_drvdata(pdev
, NULL
);
810 free_irq(gpio_to_irq(c
->gpio_irq
), c
);
811 gpio_free(c
->gpio_irq
);
813 iounmap(c
->onenand
.base
);
814 release_mem_region(c
->phys_base
, ONENAND_IO_SIZE
);
815 gpmc_cs_free(c
->gpmc_cs
);
822 static struct platform_driver omap2_onenand_driver
= {
823 .probe
= omap2_onenand_probe
,
824 .remove
= __devexit_p(omap2_onenand_remove
),
825 .shutdown
= omap2_onenand_shutdown
,
828 .owner
= THIS_MODULE
,
832 static int __init
omap2_onenand_init(void)
834 printk(KERN_INFO
"OneNAND driver initializing\n");
835 return platform_driver_register(&omap2_onenand_driver
);
838 static void __exit
omap2_onenand_exit(void)
840 platform_driver_unregister(&omap2_onenand_driver
);
843 module_init(omap2_onenand_init
);
844 module_exit(omap2_onenand_exit
);
846 MODULE_ALIAS("platform:" DRIVER_NAME
);
847 MODULE_LICENSE("GPL");
848 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
849 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");