2 * linux/drivers/mtd/onenand/omap2.c
4 * OneNAND driver for OMAP2 / OMAP3
6 * Copyright © 2005-2006 Nokia Corporation
8 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
9 * IRQ and DMA support written by Timo Teras
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; see the file COPYING. If not, write to the Free Software
22 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/onenand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/dma-mapping.h>
37 #include <linux/slab.h>
38 #include <linux/regulator/consumer.h>
40 #include <asm/mach/flash.h>
41 #include <plat/gpmc.h>
42 #include <plat/onenand.h>
43 #include <mach/gpio.h>
47 #include <plat/board.h>
49 #define DRIVER_NAME "omap2-onenand"
51 #define ONENAND_IO_SIZE SZ_128K
52 #define ONENAND_BUFRAM_SIZE (1024 * 5)
54 struct omap2_onenand
{
55 struct platform_device
*pdev
;
57 unsigned long phys_base
;
60 struct mtd_partition
*parts
;
61 struct onenand_chip onenand
;
62 struct completion irq_done
;
63 struct completion dma_done
;
66 int (*setup
)(void __iomem
*base
, int freq
);
67 struct regulator
*regulator
;
70 #ifdef CONFIG_MTD_PARTITIONS
71 static const char *part_probes
[] = { "cmdlinepart", NULL
, };
74 static void omap2_onenand_dma_cb(int lch
, u16 ch_status
, void *data
)
76 struct omap2_onenand
*c
= data
;
78 complete(&c
->dma_done
);
81 static irqreturn_t
omap2_onenand_interrupt(int irq
, void *dev_id
)
83 struct omap2_onenand
*c
= dev_id
;
85 complete(&c
->irq_done
);
90 static inline unsigned short read_reg(struct omap2_onenand
*c
, int reg
)
92 return readw(c
->onenand
.base
+ reg
);
95 static inline void write_reg(struct omap2_onenand
*c
, unsigned short value
,
98 writew(value
, c
->onenand
.base
+ reg
);
101 static void wait_err(char *msg
, int state
, unsigned int ctrl
, unsigned int intr
)
103 printk(KERN_ERR
"onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
104 msg
, state
, ctrl
, intr
);
107 static void wait_warn(char *msg
, int state
, unsigned int ctrl
,
110 printk(KERN_WARNING
"onenand_wait: %s! state %d ctrl 0x%04x "
111 "intr 0x%04x\n", msg
, state
, ctrl
, intr
);
114 static int omap2_onenand_wait(struct mtd_info
*mtd
, int state
)
116 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
117 struct onenand_chip
*this = mtd
->priv
;
118 unsigned int intr
= 0;
119 unsigned int ctrl
, ctrl_mask
;
120 unsigned long timeout
;
123 if (state
== FL_RESETING
|| state
== FL_PREPARING_ERASE
||
124 state
== FL_VERIFYING_ERASE
) {
126 unsigned int intr_flags
= ONENAND_INT_MASTER
;
130 intr_flags
|= ONENAND_INT_RESET
;
132 case FL_PREPARING_ERASE
:
133 intr_flags
|= ONENAND_INT_ERASE
;
135 case FL_VERIFYING_ERASE
:
142 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
143 if (intr
& ONENAND_INT_MASTER
)
146 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
147 if (ctrl
& ONENAND_CTRL_ERROR
) {
148 wait_err("controller error", state
, ctrl
, intr
);
151 if ((intr
& intr_flags
) != intr_flags
) {
152 wait_err("timeout", state
, ctrl
, intr
);
158 if (state
!= FL_READING
) {
161 /* Turn interrupts on */
162 syscfg
= read_reg(c
, ONENAND_REG_SYS_CFG1
);
163 if (!(syscfg
& ONENAND_SYS_CFG1_IOBE
)) {
164 syscfg
|= ONENAND_SYS_CFG1_IOBE
;
165 write_reg(c
, syscfg
, ONENAND_REG_SYS_CFG1
);
166 if (cpu_is_omap34xx())
167 /* Add a delay to let GPIO settle */
168 syscfg
= read_reg(c
, ONENAND_REG_SYS_CFG1
);
171 INIT_COMPLETION(c
->irq_done
);
173 result
= gpio_get_value(c
->gpio_irq
);
175 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
176 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
177 wait_err("gpio error", state
, ctrl
, intr
);
185 result
= wait_for_completion_timeout(&c
->irq_done
,
186 msecs_to_jiffies(20));
188 /* Timeout after 20ms */
189 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
190 if (ctrl
& ONENAND_CTRL_ONGO
&&
193 * The operation seems to be still going
194 * so give it some more time.
200 ONENAND_REG_INTERRUPT
);
201 wait_err("timeout", state
, ctrl
, intr
);
204 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
205 if ((intr
& ONENAND_INT_MASTER
) == 0)
206 wait_warn("timeout", state
, ctrl
, intr
);
212 /* Turn interrupts off */
213 syscfg
= read_reg(c
, ONENAND_REG_SYS_CFG1
);
214 syscfg
&= ~ONENAND_SYS_CFG1_IOBE
;
215 write_reg(c
, syscfg
, ONENAND_REG_SYS_CFG1
);
217 timeout
= jiffies
+ msecs_to_jiffies(20);
219 if (time_before(jiffies
, timeout
)) {
220 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
221 if (intr
& ONENAND_INT_MASTER
)
224 /* Timeout after 20ms */
225 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
226 if (ctrl
& ONENAND_CTRL_ONGO
) {
228 * The operation seems to be still going
229 * so give it some more time.
234 msecs_to_jiffies(20);
243 intr
= read_reg(c
, ONENAND_REG_INTERRUPT
);
244 ctrl
= read_reg(c
, ONENAND_REG_CTRL_STATUS
);
246 if (intr
& ONENAND_INT_READ
) {
247 int ecc
= read_reg(c
, ONENAND_REG_ECC_STATUS
);
250 unsigned int addr1
, addr8
;
252 addr1
= read_reg(c
, ONENAND_REG_START_ADDRESS1
);
253 addr8
= read_reg(c
, ONENAND_REG_START_ADDRESS8
);
254 if (ecc
& ONENAND_ECC_2BIT_ALL
) {
255 printk(KERN_ERR
"onenand_wait: ECC error = "
256 "0x%04x, addr1 %#x, addr8 %#x\n",
258 mtd
->ecc_stats
.failed
++;
260 } else if (ecc
& ONENAND_ECC_1BIT_ALL
) {
261 printk(KERN_NOTICE
"onenand_wait: correctable "
262 "ECC error = 0x%04x, addr1 %#x, "
263 "addr8 %#x\n", ecc
, addr1
, addr8
);
264 mtd
->ecc_stats
.corrected
++;
267 } else if (state
== FL_READING
) {
268 wait_err("timeout", state
, ctrl
, intr
);
272 if (ctrl
& ONENAND_CTRL_ERROR
) {
273 wait_err("controller error", state
, ctrl
, intr
);
274 if (ctrl
& ONENAND_CTRL_LOCK
)
275 printk(KERN_ERR
"onenand_wait: "
276 "Device is write protected!!!\n");
282 ctrl_mask
&= ~0x8000;
284 if (ctrl
& ctrl_mask
)
285 wait_warn("unexpected controller status", state
, ctrl
, intr
);
290 static inline int omap2_onenand_bufferram_offset(struct mtd_info
*mtd
, int area
)
292 struct onenand_chip
*this = mtd
->priv
;
294 if (ONENAND_CURRENT_BUFFERRAM(this)) {
295 if (area
== ONENAND_DATARAM
)
296 return this->writesize
;
297 if (area
== ONENAND_SPARERAM
)
304 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
306 static int omap3_onenand_read_bufferram(struct mtd_info
*mtd
, int area
,
307 unsigned char *buffer
, int offset
,
310 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
311 struct onenand_chip
*this = mtd
->priv
;
312 dma_addr_t dma_src
, dma_dst
;
314 unsigned long timeout
;
315 void *buf
= (void *)buffer
;
317 volatile unsigned *done
;
319 bram_offset
= omap2_onenand_bufferram_offset(mtd
, area
) + area
+ offset
;
320 if (bram_offset
& 3 || (size_t)buf
& 3 || count
< 384)
323 /* panic_write() may be in an interrupt context */
324 if (in_interrupt() || oops_in_progress
)
327 if (buf
>= high_memory
) {
330 if (((size_t)buf
& PAGE_MASK
) !=
331 ((size_t)(buf
+ count
- 1) & PAGE_MASK
))
333 p1
= vmalloc_to_page(buf
);
336 buf
= page_address(p1
) + ((size_t)buf
& ~PAGE_MASK
);
342 memcpy(buf
+ count
, this->base
+ bram_offset
+ count
, xtra
);
345 dma_src
= c
->phys_base
+ bram_offset
;
346 dma_dst
= dma_map_single(&c
->pdev
->dev
, buf
, count
, DMA_FROM_DEVICE
);
347 if (dma_mapping_error(&c
->pdev
->dev
, dma_dst
)) {
348 dev_err(&c
->pdev
->dev
,
349 "Couldn't DMA map a %d byte buffer\n",
354 omap_set_dma_transfer_params(c
->dma_channel
, OMAP_DMA_DATA_TYPE_S32
,
355 count
>> 2, 1, 0, 0, 0);
356 omap_set_dma_src_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
358 omap_set_dma_dest_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
361 INIT_COMPLETION(c
->dma_done
);
362 omap_start_dma(c
->dma_channel
);
364 timeout
= jiffies
+ msecs_to_jiffies(20);
365 done
= &c
->dma_done
.done
;
366 while (time_before(jiffies
, timeout
))
370 dma_unmap_single(&c
->pdev
->dev
, dma_dst
, count
, DMA_FROM_DEVICE
);
373 dev_err(&c
->pdev
->dev
, "timeout waiting for DMA\n");
380 memcpy(buf
, this->base
+ bram_offset
, count
);
384 static int omap3_onenand_write_bufferram(struct mtd_info
*mtd
, int area
,
385 const unsigned char *buffer
,
386 int offset
, size_t count
)
388 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
389 struct onenand_chip
*this = mtd
->priv
;
390 dma_addr_t dma_src
, dma_dst
;
392 unsigned long timeout
;
393 void *buf
= (void *)buffer
;
394 volatile unsigned *done
;
396 bram_offset
= omap2_onenand_bufferram_offset(mtd
, area
) + area
+ offset
;
397 if (bram_offset
& 3 || (size_t)buf
& 3 || count
< 384)
400 /* panic_write() may be in an interrupt context */
401 if (in_interrupt() || oops_in_progress
)
404 if (buf
>= high_memory
) {
407 if (((size_t)buf
& PAGE_MASK
) !=
408 ((size_t)(buf
+ count
- 1) & PAGE_MASK
))
410 p1
= vmalloc_to_page(buf
);
413 buf
= page_address(p1
) + ((size_t)buf
& ~PAGE_MASK
);
416 dma_src
= dma_map_single(&c
->pdev
->dev
, buf
, count
, DMA_TO_DEVICE
);
417 dma_dst
= c
->phys_base
+ bram_offset
;
418 if (dma_mapping_error(&c
->pdev
->dev
, dma_src
)) {
419 dev_err(&c
->pdev
->dev
,
420 "Couldn't DMA map a %d byte buffer\n",
425 omap_set_dma_transfer_params(c
->dma_channel
, OMAP_DMA_DATA_TYPE_S32
,
426 count
>> 2, 1, 0, 0, 0);
427 omap_set_dma_src_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
429 omap_set_dma_dest_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
432 INIT_COMPLETION(c
->dma_done
);
433 omap_start_dma(c
->dma_channel
);
435 timeout
= jiffies
+ msecs_to_jiffies(20);
436 done
= &c
->dma_done
.done
;
437 while (time_before(jiffies
, timeout
))
441 dma_unmap_single(&c
->pdev
->dev
, dma_src
, count
, DMA_TO_DEVICE
);
444 dev_err(&c
->pdev
->dev
, "timeout waiting for DMA\n");
451 memcpy(this->base
+ bram_offset
, buf
, count
);
457 int omap3_onenand_read_bufferram(struct mtd_info
*mtd
, int area
,
458 unsigned char *buffer
, int offset
,
461 int omap3_onenand_write_bufferram(struct mtd_info
*mtd
, int area
,
462 const unsigned char *buffer
,
463 int offset
, size_t count
);
467 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
469 static int omap2_onenand_read_bufferram(struct mtd_info
*mtd
, int area
,
470 unsigned char *buffer
, int offset
,
473 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
474 struct onenand_chip
*this = mtd
->priv
;
475 dma_addr_t dma_src
, dma_dst
;
478 bram_offset
= omap2_onenand_bufferram_offset(mtd
, area
) + area
+ offset
;
479 /* DMA is not used. Revisit PM requirements before enabling it. */
480 if (1 || (c
->dma_channel
< 0) ||
481 ((void *) buffer
>= (void *) high_memory
) || (bram_offset
& 3) ||
482 (((unsigned int) buffer
) & 3) || (count
< 1024) || (count
& 3)) {
483 memcpy(buffer
, (__force
void *)(this->base
+ bram_offset
),
488 dma_src
= c
->phys_base
+ bram_offset
;
489 dma_dst
= dma_map_single(&c
->pdev
->dev
, buffer
, count
,
491 if (dma_mapping_error(&c
->pdev
->dev
, dma_dst
)) {
492 dev_err(&c
->pdev
->dev
,
493 "Couldn't DMA map a %d byte buffer\n",
498 omap_set_dma_transfer_params(c
->dma_channel
, OMAP_DMA_DATA_TYPE_S32
,
499 count
/ 4, 1, 0, 0, 0);
500 omap_set_dma_src_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
502 omap_set_dma_dest_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
505 INIT_COMPLETION(c
->dma_done
);
506 omap_start_dma(c
->dma_channel
);
507 wait_for_completion(&c
->dma_done
);
509 dma_unmap_single(&c
->pdev
->dev
, dma_dst
, count
, DMA_FROM_DEVICE
);
514 static int omap2_onenand_write_bufferram(struct mtd_info
*mtd
, int area
,
515 const unsigned char *buffer
,
516 int offset
, size_t count
)
518 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
519 struct onenand_chip
*this = mtd
->priv
;
520 dma_addr_t dma_src
, dma_dst
;
523 bram_offset
= omap2_onenand_bufferram_offset(mtd
, area
) + area
+ offset
;
524 /* DMA is not used. Revisit PM requirements before enabling it. */
525 if (1 || (c
->dma_channel
< 0) ||
526 ((void *) buffer
>= (void *) high_memory
) || (bram_offset
& 3) ||
527 (((unsigned int) buffer
) & 3) || (count
< 1024) || (count
& 3)) {
528 memcpy((__force
void *)(this->base
+ bram_offset
), buffer
,
533 dma_src
= dma_map_single(&c
->pdev
->dev
, (void *) buffer
, count
,
535 dma_dst
= c
->phys_base
+ bram_offset
;
536 if (dma_mapping_error(&c
->pdev
->dev
, dma_src
)) {
537 dev_err(&c
->pdev
->dev
,
538 "Couldn't DMA map a %d byte buffer\n",
543 omap_set_dma_transfer_params(c
->dma_channel
, OMAP_DMA_DATA_TYPE_S16
,
544 count
/ 2, 1, 0, 0, 0);
545 omap_set_dma_src_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
547 omap_set_dma_dest_params(c
->dma_channel
, 0, OMAP_DMA_AMODE_POST_INC
,
550 INIT_COMPLETION(c
->dma_done
);
551 omap_start_dma(c
->dma_channel
);
552 wait_for_completion(&c
->dma_done
);
554 dma_unmap_single(&c
->pdev
->dev
, dma_src
, count
, DMA_TO_DEVICE
);
561 int omap2_onenand_read_bufferram(struct mtd_info
*mtd
, int area
,
562 unsigned char *buffer
, int offset
,
565 int omap2_onenand_write_bufferram(struct mtd_info
*mtd
, int area
,
566 const unsigned char *buffer
,
567 int offset
, size_t count
);
571 static struct platform_driver omap2_onenand_driver
;
573 static int __adjust_timing(struct device
*dev
, void *data
)
576 struct omap2_onenand
*c
;
578 c
= dev_get_drvdata(dev
);
580 BUG_ON(c
->setup
== NULL
);
582 /* DMA is not in use so this is all that is needed */
583 /* Revisit for OMAP3! */
584 ret
= c
->setup(c
->onenand
.base
, c
->freq
);
589 int omap2_onenand_rephase(void)
591 return driver_for_each_device(&omap2_onenand_driver
.driver
, NULL
,
592 NULL
, __adjust_timing
);
595 static void omap2_onenand_shutdown(struct platform_device
*pdev
)
597 struct omap2_onenand
*c
= dev_get_drvdata(&pdev
->dev
);
599 /* With certain content in the buffer RAM, the OMAP boot ROM code
600 * can recognize the flash chip incorrectly. Zero it out before
603 memset((__force
void *)c
->onenand
.base
, 0, ONENAND_BUFRAM_SIZE
);
606 static int omap2_onenand_enable(struct mtd_info
*mtd
)
609 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
611 ret
= regulator_enable(c
->regulator
);
613 dev_err(&c
->pdev
->dev
, "cant enable regulator\n");
618 static int omap2_onenand_disable(struct mtd_info
*mtd
)
621 struct omap2_onenand
*c
= container_of(mtd
, struct omap2_onenand
, mtd
);
623 ret
= regulator_disable(c
->regulator
);
625 dev_err(&c
->pdev
->dev
, "cant disable regulator\n");
630 static int __devinit
omap2_onenand_probe(struct platform_device
*pdev
)
632 struct omap_onenand_platform_data
*pdata
;
633 struct omap2_onenand
*c
;
636 pdata
= pdev
->dev
.platform_data
;
638 dev_err(&pdev
->dev
, "platform data missing\n");
642 c
= kzalloc(sizeof(struct omap2_onenand
), GFP_KERNEL
);
646 init_completion(&c
->irq_done
);
647 init_completion(&c
->dma_done
);
648 c
->gpmc_cs
= pdata
->cs
;
649 c
->gpio_irq
= pdata
->gpio_irq
;
650 c
->dma_channel
= pdata
->dma_channel
;
651 if (c
->dma_channel
< 0) {
652 /* if -1, don't use DMA */
656 r
= gpmc_cs_request(c
->gpmc_cs
, ONENAND_IO_SIZE
, &c
->phys_base
);
658 dev_err(&pdev
->dev
, "Cannot request GPMC CS\n");
662 if (request_mem_region(c
->phys_base
, ONENAND_IO_SIZE
,
663 pdev
->dev
.driver
->name
) == NULL
) {
664 dev_err(&pdev
->dev
, "Cannot reserve memory region at 0x%08lx, "
665 "size: 0x%x\n", c
->phys_base
, ONENAND_IO_SIZE
);
669 c
->onenand
.base
= ioremap(c
->phys_base
, ONENAND_IO_SIZE
);
670 if (c
->onenand
.base
== NULL
) {
672 goto err_release_mem_region
;
675 if (pdata
->onenand_setup
!= NULL
) {
676 r
= pdata
->onenand_setup(c
->onenand
.base
, c
->freq
);
678 dev_err(&pdev
->dev
, "Onenand platform setup failed: "
682 c
->setup
= pdata
->onenand_setup
;
686 if ((r
= gpio_request(c
->gpio_irq
, "OneNAND irq")) < 0) {
687 dev_err(&pdev
->dev
, "Failed to request GPIO%d for "
688 "OneNAND\n", c
->gpio_irq
);
691 gpio_direction_input(c
->gpio_irq
);
693 if ((r
= request_irq(gpio_to_irq(c
->gpio_irq
),
694 omap2_onenand_interrupt
, IRQF_TRIGGER_RISING
,
695 pdev
->dev
.driver
->name
, c
)) < 0)
696 goto err_release_gpio
;
699 if (c
->dma_channel
>= 0) {
700 r
= omap_request_dma(0, pdev
->dev
.driver
->name
,
701 omap2_onenand_dma_cb
, (void *) c
,
704 omap_set_dma_write_mode(c
->dma_channel
,
705 OMAP_DMA_WRITE_NON_POSTED
);
706 omap_set_dma_src_data_pack(c
->dma_channel
, 1);
707 omap_set_dma_src_burst_mode(c
->dma_channel
,
708 OMAP_DMA_DATA_BURST_8
);
709 omap_set_dma_dest_data_pack(c
->dma_channel
, 1);
710 omap_set_dma_dest_burst_mode(c
->dma_channel
,
711 OMAP_DMA_DATA_BURST_8
);
714 "failed to allocate DMA for OneNAND, "
715 "using PIO instead\n");
720 dev_info(&pdev
->dev
, "initializing on CS%d, phys base 0x%08lx, virtual "
721 "base %p\n", c
->gpmc_cs
, c
->phys_base
,
725 c
->mtd
.name
= dev_name(&pdev
->dev
);
726 c
->mtd
.priv
= &c
->onenand
;
727 c
->mtd
.owner
= THIS_MODULE
;
729 c
->mtd
.dev
.parent
= &pdev
->dev
;
731 if (c
->dma_channel
>= 0) {
732 struct onenand_chip
*this = &c
->onenand
;
734 this->wait
= omap2_onenand_wait
;
735 if (cpu_is_omap34xx()) {
736 this->read_bufferram
= omap3_onenand_read_bufferram
;
737 this->write_bufferram
= omap3_onenand_write_bufferram
;
739 this->read_bufferram
= omap2_onenand_read_bufferram
;
740 this->write_bufferram
= omap2_onenand_write_bufferram
;
744 if (pdata
->regulator_can_sleep
) {
745 c
->regulator
= regulator_get(&pdev
->dev
, "vonenand");
746 if (IS_ERR(c
->regulator
)) {
747 dev_err(&pdev
->dev
, "Failed to get regulator\n");
748 goto err_release_dma
;
750 c
->onenand
.enable
= omap2_onenand_enable
;
751 c
->onenand
.disable
= omap2_onenand_disable
;
754 if ((r
= onenand_scan(&c
->mtd
, 1)) < 0)
755 goto err_release_regulator
;
757 switch ((c
->onenand
.version_id
>> 4) & 0xf) {
775 #ifdef CONFIG_MTD_PARTITIONS
776 r
= parse_mtd_partitions(&c
->mtd
, part_probes
, &c
->parts
, 0);
778 r
= add_mtd_partitions(&c
->mtd
, c
->parts
, r
);
779 else if (pdata
->parts
!= NULL
)
780 r
= add_mtd_partitions(&c
->mtd
, pdata
->parts
, pdata
->nr_parts
);
783 r
= add_mtd_device(&c
->mtd
);
785 goto err_release_onenand
;
787 platform_set_drvdata(pdev
, c
);
792 onenand_release(&c
->mtd
);
793 err_release_regulator
:
794 regulator_put(c
->regulator
);
796 if (c
->dma_channel
!= -1)
797 omap_free_dma(c
->dma_channel
);
799 free_irq(gpio_to_irq(c
->gpio_irq
), c
);
802 gpio_free(c
->gpio_irq
);
804 iounmap(c
->onenand
.base
);
805 err_release_mem_region
:
806 release_mem_region(c
->phys_base
, ONENAND_IO_SIZE
);
808 gpmc_cs_free(c
->gpmc_cs
);
816 static int __devexit
omap2_onenand_remove(struct platform_device
*pdev
)
818 struct omap2_onenand
*c
= dev_get_drvdata(&pdev
->dev
);
820 onenand_release(&c
->mtd
);
821 regulator_put(c
->regulator
);
822 if (c
->dma_channel
!= -1)
823 omap_free_dma(c
->dma_channel
);
824 omap2_onenand_shutdown(pdev
);
825 platform_set_drvdata(pdev
, NULL
);
827 free_irq(gpio_to_irq(c
->gpio_irq
), c
);
828 gpio_free(c
->gpio_irq
);
830 iounmap(c
->onenand
.base
);
831 release_mem_region(c
->phys_base
, ONENAND_IO_SIZE
);
832 gpmc_cs_free(c
->gpmc_cs
);
839 static struct platform_driver omap2_onenand_driver
= {
840 .probe
= omap2_onenand_probe
,
841 .remove
= __devexit_p(omap2_onenand_remove
),
842 .shutdown
= omap2_onenand_shutdown
,
845 .owner
= THIS_MODULE
,
849 static int __init
omap2_onenand_init(void)
851 printk(KERN_INFO
"OneNAND driver initializing\n");
852 return platform_driver_register(&omap2_onenand_driver
);
855 static void __exit
omap2_onenand_exit(void)
857 platform_driver_unregister(&omap2_onenand_driver
);
860 module_init(omap2_onenand_init
);
861 module_exit(omap2_onenand_exit
);
863 MODULE_ALIAS(DRIVER_NAME
);
864 MODULE_LICENSE("GPL");
865 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
866 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");