2 * Intel PCH/PCU SPI flash driver.
4 * Copyright (C) 2016, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/err.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/sizes.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/mtd/spi-nor.h>
21 #include <linux/platform_data/intel-spi.h>
23 #include "intel-spi.h"
25 /* Offsets are from @ispi->base */
28 #define HSFSTS_CTL 0x04
29 #define HSFSTS_CTL_FSMIE BIT(31)
30 #define HSFSTS_CTL_FDBC_SHIFT 24
31 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
33 #define HSFSTS_CTL_FCYCLE_SHIFT 17
34 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
35 /* HW sequencer opcodes */
36 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
37 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
38 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
39 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
40 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
41 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
42 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
44 #define HSFSTS_CTL_FGO BIT(16)
45 #define HSFSTS_CTL_FLOCKDN BIT(15)
46 #define HSFSTS_CTL_FDV BIT(14)
47 #define HSFSTS_CTL_SCIP BIT(5)
48 #define HSFSTS_CTL_AEL BIT(2)
49 #define HSFSTS_CTL_FCERR BIT(1)
50 #define HSFSTS_CTL_FDONE BIT(0)
54 #define FDATA(n) (0x10 + ((n) * 4))
58 #define FREG(n) (0x54 + ((n) * 4))
59 #define FREG_BASE_MASK 0x3fff
60 #define FREG_LIMIT_SHIFT 16
61 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
63 /* Offset is from @ispi->pregs */
64 #define PR(n) ((n) * 4)
65 #define PR_WPE BIT(31)
66 #define PR_LIMIT_SHIFT 16
67 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
68 #define PR_RPE BIT(15)
69 #define PR_BASE_MASK 0x3fff
71 /* Offsets are from @ispi->sregs */
72 #define SSFSTS_CTL 0x00
73 #define SSFSTS_CTL_FSMIE BIT(23)
74 #define SSFSTS_CTL_DS BIT(22)
75 #define SSFSTS_CTL_DBC_SHIFT 16
76 #define SSFSTS_CTL_SPOP BIT(11)
77 #define SSFSTS_CTL_ACS BIT(10)
78 #define SSFSTS_CTL_SCGO BIT(9)
79 #define SSFSTS_CTL_COP_SHIFT 12
80 #define SSFSTS_CTL_FRS BIT(7)
81 #define SSFSTS_CTL_DOFRS BIT(6)
82 #define SSFSTS_CTL_AEL BIT(4)
83 #define SSFSTS_CTL_FCERR BIT(3)
84 #define SSFSTS_CTL_FDONE BIT(2)
85 #define SSFSTS_CTL_SCIP BIT(0)
87 #define PREOP_OPTYPE 0x04
91 #define OPTYPE_READ_NO_ADDR 0
92 #define OPTYPE_WRITE_NO_ADDR 1
93 #define OPTYPE_READ_WITH_ADDR 2
94 #define OPTYPE_WRITE_WITH_ADDR 3
98 #define BYT_SSFSTS_CTL 0x90
100 #define BYT_BCR_WPD BIT(0)
101 #define BYT_FREG_NUM 5
105 #define LPT_SSFSTS_CTL 0x90
106 #define LPT_FREG_NUM 5
110 #define BXT_SSFSTS_CTL 0xa0
111 #define BXT_FREG_NUM 12
116 #define ERASE_OPCODE_SHIFT 8
117 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
118 #define ERASE_64K_OPCODE_SHIFT 16
119 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
121 #define INTEL_SPI_TIMEOUT 5000 /* ms */
122 #define INTEL_SPI_FIFO_SZ 64
125 * struct intel_spi - Driver private data
126 * @dev: Device pointer
127 * @info: Pointer to board specific info
128 * @nor: SPI NOR layer structure
129 * @base: Beginning of MMIO space
130 * @pregs: Start of protection registers
131 * @sregs: Start of software sequencer registers
132 * @nregions: Maximum number of regions
133 * @pr_num: Maximum number of protected range registers
134 * @writeable: Is the chip writeable
135 * @locked: Is SPI setting locked
136 * @swseq_reg: Use SW sequencer in register reads/writes
137 * @swseq_erase: Use SW sequencer in erase operation
138 * @erase_64k: 64k erase supported
139 * @opcodes: Opcodes which are supported. This are programmed by BIOS
140 * before it locks down the controller.
141 * @preopcodes: Preopcodes which are supported.
145 const struct intel_spi_boardinfo
*info
;
161 static bool writeable
;
162 module_param(writeable
, bool, 0);
163 MODULE_PARM_DESC(writeable
, "Enable write access to SPI flash chip (default=0)");
165 static void intel_spi_dump_regs(struct intel_spi
*ispi
)
170 dev_dbg(ispi
->dev
, "BFPREG=0x%08x\n", readl(ispi
->base
+ BFPREG
));
172 value
= readl(ispi
->base
+ HSFSTS_CTL
);
173 dev_dbg(ispi
->dev
, "HSFSTS_CTL=0x%08x\n", value
);
174 if (value
& HSFSTS_CTL_FLOCKDN
)
175 dev_dbg(ispi
->dev
, "-> Locked\n");
177 dev_dbg(ispi
->dev
, "FADDR=0x%08x\n", readl(ispi
->base
+ FADDR
));
178 dev_dbg(ispi
->dev
, "DLOCK=0x%08x\n", readl(ispi
->base
+ DLOCK
));
180 for (i
= 0; i
< 16; i
++)
181 dev_dbg(ispi
->dev
, "FDATA(%d)=0x%08x\n",
182 i
, readl(ispi
->base
+ FDATA(i
)));
184 dev_dbg(ispi
->dev
, "FRACC=0x%08x\n", readl(ispi
->base
+ FRACC
));
186 for (i
= 0; i
< ispi
->nregions
; i
++)
187 dev_dbg(ispi
->dev
, "FREG(%d)=0x%08x\n", i
,
188 readl(ispi
->base
+ FREG(i
)));
189 for (i
= 0; i
< ispi
->pr_num
; i
++)
190 dev_dbg(ispi
->dev
, "PR(%d)=0x%08x\n", i
,
191 readl(ispi
->pregs
+ PR(i
)));
193 value
= readl(ispi
->sregs
+ SSFSTS_CTL
);
194 dev_dbg(ispi
->dev
, "SSFSTS_CTL=0x%08x\n", value
);
195 dev_dbg(ispi
->dev
, "PREOP_OPTYPE=0x%08x\n",
196 readl(ispi
->sregs
+ PREOP_OPTYPE
));
197 dev_dbg(ispi
->dev
, "OPMENU0=0x%08x\n", readl(ispi
->sregs
+ OPMENU0
));
198 dev_dbg(ispi
->dev
, "OPMENU1=0x%08x\n", readl(ispi
->sregs
+ OPMENU1
));
200 if (ispi
->info
->type
== INTEL_SPI_BYT
)
201 dev_dbg(ispi
->dev
, "BCR=0x%08x\n", readl(ispi
->base
+ BYT_BCR
));
203 dev_dbg(ispi
->dev
, "LVSCC=0x%08x\n", readl(ispi
->base
+ LVSCC
));
204 dev_dbg(ispi
->dev
, "UVSCC=0x%08x\n", readl(ispi
->base
+ UVSCC
));
206 dev_dbg(ispi
->dev
, "Protected regions:\n");
207 for (i
= 0; i
< ispi
->pr_num
; i
++) {
210 value
= readl(ispi
->pregs
+ PR(i
));
211 if (!(value
& (PR_WPE
| PR_RPE
)))
214 limit
= (value
& PR_LIMIT_MASK
) >> PR_LIMIT_SHIFT
;
215 base
= value
& PR_BASE_MASK
;
217 dev_dbg(ispi
->dev
, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
218 i
, base
<< 12, (limit
<< 12) | 0xfff,
219 value
& PR_WPE
? 'W' : '.',
220 value
& PR_RPE
? 'R' : '.');
223 dev_dbg(ispi
->dev
, "Flash regions:\n");
224 for (i
= 0; i
< ispi
->nregions
; i
++) {
225 u32 region
, base
, limit
;
227 region
= readl(ispi
->base
+ FREG(i
));
228 base
= region
& FREG_BASE_MASK
;
229 limit
= (region
& FREG_LIMIT_MASK
) >> FREG_LIMIT_SHIFT
;
231 if (base
>= limit
|| (i
> 0 && limit
== 0))
232 dev_dbg(ispi
->dev
, " %02d disabled\n", i
);
234 dev_dbg(ispi
->dev
, " %02d base: 0x%08x limit: 0x%08x\n",
235 i
, base
<< 12, (limit
<< 12) | 0xfff);
238 dev_dbg(ispi
->dev
, "Using %cW sequencer for register access\n",
239 ispi
->swseq_reg
? 'S' : 'H');
240 dev_dbg(ispi
->dev
, "Using %cW sequencer for erase operation\n",
241 ispi
->swseq_erase
? 'S' : 'H');
244 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
245 static int intel_spi_read_block(struct intel_spi
*ispi
, void *buf
, size_t size
)
250 if (size
> INTEL_SPI_FIFO_SZ
)
254 bytes
= min_t(size_t, size
, 4);
255 memcpy_fromio(buf
, ispi
->base
+ FDATA(i
), bytes
);
264 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
265 static int intel_spi_write_block(struct intel_spi
*ispi
, const void *buf
,
271 if (size
> INTEL_SPI_FIFO_SZ
)
275 bytes
= min_t(size_t, size
, 4);
276 memcpy_toio(ispi
->base
+ FDATA(i
), buf
, bytes
);
285 static int intel_spi_wait_hw_busy(struct intel_spi
*ispi
)
289 return readl_poll_timeout(ispi
->base
+ HSFSTS_CTL
, val
,
290 !(val
& HSFSTS_CTL_SCIP
), 0,
291 INTEL_SPI_TIMEOUT
* 1000);
294 static int intel_spi_wait_sw_busy(struct intel_spi
*ispi
)
298 return readl_poll_timeout(ispi
->sregs
+ SSFSTS_CTL
, val
,
299 !(val
& SSFSTS_CTL_SCIP
), 0,
300 INTEL_SPI_TIMEOUT
* 1000);
303 static int intel_spi_init(struct intel_spi
*ispi
)
305 u32 opmenu0
, opmenu1
, lvscc
, uvscc
, val
;
308 switch (ispi
->info
->type
) {
310 ispi
->sregs
= ispi
->base
+ BYT_SSFSTS_CTL
;
311 ispi
->pregs
= ispi
->base
+ BYT_PR
;
312 ispi
->nregions
= BYT_FREG_NUM
;
313 ispi
->pr_num
= BYT_PR_NUM
;
314 ispi
->swseq_reg
= true;
317 /* Disable write protection */
318 val
= readl(ispi
->base
+ BYT_BCR
);
319 if (!(val
& BYT_BCR_WPD
)) {
321 writel(val
, ispi
->base
+ BYT_BCR
);
322 val
= readl(ispi
->base
+ BYT_BCR
);
325 ispi
->writeable
= !!(val
& BYT_BCR_WPD
);
331 ispi
->sregs
= ispi
->base
+ LPT_SSFSTS_CTL
;
332 ispi
->pregs
= ispi
->base
+ LPT_PR
;
333 ispi
->nregions
= LPT_FREG_NUM
;
334 ispi
->pr_num
= LPT_PR_NUM
;
335 ispi
->swseq_reg
= true;
339 ispi
->sregs
= ispi
->base
+ BXT_SSFSTS_CTL
;
340 ispi
->pregs
= ispi
->base
+ BXT_PR
;
341 ispi
->nregions
= BXT_FREG_NUM
;
342 ispi
->pr_num
= BXT_PR_NUM
;
343 ispi
->erase_64k
= true;
350 /* Disable #SMI generation from HW sequencer */
351 val
= readl(ispi
->base
+ HSFSTS_CTL
);
352 val
&= ~HSFSTS_CTL_FSMIE
;
353 writel(val
, ispi
->base
+ HSFSTS_CTL
);
356 * Determine whether erase operation should use HW or SW sequencer.
358 * The HW sequencer has a predefined list of opcodes, with only the
359 * erase opcode being programmable in LVSCC and UVSCC registers.
360 * If these registers don't contain a valid erase opcode, erase
361 * cannot be done using HW sequencer.
363 lvscc
= readl(ispi
->base
+ LVSCC
);
364 uvscc
= readl(ispi
->base
+ UVSCC
);
365 if (!(lvscc
& ERASE_OPCODE_MASK
) || !(uvscc
& ERASE_OPCODE_MASK
))
366 ispi
->swseq_erase
= true;
367 /* SPI controller on Intel BXT supports 64K erase opcode */
368 if (ispi
->info
->type
== INTEL_SPI_BXT
&& !ispi
->swseq_erase
)
369 if (!(lvscc
& ERASE_64K_OPCODE_MASK
) ||
370 !(uvscc
& ERASE_64K_OPCODE_MASK
))
371 ispi
->erase_64k
= false;
374 * Some controllers can only do basic operations using hardware
375 * sequencer. All other operations are supposed to be carried out
376 * using software sequencer.
378 if (ispi
->swseq_reg
) {
379 /* Disable #SMI generation from SW sequencer */
380 val
= readl(ispi
->sregs
+ SSFSTS_CTL
);
381 val
&= ~SSFSTS_CTL_FSMIE
;
382 writel(val
, ispi
->sregs
+ SSFSTS_CTL
);
385 /* Check controller's lock status */
386 val
= readl(ispi
->base
+ HSFSTS_CTL
);
387 ispi
->locked
= !!(val
& HSFSTS_CTL_FLOCKDN
);
391 * BIOS programs allowed opcodes and then locks down the
392 * register. So read back what opcodes it decided to support.
393 * That's the set we are going to support as well.
395 opmenu0
= readl(ispi
->sregs
+ OPMENU0
);
396 opmenu1
= readl(ispi
->sregs
+ OPMENU1
);
398 if (opmenu0
&& opmenu1
) {
399 for (i
= 0; i
< ARRAY_SIZE(ispi
->opcodes
) / 2; i
++) {
400 ispi
->opcodes
[i
] = opmenu0
>> i
* 8;
401 ispi
->opcodes
[i
+ 4] = opmenu1
>> i
* 8;
404 val
= readl(ispi
->sregs
+ PREOP_OPTYPE
);
405 ispi
->preopcodes
[0] = val
;
406 ispi
->preopcodes
[1] = val
>> 8;
410 intel_spi_dump_regs(ispi
);
415 static int intel_spi_opcode_index(struct intel_spi
*ispi
, u8 opcode
, int optype
)
421 for (i
= 0; i
< ARRAY_SIZE(ispi
->opcodes
); i
++)
422 if (ispi
->opcodes
[i
] == opcode
)
428 /* The lock is off, so just use index 0 */
429 writel(opcode
, ispi
->sregs
+ OPMENU0
);
430 preop
= readw(ispi
->sregs
+ PREOP_OPTYPE
);
431 writel(optype
<< 16 | preop
, ispi
->sregs
+ PREOP_OPTYPE
);
436 static int intel_spi_hw_cycle(struct intel_spi
*ispi
, u8 opcode
, int len
)
441 val
= readl(ispi
->base
+ HSFSTS_CTL
);
442 val
&= ~(HSFSTS_CTL_FCYCLE_MASK
| HSFSTS_CTL_FDBC_MASK
);
446 val
|= HSFSTS_CTL_FCYCLE_RDID
;
449 val
|= HSFSTS_CTL_FCYCLE_WRSR
;
452 val
|= HSFSTS_CTL_FCYCLE_RDSR
;
458 if (len
> INTEL_SPI_FIFO_SZ
)
461 val
|= (len
- 1) << HSFSTS_CTL_FDBC_SHIFT
;
462 val
|= HSFSTS_CTL_FCERR
| HSFSTS_CTL_FDONE
;
463 val
|= HSFSTS_CTL_FGO
;
464 writel(val
, ispi
->base
+ HSFSTS_CTL
);
466 ret
= intel_spi_wait_hw_busy(ispi
);
470 status
= readl(ispi
->base
+ HSFSTS_CTL
);
471 if (status
& HSFSTS_CTL_FCERR
)
473 else if (status
& HSFSTS_CTL_AEL
)
479 static int intel_spi_sw_cycle(struct intel_spi
*ispi
, u8 opcode
, int len
,
486 ret
= intel_spi_opcode_index(ispi
, opcode
, optype
);
490 if (len
> INTEL_SPI_FIFO_SZ
)
493 /* Only mark 'Data Cycle' bit when there is data to be transferred */
495 val
= ((len
- 1) << SSFSTS_CTL_DBC_SHIFT
) | SSFSTS_CTL_DS
;
496 val
|= ret
<< SSFSTS_CTL_COP_SHIFT
;
497 val
|= SSFSTS_CTL_FCERR
| SSFSTS_CTL_FDONE
;
498 val
|= SSFSTS_CTL_SCGO
;
499 preop
= readw(ispi
->sregs
+ PREOP_OPTYPE
);
501 val
|= SSFSTS_CTL_ACS
;
503 val
|= SSFSTS_CTL_SPOP
;
505 writel(val
, ispi
->sregs
+ SSFSTS_CTL
);
507 ret
= intel_spi_wait_sw_busy(ispi
);
511 status
= readl(ispi
->sregs
+ SSFSTS_CTL
);
512 if (status
& SSFSTS_CTL_FCERR
)
514 else if (status
& SSFSTS_CTL_AEL
)
520 static int intel_spi_read_reg(struct spi_nor
*nor
, u8 opcode
, u8
*buf
, int len
)
522 struct intel_spi
*ispi
= nor
->priv
;
525 /* Address of the first chip */
526 writel(0, ispi
->base
+ FADDR
);
529 ret
= intel_spi_sw_cycle(ispi
, opcode
, len
,
530 OPTYPE_READ_NO_ADDR
);
532 ret
= intel_spi_hw_cycle(ispi
, opcode
, len
);
537 return intel_spi_read_block(ispi
, buf
, len
);
540 static int intel_spi_write_reg(struct spi_nor
*nor
, u8 opcode
, u8
*buf
, int len
)
542 struct intel_spi
*ispi
= nor
->priv
;
546 * This is handled with atomic operation and preop code in Intel
547 * controller so skip it here now. If the controller is not locked,
548 * program the opcode to the PREOP register for later use.
550 if (opcode
== SPINOR_OP_WREN
) {
552 writel(opcode
, ispi
->sregs
+ PREOP_OPTYPE
);
557 writel(0, ispi
->base
+ FADDR
);
559 /* Write the value beforehand */
560 ret
= intel_spi_write_block(ispi
, buf
, len
);
565 return intel_spi_sw_cycle(ispi
, opcode
, len
,
566 OPTYPE_WRITE_NO_ADDR
);
567 return intel_spi_hw_cycle(ispi
, opcode
, len
);
570 static ssize_t
intel_spi_read(struct spi_nor
*nor
, loff_t from
, size_t len
,
573 struct intel_spi
*ispi
= nor
->priv
;
574 size_t block_size
, retlen
= 0;
578 switch (nor
->read_opcode
) {
580 case SPINOR_OP_READ_FAST
:
587 block_size
= min_t(size_t, len
, INTEL_SPI_FIFO_SZ
);
589 writel(from
, ispi
->base
+ FADDR
);
591 val
= readl(ispi
->base
+ HSFSTS_CTL
);
592 val
&= ~(HSFSTS_CTL_FDBC_MASK
| HSFSTS_CTL_FCYCLE_MASK
);
593 val
|= HSFSTS_CTL_AEL
| HSFSTS_CTL_FCERR
| HSFSTS_CTL_FDONE
;
594 val
|= (block_size
- 1) << HSFSTS_CTL_FDBC_SHIFT
;
595 val
|= HSFSTS_CTL_FCYCLE_READ
;
596 val
|= HSFSTS_CTL_FGO
;
597 writel(val
, ispi
->base
+ HSFSTS_CTL
);
599 ret
= intel_spi_wait_hw_busy(ispi
);
603 status
= readl(ispi
->base
+ HSFSTS_CTL
);
604 if (status
& HSFSTS_CTL_FCERR
)
606 else if (status
& HSFSTS_CTL_AEL
)
610 dev_err(ispi
->dev
, "read error: %llx: %#x\n", from
,
615 ret
= intel_spi_read_block(ispi
, read_buf
, block_size
);
621 retlen
+= block_size
;
622 read_buf
+= block_size
;
628 static ssize_t
intel_spi_write(struct spi_nor
*nor
, loff_t to
, size_t len
,
629 const u_char
*write_buf
)
631 struct intel_spi
*ispi
= nor
->priv
;
632 size_t block_size
, retlen
= 0;
637 block_size
= min_t(size_t, len
, INTEL_SPI_FIFO_SZ
);
639 writel(to
, ispi
->base
+ FADDR
);
641 val
= readl(ispi
->base
+ HSFSTS_CTL
);
642 val
&= ~(HSFSTS_CTL_FDBC_MASK
| HSFSTS_CTL_FCYCLE_MASK
);
643 val
|= HSFSTS_CTL_AEL
| HSFSTS_CTL_FCERR
| HSFSTS_CTL_FDONE
;
644 val
|= (block_size
- 1) << HSFSTS_CTL_FDBC_SHIFT
;
645 val
|= HSFSTS_CTL_FCYCLE_WRITE
;
647 ret
= intel_spi_write_block(ispi
, write_buf
, block_size
);
649 dev_err(ispi
->dev
, "failed to write block\n");
653 /* Start the write now */
654 val
|= HSFSTS_CTL_FGO
;
655 writel(val
, ispi
->base
+ HSFSTS_CTL
);
657 ret
= intel_spi_wait_hw_busy(ispi
);
659 dev_err(ispi
->dev
, "timeout\n");
663 status
= readl(ispi
->base
+ HSFSTS_CTL
);
664 if (status
& HSFSTS_CTL_FCERR
)
666 else if (status
& HSFSTS_CTL_AEL
)
670 dev_err(ispi
->dev
, "write error: %llx: %#x\n", to
,
677 retlen
+= block_size
;
678 write_buf
+= block_size
;
684 static int intel_spi_erase(struct spi_nor
*nor
, loff_t offs
)
686 size_t erase_size
, len
= nor
->mtd
.erasesize
;
687 struct intel_spi
*ispi
= nor
->priv
;
688 u32 val
, status
, cmd
;
691 /* If the hardware can do 64k erase use that when possible */
692 if (len
>= SZ_64K
&& ispi
->erase_64k
) {
693 cmd
= HSFSTS_CTL_FCYCLE_ERASE_64K
;
696 cmd
= HSFSTS_CTL_FCYCLE_ERASE
;
700 if (ispi
->swseq_erase
) {
702 writel(offs
, ispi
->base
+ FADDR
);
704 ret
= intel_spi_sw_cycle(ispi
, nor
->erase_opcode
,
705 0, OPTYPE_WRITE_WITH_ADDR
);
717 writel(offs
, ispi
->base
+ FADDR
);
719 val
= readl(ispi
->base
+ HSFSTS_CTL
);
720 val
&= ~(HSFSTS_CTL_FDBC_MASK
| HSFSTS_CTL_FCYCLE_MASK
);
721 val
|= HSFSTS_CTL_AEL
| HSFSTS_CTL_FCERR
| HSFSTS_CTL_FDONE
;
723 val
|= HSFSTS_CTL_FGO
;
724 writel(val
, ispi
->base
+ HSFSTS_CTL
);
726 ret
= intel_spi_wait_hw_busy(ispi
);
730 status
= readl(ispi
->base
+ HSFSTS_CTL
);
731 if (status
& HSFSTS_CTL_FCERR
)
733 else if (status
& HSFSTS_CTL_AEL
)
743 static bool intel_spi_is_protected(const struct intel_spi
*ispi
,
744 unsigned int base
, unsigned int limit
)
748 for (i
= 0; i
< ispi
->pr_num
; i
++) {
749 u32 pr_base
, pr_limit
, pr_value
;
751 pr_value
= readl(ispi
->pregs
+ PR(i
));
752 if (!(pr_value
& (PR_WPE
| PR_RPE
)))
755 pr_limit
= (pr_value
& PR_LIMIT_MASK
) >> PR_LIMIT_SHIFT
;
756 pr_base
= pr_value
& PR_BASE_MASK
;
758 if (pr_base
>= base
&& pr_limit
<= limit
)
766 * There will be a single partition holding all enabled flash regions. We
769 static void intel_spi_fill_partition(struct intel_spi
*ispi
,
770 struct mtd_partition
*part
)
775 memset(part
, 0, sizeof(*part
));
777 /* Start from the mandatory descriptor region */
782 * Now try to find where this partition ends based on the flash
785 for (i
= 1; i
< ispi
->nregions
; i
++) {
786 u32 region
, base
, limit
;
788 region
= readl(ispi
->base
+ FREG(i
));
789 base
= region
& FREG_BASE_MASK
;
790 limit
= (region
& FREG_LIMIT_MASK
) >> FREG_LIMIT_SHIFT
;
792 if (base
>= limit
|| limit
== 0)
796 * If any of the regions have protection bits set, make the
797 * whole partition read-only to be on the safe side.
799 if (intel_spi_is_protected(ispi
, base
, limit
))
800 ispi
->writeable
= false;
802 end
= (limit
<< 12) + 4096;
803 if (end
> part
->size
)
808 struct intel_spi
*intel_spi_probe(struct device
*dev
,
809 struct resource
*mem
, const struct intel_spi_boardinfo
*info
)
811 const struct spi_nor_hwcaps hwcaps
= {
812 .mask
= SNOR_HWCAPS_READ
|
813 SNOR_HWCAPS_READ_FAST
|
816 struct mtd_partition part
;
817 struct intel_spi
*ispi
;
821 return ERR_PTR(-EINVAL
);
823 ispi
= devm_kzalloc(dev
, sizeof(*ispi
), GFP_KERNEL
);
825 return ERR_PTR(-ENOMEM
);
827 ispi
->base
= devm_ioremap_resource(dev
, mem
);
828 if (IS_ERR(ispi
->base
))
829 return ERR_CAST(ispi
->base
);
833 ispi
->writeable
= info
->writeable
;
835 ret
= intel_spi_init(ispi
);
839 ispi
->nor
.dev
= ispi
->dev
;
840 ispi
->nor
.priv
= ispi
;
841 ispi
->nor
.read_reg
= intel_spi_read_reg
;
842 ispi
->nor
.write_reg
= intel_spi_write_reg
;
843 ispi
->nor
.read
= intel_spi_read
;
844 ispi
->nor
.write
= intel_spi_write
;
845 ispi
->nor
.erase
= intel_spi_erase
;
847 ret
= spi_nor_scan(&ispi
->nor
, NULL
, &hwcaps
);
849 dev_info(dev
, "failed to locate the chip\n");
853 intel_spi_fill_partition(ispi
, &part
);
855 /* Prevent writes if not explicitly enabled */
856 if (!ispi
->writeable
|| !writeable
)
857 ispi
->nor
.mtd
.flags
&= ~MTD_WRITEABLE
;
859 ret
= mtd_device_parse_register(&ispi
->nor
.mtd
, NULL
, NULL
, &part
, 1);
865 EXPORT_SYMBOL_GPL(intel_spi_probe
);
867 int intel_spi_remove(struct intel_spi
*ispi
)
869 return mtd_device_unregister(&ispi
->nor
.mtd
);
871 EXPORT_SYMBOL_GPL(intel_spi_remove
);
873 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
874 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
875 MODULE_LICENSE("GPL v2");