2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
32 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
35 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
38 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40 #define SPI_NOR_MAX_ID_LEN 6
41 #define SPI_NOR_MAX_ADDR_WIDTH 4
47 * This array stores the ID bytes.
48 * The first three bytes are the JEDIC ID.
49 * JEDEC ID zero means "no ID" (mostly older chips).
51 u8 id
[SPI_NOR_MAX_ID_LEN
];
54 /* The size listed here is what works with SPINOR_OP_SE, which isn't
55 * necessarily called a "sector" by the vendor.
64 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
65 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
66 #define SST_WRITE BIT(2) /* use SST byte programming */
67 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
68 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
69 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
70 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
71 #define USE_FSR BIT(7) /* use flag status register */
72 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
73 #define SPI_NOR_HAS_TB BIT(9) /*
74 * Flash SR has Top/Bottom (TB) protect
75 * bit. Must be used with
78 #define SPI_S3AN BIT(10) /*
79 * Xilinx Spartan 3AN In-System Flash
80 * (MFR cannot be used for probing
81 * because it has the same value as
84 #define SPI_NOR_4B_OPCODES BIT(11) /*
85 * Use dedicated 4byte address op codes
86 * to support memory size above 128Mib.
90 #define JEDEC_MFR(info) ((info)->id[0])
92 static const struct flash_info
*spi_nor_match_id(const char *name
);
95 * Read the status register, returning its value in the location
96 * Return the status register value.
97 * Returns negative if error occurred.
99 static int read_sr(struct spi_nor
*nor
)
104 ret
= nor
->read_reg(nor
, SPINOR_OP_RDSR
, &val
, 1);
106 pr_err("error %d reading SR\n", (int) ret
);
114 * Read the flag status register, returning its value in the location
115 * Return the status register value.
116 * Returns negative if error occurred.
118 static int read_fsr(struct spi_nor
*nor
)
123 ret
= nor
->read_reg(nor
, SPINOR_OP_RDFSR
, &val
, 1);
125 pr_err("error %d reading FSR\n", ret
);
133 * Read configuration register, returning its value in the
134 * location. Return the configuration register value.
135 * Returns negative if error occurred.
137 static int read_cr(struct spi_nor
*nor
)
142 ret
= nor
->read_reg(nor
, SPINOR_OP_RDCR
, &val
, 1);
144 dev_err(nor
->dev
, "error %d reading CR\n", ret
);
152 * Dummy Cycle calculation for different type of read.
153 * It can be used to support more commands with
154 * different dummy cycle requirements.
156 static inline int spi_nor_read_dummy_cycles(struct spi_nor
*nor
)
158 switch (nor
->flash_read
) {
170 * Write status register 1 byte
171 * Returns negative if error occurred.
173 static inline int write_sr(struct spi_nor
*nor
, u8 val
)
175 nor
->cmd_buf
[0] = val
;
176 return nor
->write_reg(nor
, SPINOR_OP_WRSR
, nor
->cmd_buf
, 1);
180 * Set write enable latch with Write Enable command.
181 * Returns negative if error occurred.
183 static inline int write_enable(struct spi_nor
*nor
)
185 return nor
->write_reg(nor
, SPINOR_OP_WREN
, NULL
, 0);
189 * Send write disble instruction to the chip.
191 static inline int write_disable(struct spi_nor
*nor
)
193 return nor
->write_reg(nor
, SPINOR_OP_WRDI
, NULL
, 0);
196 static inline struct spi_nor
*mtd_to_spi_nor(struct mtd_info
*mtd
)
202 static u8
spi_nor_convert_opcode(u8 opcode
, const u8 table
[][2], size_t size
)
206 for (i
= 0; i
< size
; i
++)
207 if (table
[i
][0] == opcode
)
210 /* No conversion found, keep input op code. */
214 static inline u8
spi_nor_convert_3to4_read(u8 opcode
)
216 static const u8 spi_nor_3to4_read
[][2] = {
217 { SPINOR_OP_READ
, SPINOR_OP_READ_4B
},
218 { SPINOR_OP_READ_FAST
, SPINOR_OP_READ_FAST_4B
},
219 { SPINOR_OP_READ_1_1_2
, SPINOR_OP_READ_1_1_2_4B
},
220 { SPINOR_OP_READ_1_2_2
, SPINOR_OP_READ_1_2_2_4B
},
221 { SPINOR_OP_READ_1_1_4
, SPINOR_OP_READ_1_1_4_4B
},
222 { SPINOR_OP_READ_1_4_4
, SPINOR_OP_READ_1_4_4_4B
},
225 return spi_nor_convert_opcode(opcode
, spi_nor_3to4_read
,
226 ARRAY_SIZE(spi_nor_3to4_read
));
229 static inline u8
spi_nor_convert_3to4_program(u8 opcode
)
231 static const u8 spi_nor_3to4_program
[][2] = {
232 { SPINOR_OP_PP
, SPINOR_OP_PP_4B
},
233 { SPINOR_OP_PP_1_1_4
, SPINOR_OP_PP_1_1_4_4B
},
234 { SPINOR_OP_PP_1_4_4
, SPINOR_OP_PP_1_4_4_4B
},
237 return spi_nor_convert_opcode(opcode
, spi_nor_3to4_program
,
238 ARRAY_SIZE(spi_nor_3to4_program
));
241 static inline u8
spi_nor_convert_3to4_erase(u8 opcode
)
243 static const u8 spi_nor_3to4_erase
[][2] = {
244 { SPINOR_OP_BE_4K
, SPINOR_OP_BE_4K_4B
},
245 { SPINOR_OP_BE_32K
, SPINOR_OP_BE_32K_4B
},
246 { SPINOR_OP_SE
, SPINOR_OP_SE_4B
},
249 return spi_nor_convert_opcode(opcode
, spi_nor_3to4_erase
,
250 ARRAY_SIZE(spi_nor_3to4_erase
));
253 static void spi_nor_set_4byte_opcodes(struct spi_nor
*nor
,
254 const struct flash_info
*info
)
256 /* Do some manufacturer fixups first */
257 switch (JEDEC_MFR(info
)) {
258 case SNOR_MFR_SPANSION
:
259 /* No small sector erase for 4-byte command set */
260 nor
->erase_opcode
= SPINOR_OP_SE
;
261 nor
->mtd
.erasesize
= info
->sector_size
;
268 nor
->read_opcode
= spi_nor_convert_3to4_read(nor
->read_opcode
);
269 nor
->program_opcode
= spi_nor_convert_3to4_program(nor
->program_opcode
);
270 nor
->erase_opcode
= spi_nor_convert_3to4_erase(nor
->erase_opcode
);
273 /* Enable/disable 4-byte addressing mode. */
274 static inline int set_4byte(struct spi_nor
*nor
, const struct flash_info
*info
,
278 bool need_wren
= false;
281 switch (JEDEC_MFR(info
)) {
282 case SNOR_MFR_MICRON
:
283 /* Some Micron need WREN command; all will accept it */
285 case SNOR_MFR_MACRONIX
:
286 case SNOR_MFR_WINBOND
:
290 cmd
= enable
? SPINOR_OP_EN4B
: SPINOR_OP_EX4B
;
291 status
= nor
->write_reg(nor
, cmd
, NULL
, 0);
298 nor
->cmd_buf
[0] = enable
<< 7;
299 return nor
->write_reg(nor
, SPINOR_OP_BRWR
, nor
->cmd_buf
, 1);
303 static int s3an_sr_ready(struct spi_nor
*nor
)
308 ret
= nor
->read_reg(nor
, SPINOR_OP_XRDSR
, &val
, 1);
310 dev_err(nor
->dev
, "error %d reading XRDSR\n", (int) ret
);
314 return !!(val
& XSR_RDY
);
317 static inline int spi_nor_sr_ready(struct spi_nor
*nor
)
319 int sr
= read_sr(nor
);
323 return !(sr
& SR_WIP
);
326 static inline int spi_nor_fsr_ready(struct spi_nor
*nor
)
328 int fsr
= read_fsr(nor
);
332 return fsr
& FSR_READY
;
335 static int spi_nor_ready(struct spi_nor
*nor
)
339 if (nor
->flags
& SNOR_F_READY_XSR_RDY
)
340 sr
= s3an_sr_ready(nor
);
342 sr
= spi_nor_sr_ready(nor
);
345 fsr
= nor
->flags
& SNOR_F_USE_FSR
? spi_nor_fsr_ready(nor
) : 1;
352 * Service routine to read status register until ready, or timeout occurs.
353 * Returns non-zero if error.
355 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor
*nor
,
356 unsigned long timeout_jiffies
)
358 unsigned long deadline
;
359 int timeout
= 0, ret
;
361 deadline
= jiffies
+ timeout_jiffies
;
364 if (time_after_eq(jiffies
, deadline
))
367 ret
= spi_nor_ready(nor
);
376 dev_err(nor
->dev
, "flash operation timed out\n");
381 static int spi_nor_wait_till_ready(struct spi_nor
*nor
)
383 return spi_nor_wait_till_ready_with_timeout(nor
,
384 DEFAULT_READY_WAIT_JIFFIES
);
388 * Erase the whole flash memory
390 * Returns 0 if successful, non-zero otherwise.
392 static int erase_chip(struct spi_nor
*nor
)
394 dev_dbg(nor
->dev
, " %lldKiB\n", (long long)(nor
->mtd
.size
>> 10));
396 return nor
->write_reg(nor
, SPINOR_OP_CHIP_ERASE
, NULL
, 0);
399 static int spi_nor_lock_and_prep(struct spi_nor
*nor
, enum spi_nor_ops ops
)
403 mutex_lock(&nor
->lock
);
406 ret
= nor
->prepare(nor
, ops
);
408 dev_err(nor
->dev
, "failed in the preparation.\n");
409 mutex_unlock(&nor
->lock
);
416 static void spi_nor_unlock_and_unprep(struct spi_nor
*nor
, enum spi_nor_ops ops
)
419 nor
->unprepare(nor
, ops
);
420 mutex_unlock(&nor
->lock
);
424 * This code converts an address to the Default Address Mode, that has non
425 * power of two page sizes. We must support this mode because it is the default
426 * mode supported by Xilinx tools, it can access the whole flash area and
427 * changing over to the Power-of-two mode is irreversible and corrupts the
429 * Addr can safely be unsigned int, the biggest S3AN device is smaller than
432 static loff_t
spi_nor_s3an_addr_convert(struct spi_nor
*nor
, unsigned int addr
)
437 offset
= addr
% nor
->page_size
;
438 page
= addr
/ nor
->page_size
;
439 page
<<= (nor
->page_size
> 512) ? 10 : 9;
441 return page
| offset
;
445 * Initiate the erasure of a single sector
447 static int spi_nor_erase_sector(struct spi_nor
*nor
, u32 addr
)
449 u8 buf
[SPI_NOR_MAX_ADDR_WIDTH
];
452 if (nor
->flags
& SNOR_F_S3AN_ADDR_DEFAULT
)
453 addr
= spi_nor_s3an_addr_convert(nor
, addr
);
456 return nor
->erase(nor
, addr
);
459 * Default implementation, if driver doesn't have a specialized HW
462 for (i
= nor
->addr_width
- 1; i
>= 0; i
--) {
463 buf
[i
] = addr
& 0xff;
467 return nor
->write_reg(nor
, nor
->erase_opcode
, buf
, nor
->addr_width
);
471 * Erase an address range on the nor chip. The address range may extend
472 * one or more erase sectors. Return an error is there is a problem erasing.
474 static int spi_nor_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
476 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
481 dev_dbg(nor
->dev
, "at 0x%llx, len %lld\n", (long long)instr
->addr
,
482 (long long)instr
->len
);
484 div_u64_rem(instr
->len
, mtd
->erasesize
, &rem
);
491 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_ERASE
);
495 /* whole-chip erase? */
496 if (len
== mtd
->size
&& !(nor
->flags
& SNOR_F_NO_OP_CHIP_ERASE
)) {
497 unsigned long timeout
;
501 if (erase_chip(nor
)) {
507 * Scale the timeout linearly with the size of the flash, with
508 * a minimum calibrated to an old 2MB flash. We could try to
509 * pull these from CFI/SFDP, but these values should be good
512 timeout
= max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES
,
513 CHIP_ERASE_2MB_READY_WAIT_JIFFIES
*
514 (unsigned long)(mtd
->size
/ SZ_2M
));
515 ret
= spi_nor_wait_till_ready_with_timeout(nor
, timeout
);
519 /* REVISIT in some cases we could speed up erasing large regions
520 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
521 * to use "small sector erase", but that's not always optimal.
524 /* "sector"-at-a-time erase */
529 ret
= spi_nor_erase_sector(nor
, addr
);
533 addr
+= mtd
->erasesize
;
534 len
-= mtd
->erasesize
;
536 ret
= spi_nor_wait_till_ready(nor
);
545 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_ERASE
);
547 instr
->state
= ret
? MTD_ERASE_FAILED
: MTD_ERASE_DONE
;
548 mtd_erase_callback(instr
);
553 static void stm_get_locked_range(struct spi_nor
*nor
, u8 sr
, loff_t
*ofs
,
556 struct mtd_info
*mtd
= &nor
->mtd
;
557 u8 mask
= SR_BP2
| SR_BP1
| SR_BP0
;
558 int shift
= ffs(mask
) - 1;
566 pow
= ((sr
& mask
) ^ mask
) >> shift
;
567 *len
= mtd
->size
>> pow
;
568 if (nor
->flags
& SNOR_F_HAS_SR_TB
&& sr
& SR_TB
)
571 *ofs
= mtd
->size
- *len
;
576 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
577 * @locked is false); 0 otherwise
579 static int stm_check_lock_status_sr(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
,
588 stm_get_locked_range(nor
, sr
, &lock_offs
, &lock_len
);
591 /* Requested range is a sub-range of locked range */
592 return (ofs
+ len
<= lock_offs
+ lock_len
) && (ofs
>= lock_offs
);
594 /* Requested range does not overlap with locked range */
595 return (ofs
>= lock_offs
+ lock_len
) || (ofs
+ len
<= lock_offs
);
598 static int stm_is_locked_sr(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
,
601 return stm_check_lock_status_sr(nor
, ofs
, len
, sr
, true);
604 static int stm_is_unlocked_sr(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
,
607 return stm_check_lock_status_sr(nor
, ofs
, len
, sr
, false);
611 * Lock a region of the flash. Compatible with ST Micro and similar flash.
612 * Supports the block protection bits BP{0,1,2} in the status register
613 * (SR). Does not support these features found in newer SR bitfields:
614 * - SEC: sector/block protect - only handle SEC=0 (block protect)
615 * - CMP: complement protect - only support CMP=0 (range is not complemented)
617 * Support for the following is provided conditionally for some flash:
618 * - TB: top/bottom protect
620 * Sample table portion for 8MB flash (Winbond w25q64fw):
622 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
623 * --------------------------------------------------------------------------
624 * X | X | 0 | 0 | 0 | NONE | NONE
625 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
626 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
627 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
628 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
629 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
630 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
631 * X | X | 1 | 1 | 1 | 8 MB | ALL
632 * ------|-------|-------|-------|-------|---------------|-------------------
633 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
634 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
635 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
636 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
637 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
638 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
640 * Returns negative on errors, 0 on success.
642 static int stm_lock(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
)
644 struct mtd_info
*mtd
= &nor
->mtd
;
645 int status_old
, status_new
;
646 u8 mask
= SR_BP2
| SR_BP1
| SR_BP0
;
647 u8 shift
= ffs(mask
) - 1, pow
, val
;
649 bool can_be_top
= true, can_be_bottom
= nor
->flags
& SNOR_F_HAS_SR_TB
;
653 status_old
= read_sr(nor
);
657 /* If nothing in our range is unlocked, we don't need to do anything */
658 if (stm_is_locked_sr(nor
, ofs
, len
, status_old
))
661 /* If anything below us is unlocked, we can't use 'bottom' protection */
662 if (!stm_is_locked_sr(nor
, 0, ofs
, status_old
))
663 can_be_bottom
= false;
665 /* If anything above us is unlocked, we can't use 'top' protection */
666 if (!stm_is_locked_sr(nor
, ofs
+ len
, mtd
->size
- (ofs
+ len
),
670 if (!can_be_bottom
&& !can_be_top
)
673 /* Prefer top, if both are valid */
674 use_top
= can_be_top
;
676 /* lock_len: length of region that should end up locked */
678 lock_len
= mtd
->size
- ofs
;
680 lock_len
= ofs
+ len
;
683 * Need smallest pow such that:
685 * 1 / (2^pow) <= (len / size)
687 * so (assuming power-of-2 size) we do:
689 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
691 pow
= ilog2(mtd
->size
) - ilog2(lock_len
);
692 val
= mask
- (pow
<< shift
);
695 /* Don't "lock" with no region! */
699 status_new
= (status_old
& ~mask
& ~SR_TB
) | val
;
701 /* Disallow further writes if WP pin is asserted */
702 status_new
|= SR_SRWD
;
707 /* Don't bother if they're the same */
708 if (status_new
== status_old
)
711 /* Only modify protection if it will not unlock other areas */
712 if ((status_new
& mask
) < (status_old
& mask
))
716 ret
= write_sr(nor
, status_new
);
719 return spi_nor_wait_till_ready(nor
);
723 * Unlock a region of the flash. See stm_lock() for more info
725 * Returns negative on errors, 0 on success.
727 static int stm_unlock(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
)
729 struct mtd_info
*mtd
= &nor
->mtd
;
730 int status_old
, status_new
;
731 u8 mask
= SR_BP2
| SR_BP1
| SR_BP0
;
732 u8 shift
= ffs(mask
) - 1, pow
, val
;
734 bool can_be_top
= true, can_be_bottom
= nor
->flags
& SNOR_F_HAS_SR_TB
;
738 status_old
= read_sr(nor
);
742 /* If nothing in our range is locked, we don't need to do anything */
743 if (stm_is_unlocked_sr(nor
, ofs
, len
, status_old
))
746 /* If anything below us is locked, we can't use 'top' protection */
747 if (!stm_is_unlocked_sr(nor
, 0, ofs
, status_old
))
750 /* If anything above us is locked, we can't use 'bottom' protection */
751 if (!stm_is_unlocked_sr(nor
, ofs
+ len
, mtd
->size
- (ofs
+ len
),
753 can_be_bottom
= false;
755 if (!can_be_bottom
&& !can_be_top
)
758 /* Prefer top, if both are valid */
759 use_top
= can_be_top
;
761 /* lock_len: length of region that should remain locked */
763 lock_len
= mtd
->size
- (ofs
+ len
);
768 * Need largest pow such that:
770 * 1 / (2^pow) >= (len / size)
772 * so (assuming power-of-2 size) we do:
774 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
776 pow
= ilog2(mtd
->size
) - order_base_2(lock_len
);
778 val
= 0; /* fully unlocked */
780 val
= mask
- (pow
<< shift
);
781 /* Some power-of-two sizes are not supported */
786 status_new
= (status_old
& ~mask
& ~SR_TB
) | val
;
788 /* Don't protect status register if we're fully unlocked */
790 status_new
&= ~SR_SRWD
;
795 /* Don't bother if they're the same */
796 if (status_new
== status_old
)
799 /* Only modify protection if it will not lock other areas */
800 if ((status_new
& mask
) > (status_old
& mask
))
804 ret
= write_sr(nor
, status_new
);
807 return spi_nor_wait_till_ready(nor
);
811 * Check if a region of the flash is (completely) locked. See stm_lock() for
814 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
815 * negative on errors.
817 static int stm_is_locked(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
)
821 status
= read_sr(nor
);
825 return stm_is_locked_sr(nor
, ofs
, len
, status
);
828 static int spi_nor_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
830 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
833 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_LOCK
);
837 ret
= nor
->flash_lock(nor
, ofs
, len
);
839 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_UNLOCK
);
843 static int spi_nor_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
845 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
848 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_UNLOCK
);
852 ret
= nor
->flash_unlock(nor
, ofs
, len
);
854 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_LOCK
);
858 static int spi_nor_is_locked(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
860 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
863 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_UNLOCK
);
867 ret
= nor
->flash_is_locked(nor
, ofs
, len
);
869 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_LOCK
);
873 /* Used when the "_ext_id" is two bytes at most */
874 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
876 ((_jedec_id) >> 16) & 0xff, \
877 ((_jedec_id) >> 8) & 0xff, \
878 (_jedec_id) & 0xff, \
879 ((_ext_id) >> 8) & 0xff, \
882 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
883 .sector_size = (_sector_size), \
884 .n_sectors = (_n_sectors), \
888 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
890 ((_jedec_id) >> 16) & 0xff, \
891 ((_jedec_id) >> 8) & 0xff, \
892 (_jedec_id) & 0xff, \
893 ((_ext_id) >> 16) & 0xff, \
894 ((_ext_id) >> 8) & 0xff, \
898 .sector_size = (_sector_size), \
899 .n_sectors = (_n_sectors), \
903 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
904 .sector_size = (_sector_size), \
905 .n_sectors = (_n_sectors), \
906 .page_size = (_page_size), \
907 .addr_width = (_addr_width), \
910 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
912 ((_jedec_id) >> 16) & 0xff, \
913 ((_jedec_id) >> 8) & 0xff, \
917 .sector_size = (8*_page_size), \
918 .n_sectors = (_n_sectors), \
919 .page_size = _page_size, \
921 .flags = SPI_NOR_NO_FR | SPI_S3AN,
923 /* NOTE: double check command sets and memory organization when you add
924 * more nor chips. This current list focusses on newer chips, which
925 * have been converging on command sets which including JEDEC ID.
927 * All newly added entries should describe *hardware* and should use SECT_4K
928 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
929 * scenarios excluding small sectors there is config option that can be
930 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
931 * For historical (and compatibility) reasons (before we got above config) some
932 * old entries may be missing 4K flag.
934 static const struct flash_info spi_nor_ids
[] = {
935 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
936 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K
) },
937 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K
) },
939 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K
) },
940 { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K
) },
941 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K
) },
942 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K
) },
944 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K
) },
945 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K
) },
946 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K
) },
947 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K
) },
949 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K
) },
952 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K
) },
953 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
954 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
955 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
956 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K
) },
957 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
958 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
959 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K
) },
962 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K
| SPI_NOR_HAS_LOCK
) },
965 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
966 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
967 { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
970 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE
) },
974 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
975 SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
|
976 SPI_NOR_HAS_LOCK
| SPI_NOR_HAS_TB
)
979 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
980 SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
|
981 SPI_NOR_HAS_LOCK
| SPI_NOR_HAS_TB
)
984 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
985 SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
|
986 SPI_NOR_HAS_LOCK
| SPI_NOR_HAS_TB
)
989 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
990 SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
|
991 SPI_NOR_HAS_LOCK
| SPI_NOR_HAS_TB
)
994 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
995 SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
|
996 SPI_NOR_HAS_LOCK
| SPI_NOR_HAS_TB
)
999 /* Intel/Numonyx -- xxxs33b */
1000 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
1001 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
1002 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
1005 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K
) },
1008 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K
) },
1009 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K
) },
1010 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K
) },
1011 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
1012 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K
) },
1013 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K
) },
1014 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K
) },
1015 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K
) },
1016 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K
) },
1017 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1018 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1019 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
1020 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K
) },
1021 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1022 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ
) },
1023 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ
) },
1026 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K
| SPI_NOR_QUAD_READ
) },
1027 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ
) },
1028 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ
) },
1029 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K
| SPI_NOR_QUAD_READ
) },
1030 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K
| SPI_NOR_QUAD_READ
) },
1031 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K
| SPI_NOR_QUAD_READ
) },
1032 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K
| SPI_NOR_QUAD_READ
) },
1033 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K
| SPI_NOR_QUAD_READ
) },
1034 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K
| USE_FSR
| SPI_NOR_QUAD_READ
) },
1035 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K
| USE_FSR
| SPI_NOR_QUAD_READ
) },
1036 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K
| USE_FSR
| SPI_NOR_QUAD_READ
) },
1037 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K
| USE_FSR
| SPI_NOR_QUAD_READ
) },
1040 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC
) },
1041 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC
) },
1042 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K
) },
1044 /* Spansion -- single (large) sector size only, at least
1045 * for the chips listed here (without boot sectors).
1047 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1048 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1049 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
1050 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1051 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1052 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
1053 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1054 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1055 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1056 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1057 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1058 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
1059 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1060 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
1061 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
1062 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
1063 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1064 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1065 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1066 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
) },
1067 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
1068 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K
) },
1069 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K
) },
1070 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K
| SPI_NOR_DUAL_READ
) },
1071 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K
| SPI_NOR_DUAL_READ
) },
1073 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1074 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K
| SST_WRITE
) },
1075 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K
| SST_WRITE
) },
1076 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K
| SST_WRITE
) },
1077 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K
| SST_WRITE
) },
1078 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K
) },
1079 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K
| SST_WRITE
) },
1080 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K
| SST_WRITE
) },
1081 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K
| SST_WRITE
) },
1082 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K
) },
1083 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K
) },
1084 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K
| SST_WRITE
) },
1085 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K
| SST_WRITE
) },
1087 /* ST Microelectronics -- newer production may have feature updates */
1088 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
1089 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1090 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1091 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1092 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1093 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1094 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1095 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1096 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1098 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
1099 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
1100 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
1101 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
1102 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
1103 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1104 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1105 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1106 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1108 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1109 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1110 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1112 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1113 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1114 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K
) },
1116 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K
) },
1117 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K
) },
1118 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K
) },
1119 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K
) },
1120 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1121 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
1123 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1124 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K
) },
1125 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K
) },
1126 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K
) },
1127 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K
) },
1128 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K
) },
1129 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K
) },
1130 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K
) },
1131 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K
) },
1133 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
1134 SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
|
1135 SPI_NOR_HAS_LOCK
| SPI_NOR_HAS_TB
)
1137 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K
) },
1138 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
) },
1140 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1141 SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
|
1142 SPI_NOR_HAS_LOCK
| SPI_NOR_HAS_TB
)
1145 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1146 SECT_4K
| SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
|
1147 SPI_NOR_HAS_LOCK
| SPI_NOR_HAS_TB
)
1149 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K
) },
1150 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K
) },
1151 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K
) },
1152 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K
) },
1154 /* Catalyst / On Semiconductor -- non-JEDEC */
1155 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
1156 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
1157 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
1158 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
1159 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
1161 /* Xilinx S3AN Internal Flash */
1162 { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
1163 { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
1164 { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
1165 { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
1166 { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
1170 static const struct flash_info
*spi_nor_read_id(struct spi_nor
*nor
)
1173 u8 id
[SPI_NOR_MAX_ID_LEN
];
1174 const struct flash_info
*info
;
1176 tmp
= nor
->read_reg(nor
, SPINOR_OP_RDID
, id
, SPI_NOR_MAX_ID_LEN
);
1178 dev_dbg(nor
->dev
, "error %d reading JEDEC ID\n", tmp
);
1179 return ERR_PTR(tmp
);
1182 for (tmp
= 0; tmp
< ARRAY_SIZE(spi_nor_ids
) - 1; tmp
++) {
1183 info
= &spi_nor_ids
[tmp
];
1185 if (!memcmp(info
->id
, id
, info
->id_len
))
1186 return &spi_nor_ids
[tmp
];
1189 dev_err(nor
->dev
, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1190 id
[0], id
[1], id
[2]);
1191 return ERR_PTR(-ENODEV
);
1194 static int spi_nor_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1195 size_t *retlen
, u_char
*buf
)
1197 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
1200 dev_dbg(nor
->dev
, "from 0x%08x, len %zd\n", (u32
)from
, len
);
1202 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_READ
);
1209 if (nor
->flags
& SNOR_F_S3AN_ADDR_DEFAULT
)
1210 addr
= spi_nor_s3an_addr_convert(nor
, addr
);
1212 ret
= nor
->read(nor
, addr
, len
, buf
);
1214 /* We shouldn't see 0-length reads */
1230 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_READ
);
1234 static int sst_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
1235 size_t *retlen
, const u_char
*buf
)
1237 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
1241 dev_dbg(nor
->dev
, "to 0x%08x, len %zd\n", (u32
)to
, len
);
1243 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_WRITE
);
1249 nor
->sst_write_second
= false;
1252 /* Start write from odd address. */
1254 nor
->program_opcode
= SPINOR_OP_BP
;
1256 /* write one byte. */
1257 ret
= nor
->write(nor
, to
, 1, buf
);
1260 WARN(ret
!= 1, "While writing 1 byte written %i bytes\n",
1262 ret
= spi_nor_wait_till_ready(nor
);
1268 /* Write out most of the data here. */
1269 for (; actual
< len
- 1; actual
+= 2) {
1270 nor
->program_opcode
= SPINOR_OP_AAI_WP
;
1272 /* write two bytes. */
1273 ret
= nor
->write(nor
, to
, 2, buf
+ actual
);
1276 WARN(ret
!= 2, "While writing 2 bytes written %i bytes\n",
1278 ret
= spi_nor_wait_till_ready(nor
);
1282 nor
->sst_write_second
= true;
1284 nor
->sst_write_second
= false;
1287 ret
= spi_nor_wait_till_ready(nor
);
1291 /* Write out trailing byte if it exists. */
1292 if (actual
!= len
) {
1295 nor
->program_opcode
= SPINOR_OP_BP
;
1296 ret
= nor
->write(nor
, to
, 1, buf
+ actual
);
1299 WARN(ret
!= 1, "While writing 1 byte written %i bytes\n",
1301 ret
= spi_nor_wait_till_ready(nor
);
1309 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_WRITE
);
1314 * Write an address range to the nor chip. Data must be written in
1315 * FLASH_PAGESIZE chunks. The address range may be any size provided
1316 * it is within the physical boundaries.
1318 static int spi_nor_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
1319 size_t *retlen
, const u_char
*buf
)
1321 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
1322 size_t page_offset
, page_remain
, i
;
1325 dev_dbg(nor
->dev
, "to 0x%08x, len %zd\n", (u32
)to
, len
);
1327 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_WRITE
);
1331 for (i
= 0; i
< len
; ) {
1333 loff_t addr
= to
+ i
;
1336 * If page_size is a power of two, the offset can be quickly
1337 * calculated with an AND operation. On the other cases we
1338 * need to do a modulus operation (more expensive).
1339 * Power of two numbers have only one bit set and we can use
1340 * the instruction hweight32 to detect if we need to do a
1341 * modulus (do_div()) or not.
1343 if (hweight32(nor
->page_size
) == 1) {
1344 page_offset
= addr
& (nor
->page_size
- 1);
1346 uint64_t aux
= addr
;
1348 page_offset
= do_div(aux
, nor
->page_size
);
1350 /* the size of data remaining on the first page */
1351 page_remain
= min_t(size_t,
1352 nor
->page_size
- page_offset
, len
- i
);
1354 if (nor
->flags
& SNOR_F_S3AN_ADDR_DEFAULT
)
1355 addr
= spi_nor_s3an_addr_convert(nor
, addr
);
1358 ret
= nor
->write(nor
, addr
, page_remain
, buf
+ i
);
1363 ret
= spi_nor_wait_till_ready(nor
);
1368 if (written
!= page_remain
) {
1370 "While writing %zu bytes written %zd bytes\n",
1371 page_remain
, written
);
1378 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_WRITE
);
1382 static int macronix_quad_enable(struct spi_nor
*nor
)
1389 if (val
& SR_QUAD_EN_MX
)
1394 write_sr(nor
, val
| SR_QUAD_EN_MX
);
1396 if (spi_nor_wait_till_ready(nor
))
1400 if (!(ret
> 0 && (ret
& SR_QUAD_EN_MX
))) {
1401 dev_err(nor
->dev
, "Macronix Quad bit not set\n");
1409 * Write status Register and configuration register with 2 bytes
1410 * The first byte will be written to the status register, while the
1411 * second byte will be written to the configuration register.
1412 * Return negative if error occurred.
1414 static int write_sr_cr(struct spi_nor
*nor
, u16 val
)
1416 nor
->cmd_buf
[0] = val
& 0xff;
1417 nor
->cmd_buf
[1] = (val
>> 8);
1419 return nor
->write_reg(nor
, SPINOR_OP_WRSR
, nor
->cmd_buf
, 2);
1422 static int spansion_quad_enable(struct spi_nor
*nor
)
1425 int quad_en
= CR_QUAD_EN_SPAN
<< 8;
1429 ret
= write_sr_cr(nor
, quad_en
);
1432 "error while writing configuration register\n");
1436 ret
= spi_nor_wait_till_ready(nor
);
1439 "timeout while writing configuration register\n");
1443 /* read back and check it */
1445 if (!(ret
> 0 && (ret
& CR_QUAD_EN_SPAN
))) {
1446 dev_err(nor
->dev
, "Spansion Quad bit not set\n");
1453 static int set_quad_mode(struct spi_nor
*nor
, const struct flash_info
*info
)
1457 switch (JEDEC_MFR(info
)) {
1458 case SNOR_MFR_MACRONIX
:
1459 status
= macronix_quad_enable(nor
);
1461 dev_err(nor
->dev
, "Macronix quad-read not enabled\n");
1465 case SNOR_MFR_MICRON
:
1468 status
= spansion_quad_enable(nor
);
1470 dev_err(nor
->dev
, "Spansion quad-read not enabled\n");
1477 static int spi_nor_check(struct spi_nor
*nor
)
1479 if (!nor
->dev
|| !nor
->read
|| !nor
->write
||
1480 !nor
->read_reg
|| !nor
->write_reg
) {
1481 pr_err("spi-nor: please fill all the necessary fields!\n");
1488 static int s3an_nor_scan(const struct flash_info
*info
, struct spi_nor
*nor
)
1493 ret
= nor
->read_reg(nor
, SPINOR_OP_XRDSR
, &val
, 1);
1495 dev_err(nor
->dev
, "error %d reading XRDSR\n", (int) ret
);
1499 nor
->erase_opcode
= SPINOR_OP_XSE
;
1500 nor
->program_opcode
= SPINOR_OP_XPP
;
1501 nor
->read_opcode
= SPINOR_OP_READ
;
1502 nor
->flags
|= SNOR_F_NO_OP_CHIP_ERASE
;
1505 * This flashes have a page size of 264 or 528 bytes (known as
1506 * Default addressing mode). It can be changed to a more standard
1507 * Power of two mode where the page size is 256/512. This comes
1508 * with a price: there is 3% less of space, the data is corrupted
1509 * and the page size cannot be changed back to default addressing
1512 * The current addressing mode can be read from the XRDSR register
1513 * and should not be changed, because is a destructive operation.
1515 if (val
& XSR_PAGESIZE
) {
1516 /* Flash in Power of 2 mode */
1517 nor
->page_size
= (nor
->page_size
== 264) ? 256 : 512;
1518 nor
->mtd
.writebufsize
= nor
->page_size
;
1519 nor
->mtd
.size
= 8 * nor
->page_size
* info
->n_sectors
;
1520 nor
->mtd
.erasesize
= 8 * nor
->page_size
;
1522 /* Flash in Default addressing mode */
1523 nor
->flags
|= SNOR_F_S3AN_ADDR_DEFAULT
;
1529 int spi_nor_scan(struct spi_nor
*nor
, const char *name
, enum read_mode mode
)
1531 const struct flash_info
*info
= NULL
;
1532 struct device
*dev
= nor
->dev
;
1533 struct mtd_info
*mtd
= &nor
->mtd
;
1534 struct device_node
*np
= spi_nor_get_flash_node(nor
);
1538 ret
= spi_nor_check(nor
);
1543 info
= spi_nor_match_id(name
);
1544 /* Try to auto-detect if chip name wasn't specified or not found */
1546 info
= spi_nor_read_id(nor
);
1547 if (IS_ERR_OR_NULL(info
))
1551 * If caller has specified name of flash model that can normally be
1552 * detected using JEDEC, let's verify it.
1554 if (name
&& info
->id_len
) {
1555 const struct flash_info
*jinfo
;
1557 jinfo
= spi_nor_read_id(nor
);
1558 if (IS_ERR(jinfo
)) {
1559 return PTR_ERR(jinfo
);
1560 } else if (jinfo
!= info
) {
1562 * JEDEC knows better, so overwrite platform ID. We
1563 * can't trust partitions any longer, but we'll let
1564 * mtd apply them anyway, since some partitions may be
1565 * marked read-only, and we don't want to lose that
1566 * information, even if it's not 100% accurate.
1568 dev_warn(dev
, "found %s, expected %s\n",
1569 jinfo
->name
, info
->name
);
1574 mutex_init(&nor
->lock
);
1577 * Make sure the XSR_RDY flag is set before calling
1578 * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
1579 * with Atmel spi-nor
1581 if (info
->flags
& SPI_S3AN
)
1582 nor
->flags
|= SNOR_F_READY_XSR_RDY
;
1585 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1586 * with the software protection bits set
1589 if (JEDEC_MFR(info
) == SNOR_MFR_ATMEL
||
1590 JEDEC_MFR(info
) == SNOR_MFR_INTEL
||
1591 JEDEC_MFR(info
) == SNOR_MFR_SST
||
1592 info
->flags
& SPI_NOR_HAS_LOCK
) {
1595 spi_nor_wait_till_ready(nor
);
1599 mtd
->name
= dev_name(dev
);
1601 mtd
->type
= MTD_NORFLASH
;
1603 mtd
->flags
= MTD_CAP_NORFLASH
;
1604 mtd
->size
= info
->sector_size
* info
->n_sectors
;
1605 mtd
->_erase
= spi_nor_erase
;
1606 mtd
->_read
= spi_nor_read
;
1608 /* NOR protection support for STmicro/Micron chips and similar */
1609 if (JEDEC_MFR(info
) == SNOR_MFR_MICRON
||
1610 info
->flags
& SPI_NOR_HAS_LOCK
) {
1611 nor
->flash_lock
= stm_lock
;
1612 nor
->flash_unlock
= stm_unlock
;
1613 nor
->flash_is_locked
= stm_is_locked
;
1616 if (nor
->flash_lock
&& nor
->flash_unlock
&& nor
->flash_is_locked
) {
1617 mtd
->_lock
= spi_nor_lock
;
1618 mtd
->_unlock
= spi_nor_unlock
;
1619 mtd
->_is_locked
= spi_nor_is_locked
;
1622 /* sst nor chips use AAI word program */
1623 if (info
->flags
& SST_WRITE
)
1624 mtd
->_write
= sst_write
;
1626 mtd
->_write
= spi_nor_write
;
1628 if (info
->flags
& USE_FSR
)
1629 nor
->flags
|= SNOR_F_USE_FSR
;
1630 if (info
->flags
& SPI_NOR_HAS_TB
)
1631 nor
->flags
|= SNOR_F_HAS_SR_TB
;
1633 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1634 /* prefer "small sector" erase if possible */
1635 if (info
->flags
& SECT_4K
) {
1636 nor
->erase_opcode
= SPINOR_OP_BE_4K
;
1637 mtd
->erasesize
= 4096;
1638 } else if (info
->flags
& SECT_4K_PMC
) {
1639 nor
->erase_opcode
= SPINOR_OP_BE_4K_PMC
;
1640 mtd
->erasesize
= 4096;
1644 nor
->erase_opcode
= SPINOR_OP_SE
;
1645 mtd
->erasesize
= info
->sector_size
;
1648 if (info
->flags
& SPI_NOR_NO_ERASE
)
1649 mtd
->flags
|= MTD_NO_ERASE
;
1651 mtd
->dev
.parent
= dev
;
1652 nor
->page_size
= info
->page_size
;
1653 mtd
->writebufsize
= nor
->page_size
;
1656 /* If we were instantiated by DT, use it */
1657 if (of_property_read_bool(np
, "m25p,fast-read"))
1658 nor
->flash_read
= SPI_NOR_FAST
;
1660 nor
->flash_read
= SPI_NOR_NORMAL
;
1662 /* If we weren't instantiated by DT, default to fast-read */
1663 nor
->flash_read
= SPI_NOR_FAST
;
1666 /* Some devices cannot do fast-read, no matter what DT tells us */
1667 if (info
->flags
& SPI_NOR_NO_FR
)
1668 nor
->flash_read
= SPI_NOR_NORMAL
;
1670 /* Quad/Dual-read mode takes precedence over fast/normal */
1671 if (mode
== SPI_NOR_QUAD
&& info
->flags
& SPI_NOR_QUAD_READ
) {
1672 ret
= set_quad_mode(nor
, info
);
1674 dev_err(dev
, "quad mode not supported\n");
1677 nor
->flash_read
= SPI_NOR_QUAD
;
1678 } else if (mode
== SPI_NOR_DUAL
&& info
->flags
& SPI_NOR_DUAL_READ
) {
1679 nor
->flash_read
= SPI_NOR_DUAL
;
1682 /* Default commands */
1683 switch (nor
->flash_read
) {
1685 nor
->read_opcode
= SPINOR_OP_READ_1_1_4
;
1688 nor
->read_opcode
= SPINOR_OP_READ_1_1_2
;
1691 nor
->read_opcode
= SPINOR_OP_READ_FAST
;
1693 case SPI_NOR_NORMAL
:
1694 nor
->read_opcode
= SPINOR_OP_READ
;
1697 dev_err(dev
, "No Read opcode defined\n");
1701 nor
->program_opcode
= SPINOR_OP_PP
;
1703 if (info
->addr_width
)
1704 nor
->addr_width
= info
->addr_width
;
1705 else if (mtd
->size
> 0x1000000) {
1706 /* enable 4-byte addressing if the device exceeds 16MiB */
1707 nor
->addr_width
= 4;
1708 if (JEDEC_MFR(info
) == SNOR_MFR_SPANSION
||
1709 info
->flags
& SPI_NOR_4B_OPCODES
)
1710 spi_nor_set_4byte_opcodes(nor
, info
);
1712 set_4byte(nor
, info
, 1);
1714 nor
->addr_width
= 3;
1717 if (nor
->addr_width
> SPI_NOR_MAX_ADDR_WIDTH
) {
1718 dev_err(dev
, "address width is too large: %u\n",
1723 nor
->read_dummy
= spi_nor_read_dummy_cycles(nor
);
1725 if (info
->flags
& SPI_S3AN
) {
1726 ret
= s3an_nor_scan(info
, nor
);
1731 dev_info(dev
, "%s (%lld Kbytes)\n", info
->name
,
1732 (long long)mtd
->size
>> 10);
1735 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1736 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1737 mtd
->name
, (long long)mtd
->size
, (long long)(mtd
->size
>> 20),
1738 mtd
->erasesize
, mtd
->erasesize
/ 1024, mtd
->numeraseregions
);
1740 if (mtd
->numeraseregions
)
1741 for (i
= 0; i
< mtd
->numeraseregions
; i
++)
1743 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1744 ".erasesize = 0x%.8x (%uKiB), "
1745 ".numblocks = %d }\n",
1746 i
, (long long)mtd
->eraseregions
[i
].offset
,
1747 mtd
->eraseregions
[i
].erasesize
,
1748 mtd
->eraseregions
[i
].erasesize
/ 1024,
1749 mtd
->eraseregions
[i
].numblocks
);
1752 EXPORT_SYMBOL_GPL(spi_nor_scan
);
1754 static const struct flash_info
*spi_nor_match_id(const char *name
)
1756 const struct flash_info
*id
= spi_nor_ids
;
1759 if (!strcmp(name
, id
->name
))
1766 MODULE_LICENSE("GPL");
1767 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1768 MODULE_AUTHOR("Mike Lavender");
1769 MODULE_DESCRIPTION("framework for SPI NOR");