2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
20 #include <linux/mtd/cfi.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
26 /* Define max times to check status register before we give up. */
27 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
29 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
31 static const struct spi_device_id
*spi_nor_match_id(const char *name
);
34 * Read the status register, returning its value in the location
35 * Return the status register value.
36 * Returns negative if error occurred.
38 static int read_sr(struct spi_nor
*nor
)
43 ret
= nor
->read_reg(nor
, SPINOR_OP_RDSR
, &val
, 1);
45 pr_err("error %d reading SR\n", (int) ret
);
53 * Read the flag status register, returning its value in the location
54 * Return the status register value.
55 * Returns negative if error occurred.
57 static int read_fsr(struct spi_nor
*nor
)
62 ret
= nor
->read_reg(nor
, SPINOR_OP_RDFSR
, &val
, 1);
64 pr_err("error %d reading FSR\n", ret
);
72 * Read configuration register, returning its value in the
73 * location. Return the configuration register value.
74 * Returns negative if error occured.
76 static int read_cr(struct spi_nor
*nor
)
81 ret
= nor
->read_reg(nor
, SPINOR_OP_RDCR
, &val
, 1);
83 dev_err(nor
->dev
, "error %d reading CR\n", ret
);
91 * Dummy Cycle calculation for different type of read.
92 * It can be used to support more commands with
93 * different dummy cycle requirements.
95 static inline int spi_nor_read_dummy_cycles(struct spi_nor
*nor
)
97 switch (nor
->flash_read
) {
109 * Write status register 1 byte
110 * Returns negative if error occurred.
112 static inline int write_sr(struct spi_nor
*nor
, u8 val
)
114 nor
->cmd_buf
[0] = val
;
115 return nor
->write_reg(nor
, SPINOR_OP_WRSR
, nor
->cmd_buf
, 1, 0);
119 * Set write enable latch with Write Enable command.
120 * Returns negative if error occurred.
122 static inline int write_enable(struct spi_nor
*nor
)
124 return nor
->write_reg(nor
, SPINOR_OP_WREN
, NULL
, 0, 0);
128 * Send write disble instruction to the chip.
130 static inline int write_disable(struct spi_nor
*nor
)
132 return nor
->write_reg(nor
, SPINOR_OP_WRDI
, NULL
, 0, 0);
135 static inline struct spi_nor
*mtd_to_spi_nor(struct mtd_info
*mtd
)
140 /* Enable/disable 4-byte addressing mode. */
141 static inline int set_4byte(struct spi_nor
*nor
, u32 jedec_id
, int enable
)
144 bool need_wren
= false;
147 switch (JEDEC_MFR(jedec_id
)) {
148 case CFI_MFR_ST
: /* Micron, actually */
149 /* Some Micron need WREN command; all will accept it */
151 case CFI_MFR_MACRONIX
:
152 case 0xEF /* winbond */:
156 cmd
= enable
? SPINOR_OP_EN4B
: SPINOR_OP_EX4B
;
157 status
= nor
->write_reg(nor
, cmd
, NULL
, 0, 0);
164 nor
->cmd_buf
[0] = enable
<< 7;
165 return nor
->write_reg(nor
, SPINOR_OP_BRWR
, nor
->cmd_buf
, 1, 0);
168 static inline int spi_nor_sr_ready(struct spi_nor
*nor
)
170 int sr
= read_sr(nor
);
174 return !(sr
& SR_WIP
);
177 static inline int spi_nor_fsr_ready(struct spi_nor
*nor
)
179 int fsr
= read_fsr(nor
);
183 return fsr
& FSR_READY
;
186 static int spi_nor_ready(struct spi_nor
*nor
)
189 sr
= spi_nor_sr_ready(nor
);
192 fsr
= nor
->flags
& SNOR_F_USE_FSR
? spi_nor_fsr_ready(nor
) : 1;
198 static int spi_nor_wait_till_ready(struct spi_nor
*nor
)
200 unsigned long deadline
;
203 deadline
= jiffies
+ MAX_READY_WAIT_JIFFIES
;
208 ret
= spi_nor_ready(nor
);
213 } while (!time_after_eq(jiffies
, deadline
));
219 * Service routine to read status register until ready, or timeout occurs.
220 * Returns non-zero if error.
222 static int wait_till_ready(struct spi_nor
*nor
)
224 return nor
->wait_till_ready(nor
);
228 * Erase the whole flash memory
230 * Returns 0 if successful, non-zero otherwise.
232 static int erase_chip(struct spi_nor
*nor
)
236 dev_dbg(nor
->dev
, " %lldKiB\n", (long long)(nor
->mtd
->size
>> 10));
238 /* Wait until finished previous write command. */
239 ret
= wait_till_ready(nor
);
243 /* Send write enable, then erase commands. */
246 return nor
->write_reg(nor
, SPINOR_OP_CHIP_ERASE
, NULL
, 0, 0);
249 static int spi_nor_lock_and_prep(struct spi_nor
*nor
, enum spi_nor_ops ops
)
253 mutex_lock(&nor
->lock
);
256 ret
= nor
->prepare(nor
, ops
);
258 dev_err(nor
->dev
, "failed in the preparation.\n");
259 mutex_unlock(&nor
->lock
);
266 static void spi_nor_unlock_and_unprep(struct spi_nor
*nor
, enum spi_nor_ops ops
)
269 nor
->unprepare(nor
, ops
);
270 mutex_unlock(&nor
->lock
);
274 * Erase an address range on the nor chip. The address range may extend
275 * one or more erase sectors. Return an error is there is a problem erasing.
277 static int spi_nor_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
279 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
284 dev_dbg(nor
->dev
, "at 0x%llx, len %lld\n", (long long)instr
->addr
,
285 (long long)instr
->len
);
287 div_u64_rem(instr
->len
, mtd
->erasesize
, &rem
);
294 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_ERASE
);
298 /* whole-chip erase? */
299 if (len
== mtd
->size
) {
300 if (erase_chip(nor
)) {
305 /* REVISIT in some cases we could speed up erasing large regions
306 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
307 * to use "small sector erase", but that's not always optimal.
310 /* "sector"-at-a-time erase */
313 if (nor
->erase(nor
, addr
)) {
318 addr
+= mtd
->erasesize
;
319 len
-= mtd
->erasesize
;
323 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_ERASE
);
325 instr
->state
= MTD_ERASE_DONE
;
326 mtd_erase_callback(instr
);
331 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_ERASE
);
332 instr
->state
= MTD_ERASE_FAILED
;
336 static int spi_nor_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
338 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
339 uint32_t offset
= ofs
;
340 uint8_t status_old
, status_new
;
343 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_LOCK
);
347 /* Wait until finished previous command */
348 ret
= wait_till_ready(nor
);
352 status_old
= read_sr(nor
);
354 if (offset
< mtd
->size
- (mtd
->size
/ 2))
355 status_new
= status_old
| SR_BP2
| SR_BP1
| SR_BP0
;
356 else if (offset
< mtd
->size
- (mtd
->size
/ 4))
357 status_new
= (status_old
& ~SR_BP0
) | SR_BP2
| SR_BP1
;
358 else if (offset
< mtd
->size
- (mtd
->size
/ 8))
359 status_new
= (status_old
& ~SR_BP1
) | SR_BP2
| SR_BP0
;
360 else if (offset
< mtd
->size
- (mtd
->size
/ 16))
361 status_new
= (status_old
& ~(SR_BP0
| SR_BP1
)) | SR_BP2
;
362 else if (offset
< mtd
->size
- (mtd
->size
/ 32))
363 status_new
= (status_old
& ~SR_BP2
) | SR_BP1
| SR_BP0
;
364 else if (offset
< mtd
->size
- (mtd
->size
/ 64))
365 status_new
= (status_old
& ~(SR_BP2
| SR_BP0
)) | SR_BP1
;
367 status_new
= (status_old
& ~(SR_BP2
| SR_BP1
)) | SR_BP0
;
369 /* Only modify protection if it will not unlock other areas */
370 if ((status_new
& (SR_BP2
| SR_BP1
| SR_BP0
)) >
371 (status_old
& (SR_BP2
| SR_BP1
| SR_BP0
))) {
373 ret
= write_sr(nor
, status_new
);
379 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_LOCK
);
383 static int spi_nor_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
385 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
386 uint32_t offset
= ofs
;
387 uint8_t status_old
, status_new
;
390 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_UNLOCK
);
394 /* Wait until finished previous command */
395 ret
= wait_till_ready(nor
);
399 status_old
= read_sr(nor
);
401 if (offset
+len
> mtd
->size
- (mtd
->size
/ 64))
402 status_new
= status_old
& ~(SR_BP2
| SR_BP1
| SR_BP0
);
403 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 32))
404 status_new
= (status_old
& ~(SR_BP2
| SR_BP1
)) | SR_BP0
;
405 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 16))
406 status_new
= (status_old
& ~(SR_BP2
| SR_BP0
)) | SR_BP1
;
407 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 8))
408 status_new
= (status_old
& ~SR_BP2
) | SR_BP1
| SR_BP0
;
409 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 4))
410 status_new
= (status_old
& ~(SR_BP0
| SR_BP1
)) | SR_BP2
;
411 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 2))
412 status_new
= (status_old
& ~SR_BP1
) | SR_BP2
| SR_BP0
;
414 status_new
= (status_old
& ~SR_BP0
) | SR_BP2
| SR_BP1
;
416 /* Only modify protection if it will not lock other areas */
417 if ((status_new
& (SR_BP2
| SR_BP1
| SR_BP0
)) <
418 (status_old
& (SR_BP2
| SR_BP1
| SR_BP0
))) {
420 ret
= write_sr(nor
, status_new
);
426 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_UNLOCK
);
431 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
432 * a high byte of zero plus three data bytes: the manufacturer id,
433 * then a two byte device id.
438 /* The size listed here is what works with SPINOR_OP_SE, which isn't
439 * necessarily called a "sector" by the vendor.
441 unsigned sector_size
;
448 #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
449 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
450 #define SST_WRITE 0x04 /* use SST byte programming */
451 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
452 #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
453 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
454 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
455 #define USE_FSR 0x80 /* use flag status register */
458 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
459 ((kernel_ulong_t)&(struct flash_info) { \
460 .jedec_id = (_jedec_id), \
461 .ext_id = (_ext_id), \
462 .sector_size = (_sector_size), \
463 .n_sectors = (_n_sectors), \
468 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
469 ((kernel_ulong_t)&(struct flash_info) { \
470 .sector_size = (_sector_size), \
471 .n_sectors = (_n_sectors), \
472 .page_size = (_page_size), \
473 .addr_width = (_addr_width), \
477 /* NOTE: double check command sets and memory organization when you add
478 * more nor chips. This current list focusses on newer chips, which
479 * have been converging on command sets which including JEDEC ID.
481 static const struct spi_device_id spi_nor_ids
[] = {
482 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
483 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K
) },
484 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K
) },
486 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K
) },
487 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K
) },
488 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K
) },
490 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K
) },
491 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K
) },
492 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K
) },
493 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K
) },
495 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K
) },
498 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K
) },
499 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
500 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
501 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
502 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K
) },
503 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
504 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
507 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K
) },
510 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
511 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
514 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K
) },
515 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K
) },
517 /* Intel/Numonyx -- xxxs33b */
518 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
519 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
520 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
523 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K
) },
524 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K
) },
525 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
526 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K
) },
527 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
528 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K
) },
529 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
530 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
531 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
532 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
533 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
534 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ
) },
535 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ
) },
538 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
539 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
540 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
541 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K
) },
542 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K
) },
543 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR
) },
544 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR
) },
547 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC
) },
548 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC
) },
549 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K
) },
551 /* Spansion -- single (large) sector size only, at least
552 * for the chips listed here (without boot sectors).
554 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
555 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
556 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
557 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
558 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
559 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
560 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
561 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
562 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
563 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
564 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
565 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
566 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
567 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
568 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
569 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K
) },
570 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K
) },
571 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
) },
573 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
574 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K
| SST_WRITE
) },
575 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K
| SST_WRITE
) },
576 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K
| SST_WRITE
) },
577 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K
| SST_WRITE
) },
578 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K
) },
579 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K
| SST_WRITE
) },
580 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K
| SST_WRITE
) },
581 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K
| SST_WRITE
) },
582 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K
| SST_WRITE
) },
584 /* ST Microelectronics -- newer production may have feature updates */
585 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
586 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
587 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
588 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
589 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
590 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
591 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
592 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
593 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
594 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
596 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
597 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
598 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
599 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
600 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
601 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
602 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
603 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
604 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
606 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
607 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
608 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
610 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
611 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
612 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K
) },
614 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K
) },
615 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K
) },
616 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K
) },
617 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K
) },
618 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
619 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
621 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
622 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K
) },
623 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K
) },
624 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K
) },
625 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K
) },
626 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K
) },
627 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K
) },
628 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K
) },
629 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K
) },
630 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K
) },
631 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
) },
632 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K
) },
633 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K
) },
634 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K
) },
635 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K
) },
637 /* Catalyst / On Semiconductor -- non-JEDEC */
638 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
639 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
640 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
641 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
642 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
646 static const struct spi_device_id
*spi_nor_read_id(struct spi_nor
*nor
)
652 struct flash_info
*info
;
654 tmp
= nor
->read_reg(nor
, SPINOR_OP_RDID
, id
, 5);
656 dev_dbg(nor
->dev
, " error %d reading JEDEC ID\n", tmp
);
665 ext_jedec
= id
[3] << 8 | id
[4];
667 for (tmp
= 0; tmp
< ARRAY_SIZE(spi_nor_ids
) - 1; tmp
++) {
668 info
= (void *)spi_nor_ids
[tmp
].driver_data
;
669 if (info
->jedec_id
== jedec
) {
670 if (info
->ext_id
== 0 || info
->ext_id
== ext_jedec
)
671 return &spi_nor_ids
[tmp
];
674 dev_err(nor
->dev
, "unrecognized JEDEC id %06x\n", jedec
);
675 return ERR_PTR(-ENODEV
);
678 static int spi_nor_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
679 size_t *retlen
, u_char
*buf
)
681 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
684 dev_dbg(nor
->dev
, "from 0x%08x, len %zd\n", (u32
)from
, len
);
686 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_READ
);
690 ret
= nor
->read(nor
, from
, len
, retlen
, buf
);
692 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_READ
);
696 static int sst_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
697 size_t *retlen
, const u_char
*buf
)
699 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
703 dev_dbg(nor
->dev
, "to 0x%08x, len %zd\n", (u32
)to
, len
);
705 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_WRITE
);
709 /* Wait until finished previous write command. */
710 ret
= wait_till_ready(nor
);
716 nor
->sst_write_second
= false;
719 /* Start write from odd address. */
721 nor
->program_opcode
= SPINOR_OP_BP
;
723 /* write one byte. */
724 nor
->write(nor
, to
, 1, retlen
, buf
);
725 ret
= wait_till_ready(nor
);
731 /* Write out most of the data here. */
732 for (; actual
< len
- 1; actual
+= 2) {
733 nor
->program_opcode
= SPINOR_OP_AAI_WP
;
735 /* write two bytes. */
736 nor
->write(nor
, to
, 2, retlen
, buf
+ actual
);
737 ret
= wait_till_ready(nor
);
741 nor
->sst_write_second
= true;
743 nor
->sst_write_second
= false;
746 ret
= wait_till_ready(nor
);
750 /* Write out trailing byte if it exists. */
754 nor
->program_opcode
= SPINOR_OP_BP
;
755 nor
->write(nor
, to
, 1, retlen
, buf
+ actual
);
757 ret
= wait_till_ready(nor
);
763 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_WRITE
);
768 * Write an address range to the nor chip. Data must be written in
769 * FLASH_PAGESIZE chunks. The address range may be any size provided
770 * it is within the physical boundaries.
772 static int spi_nor_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
773 size_t *retlen
, const u_char
*buf
)
775 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
776 u32 page_offset
, page_size
, i
;
779 dev_dbg(nor
->dev
, "to 0x%08x, len %zd\n", (u32
)to
, len
);
781 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_WRITE
);
785 /* Wait until finished previous write command. */
786 ret
= wait_till_ready(nor
);
792 page_offset
= to
& (nor
->page_size
- 1);
794 /* do all the bytes fit onto one page? */
795 if (page_offset
+ len
<= nor
->page_size
) {
796 nor
->write(nor
, to
, len
, retlen
, buf
);
798 /* the size of data remaining on the first page */
799 page_size
= nor
->page_size
- page_offset
;
800 nor
->write(nor
, to
, page_size
, retlen
, buf
);
802 /* write everything in nor->page_size chunks */
803 for (i
= page_size
; i
< len
; i
+= page_size
) {
805 if (page_size
> nor
->page_size
)
806 page_size
= nor
->page_size
;
808 ret
= wait_till_ready(nor
);
814 nor
->write(nor
, to
+ i
, page_size
, retlen
, buf
+ i
);
819 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_WRITE
);
823 static int macronix_quad_enable(struct spi_nor
*nor
)
830 nor
->cmd_buf
[0] = val
| SR_QUAD_EN_MX
;
831 nor
->write_reg(nor
, SPINOR_OP_WRSR
, nor
->cmd_buf
, 1, 0);
833 if (wait_till_ready(nor
))
837 if (!(ret
> 0 && (ret
& SR_QUAD_EN_MX
))) {
838 dev_err(nor
->dev
, "Macronix Quad bit not set\n");
846 * Write status Register and configuration register with 2 bytes
847 * The first byte will be written to the status register, while the
848 * second byte will be written to the configuration register.
849 * Return negative if error occured.
851 static int write_sr_cr(struct spi_nor
*nor
, u16 val
)
853 nor
->cmd_buf
[0] = val
& 0xff;
854 nor
->cmd_buf
[1] = (val
>> 8);
856 return nor
->write_reg(nor
, SPINOR_OP_WRSR
, nor
->cmd_buf
, 2, 0);
859 static int spansion_quad_enable(struct spi_nor
*nor
)
862 int quad_en
= CR_QUAD_EN_SPAN
<< 8;
866 ret
= write_sr_cr(nor
, quad_en
);
869 "error while writing configuration register\n");
873 /* read back and check it */
875 if (!(ret
> 0 && (ret
& CR_QUAD_EN_SPAN
))) {
876 dev_err(nor
->dev
, "Spansion Quad bit not set\n");
883 static int set_quad_mode(struct spi_nor
*nor
, u32 jedec_id
)
887 switch (JEDEC_MFR(jedec_id
)) {
888 case CFI_MFR_MACRONIX
:
889 status
= macronix_quad_enable(nor
);
891 dev_err(nor
->dev
, "Macronix quad-read not enabled\n");
896 status
= spansion_quad_enable(nor
);
898 dev_err(nor
->dev
, "Spansion quad-read not enabled\n");
905 static int spi_nor_check(struct spi_nor
*nor
)
907 if (!nor
->dev
|| !nor
->read
|| !nor
->write
||
908 !nor
->read_reg
|| !nor
->write_reg
|| !nor
->erase
) {
909 pr_err("spi-nor: please fill all the necessary fields!\n");
913 if (!nor
->wait_till_ready
)
914 nor
->wait_till_ready
= spi_nor_wait_till_ready
;
919 int spi_nor_scan(struct spi_nor
*nor
, const char *name
, enum read_mode mode
)
921 const struct spi_device_id
*id
= NULL
;
922 struct flash_info
*info
;
923 struct device
*dev
= nor
->dev
;
924 struct mtd_info
*mtd
= nor
->mtd
;
925 struct device_node
*np
= dev
->of_node
;
929 ret
= spi_nor_check(nor
);
933 id
= spi_nor_match_id(name
);
937 info
= (void *)id
->driver_data
;
939 if (info
->jedec_id
) {
940 const struct spi_device_id
*jid
;
942 jid
= spi_nor_read_id(nor
);
945 } else if (jid
!= id
) {
947 * JEDEC knows better, so overwrite platform ID. We
948 * can't trust partitions any longer, but we'll let
949 * mtd apply them anyway, since some partitions may be
950 * marked read-only, and we don't want to lose that
951 * information, even if it's not 100% accurate.
953 dev_warn(dev
, "found %s, expected %s\n",
954 jid
->name
, id
->name
);
956 info
= (void *)jid
->driver_data
;
960 mutex_init(&nor
->lock
);
963 * Atmel, SST and Intel/Numonyx serial nor tend to power
964 * up with the software protection bits set
967 if (JEDEC_MFR(info
->jedec_id
) == CFI_MFR_ATMEL
||
968 JEDEC_MFR(info
->jedec_id
) == CFI_MFR_INTEL
||
969 JEDEC_MFR(info
->jedec_id
) == CFI_MFR_SST
) {
975 mtd
->name
= dev_name(dev
);
976 mtd
->type
= MTD_NORFLASH
;
978 mtd
->flags
= MTD_CAP_NORFLASH
;
979 mtd
->size
= info
->sector_size
* info
->n_sectors
;
980 mtd
->_erase
= spi_nor_erase
;
981 mtd
->_read
= spi_nor_read
;
983 /* nor protection support for STmicro chips */
984 if (JEDEC_MFR(info
->jedec_id
) == CFI_MFR_ST
) {
985 mtd
->_lock
= spi_nor_lock
;
986 mtd
->_unlock
= spi_nor_unlock
;
989 /* sst nor chips use AAI word program */
990 if (info
->flags
& SST_WRITE
)
991 mtd
->_write
= sst_write
;
993 mtd
->_write
= spi_nor_write
;
995 if (info
->flags
& USE_FSR
)
996 nor
->flags
|= SNOR_F_USE_FSR
;
998 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
999 /* prefer "small sector" erase if possible */
1000 if (info
->flags
& SECT_4K
) {
1001 nor
->erase_opcode
= SPINOR_OP_BE_4K
;
1002 mtd
->erasesize
= 4096;
1003 } else if (info
->flags
& SECT_4K_PMC
) {
1004 nor
->erase_opcode
= SPINOR_OP_BE_4K_PMC
;
1005 mtd
->erasesize
= 4096;
1009 nor
->erase_opcode
= SPINOR_OP_SE
;
1010 mtd
->erasesize
= info
->sector_size
;
1013 if (info
->flags
& SPI_NOR_NO_ERASE
)
1014 mtd
->flags
|= MTD_NO_ERASE
;
1016 mtd
->dev
.parent
= dev
;
1017 nor
->page_size
= info
->page_size
;
1018 mtd
->writebufsize
= nor
->page_size
;
1021 /* If we were instantiated by DT, use it */
1022 if (of_property_read_bool(np
, "m25p,fast-read"))
1023 nor
->flash_read
= SPI_NOR_FAST
;
1025 nor
->flash_read
= SPI_NOR_NORMAL
;
1027 /* If we weren't instantiated by DT, default to fast-read */
1028 nor
->flash_read
= SPI_NOR_FAST
;
1031 /* Some devices cannot do fast-read, no matter what DT tells us */
1032 if (info
->flags
& SPI_NOR_NO_FR
)
1033 nor
->flash_read
= SPI_NOR_NORMAL
;
1035 /* Quad/Dual-read mode takes precedence over fast/normal */
1036 if (mode
== SPI_NOR_QUAD
&& info
->flags
& SPI_NOR_QUAD_READ
) {
1037 ret
= set_quad_mode(nor
, info
->jedec_id
);
1039 dev_err(dev
, "quad mode not supported\n");
1042 nor
->flash_read
= SPI_NOR_QUAD
;
1043 } else if (mode
== SPI_NOR_DUAL
&& info
->flags
& SPI_NOR_DUAL_READ
) {
1044 nor
->flash_read
= SPI_NOR_DUAL
;
1047 /* Default commands */
1048 switch (nor
->flash_read
) {
1050 nor
->read_opcode
= SPINOR_OP_READ_1_1_4
;
1053 nor
->read_opcode
= SPINOR_OP_READ_1_1_2
;
1056 nor
->read_opcode
= SPINOR_OP_READ_FAST
;
1058 case SPI_NOR_NORMAL
:
1059 nor
->read_opcode
= SPINOR_OP_READ
;
1062 dev_err(dev
, "No Read opcode defined\n");
1066 nor
->program_opcode
= SPINOR_OP_PP
;
1068 if (info
->addr_width
)
1069 nor
->addr_width
= info
->addr_width
;
1070 else if (mtd
->size
> 0x1000000) {
1071 /* enable 4-byte addressing if the device exceeds 16MiB */
1072 nor
->addr_width
= 4;
1073 if (JEDEC_MFR(info
->jedec_id
) == CFI_MFR_AMD
) {
1074 /* Dedicated 4-byte command set */
1075 switch (nor
->flash_read
) {
1077 nor
->read_opcode
= SPINOR_OP_READ4_1_1_4
;
1080 nor
->read_opcode
= SPINOR_OP_READ4_1_1_2
;
1083 nor
->read_opcode
= SPINOR_OP_READ4_FAST
;
1085 case SPI_NOR_NORMAL
:
1086 nor
->read_opcode
= SPINOR_OP_READ4
;
1089 nor
->program_opcode
= SPINOR_OP_PP_4B
;
1090 /* No small sector erase for 4-byte command set */
1091 nor
->erase_opcode
= SPINOR_OP_SE_4B
;
1092 mtd
->erasesize
= info
->sector_size
;
1094 set_4byte(nor
, info
->jedec_id
, 1);
1096 nor
->addr_width
= 3;
1099 nor
->read_dummy
= spi_nor_read_dummy_cycles(nor
);
1101 dev_info(dev
, "%s (%lld Kbytes)\n", id
->name
,
1102 (long long)mtd
->size
>> 10);
1105 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1106 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1107 mtd
->name
, (long long)mtd
->size
, (long long)(mtd
->size
>> 20),
1108 mtd
->erasesize
, mtd
->erasesize
/ 1024, mtd
->numeraseregions
);
1110 if (mtd
->numeraseregions
)
1111 for (i
= 0; i
< mtd
->numeraseregions
; i
++)
1113 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1114 ".erasesize = 0x%.8x (%uKiB), "
1115 ".numblocks = %d }\n",
1116 i
, (long long)mtd
->eraseregions
[i
].offset
,
1117 mtd
->eraseregions
[i
].erasesize
,
1118 mtd
->eraseregions
[i
].erasesize
/ 1024,
1119 mtd
->eraseregions
[i
].numblocks
);
1122 EXPORT_SYMBOL_GPL(spi_nor_scan
);
1124 static const struct spi_device_id
*spi_nor_match_id(const char *name
)
1126 const struct spi_device_id
*id
= spi_nor_ids
;
1128 while (id
->name
[0]) {
1129 if (!strcmp(name
, id
->name
))
1136 MODULE_LICENSE("GPL");
1137 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1138 MODULE_AUTHOR("Mike Lavender");
1139 MODULE_DESCRIPTION("framework for SPI NOR");