]>
git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/mtd/spi-nor/spi-nor.c
2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
20 #include <linux/mtd/cfi.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
26 /* Define max times to check status register before we give up. */
27 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
29 #define SPI_NOR_MAX_ID_LEN 6
35 * This array stores the ID bytes.
36 * The first three bytes are the JEDIC ID.
37 * JEDEC ID zero means "no ID" (mostly older chips).
39 u8 id
[SPI_NOR_MAX_ID_LEN
];
42 /* The size listed here is what works with SPINOR_OP_SE, which isn't
43 * necessarily called a "sector" by the vendor.
52 #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
53 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
54 #define SST_WRITE 0x04 /* use SST byte programming */
55 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
56 #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
57 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
58 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
59 #define USE_FSR 0x80 /* use flag status register */
62 #define JEDEC_MFR(info) ((info)->id[0])
64 static const struct flash_info
*spi_nor_match_id(const char *name
);
67 * Read the status register, returning its value in the location
68 * Return the status register value.
69 * Returns negative if error occurred.
71 static int read_sr(struct spi_nor
*nor
)
76 ret
= nor
->read_reg(nor
, SPINOR_OP_RDSR
, &val
, 1);
78 pr_err("error %d reading SR\n", (int) ret
);
86 * Read the flag status register, returning its value in the location
87 * Return the status register value.
88 * Returns negative if error occurred.
90 static int read_fsr(struct spi_nor
*nor
)
95 ret
= nor
->read_reg(nor
, SPINOR_OP_RDFSR
, &val
, 1);
97 pr_err("error %d reading FSR\n", ret
);
105 * Read configuration register, returning its value in the
106 * location. Return the configuration register value.
107 * Returns negative if error occured.
109 static int read_cr(struct spi_nor
*nor
)
114 ret
= nor
->read_reg(nor
, SPINOR_OP_RDCR
, &val
, 1);
116 dev_err(nor
->dev
, "error %d reading CR\n", ret
);
124 * Dummy Cycle calculation for different type of read.
125 * It can be used to support more commands with
126 * different dummy cycle requirements.
128 static inline int spi_nor_read_dummy_cycles(struct spi_nor
*nor
)
130 switch (nor
->flash_read
) {
142 * Write status register 1 byte
143 * Returns negative if error occurred.
145 static inline int write_sr(struct spi_nor
*nor
, u8 val
)
147 nor
->cmd_buf
[0] = val
;
148 return nor
->write_reg(nor
, SPINOR_OP_WRSR
, nor
->cmd_buf
, 1, 0);
152 * Set write enable latch with Write Enable command.
153 * Returns negative if error occurred.
155 static inline int write_enable(struct spi_nor
*nor
)
157 return nor
->write_reg(nor
, SPINOR_OP_WREN
, NULL
, 0, 0);
161 * Send write disble instruction to the chip.
163 static inline int write_disable(struct spi_nor
*nor
)
165 return nor
->write_reg(nor
, SPINOR_OP_WRDI
, NULL
, 0, 0);
168 static inline struct spi_nor
*mtd_to_spi_nor(struct mtd_info
*mtd
)
173 /* Enable/disable 4-byte addressing mode. */
174 static inline int set_4byte(struct spi_nor
*nor
, const struct flash_info
*info
,
178 bool need_wren
= false;
181 switch (JEDEC_MFR(info
)) {
182 case CFI_MFR_ST
: /* Micron, actually */
183 /* Some Micron need WREN command; all will accept it */
185 case CFI_MFR_MACRONIX
:
186 case 0xEF /* winbond */:
190 cmd
= enable
? SPINOR_OP_EN4B
: SPINOR_OP_EX4B
;
191 status
= nor
->write_reg(nor
, cmd
, NULL
, 0, 0);
198 nor
->cmd_buf
[0] = enable
<< 7;
199 return nor
->write_reg(nor
, SPINOR_OP_BRWR
, nor
->cmd_buf
, 1, 0);
202 static inline int spi_nor_sr_ready(struct spi_nor
*nor
)
204 int sr
= read_sr(nor
);
208 return !(sr
& SR_WIP
);
211 static inline int spi_nor_fsr_ready(struct spi_nor
*nor
)
213 int fsr
= read_fsr(nor
);
217 return fsr
& FSR_READY
;
220 static int spi_nor_ready(struct spi_nor
*nor
)
223 sr
= spi_nor_sr_ready(nor
);
226 fsr
= nor
->flags
& SNOR_F_USE_FSR
? spi_nor_fsr_ready(nor
) : 1;
233 * Service routine to read status register until ready, or timeout occurs.
234 * Returns non-zero if error.
236 static int spi_nor_wait_till_ready(struct spi_nor
*nor
)
238 unsigned long deadline
;
239 int timeout
= 0, ret
;
241 deadline
= jiffies
+ MAX_READY_WAIT_JIFFIES
;
244 if (time_after_eq(jiffies
, deadline
))
247 ret
= spi_nor_ready(nor
);
256 dev_err(nor
->dev
, "flash operation timed out\n");
262 * Erase the whole flash memory
264 * Returns 0 if successful, non-zero otherwise.
266 static int erase_chip(struct spi_nor
*nor
)
268 dev_dbg(nor
->dev
, " %lldKiB\n", (long long)(nor
->mtd
.size
>> 10));
270 return nor
->write_reg(nor
, SPINOR_OP_CHIP_ERASE
, NULL
, 0, 0);
273 static int spi_nor_lock_and_prep(struct spi_nor
*nor
, enum spi_nor_ops ops
)
277 mutex_lock(&nor
->lock
);
280 ret
= nor
->prepare(nor
, ops
);
282 dev_err(nor
->dev
, "failed in the preparation.\n");
283 mutex_unlock(&nor
->lock
);
290 static void spi_nor_unlock_and_unprep(struct spi_nor
*nor
, enum spi_nor_ops ops
)
293 nor
->unprepare(nor
, ops
);
294 mutex_unlock(&nor
->lock
);
298 * Erase an address range on the nor chip. The address range may extend
299 * one or more erase sectors. Return an error is there is a problem erasing.
301 static int spi_nor_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
303 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
308 dev_dbg(nor
->dev
, "at 0x%llx, len %lld\n", (long long)instr
->addr
,
309 (long long)instr
->len
);
311 div_u64_rem(instr
->len
, mtd
->erasesize
, &rem
);
318 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_ERASE
);
322 /* whole-chip erase? */
323 if (len
== mtd
->size
) {
326 if (erase_chip(nor
)) {
331 ret
= spi_nor_wait_till_ready(nor
);
335 /* REVISIT in some cases we could speed up erasing large regions
336 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
337 * to use "small sector erase", but that's not always optimal.
340 /* "sector"-at-a-time erase */
345 if (nor
->erase(nor
, addr
)) {
350 addr
+= mtd
->erasesize
;
351 len
-= mtd
->erasesize
;
353 ret
= spi_nor_wait_till_ready(nor
);
361 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_ERASE
);
363 instr
->state
= MTD_ERASE_DONE
;
364 mtd_erase_callback(instr
);
369 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_ERASE
);
370 instr
->state
= MTD_ERASE_FAILED
;
374 static int stm_lock(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
)
376 struct mtd_info
*mtd
= &nor
->mtd
;
377 uint32_t offset
= ofs
;
378 uint8_t status_old
, status_new
;
381 status_old
= read_sr(nor
);
383 if (offset
< mtd
->size
- (mtd
->size
/ 2))
384 status_new
= status_old
| SR_BP2
| SR_BP1
| SR_BP0
;
385 else if (offset
< mtd
->size
- (mtd
->size
/ 4))
386 status_new
= (status_old
& ~SR_BP0
) | SR_BP2
| SR_BP1
;
387 else if (offset
< mtd
->size
- (mtd
->size
/ 8))
388 status_new
= (status_old
& ~SR_BP1
) | SR_BP2
| SR_BP0
;
389 else if (offset
< mtd
->size
- (mtd
->size
/ 16))
390 status_new
= (status_old
& ~(SR_BP0
| SR_BP1
)) | SR_BP2
;
391 else if (offset
< mtd
->size
- (mtd
->size
/ 32))
392 status_new
= (status_old
& ~SR_BP2
) | SR_BP1
| SR_BP0
;
393 else if (offset
< mtd
->size
- (mtd
->size
/ 64))
394 status_new
= (status_old
& ~(SR_BP2
| SR_BP0
)) | SR_BP1
;
396 status_new
= (status_old
& ~(SR_BP2
| SR_BP1
)) | SR_BP0
;
398 /* Only modify protection if it will not unlock other areas */
399 if ((status_new
& (SR_BP2
| SR_BP1
| SR_BP0
)) >
400 (status_old
& (SR_BP2
| SR_BP1
| SR_BP0
))) {
402 ret
= write_sr(nor
, status_new
);
408 static int stm_unlock(struct spi_nor
*nor
, loff_t ofs
, uint64_t len
)
410 struct mtd_info
*mtd
= &nor
->mtd
;
411 uint32_t offset
= ofs
;
412 uint8_t status_old
, status_new
;
415 status_old
= read_sr(nor
);
417 if (offset
+len
> mtd
->size
- (mtd
->size
/ 64))
418 status_new
= status_old
& ~(SR_BP2
| SR_BP1
| SR_BP0
);
419 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 32))
420 status_new
= (status_old
& ~(SR_BP2
| SR_BP1
)) | SR_BP0
;
421 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 16))
422 status_new
= (status_old
& ~(SR_BP2
| SR_BP0
)) | SR_BP1
;
423 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 8))
424 status_new
= (status_old
& ~SR_BP2
) | SR_BP1
| SR_BP0
;
425 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 4))
426 status_new
= (status_old
& ~(SR_BP0
| SR_BP1
)) | SR_BP2
;
427 else if (offset
+len
> mtd
->size
- (mtd
->size
/ 2))
428 status_new
= (status_old
& ~SR_BP1
) | SR_BP2
| SR_BP0
;
430 status_new
= (status_old
& ~SR_BP0
) | SR_BP2
| SR_BP1
;
432 /* Only modify protection if it will not lock other areas */
433 if ((status_new
& (SR_BP2
| SR_BP1
| SR_BP0
)) <
434 (status_old
& (SR_BP2
| SR_BP1
| SR_BP0
))) {
436 ret
= write_sr(nor
, status_new
);
442 static int spi_nor_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
444 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
447 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_LOCK
);
451 ret
= nor
->flash_lock(nor
, ofs
, len
);
453 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_UNLOCK
);
457 static int spi_nor_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
459 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
462 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_UNLOCK
);
466 ret
= nor
->flash_unlock(nor
, ofs
, len
);
468 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_LOCK
);
472 /* Used when the "_ext_id" is two bytes at most */
473 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
475 ((_jedec_id) >> 16) & 0xff, \
476 ((_jedec_id) >> 8) & 0xff, \
477 (_jedec_id) & 0xff, \
478 ((_ext_id) >> 8) & 0xff, \
481 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
482 .sector_size = (_sector_size), \
483 .n_sectors = (_n_sectors), \
487 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
489 ((_jedec_id) >> 16) & 0xff, \
490 ((_jedec_id) >> 8) & 0xff, \
491 (_jedec_id) & 0xff, \
492 ((_ext_id) >> 16) & 0xff, \
493 ((_ext_id) >> 8) & 0xff, \
497 .sector_size = (_sector_size), \
498 .n_sectors = (_n_sectors), \
502 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
503 .sector_size = (_sector_size), \
504 .n_sectors = (_n_sectors), \
505 .page_size = (_page_size), \
506 .addr_width = (_addr_width), \
509 /* NOTE: double check command sets and memory organization when you add
510 * more nor chips. This current list focusses on newer chips, which
511 * have been converging on command sets which including JEDEC ID.
513 * All newly added entries should describe *hardware* and should use SECT_4K
514 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
515 * scenarios excluding small sectors there is config option that can be
516 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
517 * For historical (and compatibility) reasons (before we got above config) some
518 * old entries may be missing 4K flag.
520 static const struct flash_info spi_nor_ids
[] = {
521 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
522 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K
) },
523 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K
) },
525 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K
) },
526 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K
) },
527 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K
) },
529 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K
) },
530 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K
) },
531 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K
) },
532 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K
) },
534 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K
) },
537 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K
) },
538 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
539 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
540 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
541 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K
) },
542 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
543 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
544 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K
) },
547 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K
) },
550 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
551 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
554 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE
) },
557 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K
) },
558 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K
) },
559 { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K
) },
561 /* Intel/Numonyx -- xxxs33b */
562 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
563 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
564 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
567 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K
) },
570 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K
) },
571 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K
) },
572 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K
) },
573 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
574 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K
) },
575 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
576 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K
) },
577 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
578 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K
) },
579 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
580 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
581 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
582 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
583 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ
) },
584 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ
) },
587 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ
) },
588 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K
| SPI_NOR_QUAD_READ
) },
589 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K
| SPI_NOR_QUAD_READ
) },
590 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ
) },
591 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ
) },
592 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K
| SPI_NOR_QUAD_READ
) },
593 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K
| USE_FSR
| SPI_NOR_QUAD_READ
) },
594 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K
| USE_FSR
| SPI_NOR_QUAD_READ
) },
595 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K
| USE_FSR
| SPI_NOR_QUAD_READ
) },
598 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC
) },
599 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC
) },
600 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K
) },
602 /* Spansion -- single (large) sector size only, at least
603 * for the chips listed here (without boot sectors).
605 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
606 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
607 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
608 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
609 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
610 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
611 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
612 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
613 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K
| SPI_NOR_QUAD_READ
) },
614 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
615 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ
| SPI_NOR_QUAD_READ
) },
616 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
617 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
618 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
619 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
620 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
621 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K
) },
622 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K
) },
623 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
) },
624 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K
) },
625 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K
) },
626 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K
) },
628 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
629 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K
| SST_WRITE
) },
630 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K
| SST_WRITE
) },
631 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K
| SST_WRITE
) },
632 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K
| SST_WRITE
) },
633 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K
) },
634 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K
| SST_WRITE
) },
635 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K
| SST_WRITE
) },
636 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K
| SST_WRITE
) },
637 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K
) },
638 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K
| SST_WRITE
) },
639 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K
| SST_WRITE
) },
641 /* ST Microelectronics -- newer production may have feature updates */
642 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
643 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
644 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
645 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
646 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
647 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
648 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
649 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
650 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
652 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
653 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
654 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
655 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
656 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
657 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
658 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
659 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
660 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
662 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
663 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
664 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
666 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
667 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
668 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K
) },
670 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K
) },
671 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K
) },
672 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K
) },
673 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K
) },
674 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
675 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
677 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
678 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K
) },
679 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K
) },
680 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K
) },
681 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K
) },
682 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K
) },
683 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K
) },
684 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K
) },
685 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K
) },
686 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K
) },
687 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K
) },
688 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
) },
689 { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K
) },
690 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K
) },
691 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K
) },
692 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K
) },
693 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K
) },
695 /* Catalyst / On Semiconductor -- non-JEDEC */
696 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
697 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
698 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
699 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
700 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE
| SPI_NOR_NO_FR
) },
704 static const struct flash_info
*spi_nor_read_id(struct spi_nor
*nor
)
707 u8 id
[SPI_NOR_MAX_ID_LEN
];
708 const struct flash_info
*info
;
710 tmp
= nor
->read_reg(nor
, SPINOR_OP_RDID
, id
, SPI_NOR_MAX_ID_LEN
);
712 dev_dbg(nor
->dev
, " error %d reading JEDEC ID\n", tmp
);
716 for (tmp
= 0; tmp
< ARRAY_SIZE(spi_nor_ids
) - 1; tmp
++) {
717 info
= &spi_nor_ids
[tmp
];
719 if (!memcmp(info
->id
, id
, info
->id_len
))
720 return &spi_nor_ids
[tmp
];
723 dev_err(nor
->dev
, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
724 id
[0], id
[1], id
[2]);
725 return ERR_PTR(-ENODEV
);
728 static int spi_nor_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
729 size_t *retlen
, u_char
*buf
)
731 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
734 dev_dbg(nor
->dev
, "from 0x%08x, len %zd\n", (u32
)from
, len
);
736 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_READ
);
740 ret
= nor
->read(nor
, from
, len
, retlen
, buf
);
742 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_READ
);
746 static int sst_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
747 size_t *retlen
, const u_char
*buf
)
749 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
753 dev_dbg(nor
->dev
, "to 0x%08x, len %zd\n", (u32
)to
, len
);
755 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_WRITE
);
761 nor
->sst_write_second
= false;
764 /* Start write from odd address. */
766 nor
->program_opcode
= SPINOR_OP_BP
;
768 /* write one byte. */
769 nor
->write(nor
, to
, 1, retlen
, buf
);
770 ret
= spi_nor_wait_till_ready(nor
);
776 /* Write out most of the data here. */
777 for (; actual
< len
- 1; actual
+= 2) {
778 nor
->program_opcode
= SPINOR_OP_AAI_WP
;
780 /* write two bytes. */
781 nor
->write(nor
, to
, 2, retlen
, buf
+ actual
);
782 ret
= spi_nor_wait_till_ready(nor
);
786 nor
->sst_write_second
= true;
788 nor
->sst_write_second
= false;
791 ret
= spi_nor_wait_till_ready(nor
);
795 /* Write out trailing byte if it exists. */
799 nor
->program_opcode
= SPINOR_OP_BP
;
800 nor
->write(nor
, to
, 1, retlen
, buf
+ actual
);
802 ret
= spi_nor_wait_till_ready(nor
);
808 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_WRITE
);
813 * Write an address range to the nor chip. Data must be written in
814 * FLASH_PAGESIZE chunks. The address range may be any size provided
815 * it is within the physical boundaries.
817 static int spi_nor_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
818 size_t *retlen
, const u_char
*buf
)
820 struct spi_nor
*nor
= mtd_to_spi_nor(mtd
);
821 u32 page_offset
, page_size
, i
;
824 dev_dbg(nor
->dev
, "to 0x%08x, len %zd\n", (u32
)to
, len
);
826 ret
= spi_nor_lock_and_prep(nor
, SPI_NOR_OPS_WRITE
);
832 page_offset
= to
& (nor
->page_size
- 1);
834 /* do all the bytes fit onto one page? */
835 if (page_offset
+ len
<= nor
->page_size
) {
836 nor
->write(nor
, to
, len
, retlen
, buf
);
838 /* the size of data remaining on the first page */
839 page_size
= nor
->page_size
- page_offset
;
840 nor
->write(nor
, to
, page_size
, retlen
, buf
);
842 /* write everything in nor->page_size chunks */
843 for (i
= page_size
; i
< len
; i
+= page_size
) {
845 if (page_size
> nor
->page_size
)
846 page_size
= nor
->page_size
;
848 ret
= spi_nor_wait_till_ready(nor
);
854 nor
->write(nor
, to
+ i
, page_size
, retlen
, buf
+ i
);
858 ret
= spi_nor_wait_till_ready(nor
);
860 spi_nor_unlock_and_unprep(nor
, SPI_NOR_OPS_WRITE
);
864 static int macronix_quad_enable(struct spi_nor
*nor
)
871 nor
->cmd_buf
[0] = val
| SR_QUAD_EN_MX
;
872 nor
->write_reg(nor
, SPINOR_OP_WRSR
, nor
->cmd_buf
, 1, 0);
874 if (spi_nor_wait_till_ready(nor
))
878 if (!(ret
> 0 && (ret
& SR_QUAD_EN_MX
))) {
879 dev_err(nor
->dev
, "Macronix Quad bit not set\n");
887 * Write status Register and configuration register with 2 bytes
888 * The first byte will be written to the status register, while the
889 * second byte will be written to the configuration register.
890 * Return negative if error occured.
892 static int write_sr_cr(struct spi_nor
*nor
, u16 val
)
894 nor
->cmd_buf
[0] = val
& 0xff;
895 nor
->cmd_buf
[1] = (val
>> 8);
897 return nor
->write_reg(nor
, SPINOR_OP_WRSR
, nor
->cmd_buf
, 2, 0);
900 static int spansion_quad_enable(struct spi_nor
*nor
)
903 int quad_en
= CR_QUAD_EN_SPAN
<< 8;
907 ret
= write_sr_cr(nor
, quad_en
);
910 "error while writing configuration register\n");
914 /* read back and check it */
916 if (!(ret
> 0 && (ret
& CR_QUAD_EN_SPAN
))) {
917 dev_err(nor
->dev
, "Spansion Quad bit not set\n");
924 static int micron_quad_enable(struct spi_nor
*nor
)
929 ret
= nor
->read_reg(nor
, SPINOR_OP_RD_EVCR
, &val
, 1);
931 dev_err(nor
->dev
, "error %d reading EVCR\n", ret
);
937 /* set EVCR, enable quad I/O */
938 nor
->cmd_buf
[0] = val
& ~EVCR_QUAD_EN_MICRON
;
939 ret
= nor
->write_reg(nor
, SPINOR_OP_WD_EVCR
, nor
->cmd_buf
, 1, 0);
941 dev_err(nor
->dev
, "error while writing EVCR register\n");
945 ret
= spi_nor_wait_till_ready(nor
);
949 /* read EVCR and check it */
950 ret
= nor
->read_reg(nor
, SPINOR_OP_RD_EVCR
, &val
, 1);
952 dev_err(nor
->dev
, "error %d reading EVCR\n", ret
);
955 if (val
& EVCR_QUAD_EN_MICRON
) {
956 dev_err(nor
->dev
, "Micron EVCR Quad bit not clear\n");
963 static int set_quad_mode(struct spi_nor
*nor
, const struct flash_info
*info
)
967 switch (JEDEC_MFR(info
)) {
968 case CFI_MFR_MACRONIX
:
969 status
= macronix_quad_enable(nor
);
971 dev_err(nor
->dev
, "Macronix quad-read not enabled\n");
976 status
= micron_quad_enable(nor
);
978 dev_err(nor
->dev
, "Micron quad-read not enabled\n");
983 status
= spansion_quad_enable(nor
);
985 dev_err(nor
->dev
, "Spansion quad-read not enabled\n");
992 static int spi_nor_check(struct spi_nor
*nor
)
994 if (!nor
->dev
|| !nor
->read
|| !nor
->write
||
995 !nor
->read_reg
|| !nor
->write_reg
|| !nor
->erase
) {
996 pr_err("spi-nor: please fill all the necessary fields!\n");
1003 int spi_nor_scan(struct spi_nor
*nor
, const char *name
, enum read_mode mode
)
1005 const struct flash_info
*info
= NULL
;
1006 struct device
*dev
= nor
->dev
;
1007 struct mtd_info
*mtd
= &nor
->mtd
;
1008 struct device_node
*np
= nor
->flash_node
;
1012 ret
= spi_nor_check(nor
);
1017 info
= spi_nor_match_id(name
);
1018 /* Try to auto-detect if chip name wasn't specified or not found */
1020 info
= spi_nor_read_id(nor
);
1021 if (IS_ERR_OR_NULL(info
))
1025 * If caller has specified name of flash model that can normally be
1026 * detected using JEDEC, let's verify it.
1028 if (name
&& info
->id_len
) {
1029 const struct flash_info
*jinfo
;
1031 jinfo
= spi_nor_read_id(nor
);
1032 if (IS_ERR(jinfo
)) {
1033 return PTR_ERR(jinfo
);
1034 } else if (jinfo
!= info
) {
1036 * JEDEC knows better, so overwrite platform ID. We
1037 * can't trust partitions any longer, but we'll let
1038 * mtd apply them anyway, since some partitions may be
1039 * marked read-only, and we don't want to lose that
1040 * information, even if it's not 100% accurate.
1042 dev_warn(dev
, "found %s, expected %s\n",
1043 jinfo
->name
, info
->name
);
1048 mutex_init(&nor
->lock
);
1051 * Atmel, SST and Intel/Numonyx serial nor tend to power
1052 * up with the software protection bits set
1055 if (JEDEC_MFR(info
) == CFI_MFR_ATMEL
||
1056 JEDEC_MFR(info
) == CFI_MFR_INTEL
||
1057 JEDEC_MFR(info
) == CFI_MFR_SST
) {
1063 mtd
->name
= dev_name(dev
);
1065 mtd
->type
= MTD_NORFLASH
;
1067 mtd
->flags
= MTD_CAP_NORFLASH
;
1068 mtd
->size
= info
->sector_size
* info
->n_sectors
;
1069 mtd
->_erase
= spi_nor_erase
;
1070 mtd
->_read
= spi_nor_read
;
1072 /* nor protection support for STmicro chips */
1073 if (JEDEC_MFR(info
) == CFI_MFR_ST
) {
1074 nor
->flash_lock
= stm_lock
;
1075 nor
->flash_unlock
= stm_unlock
;
1078 if (nor
->flash_lock
&& nor
->flash_unlock
) {
1079 mtd
->_lock
= spi_nor_lock
;
1080 mtd
->_unlock
= spi_nor_unlock
;
1083 /* sst nor chips use AAI word program */
1084 if (info
->flags
& SST_WRITE
)
1085 mtd
->_write
= sst_write
;
1087 mtd
->_write
= spi_nor_write
;
1089 if (info
->flags
& USE_FSR
)
1090 nor
->flags
|= SNOR_F_USE_FSR
;
1092 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1093 /* prefer "small sector" erase if possible */
1094 if (info
->flags
& SECT_4K
) {
1095 nor
->erase_opcode
= SPINOR_OP_BE_4K
;
1096 mtd
->erasesize
= 4096;
1097 } else if (info
->flags
& SECT_4K_PMC
) {
1098 nor
->erase_opcode
= SPINOR_OP_BE_4K_PMC
;
1099 mtd
->erasesize
= 4096;
1103 nor
->erase_opcode
= SPINOR_OP_SE
;
1104 mtd
->erasesize
= info
->sector_size
;
1107 if (info
->flags
& SPI_NOR_NO_ERASE
)
1108 mtd
->flags
|= MTD_NO_ERASE
;
1110 mtd
->dev
.parent
= dev
;
1111 nor
->page_size
= info
->page_size
;
1112 mtd
->writebufsize
= nor
->page_size
;
1115 /* If we were instantiated by DT, use it */
1116 if (of_property_read_bool(np
, "m25p,fast-read"))
1117 nor
->flash_read
= SPI_NOR_FAST
;
1119 nor
->flash_read
= SPI_NOR_NORMAL
;
1121 /* If we weren't instantiated by DT, default to fast-read */
1122 nor
->flash_read
= SPI_NOR_FAST
;
1125 /* Some devices cannot do fast-read, no matter what DT tells us */
1126 if (info
->flags
& SPI_NOR_NO_FR
)
1127 nor
->flash_read
= SPI_NOR_NORMAL
;
1129 /* Quad/Dual-read mode takes precedence over fast/normal */
1130 if (mode
== SPI_NOR_QUAD
&& info
->flags
& SPI_NOR_QUAD_READ
) {
1131 ret
= set_quad_mode(nor
, info
);
1133 dev_err(dev
, "quad mode not supported\n");
1136 nor
->flash_read
= SPI_NOR_QUAD
;
1137 } else if (mode
== SPI_NOR_DUAL
&& info
->flags
& SPI_NOR_DUAL_READ
) {
1138 nor
->flash_read
= SPI_NOR_DUAL
;
1141 /* Default commands */
1142 switch (nor
->flash_read
) {
1144 nor
->read_opcode
= SPINOR_OP_READ_1_1_4
;
1147 nor
->read_opcode
= SPINOR_OP_READ_1_1_2
;
1150 nor
->read_opcode
= SPINOR_OP_READ_FAST
;
1152 case SPI_NOR_NORMAL
:
1153 nor
->read_opcode
= SPINOR_OP_READ
;
1156 dev_err(dev
, "No Read opcode defined\n");
1160 nor
->program_opcode
= SPINOR_OP_PP
;
1162 if (info
->addr_width
)
1163 nor
->addr_width
= info
->addr_width
;
1164 else if (mtd
->size
> 0x1000000) {
1165 /* enable 4-byte addressing if the device exceeds 16MiB */
1166 nor
->addr_width
= 4;
1167 if (JEDEC_MFR(info
) == CFI_MFR_AMD
) {
1168 /* Dedicated 4-byte command set */
1169 switch (nor
->flash_read
) {
1171 nor
->read_opcode
= SPINOR_OP_READ4_1_1_4
;
1174 nor
->read_opcode
= SPINOR_OP_READ4_1_1_2
;
1177 nor
->read_opcode
= SPINOR_OP_READ4_FAST
;
1179 case SPI_NOR_NORMAL
:
1180 nor
->read_opcode
= SPINOR_OP_READ4
;
1183 nor
->program_opcode
= SPINOR_OP_PP_4B
;
1184 /* No small sector erase for 4-byte command set */
1185 nor
->erase_opcode
= SPINOR_OP_SE_4B
;
1186 mtd
->erasesize
= info
->sector_size
;
1188 set_4byte(nor
, info
, 1);
1190 nor
->addr_width
= 3;
1193 nor
->read_dummy
= spi_nor_read_dummy_cycles(nor
);
1195 dev_info(dev
, "%s (%lld Kbytes)\n", info
->name
,
1196 (long long)mtd
->size
>> 10);
1199 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1200 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1201 mtd
->name
, (long long)mtd
->size
, (long long)(mtd
->size
>> 20),
1202 mtd
->erasesize
, mtd
->erasesize
/ 1024, mtd
->numeraseregions
);
1204 if (mtd
->numeraseregions
)
1205 for (i
= 0; i
< mtd
->numeraseregions
; i
++)
1207 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1208 ".erasesize = 0x%.8x (%uKiB), "
1209 ".numblocks = %d }\n",
1210 i
, (long long)mtd
->eraseregions
[i
].offset
,
1211 mtd
->eraseregions
[i
].erasesize
,
1212 mtd
->eraseregions
[i
].erasesize
/ 1024,
1213 mtd
->eraseregions
[i
].numblocks
);
1216 EXPORT_SYMBOL_GPL(spi_nor_scan
);
1218 static const struct flash_info
*spi_nor_match_id(const char *name
)
1220 const struct flash_info
*id
= spi_nor_ids
;
1223 if (!strcmp(name
, id
->name
))
1230 MODULE_LICENSE("GPL");
1231 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1232 MODULE_AUTHOR("Mike Lavender");
1233 MODULE_DESCRIPTION("framework for SPI NOR");