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1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2 /*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Linux Kernel Additions:
21
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
28
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
39 by Bogdan Costescu.
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
42 insertion oops)
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
51
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
56 as in the hardware.
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
58
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
69
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
80 Donald Becker)
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
83
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
92 have one.
93 - Added 802.3x MAC-layer flow control support
94
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
104
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
115 things happen.
116
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
121
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
124
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
132
133 LK1.1.13 27 Jan 2001
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
142
143 LK1.1.14 15 Feb 2001
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
148
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
155
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
164 NICs).
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
167 clash.
168
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
171 And it has NWAY.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
175 global_full_duplex.
176
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
180
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
183
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
186 */
187
188 /*
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
191 *
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
195 */
196
197
198 #define DRV_NAME "3c59x"
199
200
201
202 /* A few values that may be tweaked. */
203 /* Keep the ring sizes a power of two for efficiency. */
204 #define TX_RING_SIZE 16
205 #define RX_RING_SIZE 32
206 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
207
208 /* "Knobs" that adjust features and parameters. */
209 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
210 Setting to > 1512 effectively disables this feature. */
211 #ifndef __arm__
212 static int rx_copybreak = 200;
213 #else
214 /* ARM systems perform better by disregarding the bus-master
215 transfer capability of these cards. -- rmk */
216 static int rx_copybreak = 1513;
217 #endif
218 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
219 static const int mtu = 1500;
220 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
221 static int max_interrupt_work = 32;
222 /* Tx timeout interval (millisecs) */
223 static int watchdog = 5000;
224
225 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
226 * of possible Tx stalls if the system is blocking interrupts
227 * somewhere else. Undefine this to disable.
228 */
229 #define tx_interrupt_mitigation 1
230
231 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
232 #define vortex_debug debug
233 #ifdef VORTEX_DEBUG
234 static int vortex_debug = VORTEX_DEBUG;
235 #else
236 static int vortex_debug = 1;
237 #endif
238
239 #include <linux/module.h>
240 #include <linux/kernel.h>
241 #include <linux/string.h>
242 #include <linux/timer.h>
243 #include <linux/errno.h>
244 #include <linux/in.h>
245 #include <linux/ioport.h>
246 #include <linux/slab.h>
247 #include <linux/interrupt.h>
248 #include <linux/pci.h>
249 #include <linux/mii.h>
250 #include <linux/init.h>
251 #include <linux/netdevice.h>
252 #include <linux/etherdevice.h>
253 #include <linux/skbuff.h>
254 #include <linux/ethtool.h>
255 #include <linux/highmem.h>
256 #include <linux/eisa.h>
257 #include <linux/bitops.h>
258 #include <linux/jiffies.h>
259 #include <asm/irq.h> /* For NR_IRQS only. */
260 #include <asm/io.h>
261 #include <asm/uaccess.h>
262
263 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
264 This is only in the support-all-kernels source code. */
265
266 #define RUN_AT(x) (jiffies + (x))
267
268 #include <linux/delay.h>
269
270
271 static char version[] __devinitdata =
272 DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
273
274 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
275 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
276 MODULE_LICENSE("GPL");
277
278
279 /* Operational parameter that usually are not changed. */
280
281 /* The Vortex size is twice that of the original EtherLinkIII series: the
282 runtime register window, window 1, is now always mapped in.
283 The Boomerang size is twice as large as the Vortex -- it has additional
284 bus master control registers. */
285 #define VORTEX_TOTAL_SIZE 0x20
286 #define BOOMERANG_TOTAL_SIZE 0x40
287
288 /* Set iff a MII transceiver on any interface requires mdio preamble.
289 This only set with the original DP83840 on older 3c905 boards, so the extra
290 code size of a per-interface flag is not worthwhile. */
291 static char mii_preamble_required;
292
293 #define PFX DRV_NAME ": "
294
295
296
297 /*
298 Theory of Operation
299
300 I. Board Compatibility
301
302 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
303 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
304 versions of the FastEtherLink cards. The supported product IDs are
305 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
306
307 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
308 with the kernel source or available from
309 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
310
311 II. Board-specific settings
312
313 PCI bus devices are configured by the system at boot time, so no jumpers
314 need to be set on the board. The system BIOS should be set to assign the
315 PCI INTA signal to an otherwise unused system IRQ line.
316
317 The EEPROM settings for media type and forced-full-duplex are observed.
318 The EEPROM media type should be left at the default "autoselect" unless using
319 10base2 or AUI connections which cannot be reliably detected.
320
321 III. Driver operation
322
323 The 3c59x series use an interface that's very similar to the previous 3c5x9
324 series. The primary interface is two programmed-I/O FIFOs, with an
325 alternate single-contiguous-region bus-master transfer (see next).
326
327 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
328 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
329 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
330 programmed-I/O interface that has been removed in 'B' and subsequent board
331 revisions.
332
333 One extension that is advertised in a very large font is that the adapters
334 are capable of being bus masters. On the Vortex chip this capability was
335 only for a single contiguous region making it far less useful than the full
336 bus master capability. There is a significant performance impact of taking
337 an extra interrupt or polling for the completion of each transfer, as well
338 as difficulty sharing the single transfer engine between the transmit and
339 receive threads. Using DMA transfers is a win only with large blocks or
340 with the flawed versions of the Intel Orion motherboard PCI controller.
341
342 The Boomerang chip's full-bus-master interface is useful, and has the
343 currently-unused advantages over other similar chips that queued transmit
344 packets may be reordered and receive buffer groups are associated with a
345 single frame.
346
347 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
348 Rather than a fixed intermediate receive buffer, this scheme allocates
349 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
350 the copying breakpoint: it is chosen to trade-off the memory wasted by
351 passing the full-sized skbuff to the queue layer for all frames vs. the
352 copying cost of copying a frame to a correctly-sized skbuff.
353
354 IIIC. Synchronization
355 The driver runs as two independent, single-threaded flows of control. One
356 is the send-packet routine, which enforces single-threaded use by the
357 dev->tbusy flag. The other thread is the interrupt handler, which is single
358 threaded by the hardware and other software.
359
360 IV. Notes
361
362 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
363 3c590, 3c595, and 3c900 boards.
364 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
365 the EISA version is called "Demon". According to Terry these names come
366 from rides at the local amusement park.
367
368 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
369 This driver only supports ethernet packets because of the skbuff allocation
370 limit of 4K.
371 */
372
373 /* This table drives the PCI probe routines. It's mostly boilerplate in all
374 of the drivers, and will likely be provided by some future kernel.
375 */
376 enum pci_flags_bit {
377 PCI_USES_MASTER=4,
378 };
379
380 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
381 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
382 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
383 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
384 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
385 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
386
387 enum vortex_chips {
388 CH_3C590 = 0,
389 CH_3C592,
390 CH_3C597,
391 CH_3C595_1,
392 CH_3C595_2,
393
394 CH_3C595_3,
395 CH_3C900_1,
396 CH_3C900_2,
397 CH_3C900_3,
398 CH_3C900_4,
399
400 CH_3C900_5,
401 CH_3C900B_FL,
402 CH_3C905_1,
403 CH_3C905_2,
404 CH_3C905B_1,
405
406 CH_3C905B_2,
407 CH_3C905B_FX,
408 CH_3C905C,
409 CH_3C9202,
410 CH_3C980,
411 CH_3C9805,
412
413 CH_3CSOHO100_TX,
414 CH_3C555,
415 CH_3C556,
416 CH_3C556B,
417 CH_3C575,
418
419 CH_3C575_1,
420 CH_3CCFE575,
421 CH_3CCFE575CT,
422 CH_3CCFE656,
423 CH_3CCFEM656,
424
425 CH_3CCFEM656_1,
426 CH_3C450,
427 CH_3C920,
428 CH_3C982A,
429 CH_3C982B,
430
431 CH_905BT4,
432 CH_920B_EMB_WNM,
433 };
434
435
436 /* note: this array directly indexed by above enums, and MUST
437 * be kept in sync with both the enums above, and the PCI device
438 * table below
439 */
440 static struct vortex_chip_info {
441 const char *name;
442 int flags;
443 int drv_flags;
444 int io_size;
445 } vortex_info_tbl[] __devinitdata = {
446 {"3c590 Vortex 10Mbps",
447 PCI_USES_MASTER, IS_VORTEX, 32, },
448 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
449 PCI_USES_MASTER, IS_VORTEX, 32, },
450 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
451 PCI_USES_MASTER, IS_VORTEX, 32, },
452 {"3c595 Vortex 100baseTx",
453 PCI_USES_MASTER, IS_VORTEX, 32, },
454 {"3c595 Vortex 100baseT4",
455 PCI_USES_MASTER, IS_VORTEX, 32, },
456
457 {"3c595 Vortex 100base-MII",
458 PCI_USES_MASTER, IS_VORTEX, 32, },
459 {"3c900 Boomerang 10baseT",
460 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
461 {"3c900 Boomerang 10Mbps Combo",
462 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
463 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
464 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
465 {"3c900 Cyclone 10Mbps Combo",
466 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
467
468 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
469 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
470 {"3c900B-FL Cyclone 10base-FL",
471 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
472 {"3c905 Boomerang 100baseTx",
473 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
474 {"3c905 Boomerang 100baseT4",
475 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
476 {"3c905B Cyclone 100baseTx",
477 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
478
479 {"3c905B Cyclone 10/100/BNC",
480 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
481 {"3c905B-FX Cyclone 100baseFx",
482 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
483 {"3c905C Tornado",
484 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
485 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
486 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
487 {"3c980 Cyclone",
488 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
489
490 {"3c980C Python-T",
491 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
492 {"3cSOHO100-TX Hurricane",
493 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
494 {"3c555 Laptop Hurricane",
495 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
496 {"3c556 Laptop Tornado",
497 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
498 HAS_HWCKSM, 128, },
499 {"3c556B Laptop Hurricane",
500 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
501 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
502
503 {"3c575 [Megahertz] 10/100 LAN CardBus",
504 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
505 {"3c575 Boomerang CardBus",
506 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
507 {"3CCFE575BT Cyclone CardBus",
508 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
509 INVERT_LED_PWR|HAS_HWCKSM, 128, },
510 {"3CCFE575CT Tornado CardBus",
511 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
512 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
513 {"3CCFE656 Cyclone CardBus",
514 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
515 INVERT_LED_PWR|HAS_HWCKSM, 128, },
516
517 {"3CCFEM656B Cyclone+Winmodem CardBus",
518 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
519 INVERT_LED_PWR|HAS_HWCKSM, 128, },
520 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
521 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
522 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
523 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
524 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
525 {"3c920 Tornado",
526 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
527 {"3c982 Hydra Dual Port A",
528 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
529
530 {"3c982 Hydra Dual Port B",
531 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
532 {"3c905B-T4",
533 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
534 {"3c920B-EMB-WNM Tornado",
535 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
536
537 {NULL,}, /* NULL terminated list. */
538 };
539
540
541 static struct pci_device_id vortex_pci_tbl[] = {
542 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
543 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
544 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
545 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
546 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
547
548 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
549 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
550 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
551 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
552 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
553
554 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
555 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
556 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
557 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
558 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
559
560 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
561 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
562 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
563 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
564 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
565 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
566
567 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
568 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
569 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
570 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
571 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
572
573 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
574 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
575 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
576 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
577 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
578
579 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
580 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
581 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
582 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
583 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
584
585 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
586 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
587
588 {0,} /* 0 terminated list. */
589 };
590 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
591
592
593 /* Operational definitions.
594 These are not used by other compilation units and thus are not
595 exported in a ".h" file.
596
597 First the windows. There are eight register windows, with the command
598 and status registers available in each.
599 */
600 #define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
601 #define EL3_CMD 0x0e
602 #define EL3_STATUS 0x0e
603
604 /* The top five bits written to EL3_CMD are a command, the lower
605 11 bits are the parameter, if applicable.
606 Note that 11 parameters bits was fine for ethernet, but the new chip
607 can handle FDDI length frames (~4500 octets) and now parameters count
608 32-bit 'Dwords' rather than octets. */
609
610 enum vortex_cmd {
611 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
612 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
613 UpStall = 6<<11, UpUnstall = (6<<11)+1,
614 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
615 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
616 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
617 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
618 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
619 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
620 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
621
622 /* The SetRxFilter command accepts the following classes: */
623 enum RxFilter {
624 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
625
626 /* Bits in the general status register. */
627 enum vortex_status {
628 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
629 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
630 IntReq = 0x0040, StatsFull = 0x0080,
631 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
632 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
633 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
634 };
635
636 /* Register window 1 offsets, the window used in normal operation.
637 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
638 enum Window1 {
639 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
640 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
641 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
642 };
643 enum Window0 {
644 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
645 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
646 IntrStatus=0x0E, /* Valid in all windows. */
647 };
648 enum Win0_EEPROM_bits {
649 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
650 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
651 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
652 };
653 /* EEPROM locations. */
654 enum eeprom_offset {
655 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
656 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
657 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
658 DriverTune=13, Checksum=15};
659
660 enum Window2 { /* Window 2. */
661 Wn2_ResetOptions=12,
662 };
663 enum Window3 { /* Window 3: MAC/config bits. */
664 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
665 };
666
667 #define BFEXT(value, offset, bitcount) \
668 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
669
670 #define BFINS(lhs, rhs, offset, bitcount) \
671 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
672 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
673
674 #define RAM_SIZE(v) BFEXT(v, 0, 3)
675 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
676 #define RAM_SPEED(v) BFEXT(v, 4, 2)
677 #define ROM_SIZE(v) BFEXT(v, 6, 2)
678 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
679 #define XCVR(v) BFEXT(v, 20, 4)
680 #define AUTOSELECT(v) BFEXT(v, 24, 1)
681
682 enum Window4 { /* Window 4: Xcvr/media bits. */
683 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
684 };
685 enum Win4_Media_bits {
686 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
687 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
688 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
689 Media_LnkBeat = 0x0800,
690 };
691 enum Window7 { /* Window 7: Bus Master control. */
692 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
693 Wn7_MasterStatus = 12,
694 };
695 /* Boomerang bus master control registers. */
696 enum MasterCtrl {
697 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
698 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
699 };
700
701 /* The Rx and Tx descriptor lists.
702 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
703 alignment contraint on tx_ring[] and rx_ring[]. */
704 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
705 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
706 struct boom_rx_desc {
707 u32 next; /* Last entry points to 0. */
708 s32 status;
709 u32 addr; /* Up to 63 addr/len pairs possible. */
710 s32 length; /* Set LAST_FRAG to indicate last pair. */
711 };
712 /* Values for the Rx status entry. */
713 enum rx_desc_status {
714 RxDComplete=0x00008000, RxDError=0x4000,
715 /* See boomerang_rx() for actual error bits */
716 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
717 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
718 };
719
720 #ifdef MAX_SKB_FRAGS
721 #define DO_ZEROCOPY 1
722 #else
723 #define DO_ZEROCOPY 0
724 #endif
725
726 struct boom_tx_desc {
727 u32 next; /* Last entry points to 0. */
728 s32 status; /* bits 0:12 length, others see below. */
729 #if DO_ZEROCOPY
730 struct {
731 u32 addr;
732 s32 length;
733 } frag[1+MAX_SKB_FRAGS];
734 #else
735 u32 addr;
736 s32 length;
737 #endif
738 };
739
740 /* Values for the Tx status entry. */
741 enum tx_desc_status {
742 CRCDisable=0x2000, TxDComplete=0x8000,
743 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
744 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
745 };
746
747 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
748 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
749
750 struct vortex_extra_stats {
751 unsigned long tx_deferred;
752 unsigned long tx_max_collisions;
753 unsigned long tx_multiple_collisions;
754 unsigned long tx_single_collisions;
755 unsigned long rx_bad_ssd;
756 };
757
758 struct vortex_private {
759 /* The Rx and Tx rings should be quad-word-aligned. */
760 struct boom_rx_desc* rx_ring;
761 struct boom_tx_desc* tx_ring;
762 dma_addr_t rx_ring_dma;
763 dma_addr_t tx_ring_dma;
764 /* The addresses of transmit- and receive-in-place skbuffs. */
765 struct sk_buff* rx_skbuff[RX_RING_SIZE];
766 struct sk_buff* tx_skbuff[TX_RING_SIZE];
767 unsigned int cur_rx, cur_tx; /* The next free ring entry */
768 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
769 struct net_device_stats stats; /* Generic stats */
770 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
771 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
772 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
773
774 /* PCI configuration space information. */
775 struct device *gendev;
776 void __iomem *ioaddr; /* IO address space */
777 void __iomem *cb_fn_base; /* CardBus function status addr space. */
778
779 /* Some values here only for performance evaluation and path-coverage */
780 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
781 int card_idx;
782
783 /* The remainder are related to chip state, mostly media selection. */
784 struct timer_list timer; /* Media selection timer. */
785 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
786 int options; /* User-settable misc. driver options. */
787 unsigned int media_override:4, /* Passed-in media type. */
788 default_media:4, /* Read from the EEPROM/Wn3_Config. */
789 full_duplex:1, autoselect:1,
790 bus_master:1, /* Vortex can only do a fragment bus-m. */
791 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
792 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
793 partner_flow_ctrl:1, /* Partner supports flow control */
794 has_nway:1,
795 enable_wol:1, /* Wake-on-LAN is enabled */
796 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
797 open:1,
798 medialock:1,
799 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
800 large_frames:1; /* accept large frames */
801 int drv_flags;
802 u16 status_enable;
803 u16 intr_enable;
804 u16 available_media; /* From Wn3_Options. */
805 u16 capabilities, info1, info2; /* Various, from EEPROM. */
806 u16 advertising; /* NWay media advertisement */
807 unsigned char phys[2]; /* MII device addresses. */
808 u16 deferred; /* Resend these interrupts when we
809 * bale from the ISR */
810 u16 io_size; /* Size of PCI region (for release_region) */
811 spinlock_t lock; /* Serialise access to device & its vortex_private */
812 struct mii_if_info mii; /* MII lib hooks/info */
813 };
814
815 #ifdef CONFIG_PCI
816 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
817 #else
818 #define DEVICE_PCI(dev) NULL
819 #endif
820
821 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
822
823 #ifdef CONFIG_EISA
824 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
825 #else
826 #define DEVICE_EISA(dev) NULL
827 #endif
828
829 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
830
831 /* The action to take with a media selection timer tick.
832 Note that we deviate from the 3Com order by checking 10base2 before AUI.
833 */
834 enum xcvr_types {
835 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
836 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
837 };
838
839 static const struct media_table {
840 char *name;
841 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
842 mask:8, /* The transceiver-present bit in Wn3_Config.*/
843 next:8; /* The media type to try next. */
844 int wait; /* Time before we check media status. */
845 } media_tbl[] = {
846 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
847 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
848 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
849 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
850 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
851 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
852 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
853 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
854 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
855 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
856 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
857 };
858
859 static struct {
860 const char str[ETH_GSTRING_LEN];
861 } ethtool_stats_keys[] = {
862 { "tx_deferred" },
863 { "tx_max_collisions" },
864 { "tx_multiple_collisions" },
865 { "tx_single_collisions" },
866 { "rx_bad_ssd" },
867 };
868
869 /* number of ETHTOOL_GSTATS u64's */
870 #define VORTEX_NUM_STATS 5
871
872 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
873 int chip_idx, int card_idx);
874 static void vortex_up(struct net_device *dev);
875 static void vortex_down(struct net_device *dev, int final);
876 static int vortex_open(struct net_device *dev);
877 static void mdio_sync(void __iomem *ioaddr, int bits);
878 static int mdio_read(struct net_device *dev, int phy_id, int location);
879 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
880 static void vortex_timer(unsigned long arg);
881 static void rx_oom_timer(unsigned long arg);
882 static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
883 static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
884 static int vortex_rx(struct net_device *dev);
885 static int boomerang_rx(struct net_device *dev);
886 static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
887 static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
888 static int vortex_close(struct net_device *dev);
889 static void dump_tx_ring(struct net_device *dev);
890 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
891 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
892 static void set_rx_mode(struct net_device *dev);
893 #ifdef CONFIG_PCI
894 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
895 #endif
896 static void vortex_tx_timeout(struct net_device *dev);
897 static void acpi_set_WOL(struct net_device *dev);
898 static struct ethtool_ops vortex_ethtool_ops;
899 static void set_8021q_mode(struct net_device *dev, int enable);
900
901 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
902 /* Option count limit only -- unlimited interfaces are supported. */
903 #define MAX_UNITS 8
904 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
905 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
906 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
907 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
908 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
909 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
910 static int global_options = -1;
911 static int global_full_duplex = -1;
912 static int global_enable_wol = -1;
913 static int global_use_mmio = -1;
914
915 /* Variables to work-around the Compaq PCI BIOS32 problem. */
916 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
917 static struct net_device *compaq_net_device;
918
919 static int vortex_cards_found;
920
921 module_param(debug, int, 0);
922 module_param(global_options, int, 0);
923 module_param_array(options, int, NULL, 0);
924 module_param(global_full_duplex, int, 0);
925 module_param_array(full_duplex, int, NULL, 0);
926 module_param_array(hw_checksums, int, NULL, 0);
927 module_param_array(flow_ctrl, int, NULL, 0);
928 module_param(global_enable_wol, int, 0);
929 module_param_array(enable_wol, int, NULL, 0);
930 module_param(rx_copybreak, int, 0);
931 module_param(max_interrupt_work, int, 0);
932 module_param(compaq_ioaddr, int, 0);
933 module_param(compaq_irq, int, 0);
934 module_param(compaq_device_id, int, 0);
935 module_param(watchdog, int, 0);
936 module_param(global_use_mmio, int, 0);
937 module_param_array(use_mmio, int, NULL, 0);
938 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
939 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
940 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
941 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
942 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
943 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
944 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
945 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
946 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
947 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
948 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
949 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
950 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
951 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
952 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
953 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
954 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
955
956 #ifdef CONFIG_NET_POLL_CONTROLLER
957 static void poll_vortex(struct net_device *dev)
958 {
959 struct vortex_private *vp = netdev_priv(dev);
960 unsigned long flags;
961 local_save_flags(flags);
962 local_irq_disable();
963 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
964 local_irq_restore(flags);
965 }
966 #endif
967
968 #ifdef CONFIG_PM
969
970 static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
971 {
972 struct net_device *dev = pci_get_drvdata(pdev);
973
974 if (dev && dev->priv) {
975 if (netif_running(dev)) {
976 netif_device_detach(dev);
977 vortex_down(dev, 1);
978 }
979 pci_save_state(pdev);
980 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
981 free_irq(dev->irq, dev);
982 pci_disable_device(pdev);
983 pci_set_power_state(pdev, pci_choose_state(pdev, state));
984 }
985 return 0;
986 }
987
988 static int vortex_resume(struct pci_dev *pdev)
989 {
990 struct net_device *dev = pci_get_drvdata(pdev);
991 struct vortex_private *vp = netdev_priv(dev);
992
993 if (dev && vp) {
994 pci_set_power_state(pdev, PCI_D0);
995 pci_restore_state(pdev);
996 pci_enable_device(pdev);
997 pci_set_master(pdev);
998 if (request_irq(dev->irq, vp->full_bus_master_rx ?
999 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
1000 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1001 pci_disable_device(pdev);
1002 return -EBUSY;
1003 }
1004 if (netif_running(dev)) {
1005 vortex_up(dev);
1006 netif_device_attach(dev);
1007 }
1008 }
1009 return 0;
1010 }
1011
1012 #endif /* CONFIG_PM */
1013
1014 #ifdef CONFIG_EISA
1015 static struct eisa_device_id vortex_eisa_ids[] = {
1016 { "TCM5920", CH_3C592 },
1017 { "TCM5970", CH_3C597 },
1018 { "" }
1019 };
1020
1021 static int vortex_eisa_probe(struct device *device);
1022 static int vortex_eisa_remove(struct device *device);
1023
1024 static struct eisa_driver vortex_eisa_driver = {
1025 .id_table = vortex_eisa_ids,
1026 .driver = {
1027 .name = "3c59x",
1028 .probe = vortex_eisa_probe,
1029 .remove = vortex_eisa_remove
1030 }
1031 };
1032
1033 static int vortex_eisa_probe(struct device *device)
1034 {
1035 void __iomem *ioaddr;
1036 struct eisa_device *edev;
1037
1038 edev = to_eisa_device(device);
1039
1040 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1041 return -EBUSY;
1042
1043 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
1044
1045 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1046 edev->id.driver_data, vortex_cards_found)) {
1047 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1048 return -ENODEV;
1049 }
1050
1051 vortex_cards_found++;
1052
1053 return 0;
1054 }
1055
1056 static int vortex_eisa_remove(struct device *device)
1057 {
1058 struct eisa_device *edev;
1059 struct net_device *dev;
1060 struct vortex_private *vp;
1061 void __iomem *ioaddr;
1062
1063 edev = to_eisa_device(device);
1064 dev = eisa_get_drvdata(edev);
1065
1066 if (!dev) {
1067 printk("vortex_eisa_remove called for Compaq device!\n");
1068 BUG();
1069 }
1070
1071 vp = netdev_priv(dev);
1072 ioaddr = vp->ioaddr;
1073
1074 unregister_netdev(dev);
1075 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
1076 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1077
1078 free_netdev(dev);
1079 return 0;
1080 }
1081 #endif
1082
1083 /* returns count found (>= 0), or negative on error */
1084 static int __init vortex_eisa_init(void)
1085 {
1086 int eisa_found = 0;
1087 int orig_cards_found = vortex_cards_found;
1088
1089 #ifdef CONFIG_EISA
1090 int err;
1091
1092 err = eisa_driver_register (&vortex_eisa_driver);
1093 if (!err) {
1094 /*
1095 * Because of the way EISA bus is probed, we cannot assume
1096 * any device have been found when we exit from
1097 * eisa_driver_register (the bus root driver may not be
1098 * initialized yet). So we blindly assume something was
1099 * found, and let the sysfs magic happend...
1100 */
1101 eisa_found = 1;
1102 }
1103 #endif
1104
1105 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1106 if (compaq_ioaddr) {
1107 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
1108 compaq_irq, compaq_device_id, vortex_cards_found++);
1109 }
1110
1111 return vortex_cards_found - orig_cards_found + eisa_found;
1112 }
1113
1114 /* returns count (>= 0), or negative on error */
1115 static int __devinit vortex_init_one(struct pci_dev *pdev,
1116 const struct pci_device_id *ent)
1117 {
1118 int rc, unit, pci_bar;
1119 struct vortex_chip_info *vci;
1120 void __iomem *ioaddr;
1121
1122 /* wake up and enable device */
1123 rc = pci_enable_device(pdev);
1124 if (rc < 0)
1125 goto out;
1126
1127 unit = vortex_cards_found;
1128
1129 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1130 /* Determine the default if the user didn't override us */
1131 vci = &vortex_info_tbl[ent->driver_data];
1132 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1133 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1134 pci_bar = use_mmio[unit] ? 1 : 0;
1135 else
1136 pci_bar = global_use_mmio ? 1 : 0;
1137
1138 ioaddr = pci_iomap(pdev, pci_bar, 0);
1139 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1140 ioaddr = pci_iomap(pdev, 0, 0);
1141
1142 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1143 ent->driver_data, unit);
1144 if (rc < 0) {
1145 pci_disable_device(pdev);
1146 goto out;
1147 }
1148
1149 vortex_cards_found++;
1150
1151 out:
1152 return rc;
1153 }
1154
1155 /*
1156 * Start up the PCI/EISA device which is described by *gendev.
1157 * Return 0 on success.
1158 *
1159 * NOTE: pdev can be NULL, for the case of a Compaq device
1160 */
1161 static int __devinit vortex_probe1(struct device *gendev,
1162 void __iomem *ioaddr, int irq,
1163 int chip_idx, int card_idx)
1164 {
1165 struct vortex_private *vp;
1166 int option;
1167 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1168 int i, step;
1169 struct net_device *dev;
1170 static int printed_version;
1171 int retval, print_info;
1172 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1173 char *print_name = "3c59x";
1174 struct pci_dev *pdev = NULL;
1175 struct eisa_device *edev = NULL;
1176
1177 if (!printed_version) {
1178 printk (version);
1179 printed_version = 1;
1180 }
1181
1182 if (gendev) {
1183 if ((pdev = DEVICE_PCI(gendev))) {
1184 print_name = pci_name(pdev);
1185 }
1186
1187 if ((edev = DEVICE_EISA(gendev))) {
1188 print_name = edev->dev.bus_id;
1189 }
1190 }
1191
1192 dev = alloc_etherdev(sizeof(*vp));
1193 retval = -ENOMEM;
1194 if (!dev) {
1195 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1196 goto out;
1197 }
1198 SET_MODULE_OWNER(dev);
1199 SET_NETDEV_DEV(dev, gendev);
1200 vp = netdev_priv(dev);
1201
1202 option = global_options;
1203
1204 /* The lower four bits are the media type. */
1205 if (dev->mem_start) {
1206 /*
1207 * The 'options' param is passed in as the third arg to the
1208 * LILO 'ether=' argument for non-modular use
1209 */
1210 option = dev->mem_start;
1211 }
1212 else if (card_idx < MAX_UNITS) {
1213 if (options[card_idx] >= 0)
1214 option = options[card_idx];
1215 }
1216
1217 if (option > 0) {
1218 if (option & 0x8000)
1219 vortex_debug = 7;
1220 if (option & 0x4000)
1221 vortex_debug = 2;
1222 if (option & 0x0400)
1223 vp->enable_wol = 1;
1224 }
1225
1226 print_info = (vortex_debug > 1);
1227 if (print_info)
1228 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1229
1230 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1231 print_name,
1232 pdev ? "PCI" : "EISA",
1233 vci->name,
1234 ioaddr);
1235
1236 dev->base_addr = (unsigned long)ioaddr;
1237 dev->irq = irq;
1238 dev->mtu = mtu;
1239 vp->ioaddr = ioaddr;
1240 vp->large_frames = mtu > 1500;
1241 vp->drv_flags = vci->drv_flags;
1242 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1243 vp->io_size = vci->io_size;
1244 vp->card_idx = card_idx;
1245
1246 /* module list only for Compaq device */
1247 if (gendev == NULL) {
1248 compaq_net_device = dev;
1249 }
1250
1251 /* PCI-only startup logic */
1252 if (pdev) {
1253 /* EISA resources already marked, so only PCI needs to do this here */
1254 /* Ignore return value, because Cardbus drivers already allocate for us */
1255 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1256 vp->must_free_region = 1;
1257
1258 /* enable bus-mastering if necessary */
1259 if (vci->flags & PCI_USES_MASTER)
1260 pci_set_master(pdev);
1261
1262 if (vci->drv_flags & IS_VORTEX) {
1263 u8 pci_latency;
1264 u8 new_latency = 248;
1265
1266 /* Check the PCI latency value. On the 3c590 series the latency timer
1267 must be set to the maximum value to avoid data corruption that occurs
1268 when the timer expires during a transfer. This bug exists the Vortex
1269 chip only. */
1270 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1271 if (pci_latency < new_latency) {
1272 printk(KERN_INFO "%s: Overriding PCI latency"
1273 " timer (CFLT) setting of %d, new value is %d.\n",
1274 print_name, pci_latency, new_latency);
1275 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1276 }
1277 }
1278 }
1279
1280 spin_lock_init(&vp->lock);
1281 vp->gendev = gendev;
1282 vp->mii.dev = dev;
1283 vp->mii.mdio_read = mdio_read;
1284 vp->mii.mdio_write = mdio_write;
1285 vp->mii.phy_id_mask = 0x1f;
1286 vp->mii.reg_num_mask = 0x1f;
1287
1288 /* Makes sure rings are at least 16 byte aligned. */
1289 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1290 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1291 &vp->rx_ring_dma);
1292 retval = -ENOMEM;
1293 if (vp->rx_ring == 0)
1294 goto free_region;
1295
1296 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1297 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1298
1299 /* if we are a PCI driver, we store info in pdev->driver_data
1300 * instead of a module list */
1301 if (pdev)
1302 pci_set_drvdata(pdev, dev);
1303 if (edev)
1304 eisa_set_drvdata(edev, dev);
1305
1306 vp->media_override = 7;
1307 if (option >= 0) {
1308 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1309 if (vp->media_override != 7)
1310 vp->medialock = 1;
1311 vp->full_duplex = (option & 0x200) ? 1 : 0;
1312 vp->bus_master = (option & 16) ? 1 : 0;
1313 }
1314
1315 if (global_full_duplex > 0)
1316 vp->full_duplex = 1;
1317 if (global_enable_wol > 0)
1318 vp->enable_wol = 1;
1319
1320 if (card_idx < MAX_UNITS) {
1321 if (full_duplex[card_idx] > 0)
1322 vp->full_duplex = 1;
1323 if (flow_ctrl[card_idx] > 0)
1324 vp->flow_ctrl = 1;
1325 if (enable_wol[card_idx] > 0)
1326 vp->enable_wol = 1;
1327 }
1328
1329 vp->mii.force_media = vp->full_duplex;
1330 vp->options = option;
1331 /* Read the station address from the EEPROM. */
1332 EL3WINDOW(0);
1333 {
1334 int base;
1335
1336 if (vci->drv_flags & EEPROM_8BIT)
1337 base = 0x230;
1338 else if (vci->drv_flags & EEPROM_OFFSET)
1339 base = EEPROM_Read + 0x30;
1340 else
1341 base = EEPROM_Read;
1342
1343 for (i = 0; i < 0x40; i++) {
1344 int timer;
1345 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1346 /* Pause for at least 162 us. for the read to take place. */
1347 for (timer = 10; timer >= 0; timer--) {
1348 udelay(162);
1349 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1350 break;
1351 }
1352 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1353 }
1354 }
1355 for (i = 0; i < 0x18; i++)
1356 checksum ^= eeprom[i];
1357 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1358 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1359 while (i < 0x21)
1360 checksum ^= eeprom[i++];
1361 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1362 }
1363 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1364 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1365 for (i = 0; i < 3; i++)
1366 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1367 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1368 if (print_info) {
1369 for (i = 0; i < 6; i++)
1370 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1371 }
1372 /* Unfortunately an all zero eeprom passes the checksum and this
1373 gets found in the wild in failure cases. Crypto is hard 8) */
1374 if (!is_valid_ether_addr(dev->dev_addr)) {
1375 retval = -EINVAL;
1376 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1377 goto free_ring; /* With every pack */
1378 }
1379 EL3WINDOW(2);
1380 for (i = 0; i < 6; i++)
1381 iowrite8(dev->dev_addr[i], ioaddr + i);
1382
1383 if (print_info)
1384 printk(", IRQ %d\n", dev->irq);
1385 /* Tell them about an invalid IRQ. */
1386 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1387 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1388 dev->irq);
1389
1390 EL3WINDOW(4);
1391 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1392 if (print_info) {
1393 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1394 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1395 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1396 }
1397
1398
1399 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1400 unsigned short n;
1401
1402 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1403 if (!vp->cb_fn_base) {
1404 retval = -ENOMEM;
1405 goto free_ring;
1406 }
1407
1408 if (print_info) {
1409 printk(KERN_INFO "%s: CardBus functions mapped "
1410 "%16.16llx->%p\n",
1411 print_name,
1412 (unsigned long long)pci_resource_start(pdev, 2),
1413 vp->cb_fn_base);
1414 }
1415 EL3WINDOW(2);
1416
1417 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1418 if (vp->drv_flags & INVERT_LED_PWR)
1419 n |= 0x10;
1420 if (vp->drv_flags & INVERT_MII_PWR)
1421 n |= 0x4000;
1422 iowrite16(n, ioaddr + Wn2_ResetOptions);
1423 if (vp->drv_flags & WNO_XCVR_PWR) {
1424 EL3WINDOW(0);
1425 iowrite16(0x0800, ioaddr);
1426 }
1427 }
1428
1429 /* Extract our information from the EEPROM data. */
1430 vp->info1 = eeprom[13];
1431 vp->info2 = eeprom[15];
1432 vp->capabilities = eeprom[16];
1433
1434 if (vp->info1 & 0x8000) {
1435 vp->full_duplex = 1;
1436 if (print_info)
1437 printk(KERN_INFO "Full duplex capable\n");
1438 }
1439
1440 {
1441 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1442 unsigned int config;
1443 EL3WINDOW(3);
1444 vp->available_media = ioread16(ioaddr + Wn3_Options);
1445 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1446 vp->available_media = 0x40;
1447 config = ioread32(ioaddr + Wn3_Config);
1448 if (print_info) {
1449 printk(KERN_DEBUG " Internal config register is %4.4x, "
1450 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1451 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1452 8 << RAM_SIZE(config),
1453 RAM_WIDTH(config) ? "word" : "byte",
1454 ram_split[RAM_SPLIT(config)],
1455 AUTOSELECT(config) ? "autoselect/" : "",
1456 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1457 media_tbl[XCVR(config)].name);
1458 }
1459 vp->default_media = XCVR(config);
1460 if (vp->default_media == XCVR_NWAY)
1461 vp->has_nway = 1;
1462 vp->autoselect = AUTOSELECT(config);
1463 }
1464
1465 if (vp->media_override != 7) {
1466 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1467 print_name, vp->media_override,
1468 media_tbl[vp->media_override].name);
1469 dev->if_port = vp->media_override;
1470 } else
1471 dev->if_port = vp->default_media;
1472
1473 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1474 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1475 int phy, phy_idx = 0;
1476 EL3WINDOW(4);
1477 mii_preamble_required++;
1478 if (vp->drv_flags & EXTRA_PREAMBLE)
1479 mii_preamble_required++;
1480 mdio_sync(ioaddr, 32);
1481 mdio_read(dev, 24, MII_BMSR);
1482 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1483 int mii_status, phyx;
1484
1485 /*
1486 * For the 3c905CX we look at index 24 first, because it bogusly
1487 * reports an external PHY at all indices
1488 */
1489 if (phy == 0)
1490 phyx = 24;
1491 else if (phy <= 24)
1492 phyx = phy - 1;
1493 else
1494 phyx = phy;
1495 mii_status = mdio_read(dev, phyx, MII_BMSR);
1496 if (mii_status && mii_status != 0xffff) {
1497 vp->phys[phy_idx++] = phyx;
1498 if (print_info) {
1499 printk(KERN_INFO " MII transceiver found at address %d,"
1500 " status %4x.\n", phyx, mii_status);
1501 }
1502 if ((mii_status & 0x0040) == 0)
1503 mii_preamble_required++;
1504 }
1505 }
1506 mii_preamble_required--;
1507 if (phy_idx == 0) {
1508 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1509 vp->phys[0] = 24;
1510 } else {
1511 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1512 if (vp->full_duplex) {
1513 /* Only advertise the FD media types. */
1514 vp->advertising &= ~0x02A0;
1515 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1516 }
1517 }
1518 vp->mii.phy_id = vp->phys[0];
1519 }
1520
1521 if (vp->capabilities & CapBusMaster) {
1522 vp->full_bus_master_tx = 1;
1523 if (print_info) {
1524 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1525 (vp->info2 & 1) ? "early" : "whole-frame" );
1526 }
1527 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1528 vp->bus_master = 0; /* AKPM: vortex only */
1529 }
1530
1531 /* The 3c59x-specific entries in the device structure. */
1532 dev->open = vortex_open;
1533 if (vp->full_bus_master_tx) {
1534 dev->hard_start_xmit = boomerang_start_xmit;
1535 /* Actually, it still should work with iommu. */
1536 if (card_idx < MAX_UNITS &&
1537 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1538 hw_checksums[card_idx] == 1)) {
1539 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1540 }
1541 } else {
1542 dev->hard_start_xmit = vortex_start_xmit;
1543 }
1544
1545 if (print_info) {
1546 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1547 print_name,
1548 (dev->features & NETIF_F_SG) ? "en":"dis",
1549 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1550 }
1551
1552 dev->stop = vortex_close;
1553 dev->get_stats = vortex_get_stats;
1554 #ifdef CONFIG_PCI
1555 dev->do_ioctl = vortex_ioctl;
1556 #endif
1557 dev->ethtool_ops = &vortex_ethtool_ops;
1558 dev->set_multicast_list = set_rx_mode;
1559 dev->tx_timeout = vortex_tx_timeout;
1560 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1561 #ifdef CONFIG_NET_POLL_CONTROLLER
1562 dev->poll_controller = poll_vortex;
1563 #endif
1564 if (pdev) {
1565 vp->pm_state_valid = 1;
1566 pci_save_state(VORTEX_PCI(vp));
1567 acpi_set_WOL(dev);
1568 }
1569 retval = register_netdev(dev);
1570 if (retval == 0)
1571 return 0;
1572
1573 free_ring:
1574 pci_free_consistent(pdev,
1575 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1576 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1577 vp->rx_ring,
1578 vp->rx_ring_dma);
1579 free_region:
1580 if (vp->must_free_region)
1581 release_region(dev->base_addr, vci->io_size);
1582 free_netdev(dev);
1583 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1584 out:
1585 return retval;
1586 }
1587
1588 static void
1589 issue_and_wait(struct net_device *dev, int cmd)
1590 {
1591 struct vortex_private *vp = netdev_priv(dev);
1592 void __iomem *ioaddr = vp->ioaddr;
1593 int i;
1594
1595 iowrite16(cmd, ioaddr + EL3_CMD);
1596 for (i = 0; i < 2000; i++) {
1597 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1598 return;
1599 }
1600
1601 /* OK, that didn't work. Do it the slow way. One second */
1602 for (i = 0; i < 100000; i++) {
1603 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1604 if (vortex_debug > 1)
1605 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1606 dev->name, cmd, i * 10);
1607 return;
1608 }
1609 udelay(10);
1610 }
1611 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1612 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1613 }
1614
1615 static void
1616 vortex_set_duplex(struct net_device *dev)
1617 {
1618 struct vortex_private *vp = netdev_priv(dev);
1619 void __iomem *ioaddr = vp->ioaddr;
1620
1621 printk(KERN_INFO "%s: setting %s-duplex.\n",
1622 dev->name, (vp->full_duplex) ? "full" : "half");
1623
1624 EL3WINDOW(3);
1625 /* Set the full-duplex bit. */
1626 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1627 (vp->large_frames ? 0x40 : 0) |
1628 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1629 0x100 : 0),
1630 ioaddr + Wn3_MAC_Ctrl);
1631 }
1632
1633 static void vortex_check_media(struct net_device *dev, unsigned int init)
1634 {
1635 struct vortex_private *vp = netdev_priv(dev);
1636 unsigned int ok_to_print = 0;
1637
1638 if (vortex_debug > 3)
1639 ok_to_print = 1;
1640
1641 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1642 vp->full_duplex = vp->mii.full_duplex;
1643 vortex_set_duplex(dev);
1644 } else if (init) {
1645 vortex_set_duplex(dev);
1646 }
1647 }
1648
1649 static void
1650 vortex_up(struct net_device *dev)
1651 {
1652 struct vortex_private *vp = netdev_priv(dev);
1653 void __iomem *ioaddr = vp->ioaddr;
1654 unsigned int config;
1655 int i, mii_reg1, mii_reg5;
1656
1657 if (VORTEX_PCI(vp)) {
1658 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1659 if (vp->pm_state_valid)
1660 pci_restore_state(VORTEX_PCI(vp));
1661 pci_enable_device(VORTEX_PCI(vp));
1662 }
1663
1664 /* Before initializing select the active media port. */
1665 EL3WINDOW(3);
1666 config = ioread32(ioaddr + Wn3_Config);
1667
1668 if (vp->media_override != 7) {
1669 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1670 dev->name, vp->media_override,
1671 media_tbl[vp->media_override].name);
1672 dev->if_port = vp->media_override;
1673 } else if (vp->autoselect) {
1674 if (vp->has_nway) {
1675 if (vortex_debug > 1)
1676 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1677 dev->name, dev->if_port);
1678 dev->if_port = XCVR_NWAY;
1679 } else {
1680 /* Find first available media type, starting with 100baseTx. */
1681 dev->if_port = XCVR_100baseTx;
1682 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1683 dev->if_port = media_tbl[dev->if_port].next;
1684 if (vortex_debug > 1)
1685 printk(KERN_INFO "%s: first available media type: %s\n",
1686 dev->name, media_tbl[dev->if_port].name);
1687 }
1688 } else {
1689 dev->if_port = vp->default_media;
1690 if (vortex_debug > 1)
1691 printk(KERN_INFO "%s: using default media %s\n",
1692 dev->name, media_tbl[dev->if_port].name);
1693 }
1694
1695 init_timer(&vp->timer);
1696 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1697 vp->timer.data = (unsigned long)dev;
1698 vp->timer.function = vortex_timer; /* timer handler */
1699 add_timer(&vp->timer);
1700
1701 init_timer(&vp->rx_oom_timer);
1702 vp->rx_oom_timer.data = (unsigned long)dev;
1703 vp->rx_oom_timer.function = rx_oom_timer;
1704
1705 if (vortex_debug > 1)
1706 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1707 dev->name, media_tbl[dev->if_port].name);
1708
1709 vp->full_duplex = vp->mii.force_media;
1710 config = BFINS(config, dev->if_port, 20, 4);
1711 if (vortex_debug > 6)
1712 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
1713 iowrite32(config, ioaddr + Wn3_Config);
1714
1715 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1716 EL3WINDOW(4);
1717 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1718 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1719 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1720
1721 vortex_check_media(dev, 1);
1722 }
1723 else
1724 vortex_set_duplex(dev);
1725
1726 issue_and_wait(dev, TxReset);
1727 /*
1728 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1729 */
1730 issue_and_wait(dev, RxReset|0x04);
1731
1732
1733 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1734
1735 if (vortex_debug > 1) {
1736 EL3WINDOW(4);
1737 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1738 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1739 }
1740
1741 /* Set the station address and mask in window 2 each time opened. */
1742 EL3WINDOW(2);
1743 for (i = 0; i < 6; i++)
1744 iowrite8(dev->dev_addr[i], ioaddr + i);
1745 for (; i < 12; i+=2)
1746 iowrite16(0, ioaddr + i);
1747
1748 if (vp->cb_fn_base) {
1749 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1750 if (vp->drv_flags & INVERT_LED_PWR)
1751 n |= 0x10;
1752 if (vp->drv_flags & INVERT_MII_PWR)
1753 n |= 0x4000;
1754 iowrite16(n, ioaddr + Wn2_ResetOptions);
1755 }
1756
1757 if (dev->if_port == XCVR_10base2)
1758 /* Start the thinnet transceiver. We should really wait 50ms...*/
1759 iowrite16(StartCoax, ioaddr + EL3_CMD);
1760 if (dev->if_port != XCVR_NWAY) {
1761 EL3WINDOW(4);
1762 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1763 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1764 }
1765
1766 /* Switch to the stats window, and clear all stats by reading. */
1767 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1768 EL3WINDOW(6);
1769 for (i = 0; i < 10; i++)
1770 ioread8(ioaddr + i);
1771 ioread16(ioaddr + 10);
1772 ioread16(ioaddr + 12);
1773 /* New: On the Vortex we must also clear the BadSSD counter. */
1774 EL3WINDOW(4);
1775 ioread8(ioaddr + 12);
1776 /* ..and on the Boomerang we enable the extra statistics bits. */
1777 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1778
1779 /* Switch to register set 7 for normal use. */
1780 EL3WINDOW(7);
1781
1782 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1783 vp->cur_rx = vp->dirty_rx = 0;
1784 /* Initialize the RxEarly register as recommended. */
1785 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1786 iowrite32(0x0020, ioaddr + PktStatus);
1787 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1788 }
1789 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1790 vp->cur_tx = vp->dirty_tx = 0;
1791 if (vp->drv_flags & IS_BOOMERANG)
1792 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1793 /* Clear the Rx, Tx rings. */
1794 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1795 vp->rx_ring[i].status = 0;
1796 for (i = 0; i < TX_RING_SIZE; i++)
1797 vp->tx_skbuff[i] = NULL;
1798 iowrite32(0, ioaddr + DownListPtr);
1799 }
1800 /* Set receiver mode: presumably accept b-case and phys addr only. */
1801 set_rx_mode(dev);
1802 /* enable 802.1q tagged frames */
1803 set_8021q_mode(dev, 1);
1804 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1805
1806 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1807 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1808 /* Allow status bits to be seen. */
1809 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1810 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1811 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1812 (vp->bus_master ? DMADone : 0);
1813 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1814 (vp->full_bus_master_rx ? 0 : RxComplete) |
1815 StatsFull | HostError | TxComplete | IntReq
1816 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1817 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1818 /* Ack all pending events, and set active indicator mask. */
1819 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1820 ioaddr + EL3_CMD);
1821 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1822 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1823 iowrite32(0x8000, vp->cb_fn_base + 4);
1824 netif_start_queue (dev);
1825 }
1826
1827 static int
1828 vortex_open(struct net_device *dev)
1829 {
1830 struct vortex_private *vp = netdev_priv(dev);
1831 int i;
1832 int retval;
1833
1834 /* Use the now-standard shared IRQ implementation. */
1835 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1836 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1837 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1838 goto out;
1839 }
1840
1841 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1842 if (vortex_debug > 2)
1843 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1844 for (i = 0; i < RX_RING_SIZE; i++) {
1845 struct sk_buff *skb;
1846 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1847 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1848 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1849 skb = dev_alloc_skb(PKT_BUF_SZ);
1850 vp->rx_skbuff[i] = skb;
1851 if (skb == NULL)
1852 break; /* Bad news! */
1853 skb->dev = dev; /* Mark as being used by this device. */
1854 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1855 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1856 }
1857 if (i != RX_RING_SIZE) {
1858 int j;
1859 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1860 for (j = 0; j < i; j++) {
1861 if (vp->rx_skbuff[j]) {
1862 dev_kfree_skb(vp->rx_skbuff[j]);
1863 vp->rx_skbuff[j] = NULL;
1864 }
1865 }
1866 retval = -ENOMEM;
1867 goto out_free_irq;
1868 }
1869 /* Wrap the ring. */
1870 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1871 }
1872
1873 vortex_up(dev);
1874 return 0;
1875
1876 out_free_irq:
1877 free_irq(dev->irq, dev);
1878 out:
1879 if (vortex_debug > 1)
1880 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1881 return retval;
1882 }
1883
1884 static void
1885 vortex_timer(unsigned long data)
1886 {
1887 struct net_device *dev = (struct net_device *)data;
1888 struct vortex_private *vp = netdev_priv(dev);
1889 void __iomem *ioaddr = vp->ioaddr;
1890 int next_tick = 60*HZ;
1891 int ok = 0;
1892 int media_status, old_window;
1893
1894 if (vortex_debug > 2) {
1895 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1896 dev->name, media_tbl[dev->if_port].name);
1897 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1898 }
1899
1900 disable_irq_lockdep(dev->irq);
1901 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1902 EL3WINDOW(4);
1903 media_status = ioread16(ioaddr + Wn4_Media);
1904 switch (dev->if_port) {
1905 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1906 if (media_status & Media_LnkBeat) {
1907 netif_carrier_on(dev);
1908 ok = 1;
1909 if (vortex_debug > 1)
1910 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1911 dev->name, media_tbl[dev->if_port].name, media_status);
1912 } else {
1913 netif_carrier_off(dev);
1914 if (vortex_debug > 1) {
1915 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1916 dev->name, media_tbl[dev->if_port].name, media_status);
1917 }
1918 }
1919 break;
1920 case XCVR_MII: case XCVR_NWAY:
1921 {
1922 ok = 1;
1923 spin_lock_bh(&vp->lock);
1924 vortex_check_media(dev, 0);
1925 spin_unlock_bh(&vp->lock);
1926 }
1927 break;
1928 default: /* Other media types handled by Tx timeouts. */
1929 if (vortex_debug > 1)
1930 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1931 dev->name, media_tbl[dev->if_port].name, media_status);
1932 ok = 1;
1933 }
1934
1935 if (!netif_carrier_ok(dev))
1936 next_tick = 5*HZ;
1937
1938 if (vp->medialock)
1939 goto leave_media_alone;
1940
1941 if (!ok) {
1942 unsigned int config;
1943
1944 do {
1945 dev->if_port = media_tbl[dev->if_port].next;
1946 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1947 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1948 dev->if_port = vp->default_media;
1949 if (vortex_debug > 1)
1950 printk(KERN_DEBUG "%s: Media selection failing, using default "
1951 "%s port.\n",
1952 dev->name, media_tbl[dev->if_port].name);
1953 } else {
1954 if (vortex_debug > 1)
1955 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1956 "%s port.\n",
1957 dev->name, media_tbl[dev->if_port].name);
1958 next_tick = media_tbl[dev->if_port].wait;
1959 }
1960 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1961 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1962
1963 EL3WINDOW(3);
1964 config = ioread32(ioaddr + Wn3_Config);
1965 config = BFINS(config, dev->if_port, 20, 4);
1966 iowrite32(config, ioaddr + Wn3_Config);
1967
1968 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1969 ioaddr + EL3_CMD);
1970 if (vortex_debug > 1)
1971 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1972 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1973 }
1974
1975 leave_media_alone:
1976 if (vortex_debug > 2)
1977 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1978 dev->name, media_tbl[dev->if_port].name);
1979
1980 EL3WINDOW(old_window);
1981 enable_irq_lockdep(dev->irq);
1982 mod_timer(&vp->timer, RUN_AT(next_tick));
1983 if (vp->deferred)
1984 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1985 return;
1986 }
1987
1988 static void vortex_tx_timeout(struct net_device *dev)
1989 {
1990 struct vortex_private *vp = netdev_priv(dev);
1991 void __iomem *ioaddr = vp->ioaddr;
1992
1993 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1994 dev->name, ioread8(ioaddr + TxStatus),
1995 ioread16(ioaddr + EL3_STATUS));
1996 EL3WINDOW(4);
1997 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1998 ioread16(ioaddr + Wn4_NetDiag),
1999 ioread16(ioaddr + Wn4_Media),
2000 ioread32(ioaddr + PktStatus),
2001 ioread16(ioaddr + Wn4_FIFODiag));
2002 /* Slight code bloat to be user friendly. */
2003 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
2004 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
2005 " network cable problem?\n", dev->name);
2006 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
2007 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
2008 " IRQ blocked by another device?\n", dev->name);
2009 /* Bad idea here.. but we might as well handle a few events. */
2010 {
2011 /*
2012 * Block interrupts because vortex_interrupt does a bare spin_lock()
2013 */
2014 unsigned long flags;
2015 local_irq_save(flags);
2016 if (vp->full_bus_master_tx)
2017 boomerang_interrupt(dev->irq, dev, NULL);
2018 else
2019 vortex_interrupt(dev->irq, dev, NULL);
2020 local_irq_restore(flags);
2021 }
2022 }
2023
2024 if (vortex_debug > 0)
2025 dump_tx_ring(dev);
2026
2027 issue_and_wait(dev, TxReset);
2028
2029 vp->stats.tx_errors++;
2030 if (vp->full_bus_master_tx) {
2031 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
2032 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
2033 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
2034 ioaddr + DownListPtr);
2035 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
2036 netif_wake_queue (dev);
2037 if (vp->drv_flags & IS_BOOMERANG)
2038 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
2039 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2040 } else {
2041 vp->stats.tx_dropped++;
2042 netif_wake_queue(dev);
2043 }
2044
2045 /* Issue Tx Enable */
2046 iowrite16(TxEnable, ioaddr + EL3_CMD);
2047 dev->trans_start = jiffies;
2048
2049 /* Switch to register set 7 for normal use. */
2050 EL3WINDOW(7);
2051 }
2052
2053 /*
2054 * Handle uncommon interrupt sources. This is a separate routine to minimize
2055 * the cache impact.
2056 */
2057 static void
2058 vortex_error(struct net_device *dev, int status)
2059 {
2060 struct vortex_private *vp = netdev_priv(dev);
2061 void __iomem *ioaddr = vp->ioaddr;
2062 int do_tx_reset = 0, reset_mask = 0;
2063 unsigned char tx_status = 0;
2064
2065 if (vortex_debug > 2) {
2066 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
2067 }
2068
2069 if (status & TxComplete) { /* Really "TxError" for us. */
2070 tx_status = ioread8(ioaddr + TxStatus);
2071 /* Presumably a tx-timeout. We must merely re-enable. */
2072 if (vortex_debug > 2
2073 || (tx_status != 0x88 && vortex_debug > 0)) {
2074 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
2075 dev->name, tx_status);
2076 if (tx_status == 0x82) {
2077 printk(KERN_ERR "Probably a duplex mismatch. See "
2078 "Documentation/networking/vortex.txt\n");
2079 }
2080 dump_tx_ring(dev);
2081 }
2082 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2083 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2084 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
2085 iowrite8(0, ioaddr + TxStatus);
2086 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2087 do_tx_reset = 1;
2088 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
2089 do_tx_reset = 1;
2090 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2091 } else { /* Merely re-enable the transmitter. */
2092 iowrite16(TxEnable, ioaddr + EL3_CMD);
2093 }
2094 }
2095
2096 if (status & RxEarly) { /* Rx early is unused. */
2097 vortex_rx(dev);
2098 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2099 }
2100 if (status & StatsFull) { /* Empty statistics. */
2101 static int DoneDidThat;
2102 if (vortex_debug > 4)
2103 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2104 update_stats(ioaddr, dev);
2105 /* HACK: Disable statistics as an interrupt source. */
2106 /* This occurs when we have the wrong media type! */
2107 if (DoneDidThat == 0 &&
2108 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2109 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2110 "stats as an interrupt source.\n", dev->name);
2111 EL3WINDOW(5);
2112 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
2113 vp->intr_enable &= ~StatsFull;
2114 EL3WINDOW(7);
2115 DoneDidThat++;
2116 }
2117 }
2118 if (status & IntReq) { /* Restore all interrupt sources. */
2119 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2120 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2121 }
2122 if (status & HostError) {
2123 u16 fifo_diag;
2124 EL3WINDOW(4);
2125 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
2126 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2127 dev->name, fifo_diag);
2128 /* Adapter failure requires Tx/Rx reset and reinit. */
2129 if (vp->full_bus_master_tx) {
2130 int bus_status = ioread32(ioaddr + PktStatus);
2131 /* 0x80000000 PCI master abort. */
2132 /* 0x40000000 PCI target abort. */
2133 if (vortex_debug)
2134 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2135
2136 /* In this case, blow the card away */
2137 /* Must not enter D3 or we can't legally issue the reset! */
2138 vortex_down(dev, 0);
2139 issue_and_wait(dev, TotalReset | 0xff);
2140 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2141 } else if (fifo_diag & 0x0400)
2142 do_tx_reset = 1;
2143 if (fifo_diag & 0x3000) {
2144 /* Reset Rx fifo and upload logic */
2145 issue_and_wait(dev, RxReset|0x07);
2146 /* Set the Rx filter to the current state. */
2147 set_rx_mode(dev);
2148 /* enable 802.1q VLAN tagged frames */
2149 set_8021q_mode(dev, 1);
2150 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2151 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2152 }
2153 }
2154
2155 if (do_tx_reset) {
2156 issue_and_wait(dev, TxReset|reset_mask);
2157 iowrite16(TxEnable, ioaddr + EL3_CMD);
2158 if (!vp->full_bus_master_tx)
2159 netif_wake_queue(dev);
2160 }
2161 }
2162
2163 static int
2164 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2165 {
2166 struct vortex_private *vp = netdev_priv(dev);
2167 void __iomem *ioaddr = vp->ioaddr;
2168
2169 /* Put out the doubleword header... */
2170 iowrite32(skb->len, ioaddr + TX_FIFO);
2171 if (vp->bus_master) {
2172 /* Set the bus-master controller to transfer the packet. */
2173 int len = (skb->len + 3) & ~3;
2174 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2175 ioaddr + Wn7_MasterAddr);
2176 iowrite16(len, ioaddr + Wn7_MasterLen);
2177 vp->tx_skb = skb;
2178 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2179 /* netif_wake_queue() will be called at the DMADone interrupt. */
2180 } else {
2181 /* ... and the packet rounded to a doubleword. */
2182 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2183 dev_kfree_skb (skb);
2184 if (ioread16(ioaddr + TxFree) > 1536) {
2185 netif_start_queue (dev); /* AKPM: redundant? */
2186 } else {
2187 /* Interrupt us when the FIFO has room for max-sized packet. */
2188 netif_stop_queue(dev);
2189 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2190 }
2191 }
2192
2193 dev->trans_start = jiffies;
2194
2195 /* Clear the Tx status stack. */
2196 {
2197 int tx_status;
2198 int i = 32;
2199
2200 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2201 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2202 if (vortex_debug > 2)
2203 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2204 dev->name, tx_status);
2205 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2206 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2207 if (tx_status & 0x30) {
2208 issue_and_wait(dev, TxReset);
2209 }
2210 iowrite16(TxEnable, ioaddr + EL3_CMD);
2211 }
2212 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2213 }
2214 }
2215 return 0;
2216 }
2217
2218 static int
2219 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2220 {
2221 struct vortex_private *vp = netdev_priv(dev);
2222 void __iomem *ioaddr = vp->ioaddr;
2223 /* Calculate the next Tx descriptor entry. */
2224 int entry = vp->cur_tx % TX_RING_SIZE;
2225 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2226 unsigned long flags;
2227
2228 if (vortex_debug > 6) {
2229 printk(KERN_DEBUG "boomerang_start_xmit()\n");
2230 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2231 dev->name, vp->cur_tx);
2232 }
2233
2234 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2235 if (vortex_debug > 0)
2236 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2237 dev->name);
2238 netif_stop_queue(dev);
2239 return 1;
2240 }
2241
2242 vp->tx_skbuff[entry] = skb;
2243
2244 vp->tx_ring[entry].next = 0;
2245 #if DO_ZEROCOPY
2246 if (skb->ip_summed != CHECKSUM_HW)
2247 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2248 else
2249 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2250
2251 if (!skb_shinfo(skb)->nr_frags) {
2252 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2253 skb->len, PCI_DMA_TODEVICE));
2254 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2255 } else {
2256 int i;
2257
2258 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2259 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2260 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2261
2262 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2263 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2264
2265 vp->tx_ring[entry].frag[i+1].addr =
2266 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2267 (void*)page_address(frag->page) + frag->page_offset,
2268 frag->size, PCI_DMA_TODEVICE));
2269
2270 if (i == skb_shinfo(skb)->nr_frags-1)
2271 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2272 else
2273 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2274 }
2275 }
2276 #else
2277 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2278 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2279 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2280 #endif
2281
2282 spin_lock_irqsave(&vp->lock, flags);
2283 /* Wait for the stall to complete. */
2284 issue_and_wait(dev, DownStall);
2285 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2286 if (ioread32(ioaddr + DownListPtr) == 0) {
2287 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2288 vp->queued_packet++;
2289 }
2290
2291 vp->cur_tx++;
2292 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2293 netif_stop_queue (dev);
2294 } else { /* Clear previous interrupt enable. */
2295 #if defined(tx_interrupt_mitigation)
2296 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2297 * were selected, this would corrupt DN_COMPLETE. No?
2298 */
2299 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2300 #endif
2301 }
2302 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2303 spin_unlock_irqrestore(&vp->lock, flags);
2304 dev->trans_start = jiffies;
2305 return 0;
2306 }
2307
2308 /* The interrupt handler does all of the Rx thread work and cleans up
2309 after the Tx thread. */
2310
2311 /*
2312 * This is the ISR for the vortex series chips.
2313 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2314 */
2315
2316 static irqreturn_t
2317 vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2318 {
2319 struct net_device *dev = dev_id;
2320 struct vortex_private *vp = netdev_priv(dev);
2321 void __iomem *ioaddr;
2322 int status;
2323 int work_done = max_interrupt_work;
2324 int handled = 0;
2325
2326 ioaddr = vp->ioaddr;
2327 spin_lock(&vp->lock);
2328
2329 status = ioread16(ioaddr + EL3_STATUS);
2330
2331 if (vortex_debug > 6)
2332 printk("vortex_interrupt(). status=0x%4x\n", status);
2333
2334 if ((status & IntLatch) == 0)
2335 goto handler_exit; /* No interrupt: shared IRQs cause this */
2336 handled = 1;
2337
2338 if (status & IntReq) {
2339 status |= vp->deferred;
2340 vp->deferred = 0;
2341 }
2342
2343 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2344 goto handler_exit;
2345
2346 if (vortex_debug > 4)
2347 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2348 dev->name, status, ioread8(ioaddr + Timer));
2349
2350 do {
2351 if (vortex_debug > 5)
2352 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2353 dev->name, status);
2354 if (status & RxComplete)
2355 vortex_rx(dev);
2356
2357 if (status & TxAvailable) {
2358 if (vortex_debug > 5)
2359 printk(KERN_DEBUG " TX room bit was handled.\n");
2360 /* There's room in the FIFO for a full-sized packet. */
2361 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2362 netif_wake_queue (dev);
2363 }
2364
2365 if (status & DMADone) {
2366 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2367 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2368 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2369 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2370 if (ioread16(ioaddr + TxFree) > 1536) {
2371 /*
2372 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2373 * insufficient FIFO room, the TxAvailable test will succeed and call
2374 * netif_wake_queue()
2375 */
2376 netif_wake_queue(dev);
2377 } else { /* Interrupt when FIFO has room for max-sized packet. */
2378 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2379 netif_stop_queue(dev);
2380 }
2381 }
2382 }
2383 /* Check for all uncommon interrupts at once. */
2384 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2385 if (status == 0xffff)
2386 break;
2387 vortex_error(dev, status);
2388 }
2389
2390 if (--work_done < 0) {
2391 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2392 "%4.4x.\n", dev->name, status);
2393 /* Disable all pending interrupts. */
2394 do {
2395 vp->deferred |= status;
2396 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2397 ioaddr + EL3_CMD);
2398 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2399 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2400 /* The timer will reenable interrupts. */
2401 mod_timer(&vp->timer, jiffies + 1*HZ);
2402 break;
2403 }
2404 /* Acknowledge the IRQ. */
2405 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2406 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2407
2408 if (vortex_debug > 4)
2409 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2410 dev->name, status);
2411 handler_exit:
2412 spin_unlock(&vp->lock);
2413 return IRQ_RETVAL(handled);
2414 }
2415
2416 /*
2417 * This is the ISR for the boomerang series chips.
2418 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2419 */
2420
2421 static irqreturn_t
2422 boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2423 {
2424 struct net_device *dev = dev_id;
2425 struct vortex_private *vp = netdev_priv(dev);
2426 void __iomem *ioaddr;
2427 int status;
2428 int work_done = max_interrupt_work;
2429
2430 ioaddr = vp->ioaddr;
2431
2432 /*
2433 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2434 * and boomerang_start_xmit
2435 */
2436 spin_lock(&vp->lock);
2437
2438 status = ioread16(ioaddr + EL3_STATUS);
2439
2440 if (vortex_debug > 6)
2441 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2442
2443 if ((status & IntLatch) == 0)
2444 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2445
2446 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2447 if (vortex_debug > 1)
2448 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2449 goto handler_exit;
2450 }
2451
2452 if (status & IntReq) {
2453 status |= vp->deferred;
2454 vp->deferred = 0;
2455 }
2456
2457 if (vortex_debug > 4)
2458 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2459 dev->name, status, ioread8(ioaddr + Timer));
2460 do {
2461 if (vortex_debug > 5)
2462 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2463 dev->name, status);
2464 if (status & UpComplete) {
2465 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2466 if (vortex_debug > 5)
2467 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2468 boomerang_rx(dev);
2469 }
2470
2471 if (status & DownComplete) {
2472 unsigned int dirty_tx = vp->dirty_tx;
2473
2474 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2475 while (vp->cur_tx - dirty_tx > 0) {
2476 int entry = dirty_tx % TX_RING_SIZE;
2477 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2478 if (ioread32(ioaddr + DownListPtr) ==
2479 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2480 break; /* It still hasn't been processed. */
2481 #else
2482 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2483 break; /* It still hasn't been processed. */
2484 #endif
2485
2486 if (vp->tx_skbuff[entry]) {
2487 struct sk_buff *skb = vp->tx_skbuff[entry];
2488 #if DO_ZEROCOPY
2489 int i;
2490 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2491 pci_unmap_single(VORTEX_PCI(vp),
2492 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2493 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2494 PCI_DMA_TODEVICE);
2495 #else
2496 pci_unmap_single(VORTEX_PCI(vp),
2497 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2498 #endif
2499 dev_kfree_skb_irq(skb);
2500 vp->tx_skbuff[entry] = NULL;
2501 } else {
2502 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2503 }
2504 /* vp->stats.tx_packets++; Counted below. */
2505 dirty_tx++;
2506 }
2507 vp->dirty_tx = dirty_tx;
2508 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2509 if (vortex_debug > 6)
2510 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2511 netif_wake_queue (dev);
2512 }
2513 }
2514
2515 /* Check for all uncommon interrupts at once. */
2516 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2517 vortex_error(dev, status);
2518
2519 if (--work_done < 0) {
2520 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2521 "%4.4x.\n", dev->name, status);
2522 /* Disable all pending interrupts. */
2523 do {
2524 vp->deferred |= status;
2525 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2526 ioaddr + EL3_CMD);
2527 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2528 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2529 /* The timer will reenable interrupts. */
2530 mod_timer(&vp->timer, jiffies + 1*HZ);
2531 break;
2532 }
2533 /* Acknowledge the IRQ. */
2534 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2535 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2536 iowrite32(0x8000, vp->cb_fn_base + 4);
2537
2538 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2539
2540 if (vortex_debug > 4)
2541 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2542 dev->name, status);
2543 handler_exit:
2544 spin_unlock(&vp->lock);
2545 return IRQ_HANDLED;
2546 }
2547
2548 static int vortex_rx(struct net_device *dev)
2549 {
2550 struct vortex_private *vp = netdev_priv(dev);
2551 void __iomem *ioaddr = vp->ioaddr;
2552 int i;
2553 short rx_status;
2554
2555 if (vortex_debug > 5)
2556 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2557 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2558 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2559 if (rx_status & 0x4000) { /* Error, update stats. */
2560 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2561 if (vortex_debug > 2)
2562 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2563 vp->stats.rx_errors++;
2564 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2565 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2566 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2567 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2568 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2569 } else {
2570 /* The packet length: up to 4.5K!. */
2571 int pkt_len = rx_status & 0x1fff;
2572 struct sk_buff *skb;
2573
2574 skb = dev_alloc_skb(pkt_len + 5);
2575 if (vortex_debug > 4)
2576 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2577 pkt_len, rx_status);
2578 if (skb != NULL) {
2579 skb->dev = dev;
2580 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2581 /* 'skb_put()' points to the start of sk_buff data area. */
2582 if (vp->bus_master &&
2583 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2584 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2585 pkt_len, PCI_DMA_FROMDEVICE);
2586 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2587 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2588 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2589 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2590 ;
2591 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2592 } else {
2593 ioread32_rep(ioaddr + RX_FIFO,
2594 skb_put(skb, pkt_len),
2595 (pkt_len + 3) >> 2);
2596 }
2597 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2598 skb->protocol = eth_type_trans(skb, dev);
2599 netif_rx(skb);
2600 dev->last_rx = jiffies;
2601 vp->stats.rx_packets++;
2602 /* Wait a limited time to go to next packet. */
2603 for (i = 200; i >= 0; i--)
2604 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2605 break;
2606 continue;
2607 } else if (vortex_debug > 0)
2608 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2609 "size %d.\n", dev->name, pkt_len);
2610 vp->stats.rx_dropped++;
2611 }
2612 issue_and_wait(dev, RxDiscard);
2613 }
2614
2615 return 0;
2616 }
2617
2618 static int
2619 boomerang_rx(struct net_device *dev)
2620 {
2621 struct vortex_private *vp = netdev_priv(dev);
2622 int entry = vp->cur_rx % RX_RING_SIZE;
2623 void __iomem *ioaddr = vp->ioaddr;
2624 int rx_status;
2625 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2626
2627 if (vortex_debug > 5)
2628 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2629
2630 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2631 if (--rx_work_limit < 0)
2632 break;
2633 if (rx_status & RxDError) { /* Error, update stats. */
2634 unsigned char rx_error = rx_status >> 16;
2635 if (vortex_debug > 2)
2636 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2637 vp->stats.rx_errors++;
2638 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2639 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2640 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2641 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2642 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2643 } else {
2644 /* The packet length: up to 4.5K!. */
2645 int pkt_len = rx_status & 0x1fff;
2646 struct sk_buff *skb;
2647 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2648
2649 if (vortex_debug > 4)
2650 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2651 pkt_len, rx_status);
2652
2653 /* Check if the packet is long enough to just accept without
2654 copying to a properly sized skbuff. */
2655 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2656 skb->dev = dev;
2657 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2658 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2659 /* 'skb_put()' points to the start of sk_buff data area. */
2660 memcpy(skb_put(skb, pkt_len),
2661 vp->rx_skbuff[entry]->data,
2662 pkt_len);
2663 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2664 vp->rx_copy++;
2665 } else {
2666 /* Pass up the skbuff already on the Rx ring. */
2667 skb = vp->rx_skbuff[entry];
2668 vp->rx_skbuff[entry] = NULL;
2669 skb_put(skb, pkt_len);
2670 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2671 vp->rx_nocopy++;
2672 }
2673 skb->protocol = eth_type_trans(skb, dev);
2674 { /* Use hardware checksum info. */
2675 int csum_bits = rx_status & 0xee000000;
2676 if (csum_bits &&
2677 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2678 csum_bits == (IPChksumValid | UDPChksumValid))) {
2679 skb->ip_summed = CHECKSUM_UNNECESSARY;
2680 vp->rx_csumhits++;
2681 }
2682 }
2683 netif_rx(skb);
2684 dev->last_rx = jiffies;
2685 vp->stats.rx_packets++;
2686 }
2687 entry = (++vp->cur_rx) % RX_RING_SIZE;
2688 }
2689 /* Refill the Rx ring buffers. */
2690 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2691 struct sk_buff *skb;
2692 entry = vp->dirty_rx % RX_RING_SIZE;
2693 if (vp->rx_skbuff[entry] == NULL) {
2694 skb = dev_alloc_skb(PKT_BUF_SZ);
2695 if (skb == NULL) {
2696 static unsigned long last_jif;
2697 if (time_after(jiffies, last_jif + 10 * HZ)) {
2698 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2699 last_jif = jiffies;
2700 }
2701 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2702 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2703 break; /* Bad news! */
2704 }
2705 skb->dev = dev; /* Mark as being used by this device. */
2706 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2707 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2708 vp->rx_skbuff[entry] = skb;
2709 }
2710 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2711 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2712 }
2713 return 0;
2714 }
2715
2716 /*
2717 * If we've hit a total OOM refilling the Rx ring we poll once a second
2718 * for some memory. Otherwise there is no way to restart the rx process.
2719 */
2720 static void
2721 rx_oom_timer(unsigned long arg)
2722 {
2723 struct net_device *dev = (struct net_device *)arg;
2724 struct vortex_private *vp = netdev_priv(dev);
2725
2726 spin_lock_irq(&vp->lock);
2727 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2728 boomerang_rx(dev);
2729 if (vortex_debug > 1) {
2730 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2731 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2732 }
2733 spin_unlock_irq(&vp->lock);
2734 }
2735
2736 static void
2737 vortex_down(struct net_device *dev, int final_down)
2738 {
2739 struct vortex_private *vp = netdev_priv(dev);
2740 void __iomem *ioaddr = vp->ioaddr;
2741
2742 netif_stop_queue (dev);
2743
2744 del_timer_sync(&vp->rx_oom_timer);
2745 del_timer_sync(&vp->timer);
2746
2747 /* Turn off statistics ASAP. We update vp->stats below. */
2748 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2749
2750 /* Disable the receiver and transmitter. */
2751 iowrite16(RxDisable, ioaddr + EL3_CMD);
2752 iowrite16(TxDisable, ioaddr + EL3_CMD);
2753
2754 /* Disable receiving 802.1q tagged frames */
2755 set_8021q_mode(dev, 0);
2756
2757 if (dev->if_port == XCVR_10base2)
2758 /* Turn off thinnet power. Green! */
2759 iowrite16(StopCoax, ioaddr + EL3_CMD);
2760
2761 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2762
2763 update_stats(ioaddr, dev);
2764 if (vp->full_bus_master_rx)
2765 iowrite32(0, ioaddr + UpListPtr);
2766 if (vp->full_bus_master_tx)
2767 iowrite32(0, ioaddr + DownListPtr);
2768
2769 if (final_down && VORTEX_PCI(vp)) {
2770 vp->pm_state_valid = 1;
2771 pci_save_state(VORTEX_PCI(vp));
2772 acpi_set_WOL(dev);
2773 }
2774 }
2775
2776 static int
2777 vortex_close(struct net_device *dev)
2778 {
2779 struct vortex_private *vp = netdev_priv(dev);
2780 void __iomem *ioaddr = vp->ioaddr;
2781 int i;
2782
2783 if (netif_device_present(dev))
2784 vortex_down(dev, 1);
2785
2786 if (vortex_debug > 1) {
2787 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2788 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2789 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2790 " tx_queued %d Rx pre-checksummed %d.\n",
2791 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2792 }
2793
2794 #if DO_ZEROCOPY
2795 if (vp->rx_csumhits &&
2796 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2797 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2798 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2799 "not using them!\n", dev->name);
2800 }
2801 #endif
2802
2803 free_irq(dev->irq, dev);
2804
2805 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2806 for (i = 0; i < RX_RING_SIZE; i++)
2807 if (vp->rx_skbuff[i]) {
2808 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2809 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2810 dev_kfree_skb(vp->rx_skbuff[i]);
2811 vp->rx_skbuff[i] = NULL;
2812 }
2813 }
2814 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2815 for (i = 0; i < TX_RING_SIZE; i++) {
2816 if (vp->tx_skbuff[i]) {
2817 struct sk_buff *skb = vp->tx_skbuff[i];
2818 #if DO_ZEROCOPY
2819 int k;
2820
2821 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2822 pci_unmap_single(VORTEX_PCI(vp),
2823 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2824 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2825 PCI_DMA_TODEVICE);
2826 #else
2827 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2828 #endif
2829 dev_kfree_skb(skb);
2830 vp->tx_skbuff[i] = NULL;
2831 }
2832 }
2833 }
2834
2835 return 0;
2836 }
2837
2838 static void
2839 dump_tx_ring(struct net_device *dev)
2840 {
2841 if (vortex_debug > 0) {
2842 struct vortex_private *vp = netdev_priv(dev);
2843 void __iomem *ioaddr = vp->ioaddr;
2844
2845 if (vp->full_bus_master_tx) {
2846 int i;
2847 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2848
2849 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2850 vp->full_bus_master_tx,
2851 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2852 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2853 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2854 ioread32(ioaddr + DownListPtr),
2855 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2856 issue_and_wait(dev, DownStall);
2857 for (i = 0; i < TX_RING_SIZE; i++) {
2858 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2859 &vp->tx_ring[i],
2860 #if DO_ZEROCOPY
2861 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2862 #else
2863 le32_to_cpu(vp->tx_ring[i].length),
2864 #endif
2865 le32_to_cpu(vp->tx_ring[i].status));
2866 }
2867 if (!stalled)
2868 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2869 }
2870 }
2871 }
2872
2873 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2874 {
2875 struct vortex_private *vp = netdev_priv(dev);
2876 void __iomem *ioaddr = vp->ioaddr;
2877 unsigned long flags;
2878
2879 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2880 spin_lock_irqsave (&vp->lock, flags);
2881 update_stats(ioaddr, dev);
2882 spin_unlock_irqrestore (&vp->lock, flags);
2883 }
2884 return &vp->stats;
2885 }
2886
2887 /* Update statistics.
2888 Unlike with the EL3 we need not worry about interrupts changing
2889 the window setting from underneath us, but we must still guard
2890 against a race condition with a StatsUpdate interrupt updating the
2891 table. This is done by checking that the ASM (!) code generated uses
2892 atomic updates with '+='.
2893 */
2894 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2895 {
2896 struct vortex_private *vp = netdev_priv(dev);
2897 int old_window = ioread16(ioaddr + EL3_CMD);
2898
2899 if (old_window == 0xffff) /* Chip suspended or ejected. */
2900 return;
2901 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2902 /* Switch to the stats window, and read everything. */
2903 EL3WINDOW(6);
2904 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2905 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2906 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2907 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2908 vp->stats.tx_packets += ioread8(ioaddr + 6);
2909 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2910 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
2911 /* Don't bother with register 9, an extension of registers 6&7.
2912 If we do use the 6&7 values the atomic update assumption above
2913 is invalid. */
2914 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2915 vp->stats.tx_bytes += ioread16(ioaddr + 12);
2916 /* Extra stats for get_ethtool_stats() */
2917 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
2918 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
2919 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
2920 EL3WINDOW(4);
2921 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
2922
2923 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2924 + vp->xstats.tx_single_collisions
2925 + vp->xstats.tx_max_collisions;
2926
2927 {
2928 u8 up = ioread8(ioaddr + 13);
2929 vp->stats.rx_bytes += (up & 0x0f) << 16;
2930 vp->stats.tx_bytes += (up & 0xf0) << 12;
2931 }
2932
2933 EL3WINDOW(old_window >> 13);
2934 return;
2935 }
2936
2937 static int vortex_nway_reset(struct net_device *dev)
2938 {
2939 struct vortex_private *vp = netdev_priv(dev);
2940 void __iomem *ioaddr = vp->ioaddr;
2941 unsigned long flags;
2942 int rc;
2943
2944 spin_lock_irqsave(&vp->lock, flags);
2945 EL3WINDOW(4);
2946 rc = mii_nway_restart(&vp->mii);
2947 spin_unlock_irqrestore(&vp->lock, flags);
2948 return rc;
2949 }
2950
2951 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2952 {
2953 struct vortex_private *vp = netdev_priv(dev);
2954 void __iomem *ioaddr = vp->ioaddr;
2955 unsigned long flags;
2956 int rc;
2957
2958 spin_lock_irqsave(&vp->lock, flags);
2959 EL3WINDOW(4);
2960 rc = mii_ethtool_gset(&vp->mii, cmd);
2961 spin_unlock_irqrestore(&vp->lock, flags);
2962 return rc;
2963 }
2964
2965 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2966 {
2967 struct vortex_private *vp = netdev_priv(dev);
2968 void __iomem *ioaddr = vp->ioaddr;
2969 unsigned long flags;
2970 int rc;
2971
2972 spin_lock_irqsave(&vp->lock, flags);
2973 EL3WINDOW(4);
2974 rc = mii_ethtool_sset(&vp->mii, cmd);
2975 spin_unlock_irqrestore(&vp->lock, flags);
2976 return rc;
2977 }
2978
2979 static u32 vortex_get_msglevel(struct net_device *dev)
2980 {
2981 return vortex_debug;
2982 }
2983
2984 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2985 {
2986 vortex_debug = dbg;
2987 }
2988
2989 static int vortex_get_stats_count(struct net_device *dev)
2990 {
2991 return VORTEX_NUM_STATS;
2992 }
2993
2994 static void vortex_get_ethtool_stats(struct net_device *dev,
2995 struct ethtool_stats *stats, u64 *data)
2996 {
2997 struct vortex_private *vp = netdev_priv(dev);
2998 void __iomem *ioaddr = vp->ioaddr;
2999 unsigned long flags;
3000
3001 spin_lock_irqsave(&vp->lock, flags);
3002 update_stats(ioaddr, dev);
3003 spin_unlock_irqrestore(&vp->lock, flags);
3004
3005 data[0] = vp->xstats.tx_deferred;
3006 data[1] = vp->xstats.tx_max_collisions;
3007 data[2] = vp->xstats.tx_multiple_collisions;
3008 data[3] = vp->xstats.tx_single_collisions;
3009 data[4] = vp->xstats.rx_bad_ssd;
3010 }
3011
3012
3013 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3014 {
3015 switch (stringset) {
3016 case ETH_SS_STATS:
3017 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
3018 break;
3019 default:
3020 WARN_ON(1);
3021 break;
3022 }
3023 }
3024
3025 static void vortex_get_drvinfo(struct net_device *dev,
3026 struct ethtool_drvinfo *info)
3027 {
3028 struct vortex_private *vp = netdev_priv(dev);
3029
3030 strcpy(info->driver, DRV_NAME);
3031 if (VORTEX_PCI(vp)) {
3032 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
3033 } else {
3034 if (VORTEX_EISA(vp))
3035 sprintf(info->bus_info, vp->gendev->bus_id);
3036 else
3037 sprintf(info->bus_info, "EISA 0x%lx %d",
3038 dev->base_addr, dev->irq);
3039 }
3040 }
3041
3042 static struct ethtool_ops vortex_ethtool_ops = {
3043 .get_drvinfo = vortex_get_drvinfo,
3044 .get_strings = vortex_get_strings,
3045 .get_msglevel = vortex_get_msglevel,
3046 .set_msglevel = vortex_set_msglevel,
3047 .get_ethtool_stats = vortex_get_ethtool_stats,
3048 .get_stats_count = vortex_get_stats_count,
3049 .get_settings = vortex_get_settings,
3050 .set_settings = vortex_set_settings,
3051 .get_link = ethtool_op_get_link,
3052 .nway_reset = vortex_nway_reset,
3053 .get_perm_addr = ethtool_op_get_perm_addr,
3054 };
3055
3056 #ifdef CONFIG_PCI
3057 /*
3058 * Must power the device up to do MDIO operations
3059 */
3060 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3061 {
3062 int err;
3063 struct vortex_private *vp = netdev_priv(dev);
3064 void __iomem *ioaddr = vp->ioaddr;
3065 unsigned long flags;
3066 int state = 0;
3067
3068 if(VORTEX_PCI(vp))
3069 state = VORTEX_PCI(vp)->current_state;
3070
3071 /* The kernel core really should have pci_get_power_state() */
3072
3073 if(state != 0)
3074 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3075 spin_lock_irqsave(&vp->lock, flags);
3076 EL3WINDOW(4);
3077 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3078 spin_unlock_irqrestore(&vp->lock, flags);
3079 if(state != 0)
3080 pci_set_power_state(VORTEX_PCI(vp), state);
3081
3082 return err;
3083 }
3084 #endif
3085
3086
3087 /* Pre-Cyclone chips have no documented multicast filter, so the only
3088 multicast setting is to receive all multicast frames. At least
3089 the chip has a very clean way to set the mode, unlike many others. */
3090 static void set_rx_mode(struct net_device *dev)
3091 {
3092 struct vortex_private *vp = netdev_priv(dev);
3093 void __iomem *ioaddr = vp->ioaddr;
3094 int new_mode;
3095
3096 if (dev->flags & IFF_PROMISC) {
3097 if (vortex_debug > 0)
3098 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
3099 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3100 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
3101 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3102 } else
3103 new_mode = SetRxFilter | RxStation | RxBroadcast;
3104
3105 iowrite16(new_mode, ioaddr + EL3_CMD);
3106 }
3107
3108 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3109 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3110 Note that this must be done after each RxReset due to some backwards
3111 compatibility logic in the Cyclone and Tornado ASICs */
3112
3113 /* The Ethernet Type used for 802.1q tagged frames */
3114 #define VLAN_ETHER_TYPE 0x8100
3115
3116 static void set_8021q_mode(struct net_device *dev, int enable)
3117 {
3118 struct vortex_private *vp = netdev_priv(dev);
3119 void __iomem *ioaddr = vp->ioaddr;
3120 int old_window = ioread16(ioaddr + EL3_CMD);
3121 int mac_ctrl;
3122
3123 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3124 /* cyclone and tornado chipsets can recognize 802.1q
3125 * tagged frames and treat them correctly */
3126
3127 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3128 if (enable)
3129 max_pkt_size += 4; /* 802.1Q VLAN tag */
3130
3131 EL3WINDOW(3);
3132 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
3133
3134 /* set VlanEtherType to let the hardware checksumming
3135 treat tagged frames correctly */
3136 EL3WINDOW(7);
3137 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
3138 } else {
3139 /* on older cards we have to enable large frames */
3140
3141 vp->large_frames = dev->mtu > 1500 || enable;
3142
3143 EL3WINDOW(3);
3144 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
3145 if (vp->large_frames)
3146 mac_ctrl |= 0x40;
3147 else
3148 mac_ctrl &= ~0x40;
3149 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
3150 }
3151
3152 EL3WINDOW(old_window);
3153 }
3154 #else
3155
3156 static void set_8021q_mode(struct net_device *dev, int enable)
3157 {
3158 }
3159
3160
3161 #endif
3162
3163 /* MII transceiver control section.
3164 Read and write the MII registers using software-generated serial
3165 MDIO protocol. See the MII specifications or DP83840A data sheet
3166 for details. */
3167
3168 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3169 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3170 "overclocking" issues. */
3171 #define mdio_delay() ioread32(mdio_addr)
3172
3173 #define MDIO_SHIFT_CLK 0x01
3174 #define MDIO_DIR_WRITE 0x04
3175 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3176 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3177 #define MDIO_DATA_READ 0x02
3178 #define MDIO_ENB_IN 0x00
3179
3180 /* Generate the preamble required for initial synchronization and
3181 a few older transceivers. */
3182 static void mdio_sync(void __iomem *ioaddr, int bits)
3183 {
3184 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3185
3186 /* Establish sync by sending at least 32 logic ones. */
3187 while (-- bits >= 0) {
3188 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
3189 mdio_delay();
3190 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
3191 mdio_delay();
3192 }
3193 }
3194
3195 static int mdio_read(struct net_device *dev, int phy_id, int location)
3196 {
3197 int i;
3198 struct vortex_private *vp = netdev_priv(dev);
3199 void __iomem *ioaddr = vp->ioaddr;
3200 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3201 unsigned int retval = 0;
3202 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3203
3204 if (mii_preamble_required)
3205 mdio_sync(ioaddr, 32);
3206
3207 /* Shift the read command bits out. */
3208 for (i = 14; i >= 0; i--) {
3209 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3210 iowrite16(dataval, mdio_addr);
3211 mdio_delay();
3212 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3213 mdio_delay();
3214 }
3215 /* Read the two transition, 16 data, and wire-idle bits. */
3216 for (i = 19; i > 0; i--) {
3217 iowrite16(MDIO_ENB_IN, mdio_addr);
3218 mdio_delay();
3219 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3220 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3221 mdio_delay();
3222 }
3223 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3224 }
3225
3226 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3227 {
3228 struct vortex_private *vp = netdev_priv(dev);
3229 void __iomem *ioaddr = vp->ioaddr;
3230 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3231 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3232 int i;
3233
3234 if (mii_preamble_required)
3235 mdio_sync(ioaddr, 32);
3236
3237 /* Shift the command bits out. */
3238 for (i = 31; i >= 0; i--) {
3239 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3240 iowrite16(dataval, mdio_addr);
3241 mdio_delay();
3242 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3243 mdio_delay();
3244 }
3245 /* Leave the interface idle. */
3246 for (i = 1; i >= 0; i--) {
3247 iowrite16(MDIO_ENB_IN, mdio_addr);
3248 mdio_delay();
3249 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3250 mdio_delay();
3251 }
3252 return;
3253 }
3254
3255 /* ACPI: Advanced Configuration and Power Interface. */
3256 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3257 static void acpi_set_WOL(struct net_device *dev)
3258 {
3259 struct vortex_private *vp = netdev_priv(dev);
3260 void __iomem *ioaddr = vp->ioaddr;
3261
3262 if (vp->enable_wol) {
3263 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3264 EL3WINDOW(7);
3265 iowrite16(2, ioaddr + 0x0c);
3266 /* The RxFilter must accept the WOL frames. */
3267 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3268 iowrite16(RxEnable, ioaddr + EL3_CMD);
3269
3270 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3271
3272 /* Change the power state to D3; RxEnable doesn't take effect. */
3273 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3274 }
3275 }
3276
3277
3278 static void __devexit vortex_remove_one(struct pci_dev *pdev)
3279 {
3280 struct net_device *dev = pci_get_drvdata(pdev);
3281 struct vortex_private *vp;
3282
3283 if (!dev) {
3284 printk("vortex_remove_one called for Compaq device!\n");
3285 BUG();
3286 }
3287
3288 vp = netdev_priv(dev);
3289
3290 if (vp->cb_fn_base)
3291 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3292
3293 unregister_netdev(dev);
3294
3295 if (VORTEX_PCI(vp)) {
3296 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3297 if (vp->pm_state_valid)
3298 pci_restore_state(VORTEX_PCI(vp));
3299 pci_disable_device(VORTEX_PCI(vp));
3300 }
3301 /* Should really use issue_and_wait() here */
3302 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3303 vp->ioaddr + EL3_CMD);
3304
3305 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3306
3307 pci_free_consistent(pdev,
3308 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3309 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3310 vp->rx_ring,
3311 vp->rx_ring_dma);
3312 if (vp->must_free_region)
3313 release_region(dev->base_addr, vp->io_size);
3314 free_netdev(dev);
3315 }
3316
3317
3318 static struct pci_driver vortex_driver = {
3319 .name = "3c59x",
3320 .probe = vortex_init_one,
3321 .remove = __devexit_p(vortex_remove_one),
3322 .id_table = vortex_pci_tbl,
3323 #ifdef CONFIG_PM
3324 .suspend = vortex_suspend,
3325 .resume = vortex_resume,
3326 #endif
3327 };
3328
3329
3330 static int vortex_have_pci;
3331 static int vortex_have_eisa;
3332
3333
3334 static int __init vortex_init(void)
3335 {
3336 int pci_rc, eisa_rc;
3337
3338 pci_rc = pci_module_init(&vortex_driver);
3339 eisa_rc = vortex_eisa_init();
3340
3341 if (pci_rc == 0)
3342 vortex_have_pci = 1;
3343 if (eisa_rc > 0)
3344 vortex_have_eisa = 1;
3345
3346 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3347 }
3348
3349
3350 static void __exit vortex_eisa_cleanup(void)
3351 {
3352 struct vortex_private *vp;
3353 void __iomem *ioaddr;
3354
3355 #ifdef CONFIG_EISA
3356 /* Take care of the EISA devices */
3357 eisa_driver_unregister(&vortex_eisa_driver);
3358 #endif
3359
3360 if (compaq_net_device) {
3361 vp = compaq_net_device->priv;
3362 ioaddr = ioport_map(compaq_net_device->base_addr,
3363 VORTEX_TOTAL_SIZE);
3364
3365 unregister_netdev(compaq_net_device);
3366 iowrite16(TotalReset, ioaddr + EL3_CMD);
3367 release_region(compaq_net_device->base_addr,
3368 VORTEX_TOTAL_SIZE);
3369
3370 free_netdev(compaq_net_device);
3371 }
3372 }
3373
3374
3375 static void __exit vortex_cleanup(void)
3376 {
3377 if (vortex_have_pci)
3378 pci_unregister_driver(&vortex_driver);
3379 if (vortex_have_eisa)
3380 vortex_eisa_cleanup();
3381 }
3382
3383
3384 module_init(vortex_init);
3385 module_exit(vortex_cleanup);