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1 /*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/version.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/skbuff.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/mm.h>
68 #include <linux/highmem.h>
69 #include <linux/sockios.h>
70
71 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72 #include <linux/if_vlan.h>
73 #endif
74
75 #ifdef SIOCETHTOOL
76 #include <linux/ethtool.h>
77 #endif
78
79 #include <net/sock.h>
80 #include <net/ip.h>
81
82 #include <asm/system.h>
83 #include <asm/io.h>
84 #include <asm/irq.h>
85 #include <asm/byteorder.h>
86 #include <asm/uaccess.h>
87
88
89 #define DRV_NAME "acenic"
90
91 #undef INDEX_DEBUG
92
93 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
94 #define ACE_IS_TIGON_I(ap) 0
95 #define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
96 #else
97 #define ACE_IS_TIGON_I(ap) (ap->version == 1)
98 #define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
99 #endif
100
101 #ifndef PCI_VENDOR_ID_ALTEON
102 #define PCI_VENDOR_ID_ALTEON 0x12ae
103 #endif
104 #ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
105 #define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
106 #define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
107 #endif
108 #ifndef PCI_DEVICE_ID_3COM_3C985
109 #define PCI_DEVICE_ID_3COM_3C985 0x0001
110 #endif
111 #ifndef PCI_VENDOR_ID_NETGEAR
112 #define PCI_VENDOR_ID_NETGEAR 0x1385
113 #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
114 #endif
115 #ifndef PCI_DEVICE_ID_NETGEAR_GA620T
116 #define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
117 #endif
118
119
120 /*
121 * Farallon used the DEC vendor ID by mistake and they seem not
122 * to care - stinky!
123 */
124 #ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
125 #define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
126 #endif
127 #ifndef PCI_DEVICE_ID_FARALLON_PN9100T
128 #define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
129 #endif
130 #ifndef PCI_VENDOR_ID_SGI
131 #define PCI_VENDOR_ID_SGI 0x10a9
132 #endif
133 #ifndef PCI_DEVICE_ID_SGI_ACENIC
134 #define PCI_DEVICE_ID_SGI_ACENIC 0x0009
135 #endif
136
137 static struct pci_device_id acenic_pci_tbl[] = {
138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
147 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
148 /*
149 * Farallon used the DEC vendor ID on their cards incorrectly,
150 * then later Alteon's ID.
151 */
152 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
157 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
158 { }
159 };
160 MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
161
162 #ifndef SET_NETDEV_DEV
163 #define SET_NETDEV_DEV(net, pdev) do{} while(0)
164 #endif
165
166 #define ace_sync_irq(irq) synchronize_irq(irq)
167
168 #ifndef offset_in_page
169 #define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
170 #endif
171
172 #define ACE_MAX_MOD_PARMS 8
173 #define BOARD_IDX_STATIC 0
174 #define BOARD_IDX_OVERFLOW -1
175
176 #if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
177 defined(NETIF_F_HW_VLAN_RX)
178 #define ACENIC_DO_VLAN 1
179 #define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
180 #else
181 #define ACENIC_DO_VLAN 0
182 #define ACE_RCB_VLAN_FLAG 0
183 #endif
184
185 #include "acenic.h"
186
187 /*
188 * These must be defined before the firmware is included.
189 */
190 #define MAX_TEXT_LEN 96*1024
191 #define MAX_RODATA_LEN 8*1024
192 #define MAX_DATA_LEN 2*1024
193
194 #include "acenic_firmware.h"
195
196 #ifndef tigon2FwReleaseLocal
197 #define tigon2FwReleaseLocal 0
198 #endif
199
200 /*
201 * This driver currently supports Tigon I and Tigon II based cards
202 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
203 * GA620. The driver should also work on the SGI, DEC and Farallon
204 * versions of the card, however I have not been able to test that
205 * myself.
206 *
207 * This card is really neat, it supports receive hardware checksumming
208 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
209 * firmware. Also the programming interface is quite neat, except for
210 * the parts dealing with the i2c eeprom on the card ;-)
211 *
212 * Using jumbo frames:
213 *
214 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
215 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
216 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
217 * interface number and <MTU> being the MTU value.
218 *
219 * Module parameters:
220 *
221 * When compiled as a loadable module, the driver allows for a number
222 * of module parameters to be specified. The driver supports the
223 * following module parameters:
224 *
225 * trace=<val> - Firmware trace level. This requires special traced
226 * firmware to replace the firmware supplied with
227 * the driver - for debugging purposes only.
228 *
229 * link=<val> - Link state. Normally you want to use the default link
230 * parameters set by the driver. This can be used to
231 * override these in case your switch doesn't negotiate
232 * the link properly. Valid values are:
233 * 0x0001 - Force half duplex link.
234 * 0x0002 - Do not negotiate line speed with the other end.
235 * 0x0010 - 10Mbit/sec link.
236 * 0x0020 - 100Mbit/sec link.
237 * 0x0040 - 1000Mbit/sec link.
238 * 0x0100 - Do not negotiate flow control.
239 * 0x0200 - Enable RX flow control Y
240 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
241 * Default value is 0x0270, ie. enable link+flow
242 * control negotiation. Negotiating the highest
243 * possible link speed with RX flow control enabled.
244 *
245 * When disabling link speed negotiation, only one link
246 * speed is allowed to be specified!
247 *
248 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
249 * to wait for more packets to arive before
250 * interrupting the host, from the time the first
251 * packet arrives.
252 *
253 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
254 * to wait for more packets to arive in the transmit ring,
255 * before interrupting the host, after transmitting the
256 * first packet in the ring.
257 *
258 * max_tx_desc=<val> - maximum number of transmit descriptors
259 * (packets) transmitted before interrupting the host.
260 *
261 * max_rx_desc=<val> - maximum number of receive descriptors
262 * (packets) received before interrupting the host.
263 *
264 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
265 * increments of the NIC's on board memory to be used for
266 * transmit and receive buffers. For the 1MB NIC app. 800KB
267 * is available, on the 1/2MB NIC app. 300KB is available.
268 * 68KB will always be available as a minimum for both
269 * directions. The default value is a 50/50 split.
270 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
271 * operations, default (1) is to always disable this as
272 * that is what Alteon does on NT. I have not been able
273 * to measure any real performance differences with
274 * this on my systems. Set <val>=0 if you want to
275 * enable these operations.
276 *
277 * If you use more than one NIC, specify the parameters for the
278 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
279 * run tracing on NIC #2 but not on NIC #1 and #3.
280 *
281 * TODO:
282 *
283 * - Proper multicast support.
284 * - NIC dump support.
285 * - More tuning parameters.
286 *
287 * The mini ring is not used under Linux and I am not sure it makes sense
288 * to actually use it.
289 *
290 * New interrupt handler strategy:
291 *
292 * The old interrupt handler worked using the traditional method of
293 * replacing an skbuff with a new one when a packet arrives. However
294 * the rx rings do not need to contain a static number of buffer
295 * descriptors, thus it makes sense to move the memory allocation out
296 * of the main interrupt handler and do it in a bottom half handler
297 * and only allocate new buffers when the number of buffers in the
298 * ring is below a certain threshold. In order to avoid starving the
299 * NIC under heavy load it is however necessary to force allocation
300 * when hitting a minimum threshold. The strategy for alloction is as
301 * follows:
302 *
303 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
304 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
305 * the buffers in the interrupt handler
306 * RX_RING_THRES - maximum number of buffers in the rx ring
307 * RX_MINI_THRES - maximum number of buffers in the mini ring
308 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
309 *
310 * One advantagous side effect of this allocation approach is that the
311 * entire rx processing can be done without holding any spin lock
312 * since the rx rings and registers are totally independent of the tx
313 * ring and its registers. This of course includes the kmalloc's of
314 * new skb's. Thus start_xmit can run in parallel with rx processing
315 * and the memory allocation on SMP systems.
316 *
317 * Note that running the skb reallocation in a bottom half opens up
318 * another can of races which needs to be handled properly. In
319 * particular it can happen that the interrupt handler tries to run
320 * the reallocation while the bottom half is either running on another
321 * CPU or was interrupted on the same CPU. To get around this the
322 * driver uses bitops to prevent the reallocation routines from being
323 * reentered.
324 *
325 * TX handling can also be done without holding any spin lock, wheee
326 * this is fun! since tx_ret_csm is only written to by the interrupt
327 * handler. The case to be aware of is when shutting down the device
328 * and cleaning up where it is necessary to make sure that
329 * start_xmit() is not running while this is happening. Well DaveM
330 * informs me that this case is already protected against ... bye bye
331 * Mr. Spin Lock, it was nice to know you.
332 *
333 * TX interrupts are now partly disabled so the NIC will only generate
334 * TX interrupts for the number of coal ticks, not for the number of
335 * TX packets in the queue. This should reduce the number of TX only,
336 * ie. when no RX processing is done, interrupts seen.
337 */
338
339 /*
340 * Threshold values for RX buffer allocation - the low water marks for
341 * when to start refilling the rings are set to 75% of the ring
342 * sizes. It seems to make sense to refill the rings entirely from the
343 * intrrupt handler once it gets below the panic threshold, that way
344 * we don't risk that the refilling is moved to another CPU when the
345 * one running the interrupt handler just got the slab code hot in its
346 * cache.
347 */
348 #define RX_RING_SIZE 72
349 #define RX_MINI_SIZE 64
350 #define RX_JUMBO_SIZE 48
351
352 #define RX_PANIC_STD_THRES 16
353 #define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
354 #define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
355 #define RX_PANIC_MINI_THRES 12
356 #define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
357 #define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
358 #define RX_PANIC_JUMBO_THRES 6
359 #define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
360 #define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
361
362
363 /*
364 * Size of the mini ring entries, basically these just should be big
365 * enough to take TCP ACKs
366 */
367 #define ACE_MINI_SIZE 100
368
369 #define ACE_MINI_BUFSIZE ACE_MINI_SIZE
370 #define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
371 #define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
372
373 /*
374 * There seems to be a magic difference in the effect between 995 and 996
375 * but little difference between 900 and 995 ... no idea why.
376 *
377 * There is now a default set of tuning parameters which is set, depending
378 * on whether or not the user enables Jumbo frames. It's assumed that if
379 * Jumbo frames are enabled, the user wants optimal tuning for that case.
380 */
381 #define DEF_TX_COAL 400 /* 996 */
382 #define DEF_TX_MAX_DESC 60 /* was 40 */
383 #define DEF_RX_COAL 120 /* 1000 */
384 #define DEF_RX_MAX_DESC 25
385 #define DEF_TX_RATIO 21 /* 24 */
386
387 #define DEF_JUMBO_TX_COAL 20
388 #define DEF_JUMBO_TX_MAX_DESC 60
389 #define DEF_JUMBO_RX_COAL 30
390 #define DEF_JUMBO_RX_MAX_DESC 6
391 #define DEF_JUMBO_TX_RATIO 21
392
393 #if tigon2FwReleaseLocal < 20001118
394 /*
395 * Standard firmware and early modifications duplicate
396 * IRQ load without this flag (coal timer is never reset).
397 * Note that with this flag tx_coal should be less than
398 * time to xmit full tx ring.
399 * 400usec is not so bad for tx ring size of 128.
400 */
401 #define TX_COAL_INTS_ONLY 1 /* worth it */
402 #else
403 /*
404 * With modified firmware, this is not necessary, but still useful.
405 */
406 #define TX_COAL_INTS_ONLY 1
407 #endif
408
409 #define DEF_TRACE 0
410 #define DEF_STAT (2 * TICKS_PER_SEC)
411
412
413 static int link[ACE_MAX_MOD_PARMS];
414 static int trace[ACE_MAX_MOD_PARMS];
415 static int tx_coal_tick[ACE_MAX_MOD_PARMS];
416 static int rx_coal_tick[ACE_MAX_MOD_PARMS];
417 static int max_tx_desc[ACE_MAX_MOD_PARMS];
418 static int max_rx_desc[ACE_MAX_MOD_PARMS];
419 static int tx_ratio[ACE_MAX_MOD_PARMS];
420 static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
421
422 MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
423 MODULE_LICENSE("GPL");
424 MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
425
426 module_param_array(link, int, NULL, 0);
427 module_param_array(trace, int, NULL, 0);
428 module_param_array(tx_coal_tick, int, NULL, 0);
429 module_param_array(max_tx_desc, int, NULL, 0);
430 module_param_array(rx_coal_tick, int, NULL, 0);
431 module_param_array(max_rx_desc, int, NULL, 0);
432 module_param_array(tx_ratio, int, NULL, 0);
433 MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
434 MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
435 MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
436 MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
437 MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
438 MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
439 MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
440
441
442 static char version[] __devinitdata =
443 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
444 " http://home.cern.ch/~jes/gige/acenic.html\n";
445
446 static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
447 static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
448 static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
449
450 static const struct ethtool_ops ace_ethtool_ops = {
451 .get_settings = ace_get_settings,
452 .set_settings = ace_set_settings,
453 .get_drvinfo = ace_get_drvinfo,
454 };
455
456 static void ace_watchdog(struct net_device *dev);
457
458 static int __devinit acenic_probe_one(struct pci_dev *pdev,
459 const struct pci_device_id *id)
460 {
461 struct net_device *dev;
462 struct ace_private *ap;
463 static int boards_found;
464
465 dev = alloc_etherdev(sizeof(struct ace_private));
466 if (dev == NULL) {
467 printk(KERN_ERR "acenic: Unable to allocate "
468 "net_device structure!\n");
469 return -ENOMEM;
470 }
471
472 SET_MODULE_OWNER(dev);
473 SET_NETDEV_DEV(dev, &pdev->dev);
474
475 ap = dev->priv;
476 ap->pdev = pdev;
477 ap->name = pci_name(pdev);
478
479 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
480 #if ACENIC_DO_VLAN
481 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
482 dev->vlan_rx_register = ace_vlan_rx_register;
483 dev->vlan_rx_kill_vid = ace_vlan_rx_kill_vid;
484 #endif
485 if (1) {
486 dev->tx_timeout = &ace_watchdog;
487 dev->watchdog_timeo = 5*HZ;
488 }
489
490 dev->open = &ace_open;
491 dev->stop = &ace_close;
492 dev->hard_start_xmit = &ace_start_xmit;
493 dev->get_stats = &ace_get_stats;
494 dev->set_multicast_list = &ace_set_multicast_list;
495 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
496 dev->set_mac_address = &ace_set_mac_addr;
497 dev->change_mtu = &ace_change_mtu;
498
499 /* we only display this string ONCE */
500 if (!boards_found)
501 printk(version);
502
503 if (pci_enable_device(pdev))
504 goto fail_free_netdev;
505
506 /*
507 * Enable master mode before we start playing with the
508 * pci_command word since pci_set_master() will modify
509 * it.
510 */
511 pci_set_master(pdev);
512
513 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
514
515 /* OpenFirmware on Mac's does not set this - DOH.. */
516 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
517 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
518 "access - was not enabled by BIOS/Firmware\n",
519 ap->name);
520 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
521 pci_write_config_word(ap->pdev, PCI_COMMAND,
522 ap->pci_command);
523 wmb();
524 }
525
526 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
527 if (ap->pci_latency <= 0x40) {
528 ap->pci_latency = 0x40;
529 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
530 }
531
532 /*
533 * Remap the regs into kernel space - this is abuse of
534 * dev->base_addr since it was means for I/O port
535 * addresses but who gives a damn.
536 */
537 dev->base_addr = pci_resource_start(pdev, 0);
538 ap->regs = ioremap(dev->base_addr, 0x4000);
539 if (!ap->regs) {
540 printk(KERN_ERR "%s: Unable to map I/O register, "
541 "AceNIC %i will be disabled.\n",
542 ap->name, boards_found);
543 goto fail_free_netdev;
544 }
545
546 switch(pdev->vendor) {
547 case PCI_VENDOR_ID_ALTEON:
548 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
549 printk(KERN_INFO "%s: Farallon PN9100-T ",
550 ap->name);
551 } else {
552 printk(KERN_INFO "%s: Alteon AceNIC ",
553 ap->name);
554 }
555 break;
556 case PCI_VENDOR_ID_3COM:
557 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
558 break;
559 case PCI_VENDOR_ID_NETGEAR:
560 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
561 break;
562 case PCI_VENDOR_ID_DEC:
563 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
564 printk(KERN_INFO "%s: Farallon PN9000-SX ",
565 ap->name);
566 break;
567 }
568 case PCI_VENDOR_ID_SGI:
569 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
570 break;
571 default:
572 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
573 break;
574 }
575
576 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
577 printk("irq %d\n", pdev->irq);
578
579 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
580 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
581 printk(KERN_ERR "%s: Driver compiled without Tigon I"
582 " support - NIC disabled\n", dev->name);
583 goto fail_uninit;
584 }
585 #endif
586
587 if (ace_allocate_descriptors(dev))
588 goto fail_free_netdev;
589
590 #ifdef MODULE
591 if (boards_found >= ACE_MAX_MOD_PARMS)
592 ap->board_idx = BOARD_IDX_OVERFLOW;
593 else
594 ap->board_idx = boards_found;
595 #else
596 ap->board_idx = BOARD_IDX_STATIC;
597 #endif
598
599 if (ace_init(dev))
600 goto fail_free_netdev;
601
602 if (register_netdev(dev)) {
603 printk(KERN_ERR "acenic: device registration failed\n");
604 goto fail_uninit;
605 }
606 ap->name = dev->name;
607
608 if (ap->pci_using_dac)
609 dev->features |= NETIF_F_HIGHDMA;
610
611 pci_set_drvdata(pdev, dev);
612
613 boards_found++;
614 return 0;
615
616 fail_uninit:
617 ace_init_cleanup(dev);
618 fail_free_netdev:
619 free_netdev(dev);
620 return -ENODEV;
621 }
622
623 static void __devexit acenic_remove_one(struct pci_dev *pdev)
624 {
625 struct net_device *dev = pci_get_drvdata(pdev);
626 struct ace_private *ap = netdev_priv(dev);
627 struct ace_regs __iomem *regs = ap->regs;
628 short i;
629
630 unregister_netdev(dev);
631
632 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
633 if (ap->version >= 2)
634 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
635
636 /*
637 * This clears any pending interrupts
638 */
639 writel(1, &regs->Mb0Lo);
640 readl(&regs->CpuCtrl); /* flush */
641
642 /*
643 * Make sure no other CPUs are processing interrupts
644 * on the card before the buffers are being released.
645 * Otherwise one might experience some `interesting'
646 * effects.
647 *
648 * Then release the RX buffers - jumbo buffers were
649 * already released in ace_close().
650 */
651 ace_sync_irq(dev->irq);
652
653 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
654 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
655
656 if (skb) {
657 struct ring_info *ringp;
658 dma_addr_t mapping;
659
660 ringp = &ap->skb->rx_std_skbuff[i];
661 mapping = pci_unmap_addr(ringp, mapping);
662 pci_unmap_page(ap->pdev, mapping,
663 ACE_STD_BUFSIZE,
664 PCI_DMA_FROMDEVICE);
665
666 ap->rx_std_ring[i].size = 0;
667 ap->skb->rx_std_skbuff[i].skb = NULL;
668 dev_kfree_skb(skb);
669 }
670 }
671
672 if (ap->version >= 2) {
673 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
674 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
675
676 if (skb) {
677 struct ring_info *ringp;
678 dma_addr_t mapping;
679
680 ringp = &ap->skb->rx_mini_skbuff[i];
681 mapping = pci_unmap_addr(ringp,mapping);
682 pci_unmap_page(ap->pdev, mapping,
683 ACE_MINI_BUFSIZE,
684 PCI_DMA_FROMDEVICE);
685
686 ap->rx_mini_ring[i].size = 0;
687 ap->skb->rx_mini_skbuff[i].skb = NULL;
688 dev_kfree_skb(skb);
689 }
690 }
691 }
692
693 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
694 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
695 if (skb) {
696 struct ring_info *ringp;
697 dma_addr_t mapping;
698
699 ringp = &ap->skb->rx_jumbo_skbuff[i];
700 mapping = pci_unmap_addr(ringp, mapping);
701 pci_unmap_page(ap->pdev, mapping,
702 ACE_JUMBO_BUFSIZE,
703 PCI_DMA_FROMDEVICE);
704
705 ap->rx_jumbo_ring[i].size = 0;
706 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
707 dev_kfree_skb(skb);
708 }
709 }
710
711 ace_init_cleanup(dev);
712 free_netdev(dev);
713 }
714
715 static struct pci_driver acenic_pci_driver = {
716 .name = "acenic",
717 .id_table = acenic_pci_tbl,
718 .probe = acenic_probe_one,
719 .remove = __devexit_p(acenic_remove_one),
720 };
721
722 static int __init acenic_init(void)
723 {
724 return pci_register_driver(&acenic_pci_driver);
725 }
726
727 static void __exit acenic_exit(void)
728 {
729 pci_unregister_driver(&acenic_pci_driver);
730 }
731
732 module_init(acenic_init);
733 module_exit(acenic_exit);
734
735 static void ace_free_descriptors(struct net_device *dev)
736 {
737 struct ace_private *ap = netdev_priv(dev);
738 int size;
739
740 if (ap->rx_std_ring != NULL) {
741 size = (sizeof(struct rx_desc) *
742 (RX_STD_RING_ENTRIES +
743 RX_JUMBO_RING_ENTRIES +
744 RX_MINI_RING_ENTRIES +
745 RX_RETURN_RING_ENTRIES));
746 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
747 ap->rx_ring_base_dma);
748 ap->rx_std_ring = NULL;
749 ap->rx_jumbo_ring = NULL;
750 ap->rx_mini_ring = NULL;
751 ap->rx_return_ring = NULL;
752 }
753 if (ap->evt_ring != NULL) {
754 size = (sizeof(struct event) * EVT_RING_ENTRIES);
755 pci_free_consistent(ap->pdev, size, ap->evt_ring,
756 ap->evt_ring_dma);
757 ap->evt_ring = NULL;
758 }
759 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
760 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
761 pci_free_consistent(ap->pdev, size, ap->tx_ring,
762 ap->tx_ring_dma);
763 }
764 ap->tx_ring = NULL;
765
766 if (ap->evt_prd != NULL) {
767 pci_free_consistent(ap->pdev, sizeof(u32),
768 (void *)ap->evt_prd, ap->evt_prd_dma);
769 ap->evt_prd = NULL;
770 }
771 if (ap->rx_ret_prd != NULL) {
772 pci_free_consistent(ap->pdev, sizeof(u32),
773 (void *)ap->rx_ret_prd,
774 ap->rx_ret_prd_dma);
775 ap->rx_ret_prd = NULL;
776 }
777 if (ap->tx_csm != NULL) {
778 pci_free_consistent(ap->pdev, sizeof(u32),
779 (void *)ap->tx_csm, ap->tx_csm_dma);
780 ap->tx_csm = NULL;
781 }
782 }
783
784
785 static int ace_allocate_descriptors(struct net_device *dev)
786 {
787 struct ace_private *ap = netdev_priv(dev);
788 int size;
789
790 size = (sizeof(struct rx_desc) *
791 (RX_STD_RING_ENTRIES +
792 RX_JUMBO_RING_ENTRIES +
793 RX_MINI_RING_ENTRIES +
794 RX_RETURN_RING_ENTRIES));
795
796 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
797 &ap->rx_ring_base_dma);
798 if (ap->rx_std_ring == NULL)
799 goto fail;
800
801 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
802 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
803 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
804
805 size = (sizeof(struct event) * EVT_RING_ENTRIES);
806
807 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
808
809 if (ap->evt_ring == NULL)
810 goto fail;
811
812 /*
813 * Only allocate a host TX ring for the Tigon II, the Tigon I
814 * has to use PCI registers for this ;-(
815 */
816 if (!ACE_IS_TIGON_I(ap)) {
817 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
818
819 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
820 &ap->tx_ring_dma);
821
822 if (ap->tx_ring == NULL)
823 goto fail;
824 }
825
826 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
827 &ap->evt_prd_dma);
828 if (ap->evt_prd == NULL)
829 goto fail;
830
831 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
832 &ap->rx_ret_prd_dma);
833 if (ap->rx_ret_prd == NULL)
834 goto fail;
835
836 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
837 &ap->tx_csm_dma);
838 if (ap->tx_csm == NULL)
839 goto fail;
840
841 return 0;
842
843 fail:
844 /* Clean up. */
845 ace_init_cleanup(dev);
846 return 1;
847 }
848
849
850 /*
851 * Generic cleanup handling data allocated during init. Used when the
852 * module is unloaded or if an error occurs during initialization
853 */
854 static void ace_init_cleanup(struct net_device *dev)
855 {
856 struct ace_private *ap;
857
858 ap = netdev_priv(dev);
859
860 ace_free_descriptors(dev);
861
862 if (ap->info)
863 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
864 ap->info, ap->info_dma);
865 kfree(ap->skb);
866 kfree(ap->trace_buf);
867
868 if (dev->irq)
869 free_irq(dev->irq, dev);
870
871 iounmap(ap->regs);
872 }
873
874
875 /*
876 * Commands are considered to be slow.
877 */
878 static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
879 {
880 u32 idx;
881
882 idx = readl(&regs->CmdPrd);
883
884 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
885 idx = (idx + 1) % CMD_RING_ENTRIES;
886
887 writel(idx, &regs->CmdPrd);
888 }
889
890
891 static int __devinit ace_init(struct net_device *dev)
892 {
893 struct ace_private *ap;
894 struct ace_regs __iomem *regs;
895 struct ace_info *info = NULL;
896 struct pci_dev *pdev;
897 unsigned long myjif;
898 u64 tmp_ptr;
899 u32 tig_ver, mac1, mac2, tmp, pci_state;
900 int board_idx, ecode = 0;
901 short i;
902 unsigned char cache_size;
903
904 ap = netdev_priv(dev);
905 regs = ap->regs;
906
907 board_idx = ap->board_idx;
908
909 /*
910 * aman@sgi.com - its useful to do a NIC reset here to
911 * address the `Firmware not running' problem subsequent
912 * to any crashes involving the NIC
913 */
914 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
915 readl(&regs->HostCtrl); /* PCI write posting */
916 udelay(5);
917
918 /*
919 * Don't access any other registers before this point!
920 */
921 #ifdef __BIG_ENDIAN
922 /*
923 * This will most likely need BYTE_SWAP once we switch
924 * to using __raw_writel()
925 */
926 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
927 &regs->HostCtrl);
928 #else
929 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
930 &regs->HostCtrl);
931 #endif
932 readl(&regs->HostCtrl); /* PCI write posting */
933
934 /*
935 * Stop the NIC CPU and clear pending interrupts
936 */
937 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
938 readl(&regs->CpuCtrl); /* PCI write posting */
939 writel(0, &regs->Mb0Lo);
940
941 tig_ver = readl(&regs->HostCtrl) >> 28;
942
943 switch(tig_ver){
944 #ifndef CONFIG_ACENIC_OMIT_TIGON_I
945 case 4:
946 case 5:
947 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
948 tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
949 tigonFwReleaseFix);
950 writel(0, &regs->LocalCtrl);
951 ap->version = 1;
952 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
953 break;
954 #endif
955 case 6:
956 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
957 tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
958 tigon2FwReleaseFix);
959 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
960 readl(&regs->CpuBCtrl); /* PCI write posting */
961 /*
962 * The SRAM bank size does _not_ indicate the amount
963 * of memory on the card, it controls the _bank_ size!
964 * Ie. a 1MB AceNIC will have two banks of 512KB.
965 */
966 writel(SRAM_BANK_512K, &regs->LocalCtrl);
967 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
968 ap->version = 2;
969 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
970 break;
971 default:
972 printk(KERN_WARNING " Unsupported Tigon version detected "
973 "(%i)\n", tig_ver);
974 ecode = -ENODEV;
975 goto init_error;
976 }
977
978 /*
979 * ModeStat _must_ be set after the SRAM settings as this change
980 * seems to corrupt the ModeStat and possible other registers.
981 * The SRAM settings survive resets and setting it to the same
982 * value a second time works as well. This is what caused the
983 * `Firmware not running' problem on the Tigon II.
984 */
985 #ifdef __BIG_ENDIAN
986 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
987 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
988 #else
989 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
990 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
991 #endif
992 readl(&regs->ModeStat); /* PCI write posting */
993
994 mac1 = 0;
995 for(i = 0; i < 4; i++) {
996 int tmp;
997
998 mac1 = mac1 << 8;
999 tmp = read_eeprom_byte(dev, 0x8c+i);
1000 if (tmp < 0) {
1001 ecode = -EIO;
1002 goto init_error;
1003 } else
1004 mac1 |= (tmp & 0xff);
1005 }
1006 mac2 = 0;
1007 for(i = 4; i < 8; i++) {
1008 int tmp;
1009
1010 mac2 = mac2 << 8;
1011 tmp = read_eeprom_byte(dev, 0x8c+i);
1012 if (tmp < 0) {
1013 ecode = -EIO;
1014 goto init_error;
1015 } else
1016 mac2 |= (tmp & 0xff);
1017 }
1018
1019 writel(mac1, &regs->MacAddrHi);
1020 writel(mac2, &regs->MacAddrLo);
1021
1022 printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
1023 (mac1 >> 8) & 0xff, mac1 & 0xff, (mac2 >> 24) &0xff,
1024 (mac2 >> 16) & 0xff, (mac2 >> 8) & 0xff, mac2 & 0xff);
1025
1026 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1027 dev->dev_addr[1] = mac1 & 0xff;
1028 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1029 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1030 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1031 dev->dev_addr[5] = mac2 & 0xff;
1032
1033 /*
1034 * Looks like this is necessary to deal with on all architectures,
1035 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1036 * Ie. having two NICs in the machine, one will have the cache
1037 * line set at boot time, the other will not.
1038 */
1039 pdev = ap->pdev;
1040 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1041 cache_size <<= 2;
1042 if (cache_size != SMP_CACHE_BYTES) {
1043 printk(KERN_INFO " PCI cache line size set incorrectly "
1044 "(%i bytes) by BIOS/FW, ", cache_size);
1045 if (cache_size > SMP_CACHE_BYTES)
1046 printk("expecting %i\n", SMP_CACHE_BYTES);
1047 else {
1048 printk("correcting to %i\n", SMP_CACHE_BYTES);
1049 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1050 SMP_CACHE_BYTES >> 2);
1051 }
1052 }
1053
1054 pci_state = readl(&regs->PciState);
1055 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1056 "latency: %i clks\n",
1057 (pci_state & PCI_32BIT) ? 32 : 64,
1058 (pci_state & PCI_66MHZ) ? 66 : 33,
1059 ap->pci_latency);
1060
1061 /*
1062 * Set the max DMA transfer size. Seems that for most systems
1063 * the performance is better when no MAX parameter is
1064 * set. However for systems enabling PCI write and invalidate,
1065 * DMA writes must be set to the L1 cache line size to get
1066 * optimal performance.
1067 *
1068 * The default is now to turn the PCI write and invalidate off
1069 * - that is what Alteon does for NT.
1070 */
1071 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1072 if (ap->version >= 2) {
1073 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1074 /*
1075 * Tuning parameters only supported for 8 cards
1076 */
1077 if (board_idx == BOARD_IDX_OVERFLOW ||
1078 dis_pci_mem_inval[board_idx]) {
1079 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1080 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1081 pci_write_config_word(pdev, PCI_COMMAND,
1082 ap->pci_command);
1083 printk(KERN_INFO " Disabling PCI memory "
1084 "write and invalidate\n");
1085 }
1086 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1087 printk(KERN_INFO " PCI memory write & invalidate "
1088 "enabled by BIOS, enabling counter measures\n");
1089
1090 switch(SMP_CACHE_BYTES) {
1091 case 16:
1092 tmp |= DMA_WRITE_MAX_16;
1093 break;
1094 case 32:
1095 tmp |= DMA_WRITE_MAX_32;
1096 break;
1097 case 64:
1098 tmp |= DMA_WRITE_MAX_64;
1099 break;
1100 case 128:
1101 tmp |= DMA_WRITE_MAX_128;
1102 break;
1103 default:
1104 printk(KERN_INFO " Cache line size %i not "
1105 "supported, PCI write and invalidate "
1106 "disabled\n", SMP_CACHE_BYTES);
1107 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1108 pci_write_config_word(pdev, PCI_COMMAND,
1109 ap->pci_command);
1110 }
1111 }
1112 }
1113
1114 #ifdef __sparc__
1115 /*
1116 * On this platform, we know what the best dma settings
1117 * are. We use 64-byte maximum bursts, because if we
1118 * burst larger than the cache line size (or even cross
1119 * a 64byte boundary in a single burst) the UltraSparc
1120 * PCI controller will disconnect at 64-byte multiples.
1121 *
1122 * Read-multiple will be properly enabled above, and when
1123 * set will give the PCI controller proper hints about
1124 * prefetching.
1125 */
1126 tmp &= ~DMA_READ_WRITE_MASK;
1127 tmp |= DMA_READ_MAX_64;
1128 tmp |= DMA_WRITE_MAX_64;
1129 #endif
1130 #ifdef __alpha__
1131 tmp &= ~DMA_READ_WRITE_MASK;
1132 tmp |= DMA_READ_MAX_128;
1133 /*
1134 * All the docs say MUST NOT. Well, I did.
1135 * Nothing terrible happens, if we load wrong size.
1136 * Bit w&i still works better!
1137 */
1138 tmp |= DMA_WRITE_MAX_128;
1139 #endif
1140 writel(tmp, &regs->PciState);
1141
1142 #if 0
1143 /*
1144 * The Host PCI bus controller driver has to set FBB.
1145 * If all devices on that PCI bus support FBB, then the controller
1146 * can enable FBB support in the Host PCI Bus controller (or on
1147 * the PCI-PCI bridge if that applies).
1148 * -ggg
1149 */
1150 /*
1151 * I have received reports from people having problems when this
1152 * bit is enabled.
1153 */
1154 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1155 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1156 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1157 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1158 }
1159 #endif
1160
1161 /*
1162 * Configure DMA attributes.
1163 */
1164 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1165 ap->pci_using_dac = 1;
1166 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1167 ap->pci_using_dac = 0;
1168 } else {
1169 ecode = -ENODEV;
1170 goto init_error;
1171 }
1172
1173 /*
1174 * Initialize the generic info block and the command+event rings
1175 * and the control blocks for the transmit and receive rings
1176 * as they need to be setup once and for all.
1177 */
1178 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1179 &ap->info_dma))) {
1180 ecode = -EAGAIN;
1181 goto init_error;
1182 }
1183 ap->info = info;
1184
1185 /*
1186 * Get the memory for the skb rings.
1187 */
1188 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1189 ecode = -EAGAIN;
1190 goto init_error;
1191 }
1192
1193 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1194 DRV_NAME, dev);
1195 if (ecode) {
1196 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1197 DRV_NAME, pdev->irq);
1198 goto init_error;
1199 } else
1200 dev->irq = pdev->irq;
1201
1202 #ifdef INDEX_DEBUG
1203 spin_lock_init(&ap->debug_lock);
1204 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1205 ap->last_std_rx = 0;
1206 ap->last_mini_rx = 0;
1207 #endif
1208
1209 memset(ap->info, 0, sizeof(struct ace_info));
1210 memset(ap->skb, 0, sizeof(struct ace_skb));
1211
1212 ace_load_firmware(dev);
1213 ap->fw_running = 0;
1214
1215 tmp_ptr = ap->info_dma;
1216 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1217 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1218
1219 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1220
1221 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1222 info->evt_ctrl.flags = 0;
1223
1224 *(ap->evt_prd) = 0;
1225 wmb();
1226 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1227 writel(0, &regs->EvtCsm);
1228
1229 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1230 info->cmd_ctrl.flags = 0;
1231 info->cmd_ctrl.max_len = 0;
1232
1233 for (i = 0; i < CMD_RING_ENTRIES; i++)
1234 writel(0, &regs->CmdRng[i]);
1235
1236 writel(0, &regs->CmdPrd);
1237 writel(0, &regs->CmdCsm);
1238
1239 tmp_ptr = ap->info_dma;
1240 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1241 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1242
1243 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1244 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1245 info->rx_std_ctrl.flags =
1246 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1247
1248 memset(ap->rx_std_ring, 0,
1249 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1250
1251 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1252 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1253
1254 ap->rx_std_skbprd = 0;
1255 atomic_set(&ap->cur_rx_bufs, 0);
1256
1257 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1258 (ap->rx_ring_base_dma +
1259 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1260 info->rx_jumbo_ctrl.max_len = 0;
1261 info->rx_jumbo_ctrl.flags =
1262 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1263
1264 memset(ap->rx_jumbo_ring, 0,
1265 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1266
1267 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1268 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1269
1270 ap->rx_jumbo_skbprd = 0;
1271 atomic_set(&ap->cur_jumbo_bufs, 0);
1272
1273 memset(ap->rx_mini_ring, 0,
1274 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1275
1276 if (ap->version >= 2) {
1277 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1278 (ap->rx_ring_base_dma +
1279 (sizeof(struct rx_desc) *
1280 (RX_STD_RING_ENTRIES +
1281 RX_JUMBO_RING_ENTRIES))));
1282 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1283 info->rx_mini_ctrl.flags =
1284 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1285
1286 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1287 ap->rx_mini_ring[i].flags =
1288 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1289 } else {
1290 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1291 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1292 info->rx_mini_ctrl.max_len = 0;
1293 }
1294
1295 ap->rx_mini_skbprd = 0;
1296 atomic_set(&ap->cur_mini_bufs, 0);
1297
1298 set_aceaddr(&info->rx_return_ctrl.rngptr,
1299 (ap->rx_ring_base_dma +
1300 (sizeof(struct rx_desc) *
1301 (RX_STD_RING_ENTRIES +
1302 RX_JUMBO_RING_ENTRIES +
1303 RX_MINI_RING_ENTRIES))));
1304 info->rx_return_ctrl.flags = 0;
1305 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1306
1307 memset(ap->rx_return_ring, 0,
1308 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1309
1310 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1311 *(ap->rx_ret_prd) = 0;
1312
1313 writel(TX_RING_BASE, &regs->WinBase);
1314
1315 if (ACE_IS_TIGON_I(ap)) {
1316 ap->tx_ring = (struct tx_desc *) regs->Window;
1317 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1318 * sizeof(struct tx_desc)) / sizeof(u32); i++)
1319 writel(0, (void __iomem *)ap->tx_ring + i * 4);
1320
1321 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1322 } else {
1323 memset(ap->tx_ring, 0,
1324 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1325
1326 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1327 }
1328
1329 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1330 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1331
1332 /*
1333 * The Tigon I does not like having the TX ring in host memory ;-(
1334 */
1335 if (!ACE_IS_TIGON_I(ap))
1336 tmp |= RCB_FLG_TX_HOST_RING;
1337 #if TX_COAL_INTS_ONLY
1338 tmp |= RCB_FLG_COAL_INT_ONLY;
1339 #endif
1340 info->tx_ctrl.flags = tmp;
1341
1342 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1343
1344 /*
1345 * Potential item for tuning parameter
1346 */
1347 #if 0 /* NO */
1348 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1349 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1350 #else
1351 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1352 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1353 #endif
1354
1355 writel(0, &regs->MaskInt);
1356 writel(1, &regs->IfIdx);
1357 #if 0
1358 /*
1359 * McKinley boxes do not like us fiddling with AssistState
1360 * this early
1361 */
1362 writel(1, &regs->AssistState);
1363 #endif
1364
1365 writel(DEF_STAT, &regs->TuneStatTicks);
1366 writel(DEF_TRACE, &regs->TuneTrace);
1367
1368 ace_set_rxtx_parms(dev, 0);
1369
1370 if (board_idx == BOARD_IDX_OVERFLOW) {
1371 printk(KERN_WARNING "%s: more than %i NICs detected, "
1372 "ignoring module parameters!\n",
1373 ap->name, ACE_MAX_MOD_PARMS);
1374 } else if (board_idx >= 0) {
1375 if (tx_coal_tick[board_idx])
1376 writel(tx_coal_tick[board_idx],
1377 &regs->TuneTxCoalTicks);
1378 if (max_tx_desc[board_idx])
1379 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1380
1381 if (rx_coal_tick[board_idx])
1382 writel(rx_coal_tick[board_idx],
1383 &regs->TuneRxCoalTicks);
1384 if (max_rx_desc[board_idx])
1385 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1386
1387 if (trace[board_idx])
1388 writel(trace[board_idx], &regs->TuneTrace);
1389
1390 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1391 writel(tx_ratio[board_idx], &regs->TxBufRat);
1392 }
1393
1394 /*
1395 * Default link parameters
1396 */
1397 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1398 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1399 if(ap->version >= 2)
1400 tmp |= LNK_TX_FLOW_CTL_Y;
1401
1402 /*
1403 * Override link default parameters
1404 */
1405 if ((board_idx >= 0) && link[board_idx]) {
1406 int option = link[board_idx];
1407
1408 tmp = LNK_ENABLE;
1409
1410 if (option & 0x01) {
1411 printk(KERN_INFO "%s: Setting half duplex link\n",
1412 ap->name);
1413 tmp &= ~LNK_FULL_DUPLEX;
1414 }
1415 if (option & 0x02)
1416 tmp &= ~LNK_NEGOTIATE;
1417 if (option & 0x10)
1418 tmp |= LNK_10MB;
1419 if (option & 0x20)
1420 tmp |= LNK_100MB;
1421 if (option & 0x40)
1422 tmp |= LNK_1000MB;
1423 if ((option & 0x70) == 0) {
1424 printk(KERN_WARNING "%s: No media speed specified, "
1425 "forcing auto negotiation\n", ap->name);
1426 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1427 LNK_100MB | LNK_10MB;
1428 }
1429 if ((option & 0x100) == 0)
1430 tmp |= LNK_NEG_FCTL;
1431 else
1432 printk(KERN_INFO "%s: Disabling flow control "
1433 "negotiation\n", ap->name);
1434 if (option & 0x200)
1435 tmp |= LNK_RX_FLOW_CTL_Y;
1436 if ((option & 0x400) && (ap->version >= 2)) {
1437 printk(KERN_INFO "%s: Enabling TX flow control\n",
1438 ap->name);
1439 tmp |= LNK_TX_FLOW_CTL_Y;
1440 }
1441 }
1442
1443 ap->link = tmp;
1444 writel(tmp, &regs->TuneLink);
1445 if (ap->version >= 2)
1446 writel(tmp, &regs->TuneFastLink);
1447
1448 if (ACE_IS_TIGON_I(ap))
1449 writel(tigonFwStartAddr, &regs->Pc);
1450 if (ap->version == 2)
1451 writel(tigon2FwStartAddr, &regs->Pc);
1452
1453 writel(0, &regs->Mb0Lo);
1454
1455 /*
1456 * Set tx_csm before we start receiving interrupts, otherwise
1457 * the interrupt handler might think it is supposed to process
1458 * tx ints before we are up and running, which may cause a null
1459 * pointer access in the int handler.
1460 */
1461 ap->cur_rx = 0;
1462 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1463
1464 wmb();
1465 ace_set_txprd(regs, ap, 0);
1466 writel(0, &regs->RxRetCsm);
1467
1468 /*
1469 * Zero the stats before starting the interface
1470 */
1471 memset(&ap->stats, 0, sizeof(ap->stats));
1472
1473 /*
1474 * Enable DMA engine now.
1475 * If we do this sooner, Mckinley box pukes.
1476 * I assume it's because Tigon II DMA engine wants to check
1477 * *something* even before the CPU is started.
1478 */
1479 writel(1, &regs->AssistState); /* enable DMA */
1480
1481 /*
1482 * Start the NIC CPU
1483 */
1484 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1485 readl(&regs->CpuCtrl);
1486
1487 /*
1488 * Wait for the firmware to spin up - max 3 seconds.
1489 */
1490 myjif = jiffies + 3 * HZ;
1491 while (time_before(jiffies, myjif) && !ap->fw_running)
1492 cpu_relax();
1493
1494 if (!ap->fw_running) {
1495 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1496
1497 ace_dump_trace(ap);
1498 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1499 readl(&regs->CpuCtrl);
1500
1501 /* aman@sgi.com - account for badly behaving firmware/NIC:
1502 * - have observed that the NIC may continue to generate
1503 * interrupts for some reason; attempt to stop it - halt
1504 * second CPU for Tigon II cards, and also clear Mb0
1505 * - if we're a module, we'll fail to load if this was
1506 * the only GbE card in the system => if the kernel does
1507 * see an interrupt from the NIC, code to handle it is
1508 * gone and OOps! - so free_irq also
1509 */
1510 if (ap->version >= 2)
1511 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1512 &regs->CpuBCtrl);
1513 writel(0, &regs->Mb0Lo);
1514 readl(&regs->Mb0Lo);
1515
1516 ecode = -EBUSY;
1517 goto init_error;
1518 }
1519
1520 /*
1521 * We load the ring here as there seem to be no way to tell the
1522 * firmware to wipe the ring without re-initializing it.
1523 */
1524 if (!test_and_set_bit(0, &ap->std_refill_busy))
1525 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1526 else
1527 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1528 ap->name);
1529 if (ap->version >= 2) {
1530 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1531 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1532 else
1533 printk(KERN_ERR "%s: Someone is busy refilling "
1534 "the RX mini ring\n", ap->name);
1535 }
1536 return 0;
1537
1538 init_error:
1539 ace_init_cleanup(dev);
1540 return ecode;
1541 }
1542
1543
1544 static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1545 {
1546 struct ace_private *ap = netdev_priv(dev);
1547 struct ace_regs __iomem *regs = ap->regs;
1548 int board_idx = ap->board_idx;
1549
1550 if (board_idx >= 0) {
1551 if (!jumbo) {
1552 if (!tx_coal_tick[board_idx])
1553 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1554 if (!max_tx_desc[board_idx])
1555 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1556 if (!rx_coal_tick[board_idx])
1557 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1558 if (!max_rx_desc[board_idx])
1559 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1560 if (!tx_ratio[board_idx])
1561 writel(DEF_TX_RATIO, &regs->TxBufRat);
1562 } else {
1563 if (!tx_coal_tick[board_idx])
1564 writel(DEF_JUMBO_TX_COAL,
1565 &regs->TuneTxCoalTicks);
1566 if (!max_tx_desc[board_idx])
1567 writel(DEF_JUMBO_TX_MAX_DESC,
1568 &regs->TuneMaxTxDesc);
1569 if (!rx_coal_tick[board_idx])
1570 writel(DEF_JUMBO_RX_COAL,
1571 &regs->TuneRxCoalTicks);
1572 if (!max_rx_desc[board_idx])
1573 writel(DEF_JUMBO_RX_MAX_DESC,
1574 &regs->TuneMaxRxDesc);
1575 if (!tx_ratio[board_idx])
1576 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1577 }
1578 }
1579 }
1580
1581
1582 static void ace_watchdog(struct net_device *data)
1583 {
1584 struct net_device *dev = data;
1585 struct ace_private *ap = netdev_priv(dev);
1586 struct ace_regs __iomem *regs = ap->regs;
1587
1588 /*
1589 * We haven't received a stats update event for more than 2.5
1590 * seconds and there is data in the transmit queue, thus we
1591 * asume the card is stuck.
1592 */
1593 if (*ap->tx_csm != ap->tx_ret_csm) {
1594 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1595 dev->name, (unsigned int)readl(&regs->HostCtrl));
1596 /* This can happen due to ieee flow control. */
1597 } else {
1598 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1599 dev->name);
1600 #if 0
1601 netif_wake_queue(dev);
1602 #endif
1603 }
1604 }
1605
1606
1607 static void ace_tasklet(unsigned long dev)
1608 {
1609 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1610 int cur_size;
1611
1612 cur_size = atomic_read(&ap->cur_rx_bufs);
1613 if ((cur_size < RX_LOW_STD_THRES) &&
1614 !test_and_set_bit(0, &ap->std_refill_busy)) {
1615 #ifdef DEBUG
1616 printk("refilling buffers (current %i)\n", cur_size);
1617 #endif
1618 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1619 }
1620
1621 if (ap->version >= 2) {
1622 cur_size = atomic_read(&ap->cur_mini_bufs);
1623 if ((cur_size < RX_LOW_MINI_THRES) &&
1624 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1625 #ifdef DEBUG
1626 printk("refilling mini buffers (current %i)\n",
1627 cur_size);
1628 #endif
1629 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1630 }
1631 }
1632
1633 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1634 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1635 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1636 #ifdef DEBUG
1637 printk("refilling jumbo buffers (current %i)\n", cur_size);
1638 #endif
1639 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1640 }
1641 ap->tasklet_pending = 0;
1642 }
1643
1644
1645 /*
1646 * Copy the contents of the NIC's trace buffer to kernel memory.
1647 */
1648 static void ace_dump_trace(struct ace_private *ap)
1649 {
1650 #if 0
1651 if (!ap->trace_buf)
1652 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1653 return;
1654 #endif
1655 }
1656
1657
1658 /*
1659 * Load the standard rx ring.
1660 *
1661 * Loading rings is safe without holding the spin lock since this is
1662 * done only before the device is enabled, thus no interrupts are
1663 * generated and by the interrupt handler/tasklet handler.
1664 */
1665 static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1666 {
1667 struct ace_regs __iomem *regs = ap->regs;
1668 short i, idx;
1669
1670
1671 prefetchw(&ap->cur_rx_bufs);
1672
1673 idx = ap->rx_std_skbprd;
1674
1675 for (i = 0; i < nr_bufs; i++) {
1676 struct sk_buff *skb;
1677 struct rx_desc *rd;
1678 dma_addr_t mapping;
1679
1680 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1681 if (!skb)
1682 break;
1683
1684 skb_reserve(skb, NET_IP_ALIGN);
1685 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1686 offset_in_page(skb->data),
1687 ACE_STD_BUFSIZE,
1688 PCI_DMA_FROMDEVICE);
1689 ap->skb->rx_std_skbuff[idx].skb = skb;
1690 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1691 mapping, mapping);
1692
1693 rd = &ap->rx_std_ring[idx];
1694 set_aceaddr(&rd->addr, mapping);
1695 rd->size = ACE_STD_BUFSIZE;
1696 rd->idx = idx;
1697 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1698 }
1699
1700 if (!i)
1701 goto error_out;
1702
1703 atomic_add(i, &ap->cur_rx_bufs);
1704 ap->rx_std_skbprd = idx;
1705
1706 if (ACE_IS_TIGON_I(ap)) {
1707 struct cmd cmd;
1708 cmd.evt = C_SET_RX_PRD_IDX;
1709 cmd.code = 0;
1710 cmd.idx = ap->rx_std_skbprd;
1711 ace_issue_cmd(regs, &cmd);
1712 } else {
1713 writel(idx, &regs->RxStdPrd);
1714 wmb();
1715 }
1716
1717 out:
1718 clear_bit(0, &ap->std_refill_busy);
1719 return;
1720
1721 error_out:
1722 printk(KERN_INFO "Out of memory when allocating "
1723 "standard receive buffers\n");
1724 goto out;
1725 }
1726
1727
1728 static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1729 {
1730 struct ace_regs __iomem *regs = ap->regs;
1731 short i, idx;
1732
1733 prefetchw(&ap->cur_mini_bufs);
1734
1735 idx = ap->rx_mini_skbprd;
1736 for (i = 0; i < nr_bufs; i++) {
1737 struct sk_buff *skb;
1738 struct rx_desc *rd;
1739 dma_addr_t mapping;
1740
1741 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1742 if (!skb)
1743 break;
1744
1745 skb_reserve(skb, NET_IP_ALIGN);
1746 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1747 offset_in_page(skb->data),
1748 ACE_MINI_BUFSIZE,
1749 PCI_DMA_FROMDEVICE);
1750 ap->skb->rx_mini_skbuff[idx].skb = skb;
1751 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1752 mapping, mapping);
1753
1754 rd = &ap->rx_mini_ring[idx];
1755 set_aceaddr(&rd->addr, mapping);
1756 rd->size = ACE_MINI_BUFSIZE;
1757 rd->idx = idx;
1758 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1759 }
1760
1761 if (!i)
1762 goto error_out;
1763
1764 atomic_add(i, &ap->cur_mini_bufs);
1765
1766 ap->rx_mini_skbprd = idx;
1767
1768 writel(idx, &regs->RxMiniPrd);
1769 wmb();
1770
1771 out:
1772 clear_bit(0, &ap->mini_refill_busy);
1773 return;
1774 error_out:
1775 printk(KERN_INFO "Out of memory when allocating "
1776 "mini receive buffers\n");
1777 goto out;
1778 }
1779
1780
1781 /*
1782 * Load the jumbo rx ring, this may happen at any time if the MTU
1783 * is changed to a value > 1500.
1784 */
1785 static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1786 {
1787 struct ace_regs __iomem *regs = ap->regs;
1788 short i, idx;
1789
1790 idx = ap->rx_jumbo_skbprd;
1791
1792 for (i = 0; i < nr_bufs; i++) {
1793 struct sk_buff *skb;
1794 struct rx_desc *rd;
1795 dma_addr_t mapping;
1796
1797 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1798 if (!skb)
1799 break;
1800
1801 skb_reserve(skb, NET_IP_ALIGN);
1802 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1803 offset_in_page(skb->data),
1804 ACE_JUMBO_BUFSIZE,
1805 PCI_DMA_FROMDEVICE);
1806 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1807 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1808 mapping, mapping);
1809
1810 rd = &ap->rx_jumbo_ring[idx];
1811 set_aceaddr(&rd->addr, mapping);
1812 rd->size = ACE_JUMBO_BUFSIZE;
1813 rd->idx = idx;
1814 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1815 }
1816
1817 if (!i)
1818 goto error_out;
1819
1820 atomic_add(i, &ap->cur_jumbo_bufs);
1821 ap->rx_jumbo_skbprd = idx;
1822
1823 if (ACE_IS_TIGON_I(ap)) {
1824 struct cmd cmd;
1825 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1826 cmd.code = 0;
1827 cmd.idx = ap->rx_jumbo_skbprd;
1828 ace_issue_cmd(regs, &cmd);
1829 } else {
1830 writel(idx, &regs->RxJumboPrd);
1831 wmb();
1832 }
1833
1834 out:
1835 clear_bit(0, &ap->jumbo_refill_busy);
1836 return;
1837 error_out:
1838 if (net_ratelimit())
1839 printk(KERN_INFO "Out of memory when allocating "
1840 "jumbo receive buffers\n");
1841 goto out;
1842 }
1843
1844
1845 /*
1846 * All events are considered to be slow (RX/TX ints do not generate
1847 * events) and are handled here, outside the main interrupt handler,
1848 * to reduce the size of the handler.
1849 */
1850 static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1851 {
1852 struct ace_private *ap;
1853
1854 ap = netdev_priv(dev);
1855
1856 while (evtcsm != evtprd) {
1857 switch (ap->evt_ring[evtcsm].evt) {
1858 case E_FW_RUNNING:
1859 printk(KERN_INFO "%s: Firmware up and running\n",
1860 ap->name);
1861 ap->fw_running = 1;
1862 wmb();
1863 break;
1864 case E_STATS_UPDATED:
1865 break;
1866 case E_LNK_STATE:
1867 {
1868 u16 code = ap->evt_ring[evtcsm].code;
1869 switch (code) {
1870 case E_C_LINK_UP:
1871 {
1872 u32 state = readl(&ap->regs->GigLnkState);
1873 printk(KERN_WARNING "%s: Optical link UP "
1874 "(%s Duplex, Flow Control: %s%s)\n",
1875 ap->name,
1876 state & LNK_FULL_DUPLEX ? "Full":"Half",
1877 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1878 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1879 break;
1880 }
1881 case E_C_LINK_DOWN:
1882 printk(KERN_WARNING "%s: Optical link DOWN\n",
1883 ap->name);
1884 break;
1885 case E_C_LINK_10_100:
1886 printk(KERN_WARNING "%s: 10/100BaseT link "
1887 "UP\n", ap->name);
1888 break;
1889 default:
1890 printk(KERN_ERR "%s: Unknown optical link "
1891 "state %02x\n", ap->name, code);
1892 }
1893 break;
1894 }
1895 case E_ERROR:
1896 switch(ap->evt_ring[evtcsm].code) {
1897 case E_C_ERR_INVAL_CMD:
1898 printk(KERN_ERR "%s: invalid command error\n",
1899 ap->name);
1900 break;
1901 case E_C_ERR_UNIMP_CMD:
1902 printk(KERN_ERR "%s: unimplemented command "
1903 "error\n", ap->name);
1904 break;
1905 case E_C_ERR_BAD_CFG:
1906 printk(KERN_ERR "%s: bad config error\n",
1907 ap->name);
1908 break;
1909 default:
1910 printk(KERN_ERR "%s: unknown error %02x\n",
1911 ap->name, ap->evt_ring[evtcsm].code);
1912 }
1913 break;
1914 case E_RESET_JUMBO_RNG:
1915 {
1916 int i;
1917 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1918 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1919 ap->rx_jumbo_ring[i].size = 0;
1920 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1921 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1922 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1923 }
1924 }
1925
1926 if (ACE_IS_TIGON_I(ap)) {
1927 struct cmd cmd;
1928 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1929 cmd.code = 0;
1930 cmd.idx = 0;
1931 ace_issue_cmd(ap->regs, &cmd);
1932 } else {
1933 writel(0, &((ap->regs)->RxJumboPrd));
1934 wmb();
1935 }
1936
1937 ap->jumbo = 0;
1938 ap->rx_jumbo_skbprd = 0;
1939 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1940 ap->name);
1941 clear_bit(0, &ap->jumbo_refill_busy);
1942 break;
1943 }
1944 default:
1945 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1946 ap->name, ap->evt_ring[evtcsm].evt);
1947 }
1948 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1949 }
1950
1951 return evtcsm;
1952 }
1953
1954
1955 static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1956 {
1957 struct ace_private *ap = netdev_priv(dev);
1958 u32 idx;
1959 int mini_count = 0, std_count = 0;
1960
1961 idx = rxretcsm;
1962
1963 prefetchw(&ap->cur_rx_bufs);
1964 prefetchw(&ap->cur_mini_bufs);
1965
1966 while (idx != rxretprd) {
1967 struct ring_info *rip;
1968 struct sk_buff *skb;
1969 struct rx_desc *rxdesc, *retdesc;
1970 u32 skbidx;
1971 int bd_flags, desc_type, mapsize;
1972 u16 csum;
1973
1974
1975 /* make sure the rx descriptor isn't read before rxretprd */
1976 if (idx == rxretcsm)
1977 rmb();
1978
1979 retdesc = &ap->rx_return_ring[idx];
1980 skbidx = retdesc->idx;
1981 bd_flags = retdesc->flags;
1982 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1983
1984 switch(desc_type) {
1985 /*
1986 * Normal frames do not have any flags set
1987 *
1988 * Mini and normal frames arrive frequently,
1989 * so use a local counter to avoid doing
1990 * atomic operations for each packet arriving.
1991 */
1992 case 0:
1993 rip = &ap->skb->rx_std_skbuff[skbidx];
1994 mapsize = ACE_STD_BUFSIZE;
1995 rxdesc = &ap->rx_std_ring[skbidx];
1996 std_count++;
1997 break;
1998 case BD_FLG_JUMBO:
1999 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
2000 mapsize = ACE_JUMBO_BUFSIZE;
2001 rxdesc = &ap->rx_jumbo_ring[skbidx];
2002 atomic_dec(&ap->cur_jumbo_bufs);
2003 break;
2004 case BD_FLG_MINI:
2005 rip = &ap->skb->rx_mini_skbuff[skbidx];
2006 mapsize = ACE_MINI_BUFSIZE;
2007 rxdesc = &ap->rx_mini_ring[skbidx];
2008 mini_count++;
2009 break;
2010 default:
2011 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2012 "returned by NIC\n", dev->name,
2013 retdesc->flags);
2014 goto error;
2015 }
2016
2017 skb = rip->skb;
2018 rip->skb = NULL;
2019 pci_unmap_page(ap->pdev,
2020 pci_unmap_addr(rip, mapping),
2021 mapsize,
2022 PCI_DMA_FROMDEVICE);
2023 skb_put(skb, retdesc->size);
2024
2025 /*
2026 * Fly baby, fly!
2027 */
2028 csum = retdesc->tcp_udp_csum;
2029
2030 skb->dev = dev;
2031 skb->protocol = eth_type_trans(skb, dev);
2032
2033 /*
2034 * Instead of forcing the poor tigon mips cpu to calculate
2035 * pseudo hdr checksum, we do this ourselves.
2036 */
2037 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2038 skb->csum = htons(csum);
2039 skb->ip_summed = CHECKSUM_COMPLETE;
2040 } else {
2041 skb->ip_summed = CHECKSUM_NONE;
2042 }
2043
2044 /* send it up */
2045 #if ACENIC_DO_VLAN
2046 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2047 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2048 } else
2049 #endif
2050 netif_rx(skb);
2051
2052 dev->last_rx = jiffies;
2053 ap->stats.rx_packets++;
2054 ap->stats.rx_bytes += retdesc->size;
2055
2056 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2057 }
2058
2059 atomic_sub(std_count, &ap->cur_rx_bufs);
2060 if (!ACE_IS_TIGON_I(ap))
2061 atomic_sub(mini_count, &ap->cur_mini_bufs);
2062
2063 out:
2064 /*
2065 * According to the documentation RxRetCsm is obsolete with
2066 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2067 */
2068 if (ACE_IS_TIGON_I(ap)) {
2069 writel(idx, &ap->regs->RxRetCsm);
2070 }
2071 ap->cur_rx = idx;
2072
2073 return;
2074 error:
2075 idx = rxretprd;
2076 goto out;
2077 }
2078
2079
2080 static inline void ace_tx_int(struct net_device *dev,
2081 u32 txcsm, u32 idx)
2082 {
2083 struct ace_private *ap = netdev_priv(dev);
2084
2085 do {
2086 struct sk_buff *skb;
2087 dma_addr_t mapping;
2088 struct tx_ring_info *info;
2089
2090 info = ap->skb->tx_skbuff + idx;
2091 skb = info->skb;
2092 mapping = pci_unmap_addr(info, mapping);
2093
2094 if (mapping) {
2095 pci_unmap_page(ap->pdev, mapping,
2096 pci_unmap_len(info, maplen),
2097 PCI_DMA_TODEVICE);
2098 pci_unmap_addr_set(info, mapping, 0);
2099 }
2100
2101 if (skb) {
2102 ap->stats.tx_packets++;
2103 ap->stats.tx_bytes += skb->len;
2104 dev_kfree_skb_irq(skb);
2105 info->skb = NULL;
2106 }
2107
2108 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2109 } while (idx != txcsm);
2110
2111 if (netif_queue_stopped(dev))
2112 netif_wake_queue(dev);
2113
2114 wmb();
2115 ap->tx_ret_csm = txcsm;
2116
2117 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2118 *
2119 * We could try to make it before. In this case we would get
2120 * the following race condition: hard_start_xmit on other cpu
2121 * enters after we advanced tx_ret_csm and fills space,
2122 * which we have just freed, so that we make illegal device wakeup.
2123 * There is no good way to workaround this (at entry
2124 * to ace_start_xmit detects this condition and prevents
2125 * ring corruption, but it is not a good workaround.)
2126 *
2127 * When tx_ret_csm is advanced after, we wake up device _only_
2128 * if we really have some space in ring (though the core doing
2129 * hard_start_xmit can see full ring for some period and has to
2130 * synchronize.) Superb.
2131 * BUT! We get another subtle race condition. hard_start_xmit
2132 * may think that ring is full between wakeup and advancing
2133 * tx_ret_csm and will stop device instantly! It is not so bad.
2134 * We are guaranteed that there is something in ring, so that
2135 * the next irq will resume transmission. To speedup this we could
2136 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2137 * (see ace_start_xmit).
2138 *
2139 * Well, this dilemma exists in all lock-free devices.
2140 * We, following scheme used in drivers by Donald Becker,
2141 * select the least dangerous.
2142 * --ANK
2143 */
2144 }
2145
2146
2147 static irqreturn_t ace_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2148 {
2149 struct net_device *dev = (struct net_device *)dev_id;
2150 struct ace_private *ap = netdev_priv(dev);
2151 struct ace_regs __iomem *regs = ap->regs;
2152 u32 idx;
2153 u32 txcsm, rxretcsm, rxretprd;
2154 u32 evtcsm, evtprd;
2155
2156 /*
2157 * In case of PCI shared interrupts or spurious interrupts,
2158 * we want to make sure it is actually our interrupt before
2159 * spending any time in here.
2160 */
2161 if (!(readl(&regs->HostCtrl) & IN_INT))
2162 return IRQ_NONE;
2163
2164 /*
2165 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2166 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2167 * writel(0, &regs->Mb0Lo).
2168 *
2169 * "IRQ avoidance" recommended in docs applies to IRQs served
2170 * threads and it is wrong even for that case.
2171 */
2172 writel(0, &regs->Mb0Lo);
2173 readl(&regs->Mb0Lo);
2174
2175 /*
2176 * There is no conflict between transmit handling in
2177 * start_xmit and receive processing, thus there is no reason
2178 * to take a spin lock for RX handling. Wait until we start
2179 * working on the other stuff - hey we don't need a spin lock
2180 * anymore.
2181 */
2182 rxretprd = *ap->rx_ret_prd;
2183 rxretcsm = ap->cur_rx;
2184
2185 if (rxretprd != rxretcsm)
2186 ace_rx_int(dev, rxretprd, rxretcsm);
2187
2188 txcsm = *ap->tx_csm;
2189 idx = ap->tx_ret_csm;
2190
2191 if (txcsm != idx) {
2192 /*
2193 * If each skb takes only one descriptor this check degenerates
2194 * to identity, because new space has just been opened.
2195 * But if skbs are fragmented we must check that this index
2196 * update releases enough of space, otherwise we just
2197 * wait for device to make more work.
2198 */
2199 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2200 ace_tx_int(dev, txcsm, idx);
2201 }
2202
2203 evtcsm = readl(&regs->EvtCsm);
2204 evtprd = *ap->evt_prd;
2205
2206 if (evtcsm != evtprd) {
2207 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2208 writel(evtcsm, &regs->EvtCsm);
2209 }
2210
2211 /*
2212 * This has to go last in the interrupt handler and run with
2213 * the spin lock released ... what lock?
2214 */
2215 if (netif_running(dev)) {
2216 int cur_size;
2217 int run_tasklet = 0;
2218
2219 cur_size = atomic_read(&ap->cur_rx_bufs);
2220 if (cur_size < RX_LOW_STD_THRES) {
2221 if ((cur_size < RX_PANIC_STD_THRES) &&
2222 !test_and_set_bit(0, &ap->std_refill_busy)) {
2223 #ifdef DEBUG
2224 printk("low on std buffers %i\n", cur_size);
2225 #endif
2226 ace_load_std_rx_ring(ap,
2227 RX_RING_SIZE - cur_size);
2228 } else
2229 run_tasklet = 1;
2230 }
2231
2232 if (!ACE_IS_TIGON_I(ap)) {
2233 cur_size = atomic_read(&ap->cur_mini_bufs);
2234 if (cur_size < RX_LOW_MINI_THRES) {
2235 if ((cur_size < RX_PANIC_MINI_THRES) &&
2236 !test_and_set_bit(0,
2237 &ap->mini_refill_busy)) {
2238 #ifdef DEBUG
2239 printk("low on mini buffers %i\n",
2240 cur_size);
2241 #endif
2242 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2243 } else
2244 run_tasklet = 1;
2245 }
2246 }
2247
2248 if (ap->jumbo) {
2249 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2250 if (cur_size < RX_LOW_JUMBO_THRES) {
2251 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2252 !test_and_set_bit(0,
2253 &ap->jumbo_refill_busy)){
2254 #ifdef DEBUG
2255 printk("low on jumbo buffers %i\n",
2256 cur_size);
2257 #endif
2258 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2259 } else
2260 run_tasklet = 1;
2261 }
2262 }
2263 if (run_tasklet && !ap->tasklet_pending) {
2264 ap->tasklet_pending = 1;
2265 tasklet_schedule(&ap->ace_tasklet);
2266 }
2267 }
2268
2269 return IRQ_HANDLED;
2270 }
2271
2272
2273 #if ACENIC_DO_VLAN
2274 static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2275 {
2276 struct ace_private *ap = netdev_priv(dev);
2277 unsigned long flags;
2278
2279 local_irq_save(flags);
2280 ace_mask_irq(dev);
2281
2282 ap->vlgrp = grp;
2283
2284 ace_unmask_irq(dev);
2285 local_irq_restore(flags);
2286 }
2287
2288
2289 static void ace_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
2290 {
2291 struct ace_private *ap = netdev_priv(dev);
2292 unsigned long flags;
2293
2294 local_irq_save(flags);
2295 ace_mask_irq(dev);
2296
2297 if (ap->vlgrp)
2298 ap->vlgrp->vlan_devices[vid] = NULL;
2299
2300 ace_unmask_irq(dev);
2301 local_irq_restore(flags);
2302 }
2303 #endif /* ACENIC_DO_VLAN */
2304
2305
2306 static int ace_open(struct net_device *dev)
2307 {
2308 struct ace_private *ap = netdev_priv(dev);
2309 struct ace_regs __iomem *regs = ap->regs;
2310 struct cmd cmd;
2311
2312 if (!(ap->fw_running)) {
2313 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2314 return -EBUSY;
2315 }
2316
2317 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2318
2319 cmd.evt = C_CLEAR_STATS;
2320 cmd.code = 0;
2321 cmd.idx = 0;
2322 ace_issue_cmd(regs, &cmd);
2323
2324 cmd.evt = C_HOST_STATE;
2325 cmd.code = C_C_STACK_UP;
2326 cmd.idx = 0;
2327 ace_issue_cmd(regs, &cmd);
2328
2329 if (ap->jumbo &&
2330 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2331 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2332
2333 if (dev->flags & IFF_PROMISC) {
2334 cmd.evt = C_SET_PROMISC_MODE;
2335 cmd.code = C_C_PROMISC_ENABLE;
2336 cmd.idx = 0;
2337 ace_issue_cmd(regs, &cmd);
2338
2339 ap->promisc = 1;
2340 }else
2341 ap->promisc = 0;
2342 ap->mcast_all = 0;
2343
2344 #if 0
2345 cmd.evt = C_LNK_NEGOTIATION;
2346 cmd.code = 0;
2347 cmd.idx = 0;
2348 ace_issue_cmd(regs, &cmd);
2349 #endif
2350
2351 netif_start_queue(dev);
2352
2353 /*
2354 * Setup the bottom half rx ring refill handler
2355 */
2356 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2357 return 0;
2358 }
2359
2360
2361 static int ace_close(struct net_device *dev)
2362 {
2363 struct ace_private *ap = netdev_priv(dev);
2364 struct ace_regs __iomem *regs = ap->regs;
2365 struct cmd cmd;
2366 unsigned long flags;
2367 short i;
2368
2369 /*
2370 * Without (or before) releasing irq and stopping hardware, this
2371 * is an absolute non-sense, by the way. It will be reset instantly
2372 * by the first irq.
2373 */
2374 netif_stop_queue(dev);
2375
2376
2377 if (ap->promisc) {
2378 cmd.evt = C_SET_PROMISC_MODE;
2379 cmd.code = C_C_PROMISC_DISABLE;
2380 cmd.idx = 0;
2381 ace_issue_cmd(regs, &cmd);
2382 ap->promisc = 0;
2383 }
2384
2385 cmd.evt = C_HOST_STATE;
2386 cmd.code = C_C_STACK_DOWN;
2387 cmd.idx = 0;
2388 ace_issue_cmd(regs, &cmd);
2389
2390 tasklet_kill(&ap->ace_tasklet);
2391
2392 /*
2393 * Make sure one CPU is not processing packets while
2394 * buffers are being released by another.
2395 */
2396
2397 local_irq_save(flags);
2398 ace_mask_irq(dev);
2399
2400 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2401 struct sk_buff *skb;
2402 dma_addr_t mapping;
2403 struct tx_ring_info *info;
2404
2405 info = ap->skb->tx_skbuff + i;
2406 skb = info->skb;
2407 mapping = pci_unmap_addr(info, mapping);
2408
2409 if (mapping) {
2410 if (ACE_IS_TIGON_I(ap)) {
2411 struct tx_desc __iomem *tx
2412 = (struct tx_desc __iomem *) &ap->tx_ring[i];
2413 writel(0, &tx->addr.addrhi);
2414 writel(0, &tx->addr.addrlo);
2415 writel(0, &tx->flagsize);
2416 } else
2417 memset(ap->tx_ring + i, 0,
2418 sizeof(struct tx_desc));
2419 pci_unmap_page(ap->pdev, mapping,
2420 pci_unmap_len(info, maplen),
2421 PCI_DMA_TODEVICE);
2422 pci_unmap_addr_set(info, mapping, 0);
2423 }
2424 if (skb) {
2425 dev_kfree_skb(skb);
2426 info->skb = NULL;
2427 }
2428 }
2429
2430 if (ap->jumbo) {
2431 cmd.evt = C_RESET_JUMBO_RNG;
2432 cmd.code = 0;
2433 cmd.idx = 0;
2434 ace_issue_cmd(regs, &cmd);
2435 }
2436
2437 ace_unmask_irq(dev);
2438 local_irq_restore(flags);
2439
2440 return 0;
2441 }
2442
2443
2444 static inline dma_addr_t
2445 ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2446 struct sk_buff *tail, u32 idx)
2447 {
2448 dma_addr_t mapping;
2449 struct tx_ring_info *info;
2450
2451 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2452 offset_in_page(skb->data),
2453 skb->len, PCI_DMA_TODEVICE);
2454
2455 info = ap->skb->tx_skbuff + idx;
2456 info->skb = tail;
2457 pci_unmap_addr_set(info, mapping, mapping);
2458 pci_unmap_len_set(info, maplen, skb->len);
2459 return mapping;
2460 }
2461
2462
2463 static inline void
2464 ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2465 u32 flagsize, u32 vlan_tag)
2466 {
2467 #if !USE_TX_COAL_NOW
2468 flagsize &= ~BD_FLG_COAL_NOW;
2469 #endif
2470
2471 if (ACE_IS_TIGON_I(ap)) {
2472 struct tx_desc __iomem *io = (struct tx_desc __iomem *) desc;
2473 writel(addr >> 32, &io->addr.addrhi);
2474 writel(addr & 0xffffffff, &io->addr.addrlo);
2475 writel(flagsize, &io->flagsize);
2476 #if ACENIC_DO_VLAN
2477 writel(vlan_tag, &io->vlanres);
2478 #endif
2479 } else {
2480 desc->addr.addrhi = addr >> 32;
2481 desc->addr.addrlo = addr;
2482 desc->flagsize = flagsize;
2483 #if ACENIC_DO_VLAN
2484 desc->vlanres = vlan_tag;
2485 #endif
2486 }
2487 }
2488
2489
2490 static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2491 {
2492 struct ace_private *ap = netdev_priv(dev);
2493 struct ace_regs __iomem *regs = ap->regs;
2494 struct tx_desc *desc;
2495 u32 idx, flagsize;
2496 unsigned long maxjiff = jiffies + 3*HZ;
2497
2498 restart:
2499 idx = ap->tx_prd;
2500
2501 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2502 goto overflow;
2503
2504 if (!skb_shinfo(skb)->nr_frags) {
2505 dma_addr_t mapping;
2506 u32 vlan_tag = 0;
2507
2508 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2509 flagsize = (skb->len << 16) | (BD_FLG_END);
2510 if (skb->ip_summed == CHECKSUM_PARTIAL)
2511 flagsize |= BD_FLG_TCP_UDP_SUM;
2512 #if ACENIC_DO_VLAN
2513 if (vlan_tx_tag_present(skb)) {
2514 flagsize |= BD_FLG_VLAN_TAG;
2515 vlan_tag = vlan_tx_tag_get(skb);
2516 }
2517 #endif
2518 desc = ap->tx_ring + idx;
2519 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2520
2521 /* Look at ace_tx_int for explanations. */
2522 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2523 flagsize |= BD_FLG_COAL_NOW;
2524
2525 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2526 } else {
2527 dma_addr_t mapping;
2528 u32 vlan_tag = 0;
2529 int i, len = 0;
2530
2531 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2532 flagsize = (skb_headlen(skb) << 16);
2533 if (skb->ip_summed == CHECKSUM_PARTIAL)
2534 flagsize |= BD_FLG_TCP_UDP_SUM;
2535 #if ACENIC_DO_VLAN
2536 if (vlan_tx_tag_present(skb)) {
2537 flagsize |= BD_FLG_VLAN_TAG;
2538 vlan_tag = vlan_tx_tag_get(skb);
2539 }
2540 #endif
2541
2542 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2543
2544 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2545
2546 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2547 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2548 struct tx_ring_info *info;
2549
2550 len += frag->size;
2551 info = ap->skb->tx_skbuff + idx;
2552 desc = ap->tx_ring + idx;
2553
2554 mapping = pci_map_page(ap->pdev, frag->page,
2555 frag->page_offset, frag->size,
2556 PCI_DMA_TODEVICE);
2557
2558 flagsize = (frag->size << 16);
2559 if (skb->ip_summed == CHECKSUM_PARTIAL)
2560 flagsize |= BD_FLG_TCP_UDP_SUM;
2561 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2562
2563 if (i == skb_shinfo(skb)->nr_frags - 1) {
2564 flagsize |= BD_FLG_END;
2565 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2566 flagsize |= BD_FLG_COAL_NOW;
2567
2568 /*
2569 * Only the last fragment frees
2570 * the skb!
2571 */
2572 info->skb = skb;
2573 } else {
2574 info->skb = NULL;
2575 }
2576 pci_unmap_addr_set(info, mapping, mapping);
2577 pci_unmap_len_set(info, maplen, frag->size);
2578 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2579 }
2580 }
2581
2582 wmb();
2583 ap->tx_prd = idx;
2584 ace_set_txprd(regs, ap, idx);
2585
2586 if (flagsize & BD_FLG_COAL_NOW) {
2587 netif_stop_queue(dev);
2588
2589 /*
2590 * A TX-descriptor producer (an IRQ) might have gotten
2591 * inbetween, making the ring free again. Since xmit is
2592 * serialized, this is the only situation we have to
2593 * re-test.
2594 */
2595 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2596 netif_wake_queue(dev);
2597 }
2598
2599 dev->trans_start = jiffies;
2600 return NETDEV_TX_OK;
2601
2602 overflow:
2603 /*
2604 * This race condition is unavoidable with lock-free drivers.
2605 * We wake up the queue _before_ tx_prd is advanced, so that we can
2606 * enter hard_start_xmit too early, while tx ring still looks closed.
2607 * This happens ~1-4 times per 100000 packets, so that we can allow
2608 * to loop syncing to other CPU. Probably, we need an additional
2609 * wmb() in ace_tx_intr as well.
2610 *
2611 * Note that this race is relieved by reserving one more entry
2612 * in tx ring than it is necessary (see original non-SG driver).
2613 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2614 * is already overkill.
2615 *
2616 * Alternative is to return with 1 not throttling queue. In this
2617 * case loop becomes longer, no more useful effects.
2618 */
2619 if (time_before(jiffies, maxjiff)) {
2620 barrier();
2621 cpu_relax();
2622 goto restart;
2623 }
2624
2625 /* The ring is stuck full. */
2626 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2627 return NETDEV_TX_BUSY;
2628 }
2629
2630
2631 static int ace_change_mtu(struct net_device *dev, int new_mtu)
2632 {
2633 struct ace_private *ap = netdev_priv(dev);
2634 struct ace_regs __iomem *regs = ap->regs;
2635
2636 if (new_mtu > ACE_JUMBO_MTU)
2637 return -EINVAL;
2638
2639 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2640 dev->mtu = new_mtu;
2641
2642 if (new_mtu > ACE_STD_MTU) {
2643 if (!(ap->jumbo)) {
2644 printk(KERN_INFO "%s: Enabling Jumbo frame "
2645 "support\n", dev->name);
2646 ap->jumbo = 1;
2647 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2648 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2649 ace_set_rxtx_parms(dev, 1);
2650 }
2651 } else {
2652 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2653 ace_sync_irq(dev->irq);
2654 ace_set_rxtx_parms(dev, 0);
2655 if (ap->jumbo) {
2656 struct cmd cmd;
2657
2658 cmd.evt = C_RESET_JUMBO_RNG;
2659 cmd.code = 0;
2660 cmd.idx = 0;
2661 ace_issue_cmd(regs, &cmd);
2662 }
2663 }
2664
2665 return 0;
2666 }
2667
2668 static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2669 {
2670 struct ace_private *ap = netdev_priv(dev);
2671 struct ace_regs __iomem *regs = ap->regs;
2672 u32 link;
2673
2674 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2675 ecmd->supported =
2676 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2677 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2678 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2679 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2680
2681 ecmd->port = PORT_FIBRE;
2682 ecmd->transceiver = XCVR_INTERNAL;
2683
2684 link = readl(&regs->GigLnkState);
2685 if (link & LNK_1000MB)
2686 ecmd->speed = SPEED_1000;
2687 else {
2688 link = readl(&regs->FastLnkState);
2689 if (link & LNK_100MB)
2690 ecmd->speed = SPEED_100;
2691 else if (link & LNK_10MB)
2692 ecmd->speed = SPEED_10;
2693 else
2694 ecmd->speed = 0;
2695 }
2696 if (link & LNK_FULL_DUPLEX)
2697 ecmd->duplex = DUPLEX_FULL;
2698 else
2699 ecmd->duplex = DUPLEX_HALF;
2700
2701 if (link & LNK_NEGOTIATE)
2702 ecmd->autoneg = AUTONEG_ENABLE;
2703 else
2704 ecmd->autoneg = AUTONEG_DISABLE;
2705
2706 #if 0
2707 /*
2708 * Current struct ethtool_cmd is insufficient
2709 */
2710 ecmd->trace = readl(&regs->TuneTrace);
2711
2712 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2713 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2714 #endif
2715 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2716 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2717
2718 return 0;
2719 }
2720
2721 static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2722 {
2723 struct ace_private *ap = netdev_priv(dev);
2724 struct ace_regs __iomem *regs = ap->regs;
2725 u32 link, speed;
2726
2727 link = readl(&regs->GigLnkState);
2728 if (link & LNK_1000MB)
2729 speed = SPEED_1000;
2730 else {
2731 link = readl(&regs->FastLnkState);
2732 if (link & LNK_100MB)
2733 speed = SPEED_100;
2734 else if (link & LNK_10MB)
2735 speed = SPEED_10;
2736 else
2737 speed = SPEED_100;
2738 }
2739
2740 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2741 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2742 if (!ACE_IS_TIGON_I(ap))
2743 link |= LNK_TX_FLOW_CTL_Y;
2744 if (ecmd->autoneg == AUTONEG_ENABLE)
2745 link |= LNK_NEGOTIATE;
2746 if (ecmd->speed != speed) {
2747 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2748 switch (speed) {
2749 case SPEED_1000:
2750 link |= LNK_1000MB;
2751 break;
2752 case SPEED_100:
2753 link |= LNK_100MB;
2754 break;
2755 case SPEED_10:
2756 link |= LNK_10MB;
2757 break;
2758 }
2759 }
2760
2761 if (ecmd->duplex == DUPLEX_FULL)
2762 link |= LNK_FULL_DUPLEX;
2763
2764 if (link != ap->link) {
2765 struct cmd cmd;
2766 printk(KERN_INFO "%s: Renegotiating link state\n",
2767 dev->name);
2768
2769 ap->link = link;
2770 writel(link, &regs->TuneLink);
2771 if (!ACE_IS_TIGON_I(ap))
2772 writel(link, &regs->TuneFastLink);
2773 wmb();
2774
2775 cmd.evt = C_LNK_NEGOTIATION;
2776 cmd.code = 0;
2777 cmd.idx = 0;
2778 ace_issue_cmd(regs, &cmd);
2779 }
2780 return 0;
2781 }
2782
2783 static void ace_get_drvinfo(struct net_device *dev,
2784 struct ethtool_drvinfo *info)
2785 {
2786 struct ace_private *ap = netdev_priv(dev);
2787
2788 strlcpy(info->driver, "acenic", sizeof(info->driver));
2789 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
2790 tigonFwReleaseMajor, tigonFwReleaseMinor,
2791 tigonFwReleaseFix);
2792
2793 if (ap->pdev)
2794 strlcpy(info->bus_info, pci_name(ap->pdev),
2795 sizeof(info->bus_info));
2796
2797 }
2798
2799 /*
2800 * Set the hardware MAC address.
2801 */
2802 static int ace_set_mac_addr(struct net_device *dev, void *p)
2803 {
2804 struct ace_private *ap = netdev_priv(dev);
2805 struct ace_regs __iomem *regs = ap->regs;
2806 struct sockaddr *addr=p;
2807 u8 *da;
2808 struct cmd cmd;
2809
2810 if(netif_running(dev))
2811 return -EBUSY;
2812
2813 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2814
2815 da = (u8 *)dev->dev_addr;
2816
2817 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2818 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2819 &regs->MacAddrLo);
2820
2821 cmd.evt = C_SET_MAC_ADDR;
2822 cmd.code = 0;
2823 cmd.idx = 0;
2824 ace_issue_cmd(regs, &cmd);
2825
2826 return 0;
2827 }
2828
2829
2830 static void ace_set_multicast_list(struct net_device *dev)
2831 {
2832 struct ace_private *ap = netdev_priv(dev);
2833 struct ace_regs __iomem *regs = ap->regs;
2834 struct cmd cmd;
2835
2836 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2837 cmd.evt = C_SET_MULTICAST_MODE;
2838 cmd.code = C_C_MCAST_ENABLE;
2839 cmd.idx = 0;
2840 ace_issue_cmd(regs, &cmd);
2841 ap->mcast_all = 1;
2842 } else if (ap->mcast_all) {
2843 cmd.evt = C_SET_MULTICAST_MODE;
2844 cmd.code = C_C_MCAST_DISABLE;
2845 cmd.idx = 0;
2846 ace_issue_cmd(regs, &cmd);
2847 ap->mcast_all = 0;
2848 }
2849
2850 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2851 cmd.evt = C_SET_PROMISC_MODE;
2852 cmd.code = C_C_PROMISC_ENABLE;
2853 cmd.idx = 0;
2854 ace_issue_cmd(regs, &cmd);
2855 ap->promisc = 1;
2856 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2857 cmd.evt = C_SET_PROMISC_MODE;
2858 cmd.code = C_C_PROMISC_DISABLE;
2859 cmd.idx = 0;
2860 ace_issue_cmd(regs, &cmd);
2861 ap->promisc = 0;
2862 }
2863
2864 /*
2865 * For the time being multicast relies on the upper layers
2866 * filtering it properly. The Firmware does not allow one to
2867 * set the entire multicast list at a time and keeping track of
2868 * it here is going to be messy.
2869 */
2870 if ((dev->mc_count) && !(ap->mcast_all)) {
2871 cmd.evt = C_SET_MULTICAST_MODE;
2872 cmd.code = C_C_MCAST_ENABLE;
2873 cmd.idx = 0;
2874 ace_issue_cmd(regs, &cmd);
2875 }else if (!ap->mcast_all) {
2876 cmd.evt = C_SET_MULTICAST_MODE;
2877 cmd.code = C_C_MCAST_DISABLE;
2878 cmd.idx = 0;
2879 ace_issue_cmd(regs, &cmd);
2880 }
2881 }
2882
2883
2884 static struct net_device_stats *ace_get_stats(struct net_device *dev)
2885 {
2886 struct ace_private *ap = netdev_priv(dev);
2887 struct ace_mac_stats __iomem *mac_stats =
2888 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2889
2890 ap->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2891 ap->stats.multicast = readl(&mac_stats->kept_mc);
2892 ap->stats.collisions = readl(&mac_stats->coll);
2893
2894 return &ap->stats;
2895 }
2896
2897
2898 static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
2899 u32 dest, int size)
2900 {
2901 void __iomem *tdest;
2902 u32 *wsrc;
2903 short tsize, i;
2904
2905 if (size <= 0)
2906 return;
2907
2908 while (size > 0) {
2909 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2910 min_t(u32, size, ACE_WINDOW_SIZE));
2911 tdest = (void __iomem *) &regs->Window +
2912 (dest & (ACE_WINDOW_SIZE - 1));
2913 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2914 /*
2915 * This requires byte swapping on big endian, however
2916 * writel does that for us
2917 */
2918 wsrc = src;
2919 for (i = 0; i < (tsize / 4); i++) {
2920 writel(wsrc[i], tdest + i*4);
2921 }
2922 dest += tsize;
2923 src += tsize;
2924 size -= tsize;
2925 }
2926
2927 return;
2928 }
2929
2930
2931 static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2932 {
2933 void __iomem *tdest;
2934 short tsize = 0, i;
2935
2936 if (size <= 0)
2937 return;
2938
2939 while (size > 0) {
2940 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2941 min_t(u32, size, ACE_WINDOW_SIZE));
2942 tdest = (void __iomem *) &regs->Window +
2943 (dest & (ACE_WINDOW_SIZE - 1));
2944 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2945
2946 for (i = 0; i < (tsize / 4); i++) {
2947 writel(0, tdest + i*4);
2948 }
2949
2950 dest += tsize;
2951 size -= tsize;
2952 }
2953
2954 return;
2955 }
2956
2957
2958 /*
2959 * Download the firmware into the SRAM on the NIC
2960 *
2961 * This operation requires the NIC to be halted and is performed with
2962 * interrupts disabled and with the spinlock hold.
2963 */
2964 int __devinit ace_load_firmware(struct net_device *dev)
2965 {
2966 struct ace_private *ap = netdev_priv(dev);
2967 struct ace_regs __iomem *regs = ap->regs;
2968
2969 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2970 printk(KERN_ERR "%s: trying to download firmware while the "
2971 "CPU is running!\n", ap->name);
2972 return -EFAULT;
2973 }
2974
2975 /*
2976 * Do not try to clear more than 512KB or we end up seeing
2977 * funny things on NICs with only 512KB SRAM
2978 */
2979 ace_clear(regs, 0x2000, 0x80000-0x2000);
2980 if (ACE_IS_TIGON_I(ap)) {
2981 ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
2982 ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
2983 ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
2984 tigonFwRodataLen);
2985 ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
2986 ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
2987 }else if (ap->version == 2) {
2988 ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
2989 ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
2990 ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
2991 ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
2992 tigon2FwRodataLen);
2993 ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
2994 }
2995
2996 return 0;
2997 }
2998
2999
3000 /*
3001 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
3002 *
3003 * Accessing the EEPROM is `interesting' to say the least - don't read
3004 * this code right after dinner.
3005 *
3006 * This is all about black magic and bit-banging the device .... I
3007 * wonder in what hospital they have put the guy who designed the i2c
3008 * specs.
3009 *
3010 * Oh yes, this is only the beginning!
3011 *
3012 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
3013 * code i2c readout code by beta testing all my hacks.
3014 */
3015 static void __devinit eeprom_start(struct ace_regs __iomem *regs)
3016 {
3017 u32 local;
3018
3019 readl(&regs->LocalCtrl);
3020 udelay(ACE_SHORT_DELAY);
3021 local = readl(&regs->LocalCtrl);
3022 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3023 writel(local, &regs->LocalCtrl);
3024 readl(&regs->LocalCtrl);
3025 mb();
3026 udelay(ACE_SHORT_DELAY);
3027 local |= EEPROM_CLK_OUT;
3028 writel(local, &regs->LocalCtrl);
3029 readl(&regs->LocalCtrl);
3030 mb();
3031 udelay(ACE_SHORT_DELAY);
3032 local &= ~EEPROM_DATA_OUT;
3033 writel(local, &regs->LocalCtrl);
3034 readl(&regs->LocalCtrl);
3035 mb();
3036 udelay(ACE_SHORT_DELAY);
3037 local &= ~EEPROM_CLK_OUT;
3038 writel(local, &regs->LocalCtrl);
3039 readl(&regs->LocalCtrl);
3040 mb();
3041 }
3042
3043
3044 static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3045 {
3046 short i;
3047 u32 local;
3048
3049 udelay(ACE_SHORT_DELAY);
3050 local = readl(&regs->LocalCtrl);
3051 local &= ~EEPROM_DATA_OUT;
3052 local |= EEPROM_WRITE_ENABLE;
3053 writel(local, &regs->LocalCtrl);
3054 readl(&regs->LocalCtrl);
3055 mb();
3056
3057 for (i = 0; i < 8; i++, magic <<= 1) {
3058 udelay(ACE_SHORT_DELAY);
3059 if (magic & 0x80)
3060 local |= EEPROM_DATA_OUT;
3061 else
3062 local &= ~EEPROM_DATA_OUT;
3063 writel(local, &regs->LocalCtrl);
3064 readl(&regs->LocalCtrl);
3065 mb();
3066
3067 udelay(ACE_SHORT_DELAY);
3068 local |= EEPROM_CLK_OUT;
3069 writel(local, &regs->LocalCtrl);
3070 readl(&regs->LocalCtrl);
3071 mb();
3072 udelay(ACE_SHORT_DELAY);
3073 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3074 writel(local, &regs->LocalCtrl);
3075 readl(&regs->LocalCtrl);
3076 mb();
3077 }
3078 }
3079
3080
3081 static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3082 {
3083 int state;
3084 u32 local;
3085
3086 local = readl(&regs->LocalCtrl);
3087 local &= ~EEPROM_WRITE_ENABLE;
3088 writel(local, &regs->LocalCtrl);
3089 readl(&regs->LocalCtrl);
3090 mb();
3091 udelay(ACE_LONG_DELAY);
3092 local |= EEPROM_CLK_OUT;
3093 writel(local, &regs->LocalCtrl);
3094 readl(&regs->LocalCtrl);
3095 mb();
3096 udelay(ACE_SHORT_DELAY);
3097 /* sample data in middle of high clk */
3098 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3099 udelay(ACE_SHORT_DELAY);
3100 mb();
3101 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3102 readl(&regs->LocalCtrl);
3103 mb();
3104
3105 return state;
3106 }
3107
3108
3109 static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3110 {
3111 u32 local;
3112
3113 udelay(ACE_SHORT_DELAY);
3114 local = readl(&regs->LocalCtrl);
3115 local |= EEPROM_WRITE_ENABLE;
3116 writel(local, &regs->LocalCtrl);
3117 readl(&regs->LocalCtrl);
3118 mb();
3119 udelay(ACE_SHORT_DELAY);
3120 local &= ~EEPROM_DATA_OUT;
3121 writel(local, &regs->LocalCtrl);
3122 readl(&regs->LocalCtrl);
3123 mb();
3124 udelay(ACE_SHORT_DELAY);
3125 local |= EEPROM_CLK_OUT;
3126 writel(local, &regs->LocalCtrl);
3127 readl(&regs->LocalCtrl);
3128 mb();
3129 udelay(ACE_SHORT_DELAY);
3130 local |= EEPROM_DATA_OUT;
3131 writel(local, &regs->LocalCtrl);
3132 readl(&regs->LocalCtrl);
3133 mb();
3134 udelay(ACE_LONG_DELAY);
3135 local &= ~EEPROM_CLK_OUT;
3136 writel(local, &regs->LocalCtrl);
3137 mb();
3138 }
3139
3140
3141 /*
3142 * Read a whole byte from the EEPROM.
3143 */
3144 static int __devinit read_eeprom_byte(struct net_device *dev,
3145 unsigned long offset)
3146 {
3147 struct ace_private *ap = netdev_priv(dev);
3148 struct ace_regs __iomem *regs = ap->regs;
3149 unsigned long flags;
3150 u32 local;
3151 int result = 0;
3152 short i;
3153
3154 if (!dev) {
3155 printk(KERN_ERR "No device!\n");
3156 result = -ENODEV;
3157 goto out;
3158 }
3159
3160 /*
3161 * Don't take interrupts on this CPU will bit banging
3162 * the %#%#@$ I2C device
3163 */
3164 local_irq_save(flags);
3165
3166 eeprom_start(regs);
3167
3168 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3169 if (eeprom_check_ack(regs)) {
3170 local_irq_restore(flags);
3171 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3172 result = -EIO;
3173 goto eeprom_read_error;
3174 }
3175
3176 eeprom_prep(regs, (offset >> 8) & 0xff);
3177 if (eeprom_check_ack(regs)) {
3178 local_irq_restore(flags);
3179 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3180 ap->name);
3181 result = -EIO;
3182 goto eeprom_read_error;
3183 }
3184
3185 eeprom_prep(regs, offset & 0xff);
3186 if (eeprom_check_ack(regs)) {
3187 local_irq_restore(flags);
3188 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3189 ap->name);
3190 result = -EIO;
3191 goto eeprom_read_error;
3192 }
3193
3194 eeprom_start(regs);
3195 eeprom_prep(regs, EEPROM_READ_SELECT);
3196 if (eeprom_check_ack(regs)) {
3197 local_irq_restore(flags);
3198 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3199 ap->name);
3200 result = -EIO;
3201 goto eeprom_read_error;
3202 }
3203
3204 for (i = 0; i < 8; i++) {
3205 local = readl(&regs->LocalCtrl);
3206 local &= ~EEPROM_WRITE_ENABLE;
3207 writel(local, &regs->LocalCtrl);
3208 readl(&regs->LocalCtrl);
3209 udelay(ACE_LONG_DELAY);
3210 mb();
3211 local |= EEPROM_CLK_OUT;
3212 writel(local, &regs->LocalCtrl);
3213 readl(&regs->LocalCtrl);
3214 mb();
3215 udelay(ACE_SHORT_DELAY);
3216 /* sample data mid high clk */
3217 result = (result << 1) |
3218 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3219 udelay(ACE_SHORT_DELAY);
3220 mb();
3221 local = readl(&regs->LocalCtrl);
3222 local &= ~EEPROM_CLK_OUT;
3223 writel(local, &regs->LocalCtrl);
3224 readl(&regs->LocalCtrl);
3225 udelay(ACE_SHORT_DELAY);
3226 mb();
3227 if (i == 7) {
3228 local |= EEPROM_WRITE_ENABLE;
3229 writel(local, &regs->LocalCtrl);
3230 readl(&regs->LocalCtrl);
3231 mb();
3232 udelay(ACE_SHORT_DELAY);
3233 }
3234 }
3235
3236 local |= EEPROM_DATA_OUT;
3237 writel(local, &regs->LocalCtrl);
3238 readl(&regs->LocalCtrl);
3239 mb();
3240 udelay(ACE_SHORT_DELAY);
3241 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3242 readl(&regs->LocalCtrl);
3243 udelay(ACE_LONG_DELAY);
3244 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3245 readl(&regs->LocalCtrl);
3246 mb();
3247 udelay(ACE_SHORT_DELAY);
3248 eeprom_stop(regs);
3249
3250 local_irq_restore(flags);
3251 out:
3252 return result;
3253
3254 eeprom_read_error:
3255 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3256 ap->name, offset);
3257 goto out;
3258 }
3259
3260
3261 /*
3262 * Local variables:
3263 * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h -c -o acenic.o acenic.c"
3264 * End:
3265 */