2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
4 * Copyright (C) 2003 SAN People (Pty) Ltd
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/config.h>
23 #include <linux/mii.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/ethtool.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
33 #include <asm/uaccess.h>
34 #include <asm/mach-types.h>
36 #include <asm/arch/at91rm9200_emac.h>
37 #include <asm/arch/gpio.h>
38 #include <asm/arch/board.h>
40 #include "at91_ether.h"
42 #define DRV_NAME "at91_ether"
43 #define DRV_VERSION "1.0"
45 static struct net_device
*at91_dev
;
47 static struct timer_list check_timer
;
48 #define LINK_POLL_INTERVAL (HZ)
50 /* ..................................................................... */
53 * Read from a EMAC register.
55 static inline unsigned long at91_emac_read(unsigned int reg
)
57 void __iomem
*emac_base
= (void __iomem
*)AT91_VA_BASE_EMAC
;
59 return __raw_readl(emac_base
+ reg
);
63 * Write to a EMAC register.
65 static inline void at91_emac_write(unsigned int reg
, unsigned long value
)
67 void __iomem
*emac_base
= (void __iomem
*)AT91_VA_BASE_EMAC
;
69 __raw_writel(value
, emac_base
+ reg
);
72 /* ........................... PHY INTERFACE ........................... */
75 * Enable the MDIO bit in MAC control register
76 * When not called from an interrupt-handler, access to the PHY must be
77 * protected by a spinlock.
79 static void enable_mdi(void)
83 ctl
= at91_emac_read(AT91_EMAC_CTL
);
84 at91_emac_write(AT91_EMAC_CTL
, ctl
| AT91_EMAC_MPE
); /* enable management port */
88 * Disable the MDIO bit in the MAC control register
90 static void disable_mdi(void)
94 ctl
= at91_emac_read(AT91_EMAC_CTL
);
95 at91_emac_write(AT91_EMAC_CTL
, ctl
& ~AT91_EMAC_MPE
); /* disable management port */
99 * Wait until the PHY operation is complete.
101 static inline void at91_phy_wait(void) {
102 unsigned long timeout
= jiffies
+ 2;
104 while (!(at91_emac_read(AT91_EMAC_SR
) & AT91_EMAC_SR_IDLE
)) {
105 if (time_after(jiffies
, timeout
)) {
106 printk("at91_ether: MIO timeout\n");
114 * Write value to the a PHY register
115 * Note: MDI interface is assumed to already have been enabled.
117 static void write_phy(unsigned char phy_addr
, unsigned char address
, unsigned int value
)
119 at91_emac_write(AT91_EMAC_MAN
, AT91_EMAC_MAN_802_3
| AT91_EMAC_RW_W
120 | ((phy_addr
& 0x1f) << 23) | (address
<< 18) | (value
& AT91_EMAC_DATA
));
122 /* Wait until IDLE bit in Network Status register is cleared */
127 * Read value stored in a PHY register.
128 * Note: MDI interface is assumed to already have been enabled.
130 static void read_phy(unsigned char phy_addr
, unsigned char address
, unsigned int *value
)
132 at91_emac_write(AT91_EMAC_MAN
, AT91_EMAC_MAN_802_3
| AT91_EMAC_RW_R
133 | ((phy_addr
& 0x1f) << 23) | (address
<< 18));
135 /* Wait until IDLE bit in Network Status register is cleared */
138 *value
= at91_emac_read(AT91_EMAC_MAN
) & AT91_EMAC_DATA
;
141 /* ........................... PHY MANAGEMENT .......................... */
144 * Access the PHY to determine the current link speed and mode, and update the
146 * If no link or auto-negotiation is busy, then no changes are made.
148 static void update_linkspeed(struct net_device
*dev
, int silent
)
150 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
151 unsigned int bmsr
, bmcr
, lpa
, mac_cfg
;
152 unsigned int speed
, duplex
;
154 if (!mii_link_ok(&lp
->mii
)) { /* no link */
155 netif_carrier_off(dev
);
157 printk(KERN_INFO
"%s: Link down.\n", dev
->name
);
161 /* Link up, or auto-negotiation still in progress */
162 read_phy(lp
->phy_address
, MII_BMSR
, &bmsr
);
163 read_phy(lp
->phy_address
, MII_BMCR
, &bmcr
);
164 if (bmcr
& BMCR_ANENABLE
) { /* AutoNegotiation is enabled */
165 if (!(bmsr
& BMSR_ANEGCOMPLETE
))
166 return; /* Do nothing - another interrupt generated when negotiation complete */
168 read_phy(lp
->phy_address
, MII_LPA
, &lpa
);
169 if ((lpa
& LPA_100FULL
) || (lpa
& LPA_100HALF
)) speed
= SPEED_100
;
170 else speed
= SPEED_10
;
171 if ((lpa
& LPA_100FULL
) || (lpa
& LPA_10FULL
)) duplex
= DUPLEX_FULL
;
172 else duplex
= DUPLEX_HALF
;
174 speed
= (bmcr
& BMCR_SPEED100
) ? SPEED_100
: SPEED_10
;
175 duplex
= (bmcr
& BMCR_FULLDPLX
) ? DUPLEX_FULL
: DUPLEX_HALF
;
179 mac_cfg
= at91_emac_read(AT91_EMAC_CFG
) & ~(AT91_EMAC_SPD
| AT91_EMAC_FD
);
180 if (speed
== SPEED_100
) {
181 if (duplex
== DUPLEX_FULL
) /* 100 Full Duplex */
182 mac_cfg
|= AT91_EMAC_SPD
| AT91_EMAC_FD
;
183 else /* 100 Half Duplex */
184 mac_cfg
|= AT91_EMAC_SPD
;
186 if (duplex
== DUPLEX_FULL
) /* 10 Full Duplex */
187 mac_cfg
|= AT91_EMAC_FD
;
188 else {} /* 10 Half Duplex */
190 at91_emac_write(AT91_EMAC_CFG
, mac_cfg
);
193 printk(KERN_INFO
"%s: Link now %i-%s\n", dev
->name
, speed
, (duplex
== DUPLEX_FULL
) ? "FullDuplex" : "HalfDuplex");
194 netif_carrier_on(dev
);
198 * Handle interrupts from the PHY
200 static irqreturn_t
at91ether_phy_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
202 struct net_device
*dev
= (struct net_device
*) dev_id
;
203 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
207 * This hander is triggered on both edges, but the PHY chips expect
208 * level-triggering. We therefore have to check if the PHY actually has
212 if ((lp
->phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
)) {
213 read_phy(lp
->phy_address
, MII_DSINTR_REG
, &phy
); /* ack interrupt in Davicom PHY */
214 if (!(phy
& (1 << 0)))
217 else if (lp
->phy_type
== MII_LXT971A_ID
) {
218 read_phy(lp
->phy_address
, MII_ISINTS_REG
, &phy
); /* ack interrupt in Intel PHY */
219 if (!(phy
& (1 << 2)))
222 else if (lp
->phy_type
== MII_BCM5221_ID
) {
223 read_phy(lp
->phy_address
, MII_BCMINTR_REG
, &phy
); /* ack interrupt in Broadcom PHY */
224 if (!(phy
& (1 << 0)))
227 else if (lp
->phy_type
== MII_KS8721_ID
) {
228 read_phy(lp
->phy_address
, MII_TPISTATUS
, &phy
); /* ack interrupt in Micrel PHY */
229 if (!(phy
& ((1 << 2) | 1)))
233 update_linkspeed(dev
, 0);
242 * Initialize and enable the PHY interrupt for link-state changes
244 static void enable_phyirq(struct net_device
*dev
)
246 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
247 unsigned int dsintr
, irq_number
;
250 irq_number
= lp
->board_data
.phy_irq_pin
;
253 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
254 * or board does not have it connected.
256 check_timer
.expires
= jiffies
+ LINK_POLL_INTERVAL
;
257 add_timer(&check_timer
);
261 status
= request_irq(irq_number
, at91ether_phy_interrupt
, 0, dev
->name
, dev
);
263 printk(KERN_ERR
"at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number
, status
);
267 spin_lock_irq(&lp
->lock
);
270 if ((lp
->phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
)) { /* for Davicom PHY */
271 read_phy(lp
->phy_address
, MII_DSINTR_REG
, &dsintr
);
272 dsintr
= dsintr
& ~0xf00; /* clear bits 8..11 */
273 write_phy(lp
->phy_address
, MII_DSINTR_REG
, dsintr
);
275 else if (lp
->phy_type
== MII_LXT971A_ID
) { /* for Intel PHY */
276 read_phy(lp
->phy_address
, MII_ISINTE_REG
, &dsintr
);
277 dsintr
= dsintr
| 0xf2; /* set bits 1, 4..7 */
278 write_phy(lp
->phy_address
, MII_ISINTE_REG
, dsintr
);
280 else if (lp
->phy_type
== MII_BCM5221_ID
) { /* for Broadcom PHY */
281 dsintr
= (1 << 15) | ( 1 << 14);
282 write_phy(lp
->phy_address
, MII_BCMINTR_REG
, dsintr
);
284 else if (lp
->phy_type
== MII_KS8721_ID
) { /* for Micrel PHY */
285 dsintr
= (1 << 10) | ( 1 << 8);
286 write_phy(lp
->phy_address
, MII_TPISTATUS
, dsintr
);
290 spin_unlock_irq(&lp
->lock
);
294 * Disable the PHY interrupt
296 static void disable_phyirq(struct net_device
*dev
)
298 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
300 unsigned int irq_number
;
302 irq_number
= lp
->board_data
.phy_irq_pin
;
304 del_timer_sync(&check_timer
);
308 spin_lock_irq(&lp
->lock
);
311 if ((lp
->phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
)) { /* for Davicom PHY */
312 read_phy(lp
->phy_address
, MII_DSINTR_REG
, &dsintr
);
313 dsintr
= dsintr
| 0xf00; /* set bits 8..11 */
314 write_phy(lp
->phy_address
, MII_DSINTR_REG
, dsintr
);
316 else if (lp
->phy_type
== MII_LXT971A_ID
) { /* for Intel PHY */
317 read_phy(lp
->phy_address
, MII_ISINTE_REG
, &dsintr
);
318 dsintr
= dsintr
& ~0xf2; /* clear bits 1, 4..7 */
319 write_phy(lp
->phy_address
, MII_ISINTE_REG
, dsintr
);
321 else if (lp
->phy_type
== MII_BCM5221_ID
) { /* for Broadcom PHY */
322 read_phy(lp
->phy_address
, MII_BCMINTR_REG
, &dsintr
);
324 write_phy(lp
->phy_address
, MII_BCMINTR_REG
, dsintr
);
326 else if (lp
->phy_type
== MII_KS8721_ID
) { /* for Micrel PHY */
327 read_phy(lp
->phy_address
, MII_TPISTATUS
, &dsintr
);
328 dsintr
= ~((1 << 10) | (1 << 8));
329 write_phy(lp
->phy_address
, MII_TPISTATUS
, dsintr
);
333 spin_unlock_irq(&lp
->lock
);
335 free_irq(irq_number
, dev
); /* Free interrupt handler */
339 * Perform a software reset of the PHY.
342 static void reset_phy(struct net_device
*dev
)
344 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
347 spin_lock_irq(&lp
->lock
);
350 /* Perform PHY reset */
351 write_phy(lp
->phy_address
, MII_BMCR
, BMCR_RESET
);
353 /* Wait until PHY reset is complete */
355 read_phy(lp
->phy_address
, MII_BMCR
, &bmcr
);
356 } while (!(bmcr
&& BMCR_RESET
));
359 spin_unlock_irq(&lp
->lock
);
363 static void at91ether_check_link(unsigned long dev_id
)
365 struct net_device
*dev
= (struct net_device
*) dev_id
;
368 update_linkspeed(dev
, 1);
371 check_timer
.expires
= jiffies
+ LINK_POLL_INTERVAL
;
372 add_timer(&check_timer
);
375 /* ......................... ADDRESS MANAGEMENT ........................ */
378 * NOTE: Your bootloader must always set the MAC address correctly before
379 * booting into Linux.
381 * - It must always set the MAC address after reset, even if it doesn't
382 * happen to access the Ethernet while it's booting. Some versions of
383 * U-Boot on the AT91RM9200-DK do not do this.
385 * - Likewise it must store the addresses in the correct byte order.
386 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
387 * continues to do so, for bug-compatibility).
390 static short __init
unpack_mac_address(struct net_device
*dev
, unsigned int hi
, unsigned int lo
)
394 if (machine_is_csb337()) {
395 addr
[5] = (lo
& 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
396 addr
[4] = (lo
& 0xff00) >> 8;
397 addr
[3] = (lo
& 0xff0000) >> 16;
398 addr
[2] = (lo
& 0xff000000) >> 24;
399 addr
[1] = (hi
& 0xff);
400 addr
[0] = (hi
& 0xff00) >> 8;
403 addr
[0] = (lo
& 0xff);
404 addr
[1] = (lo
& 0xff00) >> 8;
405 addr
[2] = (lo
& 0xff0000) >> 16;
406 addr
[3] = (lo
& 0xff000000) >> 24;
407 addr
[4] = (hi
& 0xff);
408 addr
[5] = (hi
& 0xff00) >> 8;
411 if (is_valid_ether_addr(addr
)) {
412 memcpy(dev
->dev_addr
, &addr
, 6);
419 * Set the ethernet MAC address in dev->dev_addr
421 static void __init
get_mac_address(struct net_device
*dev
)
423 /* Check Specific-Address 1 */
424 if (unpack_mac_address(dev
, at91_emac_read(AT91_EMAC_SA1H
), at91_emac_read(AT91_EMAC_SA1L
)))
426 /* Check Specific-Address 2 */
427 if (unpack_mac_address(dev
, at91_emac_read(AT91_EMAC_SA2H
), at91_emac_read(AT91_EMAC_SA2L
)))
429 /* Check Specific-Address 3 */
430 if (unpack_mac_address(dev
, at91_emac_read(AT91_EMAC_SA3H
), at91_emac_read(AT91_EMAC_SA3L
)))
432 /* Check Specific-Address 4 */
433 if (unpack_mac_address(dev
, at91_emac_read(AT91_EMAC_SA4H
), at91_emac_read(AT91_EMAC_SA4L
)))
436 printk(KERN_ERR
"at91_ether: Your bootloader did not configure a MAC address.\n");
440 * Program the hardware MAC address from dev->dev_addr.
442 static void update_mac_address(struct net_device
*dev
)
444 at91_emac_write(AT91_EMAC_SA1L
, (dev
->dev_addr
[3] << 24) | (dev
->dev_addr
[2] << 16) | (dev
->dev_addr
[1] << 8) | (dev
->dev_addr
[0]));
445 at91_emac_write(AT91_EMAC_SA1H
, (dev
->dev_addr
[5] << 8) | (dev
->dev_addr
[4]));
447 at91_emac_write(AT91_EMAC_SA2L
, 0);
448 at91_emac_write(AT91_EMAC_SA2H
, 0);
452 * Store the new hardware address in dev->dev_addr, and update the MAC.
454 static int set_mac_address(struct net_device
*dev
, void* addr
)
456 struct sockaddr
*address
= addr
;
458 if (!is_valid_ether_addr(address
->sa_data
))
459 return -EADDRNOTAVAIL
;
461 memcpy(dev
->dev_addr
, address
->sa_data
, dev
->addr_len
);
462 update_mac_address(dev
);
464 printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", dev
->name
,
465 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
466 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
471 static int inline hash_bit_value(int bitnr
, __u8
*addr
)
473 if (addr
[bitnr
/ 8] & (1 << (bitnr
% 8)))
479 * The hash address register is 64 bits long and takes up two locations in the memory map.
480 * The least significant bits are stored in EMAC_HSL and the most significant
483 * The unicast hash enable and the multicast hash enable bits in the network configuration
484 * register enable the reception of hash matched frames. The destination address is
485 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
486 * The hash function is an exclusive or of every sixth bit of the destination address.
487 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
488 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
489 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
490 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
491 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
492 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
493 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
494 * unicast indicator, and da[47] represents the most significant bit of the last byte
496 * If the hash index points to a bit that is set in the hash register then the frame will be
497 * matched according to whether the frame is multicast or unicast.
498 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
499 * the hash index points to a bit set in the hash register.
500 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
501 * hash index points to a bit set in the hash register.
502 * To receive all multicast frames, the hash register should be set with all ones and the
503 * multicast hash enable bit should be set in the network configuration register.
507 * Return the hash index value for the specified address.
509 static int hash_get_index(__u8
*addr
)
514 for (j
= 0; j
< 6; j
++) {
515 for (i
= 0, bitval
= 0; i
< 8; i
++)
516 bitval
^= hash_bit_value(i
*6 + j
, addr
);
518 hash_index
|= (bitval
<< j
);
525 * Add multicast addresses to the internal multicast-hash table.
527 static void at91ether_sethashtable(struct net_device
*dev
)
529 struct dev_mc_list
*curr
;
530 unsigned long mc_filter
[2];
531 unsigned int i
, bitnr
;
533 mc_filter
[0] = mc_filter
[1] = 0;
536 for (i
= 0; i
< dev
->mc_count
; i
++, curr
= curr
->next
) {
537 if (!curr
) break; /* unexpected end of list */
539 bitnr
= hash_get_index(curr
->dmi_addr
);
540 mc_filter
[bitnr
>> 5] |= 1 << (bitnr
& 31);
543 at91_emac_write(AT91_EMAC_HSH
, mc_filter
[0]);
544 at91_emac_write(AT91_EMAC_HSL
, mc_filter
[1]);
548 * Enable/Disable promiscuous and multicast modes.
550 static void at91ether_set_rx_mode(struct net_device
*dev
)
554 cfg
= at91_emac_read(AT91_EMAC_CFG
);
556 if (dev
->flags
& IFF_PROMISC
) /* Enable promiscuous mode */
557 cfg
|= AT91_EMAC_CAF
;
558 else if (dev
->flags
& (~IFF_PROMISC
)) /* Disable promiscuous mode */
559 cfg
&= ~AT91_EMAC_CAF
;
561 if (dev
->flags
& IFF_ALLMULTI
) { /* Enable all multicast mode */
562 at91_emac_write(AT91_EMAC_HSH
, -1);
563 at91_emac_write(AT91_EMAC_HSL
, -1);
564 cfg
|= AT91_EMAC_MTI
;
565 } else if (dev
->mc_count
> 0) { /* Enable specific multicasts */
566 at91ether_sethashtable(dev
);
567 cfg
|= AT91_EMAC_MTI
;
568 } else if (dev
->flags
& (~IFF_ALLMULTI
)) { /* Disable all multicast mode */
569 at91_emac_write(AT91_EMAC_HSH
, 0);
570 at91_emac_write(AT91_EMAC_HSL
, 0);
571 cfg
&= ~AT91_EMAC_MTI
;
574 at91_emac_write(AT91_EMAC_CFG
, cfg
);
577 /* ......................... ETHTOOL SUPPORT ........................... */
579 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
)
583 read_phy(phy_id
, location
, &value
);
587 static void mdio_write(struct net_device
*dev
, int phy_id
, int location
, int value
)
589 write_phy(phy_id
, location
, value
);
592 static int at91ether_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
594 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
597 spin_lock_irq(&lp
->lock
);
600 ret
= mii_ethtool_gset(&lp
->mii
, cmd
);
603 spin_unlock_irq(&lp
->lock
);
605 if (lp
->phy_media
== PORT_FIBRE
) { /* override media type since mii.c doesn't know */
606 cmd
->supported
= SUPPORTED_FIBRE
;
607 cmd
->port
= PORT_FIBRE
;
613 static int at91ether_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
615 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
618 spin_lock_irq(&lp
->lock
);
621 ret
= mii_ethtool_sset(&lp
->mii
, cmd
);
624 spin_unlock_irq(&lp
->lock
);
629 static int at91ether_nwayreset(struct net_device
*dev
)
631 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
634 spin_lock_irq(&lp
->lock
);
637 ret
= mii_nway_restart(&lp
->mii
);
640 spin_unlock_irq(&lp
->lock
);
645 static void at91ether_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
647 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
648 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
649 strlcpy(info
->bus_info
, dev
->class_dev
.dev
->bus_id
, sizeof(info
->bus_info
));
652 static struct ethtool_ops at91ether_ethtool_ops
= {
653 .get_settings
= at91ether_get_settings
,
654 .set_settings
= at91ether_set_settings
,
655 .get_drvinfo
= at91ether_get_drvinfo
,
656 .nway_reset
= at91ether_nwayreset
,
657 .get_link
= ethtool_op_get_link
,
660 static int at91ether_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
662 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
665 if (!netif_running(dev
))
668 spin_lock_irq(&lp
->lock
);
670 res
= generic_mii_ioctl(&lp
->mii
, if_mii(rq
), cmd
, NULL
);
672 spin_unlock_irq(&lp
->lock
);
677 /* ................................ MAC ................................ */
680 * Initialize and start the Receiver and Transmit subsystems
682 static void at91ether_start(struct net_device
*dev
)
684 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
685 struct recv_desc_bufs
*dlist
, *dlist_phys
;
690 dlist_phys
= lp
->dlist_phys
;
692 for (i
= 0; i
< MAX_RX_DESCR
; i
++) {
693 dlist
->descriptors
[i
].addr
= (unsigned int) &dlist_phys
->recv_buf
[i
][0];
694 dlist
->descriptors
[i
].size
= 0;
697 /* Set the Wrap bit on the last descriptor */
698 dlist
->descriptors
[i
-1].addr
|= EMAC_DESC_WRAP
;
700 /* Reset buffer index */
703 /* Program address of descriptor list in Rx Buffer Queue register */
704 at91_emac_write(AT91_EMAC_RBQP
, (unsigned long) dlist_phys
);
706 /* Enable Receive and Transmit */
707 ctl
= at91_emac_read(AT91_EMAC_CTL
);
708 at91_emac_write(AT91_EMAC_CTL
, ctl
| AT91_EMAC_RE
| AT91_EMAC_TE
);
712 * Open the ethernet interface
714 static int at91ether_open(struct net_device
*dev
)
716 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
719 if (!is_valid_ether_addr(dev
->dev_addr
))
720 return -EADDRNOTAVAIL
;
722 clk_enable(lp
->ether_clk
); /* Re-enable Peripheral clock */
724 /* Clear internal statistics */
725 ctl
= at91_emac_read(AT91_EMAC_CTL
);
726 at91_emac_write(AT91_EMAC_CTL
, ctl
| AT91_EMAC_CSR
);
728 /* Update the MAC address (incase user has changed it) */
729 update_mac_address(dev
);
731 /* Enable PHY interrupt */
734 /* Enable MAC interrupts */
735 at91_emac_write(AT91_EMAC_IER
, AT91_EMAC_RCOM
| AT91_EMAC_RBNA
736 | AT91_EMAC_TUND
| AT91_EMAC_RTRY
| AT91_EMAC_TCOM
737 | AT91_EMAC_ROVR
| AT91_EMAC_ABT
);
739 /* Determine current link speed */
740 spin_lock_irq(&lp
->lock
);
742 update_linkspeed(dev
, 0);
744 spin_unlock_irq(&lp
->lock
);
746 at91ether_start(dev
);
747 netif_start_queue(dev
);
752 * Close the interface
754 static int at91ether_close(struct net_device
*dev
)
756 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
759 /* Disable Receiver and Transmitter */
760 ctl
= at91_emac_read(AT91_EMAC_CTL
);
761 at91_emac_write(AT91_EMAC_CTL
, ctl
& ~(AT91_EMAC_TE
| AT91_EMAC_RE
));
763 /* Disable PHY interrupt */
766 /* Disable MAC interrupts */
767 at91_emac_write(AT91_EMAC_IDR
, AT91_EMAC_RCOM
| AT91_EMAC_RBNA
768 | AT91_EMAC_TUND
| AT91_EMAC_RTRY
| AT91_EMAC_TCOM
769 | AT91_EMAC_ROVR
| AT91_EMAC_ABT
);
771 netif_stop_queue(dev
);
773 clk_disable(lp
->ether_clk
); /* Disable Peripheral clock */
781 static int at91ether_tx(struct sk_buff
*skb
, struct net_device
*dev
)
783 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
785 if (at91_emac_read(AT91_EMAC_TSR
) & AT91_EMAC_TSR_BNQ
) {
786 netif_stop_queue(dev
);
788 /* Store packet information (to free when Tx completed) */
790 lp
->skb_length
= skb
->len
;
791 lp
->skb_physaddr
= dma_map_single(NULL
, skb
->data
, skb
->len
, DMA_TO_DEVICE
);
792 lp
->stats
.tx_bytes
+= skb
->len
;
794 /* Set address of the data in the Transmit Address register */
795 at91_emac_write(AT91_EMAC_TAR
, lp
->skb_physaddr
);
796 /* Set length of the packet in the Transmit Control register */
797 at91_emac_write(AT91_EMAC_TCR
, skb
->len
);
799 dev
->trans_start
= jiffies
;
801 printk(KERN_ERR
"at91_ether.c: at91ether_tx() called, but device is busy!\n");
802 return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
803 on this skb, he also reports -ENETDOWN and printk's, so either
804 we free and return(0) or don't free and return 1 */
811 * Update the current statistics from the internal statistics registers.
813 static struct net_device_stats
*at91ether_stats(struct net_device
*dev
)
815 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
816 int ale
, lenerr
, seqe
, lcol
, ecol
;
818 if (netif_running(dev
)) {
819 lp
->stats
.rx_packets
+= at91_emac_read(AT91_EMAC_OK
); /* Good frames received */
820 ale
= at91_emac_read(AT91_EMAC_ALE
);
821 lp
->stats
.rx_frame_errors
+= ale
; /* Alignment errors */
822 lenerr
= at91_emac_read(AT91_EMAC_ELR
) + at91_emac_read(AT91_EMAC_USF
);
823 lp
->stats
.rx_length_errors
+= lenerr
; /* Excessive Length or Undersize Frame error */
824 seqe
= at91_emac_read(AT91_EMAC_SEQE
);
825 lp
->stats
.rx_crc_errors
+= seqe
; /* CRC error */
826 lp
->stats
.rx_fifo_errors
+= at91_emac_read(AT91_EMAC_DRFC
); /* Receive buffer not available */
827 lp
->stats
.rx_errors
+= (ale
+ lenerr
+ seqe
828 + at91_emac_read(AT91_EMAC_CDE
) + at91_emac_read(AT91_EMAC_RJB
));
830 lp
->stats
.tx_packets
+= at91_emac_read(AT91_EMAC_FRA
); /* Frames successfully transmitted */
831 lp
->stats
.tx_fifo_errors
+= at91_emac_read(AT91_EMAC_TUE
); /* Transmit FIFO underruns */
832 lp
->stats
.tx_carrier_errors
+= at91_emac_read(AT91_EMAC_CSE
); /* Carrier Sense errors */
833 lp
->stats
.tx_heartbeat_errors
+= at91_emac_read(AT91_EMAC_SQEE
);/* Heartbeat error */
835 lcol
= at91_emac_read(AT91_EMAC_LCOL
);
836 ecol
= at91_emac_read(AT91_EMAC_ECOL
);
837 lp
->stats
.tx_window_errors
+= lcol
; /* Late collisions */
838 lp
->stats
.tx_aborted_errors
+= ecol
; /* 16 collisions */
840 lp
->stats
.collisions
+= (at91_emac_read(AT91_EMAC_SCOL
) + at91_emac_read(AT91_EMAC_MCOL
) + lcol
+ ecol
);
846 * Extract received frame from buffer descriptors and sent to upper layers.
847 * (Called from interrupt context)
849 static void at91ether_rx(struct net_device
*dev
)
851 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
852 struct recv_desc_bufs
*dlist
;
853 unsigned char *p_recv
;
858 while (dlist
->descriptors
[lp
->rxBuffIndex
].addr
& EMAC_DESC_DONE
) {
859 p_recv
= dlist
->recv_buf
[lp
->rxBuffIndex
];
860 pktlen
= dlist
->descriptors
[lp
->rxBuffIndex
].size
& 0x7ff; /* Length of frame including FCS */
861 skb
= alloc_skb(pktlen
+ 2, GFP_ATOMIC
);
864 memcpy(skb_put(skb
, pktlen
), p_recv
, pktlen
);
867 skb
->protocol
= eth_type_trans(skb
, dev
);
869 dev
->last_rx
= jiffies
;
870 lp
->stats
.rx_bytes
+= pktlen
;
874 lp
->stats
.rx_dropped
+= 1;
875 printk(KERN_NOTICE
"%s: Memory squeeze, dropping packet.\n", dev
->name
);
878 if (dlist
->descriptors
[lp
->rxBuffIndex
].size
& EMAC_MULTICAST
)
879 lp
->stats
.multicast
++;
881 dlist
->descriptors
[lp
->rxBuffIndex
].addr
&= ~EMAC_DESC_DONE
; /* reset ownership bit */
882 if (lp
->rxBuffIndex
== MAX_RX_DESCR
-1) /* wrap after last buffer */
890 * MAC interrupt handler
892 static irqreturn_t
at91ether_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
894 struct net_device
*dev
= (struct net_device
*) dev_id
;
895 struct at91_private
*lp
= (struct at91_private
*) dev
->priv
;
896 unsigned long intstatus
, ctl
;
898 /* MAC Interrupt Status register indicates what interrupts are pending.
899 It is automatically cleared once read. */
900 intstatus
= at91_emac_read(AT91_EMAC_ISR
);
902 if (intstatus
& AT91_EMAC_RCOM
) /* Receive complete */
905 if (intstatus
& AT91_EMAC_TCOM
) { /* Transmit complete */
906 /* The TCOM bit is set even if the transmission failed. */
907 if (intstatus
& (AT91_EMAC_TUND
| AT91_EMAC_RTRY
))
908 lp
->stats
.tx_errors
+= 1;
911 dev_kfree_skb_irq(lp
->skb
);
913 dma_unmap_single(NULL
, lp
->skb_physaddr
, lp
->skb_length
, DMA_TO_DEVICE
);
915 netif_wake_queue(dev
);
918 /* Work-around for Errata #11 */
919 if (intstatus
& AT91_EMAC_RBNA
) {
920 ctl
= at91_emac_read(AT91_EMAC_CTL
);
921 at91_emac_write(AT91_EMAC_CTL
, ctl
& ~AT91_EMAC_RE
);
922 at91_emac_write(AT91_EMAC_CTL
, ctl
| AT91_EMAC_RE
);
925 if (intstatus
& AT91_EMAC_ROVR
)
926 printk("%s: ROVR error\n", dev
->name
);
932 * Initialize the ethernet interface
934 static int __init
at91ether_setup(unsigned long phy_type
, unsigned short phy_address
,
935 struct platform_device
*pdev
, struct clk
*ether_clk
)
937 struct at91_eth_data
*board_data
= pdev
->dev
.platform_data
;
938 struct net_device
*dev
;
939 struct at91_private
*lp
;
943 if (at91_dev
) /* already initialized */
946 dev
= alloc_etherdev(sizeof(struct at91_private
));
950 dev
->base_addr
= AT91_VA_BASE_EMAC
;
951 dev
->irq
= AT91_ID_EMAC
;
952 SET_MODULE_OWNER(dev
);
954 /* Install the interrupt handler */
955 if (request_irq(dev
->irq
, at91ether_interrupt
, 0, dev
->name
, dev
)) {
960 /* Allocate memory for DMA Receive descriptors */
961 lp
= (struct at91_private
*)dev
->priv
;
962 lp
->dlist
= (struct recv_desc_bufs
*) dma_alloc_coherent(NULL
, sizeof(struct recv_desc_bufs
), (dma_addr_t
*) &lp
->dlist_phys
, GFP_KERNEL
);
963 if (lp
->dlist
== NULL
) {
964 free_irq(dev
->irq
, dev
);
968 lp
->board_data
= *board_data
;
969 lp
->ether_clk
= ether_clk
;
970 platform_set_drvdata(pdev
, dev
);
972 spin_lock_init(&lp
->lock
);
975 dev
->open
= at91ether_open
;
976 dev
->stop
= at91ether_close
;
977 dev
->hard_start_xmit
= at91ether_tx
;
978 dev
->get_stats
= at91ether_stats
;
979 dev
->set_multicast_list
= at91ether_set_rx_mode
;
980 dev
->set_mac_address
= set_mac_address
;
981 dev
->ethtool_ops
= &at91ether_ethtool_ops
;
982 dev
->do_ioctl
= at91ether_ioctl
;
984 SET_NETDEV_DEV(dev
, &pdev
->dev
);
986 get_mac_address(dev
); /* Get ethernet address and store it in dev->dev_addr */
987 update_mac_address(dev
); /* Program ethernet address into MAC */
989 at91_emac_write(AT91_EMAC_CTL
, 0);
991 if (lp
->board_data
.is_rmii
)
992 at91_emac_write(AT91_EMAC_CFG
, AT91_EMAC_CLK_DIV32
| AT91_EMAC_BIG
| AT91_EMAC_RMII
);
994 at91_emac_write(AT91_EMAC_CFG
, AT91_EMAC_CLK_DIV32
| AT91_EMAC_BIG
);
996 /* Perform PHY-specific initialization */
997 spin_lock_irq(&lp
->lock
);
999 if ((phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
)) {
1000 read_phy(phy_address
, MII_DSCR_REG
, &val
);
1001 if ((val
& (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
1002 lp
->phy_media
= PORT_FIBRE
;
1003 } else if (machine_is_csb337()) {
1004 /* mix link activity status into LED2 link state */
1005 write_phy(phy_address
, MII_LEDCTRL_REG
, 0x0d22);
1008 spin_unlock_irq(&lp
->lock
);
1010 lp
->mii
.dev
= dev
; /* Support for ethtool */
1011 lp
->mii
.mdio_read
= mdio_read
;
1012 lp
->mii
.mdio_write
= mdio_write
;
1013 lp
->mii
.phy_id
= phy_address
;
1014 lp
->mii
.phy_id_mask
= 0x1f;
1015 lp
->mii
.reg_num_mask
= 0x1f;
1017 lp
->phy_type
= phy_type
; /* Type of PHY connected */
1018 lp
->phy_address
= phy_address
; /* MDI address of PHY */
1020 /* Register the network interface */
1021 res
= register_netdev(dev
);
1023 free_irq(dev
->irq
, dev
);
1025 dma_free_coherent(NULL
, sizeof(struct recv_desc_bufs
), lp
->dlist
, (dma_addr_t
)lp
->dlist_phys
);
1030 /* Determine current link speed */
1031 spin_lock_irq(&lp
->lock
);
1033 update_linkspeed(dev
, 0);
1035 spin_unlock_irq(&lp
->lock
);
1036 netif_carrier_off(dev
); /* will be enabled in open() */
1038 /* If board has no PHY IRQ, use a timer to poll the PHY */
1039 if (!lp
->board_data
.phy_irq_pin
) {
1040 init_timer(&check_timer
);
1041 check_timer
.data
= (unsigned long)dev
;
1042 check_timer
.function
= at91ether_check_link
;
1045 /* Display ethernet banner */
1046 printk(KERN_INFO
"%s: AT91 ethernet at 0x%08x int=%d %s%s (%02x:%02x:%02x:%02x:%02x:%02x)\n",
1047 dev
->name
, (uint
) dev
->base_addr
, dev
->irq
,
1048 at91_emac_read(AT91_EMAC_CFG
) & AT91_EMAC_SPD
? "100-" : "10-",
1049 at91_emac_read(AT91_EMAC_CFG
) & AT91_EMAC_FD
? "FullDuplex" : "HalfDuplex",
1050 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
1051 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
1052 if ((phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
))
1053 printk(KERN_INFO
"%s: Davicom 9161 PHY %s\n", dev
->name
, (lp
->phy_media
== PORT_FIBRE
) ? "(Fiber)" : "(Copper)");
1054 else if (phy_type
== MII_LXT971A_ID
)
1055 printk(KERN_INFO
"%s: Intel LXT971A PHY\n", dev
->name
);
1056 else if (phy_type
== MII_RTL8201_ID
)
1057 printk(KERN_INFO
"%s: Realtek RTL8201(B)L PHY\n", dev
->name
);
1058 else if (phy_type
== MII_BCM5221_ID
)
1059 printk(KERN_INFO
"%s: Broadcom BCM5221 PHY\n", dev
->name
);
1060 else if (phy_type
== MII_DP83847_ID
)
1061 printk(KERN_INFO
"%s: National Semiconductor DP83847 PHY\n", dev
->name
);
1062 else if (phy_type
== MII_AC101L_ID
)
1063 printk(KERN_INFO
"%s: Altima AC101L PHY\n", dev
->name
);
1064 else if (phy_type
== MII_KS8721_ID
)
1065 printk(KERN_INFO
"%s: Micrel KS8721 PHY\n", dev
->name
);
1071 * Detect MAC and PHY and perform initialization
1073 static int __init
at91ether_probe(struct platform_device
*pdev
)
1075 unsigned int phyid1
, phyid2
;
1077 unsigned long phy_id
;
1078 unsigned short phy_address
= 0;
1079 struct clk
*ether_clk
;
1081 ether_clk
= clk_get(&pdev
->dev
, "ether_clk");
1082 if (IS_ERR(ether_clk
)) {
1083 printk(KERN_ERR
"at91_ether: no clock defined\n");
1086 clk_enable(ether_clk
); /* Enable Peripheral clock */
1088 while ((detected
!= 0) && (phy_address
< 32)) {
1089 /* Read the PHY ID registers */
1091 read_phy(phy_address
, MII_PHYSID1
, &phyid1
);
1092 read_phy(phy_address
, MII_PHYSID2
, &phyid2
);
1095 phy_id
= (phyid1
<< 16) | (phyid2
& 0xfff0);
1097 case MII_DM9161_ID
: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1098 case MII_DM9161A_ID
: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1099 case MII_LXT971A_ID
: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1100 case MII_RTL8201_ID
: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1101 case MII_BCM5221_ID
: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1102 case MII_DP83847_ID
: /* National Semiconductor DP83847: */
1103 case MII_AC101L_ID
: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1104 case MII_KS8721_ID
: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1105 detected
= at91ether_setup(phy_id
, phy_address
, pdev
, ether_clk
);
1112 clk_disable(ether_clk
); /* Disable Peripheral clock */
1117 static int __devexit
at91ether_remove(struct platform_device
*pdev
)
1119 struct at91_private
*lp
= (struct at91_private
*) at91_dev
->priv
;
1121 unregister_netdev(at91_dev
);
1122 free_irq(at91_dev
->irq
, at91_dev
);
1123 dma_free_coherent(NULL
, sizeof(struct recv_desc_bufs
), lp
->dlist
, (dma_addr_t
)lp
->dlist_phys
);
1124 clk_put(lp
->ether_clk
);
1126 free_netdev(at91_dev
);
1133 static int at91ether_suspend(struct platform_device
*pdev
, pm_message_t mesg
)
1135 struct at91_private
*lp
= (struct at91_private
*) at91_dev
->priv
;
1136 struct net_device
*net_dev
= platform_get_drvdata(pdev
);
1137 int phy_irq
= lp
->board_data
.phy_irq_pin
;
1139 if (netif_running(net_dev
)) {
1141 disable_irq(phy_irq
);
1143 netif_stop_queue(net_dev
);
1144 netif_device_detach(net_dev
);
1146 clk_disable(lp
->ether_clk
);
1151 static int at91ether_resume(struct platform_device
*pdev
)
1153 struct at91_private
*lp
= (struct at91_private
*) at91_dev
->priv
;
1154 struct net_device
*net_dev
= platform_get_drvdata(pdev
);
1155 int phy_irq
= lp
->board_data
.phy_irq_pin
;
1157 if (netif_running(net_dev
)) {
1158 clk_enable(lp
->ether_clk
);
1160 netif_device_attach(net_dev
);
1161 netif_start_queue(net_dev
);
1164 enable_irq(phy_irq
);
1170 #define at91ether_suspend NULL
1171 #define at91ether_resume NULL
1174 static struct platform_driver at91ether_driver
= {
1175 .probe
= at91ether_probe
,
1176 .remove
= __devexit_p(at91ether_remove
),
1177 .suspend
= at91ether_suspend
,
1178 .resume
= at91ether_resume
,
1181 .owner
= THIS_MODULE
,
1185 static int __init
at91ether_init(void)
1187 return platform_driver_register(&at91ether_driver
);
1190 static void __exit
at91ether_exit(void)
1192 platform_driver_unregister(&at91ether_driver
);
1195 module_init(at91ether_init
)
1196 module_exit(at91ether_exit
)
1198 MODULE_LICENSE("GPL");
1199 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1200 MODULE_AUTHOR("Andrew Victor");