2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/dma-mapping.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/mii.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/init.h>
20 #include <linux/moduleparam.h>
21 #include <linux/platform_device.h>
22 #include <linux/delay.h>
23 #include <asm/arch/ep93xx-regs.h>
24 #include <asm/arch/platform.h>
27 #define DRV_MODULE_NAME "ep93xx-eth"
28 #define DRV_MODULE_VERSION "0.1"
30 #define RX_QUEUE_ENTRIES 64
31 #define TX_QUEUE_ENTRIES 8
33 #define MAX_PKT_SIZE 2044
34 #define PKT_BUF_SIZE 2048
36 #define REG_RXCTL 0x0000
37 #define REG_RXCTL_DEFAULT 0x00073800
38 #define REG_TXCTL 0x0004
39 #define REG_TXCTL_ENABLE 0x00000001
40 #define REG_MIICMD 0x0010
41 #define REG_MIICMD_READ 0x00008000
42 #define REG_MIICMD_WRITE 0x00004000
43 #define REG_MIIDATA 0x0014
44 #define REG_MIISTS 0x0018
45 #define REG_MIISTS_BUSY 0x00000001
46 #define REG_SELFCTL 0x0020
47 #define REG_SELFCTL_RESET 0x00000001
48 #define REG_INTEN 0x0024
49 #define REG_INTEN_TX 0x00000008
50 #define REG_INTEN_RX 0x00000007
51 #define REG_INTSTSP 0x0028
52 #define REG_INTSTS_TX 0x00000008
53 #define REG_INTSTS_RX 0x00000004
54 #define REG_INTSTSC 0x002c
55 #define REG_AFP 0x004c
56 #define REG_INDAD0 0x0050
57 #define REG_INDAD1 0x0051
58 #define REG_INDAD2 0x0052
59 #define REG_INDAD3 0x0053
60 #define REG_INDAD4 0x0054
61 #define REG_INDAD5 0x0055
62 #define REG_GIINTMSK 0x0064
63 #define REG_GIINTMSK_ENABLE 0x00008000
64 #define REG_BMCTL 0x0080
65 #define REG_BMCTL_ENABLE_TX 0x00000100
66 #define REG_BMCTL_ENABLE_RX 0x00000001
67 #define REG_BMSTS 0x0084
68 #define REG_BMSTS_RX_ACTIVE 0x00000008
69 #define REG_RXDQBADD 0x0090
70 #define REG_RXDQBLEN 0x0094
71 #define REG_RXDCURADD 0x0098
72 #define REG_RXDENQ 0x009c
73 #define REG_RXSTSQBADD 0x00a0
74 #define REG_RXSTSQBLEN 0x00a4
75 #define REG_RXSTSQCURADD 0x00a8
76 #define REG_RXSTSENQ 0x00ac
77 #define REG_TXDQBADD 0x00b0
78 #define REG_TXDQBLEN 0x00b4
79 #define REG_TXDQCURADD 0x00b8
80 #define REG_TXDENQ 0x00bc
81 #define REG_TXSTSQBADD 0x00c0
82 #define REG_TXSTSQBLEN 0x00c4
83 #define REG_TXSTSQCURADD 0x00c8
84 #define REG_MAXFRMLEN 0x00e8
92 #define RDESC1_NSOF 0x80000000
93 #define RDESC1_BUFFER_INDEX 0x7fff0000
94 #define RDESC1_BUFFER_LENGTH 0x0000ffff
102 #define RSTAT0_RFP 0x80000000
103 #define RSTAT0_RWE 0x40000000
104 #define RSTAT0_EOF 0x20000000
105 #define RSTAT0_EOB 0x10000000
106 #define RSTAT0_AM 0x00c00000
107 #define RSTAT0_RX_ERR 0x00200000
108 #define RSTAT0_OE 0x00100000
109 #define RSTAT0_FE 0x00080000
110 #define RSTAT0_RUNT 0x00040000
111 #define RSTAT0_EDATA 0x00020000
112 #define RSTAT0_CRCE 0x00010000
113 #define RSTAT0_CRCI 0x00008000
114 #define RSTAT0_HTI 0x00003f00
115 #define RSTAT1_RFP 0x80000000
116 #define RSTAT1_BUFFER_INDEX 0x7fff0000
117 #define RSTAT1_FRAME_LENGTH 0x0000ffff
125 #define TDESC1_EOF 0x80000000
126 #define TDESC1_BUFFER_INDEX 0x7fff0000
127 #define TDESC1_BUFFER_ABORT 0x00008000
128 #define TDESC1_BUFFER_LENGTH 0x00000fff
135 #define TSTAT0_TXFP 0x80000000
136 #define TSTAT0_TXWE 0x40000000
137 #define TSTAT0_FA 0x20000000
138 #define TSTAT0_LCRS 0x10000000
139 #define TSTAT0_OW 0x04000000
140 #define TSTAT0_TXU 0x02000000
141 #define TSTAT0_ECOLL 0x01000000
142 #define TSTAT0_NCOLL 0x001f0000
143 #define TSTAT0_BUFFER_INDEX 0x00007fff
147 struct ep93xx_rdesc rdesc
[RX_QUEUE_ENTRIES
];
148 struct ep93xx_tdesc tdesc
[TX_QUEUE_ENTRIES
];
149 struct ep93xx_rstat rstat
[RX_QUEUE_ENTRIES
];
150 struct ep93xx_tstat tstat
[TX_QUEUE_ENTRIES
];
155 struct resource
*res
;
159 struct ep93xx_descs
*descs
;
160 dma_addr_t descs_dma_addr
;
162 void *rx_buf
[RX_QUEUE_ENTRIES
];
163 void *tx_buf
[TX_QUEUE_ENTRIES
];
166 unsigned int rx_pointer
;
167 unsigned int tx_clean_pointer
;
168 unsigned int tx_pointer
;
169 spinlock_t tx_pending_lock
;
170 unsigned int tx_pending
;
172 struct net_device_stats stats
;
174 struct mii_if_info mii
;
178 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
179 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
180 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
181 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
182 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
183 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
185 static int ep93xx_mdio_read(struct net_device
*dev
, int phy_id
, int reg
);
187 static struct net_device_stats
*ep93xx_get_stats(struct net_device
*dev
)
189 struct ep93xx_priv
*ep
= netdev_priv(dev
);
193 static int ep93xx_rx(struct net_device
*dev
, int *budget
)
195 struct ep93xx_priv
*ep
= netdev_priv(dev
);
200 tail_offset
= rdl(ep
, REG_RXSTSQCURADD
) - ep
->descs_dma_addr
;
204 while (*budget
> 0) {
206 struct ep93xx_rstat
*rstat
;
212 entry
= ep
->rx_pointer
;
213 rstat
= ep
->descs
->rstat
+ entry
;
214 if ((void *)rstat
- (void *)ep
->descs
== tail_offset
) {
219 rstat0
= rstat
->rstat0
;
220 rstat1
= rstat
->rstat1
;
224 if (!(rstat0
& RSTAT0_RFP
))
225 printk(KERN_CRIT
"ep93xx_rx: buffer not done "
226 " %.8x %.8x\n", rstat0
, rstat1
);
227 if (!(rstat0
& RSTAT0_EOF
))
228 printk(KERN_CRIT
"ep93xx_rx: not end-of-frame "
229 " %.8x %.8x\n", rstat0
, rstat1
);
230 if (!(rstat0
& RSTAT0_EOB
))
231 printk(KERN_CRIT
"ep93xx_rx: not end-of-buffer "
232 " %.8x %.8x\n", rstat0
, rstat1
);
233 if (!(rstat1
& RSTAT1_RFP
))
234 printk(KERN_CRIT
"ep93xx_rx: buffer1 not done "
235 " %.8x %.8x\n", rstat0
, rstat1
);
236 if ((rstat1
& RSTAT1_BUFFER_INDEX
) >> 16 != entry
)
237 printk(KERN_CRIT
"ep93xx_rx: entry mismatch "
238 " %.8x %.8x\n", rstat0
, rstat1
);
240 if (!(rstat0
& RSTAT0_RWE
)) {
241 printk(KERN_NOTICE
"ep93xx_rx: receive error "
242 " %.8x %.8x\n", rstat0
, rstat1
);
244 ep
->stats
.rx_errors
++;
245 if (rstat0
& RSTAT0_OE
)
246 ep
->stats
.rx_fifo_errors
++;
247 if (rstat0
& RSTAT0_FE
)
248 ep
->stats
.rx_frame_errors
++;
249 if (rstat0
& (RSTAT0_RUNT
| RSTAT0_EDATA
))
250 ep
->stats
.rx_length_errors
++;
251 if (rstat0
& RSTAT0_CRCE
)
252 ep
->stats
.rx_crc_errors
++;
256 length
= rstat1
& RSTAT1_FRAME_LENGTH
;
257 if (length
> MAX_PKT_SIZE
) {
258 printk(KERN_NOTICE
"ep93xx_rx: invalid length "
259 " %.8x %.8x\n", rstat0
, rstat1
);
264 if (rstat0
& RSTAT0_CRCI
)
267 skb
= dev_alloc_skb(length
+ 2);
268 if (likely(skb
!= NULL
)) {
271 dma_sync_single(NULL
, ep
->descs
->rdesc
[entry
].buf_addr
,
272 length
, DMA_FROM_DEVICE
);
273 eth_copy_and_sum(skb
, ep
->rx_buf
[entry
], length
, 0);
274 skb_put(skb
, length
);
275 skb
->protocol
= eth_type_trans(skb
, dev
);
277 dev
->last_rx
= jiffies
;
279 netif_receive_skb(skb
);
281 ep
->stats
.rx_packets
++;
282 ep
->stats
.rx_bytes
+= length
;
284 ep
->stats
.rx_dropped
++;
288 ep
->rx_pointer
= (entry
+ 1) & (RX_QUEUE_ENTRIES
- 1);
295 wrw(ep
, REG_RXDENQ
, processed
);
296 wrw(ep
, REG_RXSTSENQ
, processed
);
302 static int ep93xx_have_more_rx(struct ep93xx_priv
*ep
)
304 struct ep93xx_rstat
*rstat
;
307 rstat
= ep
->descs
->rstat
+ ep
->rx_pointer
;
308 tail_offset
= rdl(ep
, REG_RXSTSQCURADD
) - ep
->descs_dma_addr
;
310 return !((void *)rstat
- (void *)ep
->descs
== tail_offset
);
313 static int ep93xx_poll(struct net_device
*dev
, int *budget
)
315 struct ep93xx_priv
*ep
= netdev_priv(dev
);
318 * @@@ Have to stop polling if device is downed while we
323 if (ep93xx_rx(dev
, budget
))
326 netif_rx_complete(dev
);
328 spin_lock_irq(&ep
->rx_lock
);
329 wrl(ep
, REG_INTEN
, REG_INTEN_TX
| REG_INTEN_RX
);
330 if (ep93xx_have_more_rx(ep
)) {
331 wrl(ep
, REG_INTEN
, REG_INTEN_TX
);
332 wrl(ep
, REG_INTSTSP
, REG_INTSTS_RX
);
333 spin_unlock_irq(&ep
->rx_lock
);
335 if (netif_rx_reschedule(dev
, 0))
340 spin_unlock_irq(&ep
->rx_lock
);
345 static int ep93xx_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
347 struct ep93xx_priv
*ep
= netdev_priv(dev
);
350 if (unlikely(skb
->len
) > MAX_PKT_SIZE
) {
351 ep
->stats
.tx_dropped
++;
356 entry
= ep
->tx_pointer
;
357 ep
->tx_pointer
= (ep
->tx_pointer
+ 1) & (TX_QUEUE_ENTRIES
- 1);
359 ep
->descs
->tdesc
[entry
].tdesc1
=
360 TDESC1_EOF
| (entry
<< 16) | (skb
->len
& 0xfff);
361 skb_copy_and_csum_dev(skb
, ep
->tx_buf
[entry
]);
362 dma_sync_single(NULL
, ep
->descs
->tdesc
[entry
].buf_addr
,
363 skb
->len
, DMA_TO_DEVICE
);
366 dev
->trans_start
= jiffies
;
368 spin_lock_irq(&ep
->tx_pending_lock
);
370 if (ep
->tx_pending
== TX_QUEUE_ENTRIES
)
371 netif_stop_queue(dev
);
372 spin_unlock_irq(&ep
->tx_pending_lock
);
374 wrl(ep
, REG_TXDENQ
, 1);
379 static void ep93xx_tx_complete(struct net_device
*dev
)
381 struct ep93xx_priv
*ep
= netdev_priv(dev
);
385 tail_offset
= rdl(ep
, REG_TXSTSQCURADD
) - ep
->descs_dma_addr
;
388 spin_lock(&ep
->tx_pending_lock
);
391 struct ep93xx_tstat
*tstat
;
394 entry
= ep
->tx_clean_pointer
;
395 tstat
= ep
->descs
->tstat
+ entry
;
396 if ((void *)tstat
- (void *)ep
->descs
== tail_offset
)
399 tstat0
= tstat
->tstat0
;
402 if (!(tstat0
& TSTAT0_TXFP
))
403 printk(KERN_CRIT
"ep93xx_tx_complete: buffer not done "
405 if (tstat0
& TSTAT0_FA
)
406 printk(KERN_CRIT
"ep93xx_tx_complete: frame aborted "
408 if ((tstat0
& TSTAT0_BUFFER_INDEX
) != entry
)
409 printk(KERN_CRIT
"ep93xx_tx_complete: entry mismatch "
412 if (tstat0
& TSTAT0_TXWE
) {
413 int length
= ep
->descs
->tdesc
[entry
].tdesc1
& 0xfff;
415 ep
->stats
.tx_packets
++;
416 ep
->stats
.tx_bytes
+= length
;
418 ep
->stats
.tx_errors
++;
421 if (tstat0
& TSTAT0_OW
)
422 ep
->stats
.tx_window_errors
++;
423 if (tstat0
& TSTAT0_TXU
)
424 ep
->stats
.tx_fifo_errors
++;
425 ep
->stats
.collisions
+= (tstat0
>> 16) & 0x1f;
427 ep
->tx_clean_pointer
= (entry
+ 1) & (TX_QUEUE_ENTRIES
- 1);
428 if (ep
->tx_pending
== TX_QUEUE_ENTRIES
)
432 spin_unlock(&ep
->tx_pending_lock
);
435 netif_wake_queue(dev
);
438 static irqreturn_t
ep93xx_irq(int irq
, void *dev_id
)
440 struct net_device
*dev
= dev_id
;
441 struct ep93xx_priv
*ep
= netdev_priv(dev
);
444 status
= rdl(ep
, REG_INTSTSC
);
448 if (status
& REG_INTSTS_RX
) {
449 spin_lock(&ep
->rx_lock
);
450 if (likely(__netif_rx_schedule_prep(dev
))) {
451 wrl(ep
, REG_INTEN
, REG_INTEN_TX
);
452 __netif_rx_schedule(dev
);
454 spin_unlock(&ep
->rx_lock
);
457 if (status
& REG_INTSTS_TX
)
458 ep93xx_tx_complete(dev
);
463 static void ep93xx_free_buffers(struct ep93xx_priv
*ep
)
467 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
+= 2) {
470 d
= ep
->descs
->rdesc
[i
].buf_addr
;
472 dma_unmap_single(NULL
, d
, PAGE_SIZE
, DMA_FROM_DEVICE
);
474 if (ep
->rx_buf
[i
] != NULL
)
475 free_page((unsigned long)ep
->rx_buf
[i
]);
478 for (i
= 0; i
< TX_QUEUE_ENTRIES
; i
+= 2) {
481 d
= ep
->descs
->tdesc
[i
].buf_addr
;
483 dma_unmap_single(NULL
, d
, PAGE_SIZE
, DMA_TO_DEVICE
);
485 if (ep
->tx_buf
[i
] != NULL
)
486 free_page((unsigned long)ep
->tx_buf
[i
]);
489 dma_free_coherent(NULL
, sizeof(struct ep93xx_descs
), ep
->descs
,
494 * The hardware enforces a sub-2K maximum packet size, so we put
495 * two buffers on every hardware page.
497 static int ep93xx_alloc_buffers(struct ep93xx_priv
*ep
)
501 ep
->descs
= dma_alloc_coherent(NULL
, sizeof(struct ep93xx_descs
),
502 &ep
->descs_dma_addr
, GFP_KERNEL
| GFP_DMA
);
503 if (ep
->descs
== NULL
)
506 for (i
= 0; i
< RX_QUEUE_ENTRIES
; i
+= 2) {
510 page
= (void *)__get_free_page(GFP_KERNEL
| GFP_DMA
);
514 d
= dma_map_single(NULL
, page
, PAGE_SIZE
, DMA_FROM_DEVICE
);
515 if (dma_mapping_error(d
)) {
516 free_page((unsigned long)page
);
520 ep
->rx_buf
[i
] = page
;
521 ep
->descs
->rdesc
[i
].buf_addr
= d
;
522 ep
->descs
->rdesc
[i
].rdesc1
= (i
<< 16) | PKT_BUF_SIZE
;
524 ep
->rx_buf
[i
+ 1] = page
+ PKT_BUF_SIZE
;
525 ep
->descs
->rdesc
[i
+ 1].buf_addr
= d
+ PKT_BUF_SIZE
;
526 ep
->descs
->rdesc
[i
+ 1].rdesc1
= ((i
+ 1) << 16) | PKT_BUF_SIZE
;
529 for (i
= 0; i
< TX_QUEUE_ENTRIES
; i
+= 2) {
533 page
= (void *)__get_free_page(GFP_KERNEL
| GFP_DMA
);
537 d
= dma_map_single(NULL
, page
, PAGE_SIZE
, DMA_TO_DEVICE
);
538 if (dma_mapping_error(d
)) {
539 free_page((unsigned long)page
);
543 ep
->tx_buf
[i
] = page
;
544 ep
->descs
->tdesc
[i
].buf_addr
= d
;
546 ep
->tx_buf
[i
+ 1] = page
+ PKT_BUF_SIZE
;
547 ep
->descs
->tdesc
[i
+ 1].buf_addr
= d
+ PKT_BUF_SIZE
;
553 ep93xx_free_buffers(ep
);
557 static int ep93xx_start_hw(struct net_device
*dev
)
559 struct ep93xx_priv
*ep
= netdev_priv(dev
);
563 wrl(ep
, REG_SELFCTL
, REG_SELFCTL_RESET
);
564 for (i
= 0; i
< 10; i
++) {
565 if ((rdl(ep
, REG_SELFCTL
) & REG_SELFCTL_RESET
) == 0)
571 printk(KERN_CRIT DRV_MODULE_NAME
": hw failed to reset\n");
575 wrl(ep
, REG_SELFCTL
, ((ep
->mdc_divisor
- 1) << 9));
577 /* Does the PHY support preamble suppress? */
578 if ((ep93xx_mdio_read(dev
, ep
->mii
.phy_id
, MII_BMSR
) & 0x0040) != 0)
579 wrl(ep
, REG_SELFCTL
, ((ep
->mdc_divisor
- 1) << 9) | (1 << 8));
581 /* Receive descriptor ring. */
582 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, rdesc
);
583 wrl(ep
, REG_RXDQBADD
, addr
);
584 wrl(ep
, REG_RXDCURADD
, addr
);
585 wrw(ep
, REG_RXDQBLEN
, RX_QUEUE_ENTRIES
* sizeof(struct ep93xx_rdesc
));
587 /* Receive status ring. */
588 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, rstat
);
589 wrl(ep
, REG_RXSTSQBADD
, addr
);
590 wrl(ep
, REG_RXSTSQCURADD
, addr
);
591 wrw(ep
, REG_RXSTSQBLEN
, RX_QUEUE_ENTRIES
* sizeof(struct ep93xx_rstat
));
593 /* Transmit descriptor ring. */
594 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, tdesc
);
595 wrl(ep
, REG_TXDQBADD
, addr
);
596 wrl(ep
, REG_TXDQCURADD
, addr
);
597 wrw(ep
, REG_TXDQBLEN
, TX_QUEUE_ENTRIES
* sizeof(struct ep93xx_tdesc
));
599 /* Transmit status ring. */
600 addr
= ep
->descs_dma_addr
+ offsetof(struct ep93xx_descs
, tstat
);
601 wrl(ep
, REG_TXSTSQBADD
, addr
);
602 wrl(ep
, REG_TXSTSQCURADD
, addr
);
603 wrw(ep
, REG_TXSTSQBLEN
, TX_QUEUE_ENTRIES
* sizeof(struct ep93xx_tstat
));
605 wrl(ep
, REG_BMCTL
, REG_BMCTL_ENABLE_TX
| REG_BMCTL_ENABLE_RX
);
606 wrl(ep
, REG_INTEN
, REG_INTEN_TX
| REG_INTEN_RX
);
607 wrl(ep
, REG_GIINTMSK
, 0);
609 for (i
= 0; i
< 10; i
++) {
610 if ((rdl(ep
, REG_BMSTS
) & REG_BMSTS_RX_ACTIVE
) != 0)
616 printk(KERN_CRIT DRV_MODULE_NAME
": hw failed to start\n");
620 wrl(ep
, REG_RXDENQ
, RX_QUEUE_ENTRIES
);
621 wrl(ep
, REG_RXSTSENQ
, RX_QUEUE_ENTRIES
);
623 wrb(ep
, REG_INDAD0
, dev
->dev_addr
[0]);
624 wrb(ep
, REG_INDAD1
, dev
->dev_addr
[1]);
625 wrb(ep
, REG_INDAD2
, dev
->dev_addr
[2]);
626 wrb(ep
, REG_INDAD3
, dev
->dev_addr
[3]);
627 wrb(ep
, REG_INDAD4
, dev
->dev_addr
[4]);
628 wrb(ep
, REG_INDAD5
, dev
->dev_addr
[5]);
631 wrl(ep
, REG_MAXFRMLEN
, (MAX_PKT_SIZE
<< 16) | MAX_PKT_SIZE
);
633 wrl(ep
, REG_RXCTL
, REG_RXCTL_DEFAULT
);
634 wrl(ep
, REG_TXCTL
, REG_TXCTL_ENABLE
);
639 static void ep93xx_stop_hw(struct net_device
*dev
)
641 struct ep93xx_priv
*ep
= netdev_priv(dev
);
644 wrl(ep
, REG_SELFCTL
, REG_SELFCTL_RESET
);
645 for (i
= 0; i
< 10; i
++) {
646 if ((rdl(ep
, REG_SELFCTL
) & REG_SELFCTL_RESET
) == 0)
652 printk(KERN_CRIT DRV_MODULE_NAME
": hw failed to reset\n");
655 static int ep93xx_open(struct net_device
*dev
)
657 struct ep93xx_priv
*ep
= netdev_priv(dev
);
660 if (ep93xx_alloc_buffers(ep
))
663 if (is_zero_ether_addr(dev
->dev_addr
)) {
664 random_ether_addr(dev
->dev_addr
);
665 printk(KERN_INFO
"%s: generated random MAC address "
666 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x.\n", dev
->name
,
667 dev
->dev_addr
[0], dev
->dev_addr
[1],
668 dev
->dev_addr
[2], dev
->dev_addr
[3],
669 dev
->dev_addr
[4], dev
->dev_addr
[5]);
672 if (ep93xx_start_hw(dev
)) {
673 ep93xx_free_buffers(ep
);
677 spin_lock_init(&ep
->rx_lock
);
679 ep
->tx_clean_pointer
= 0;
681 spin_lock_init(&ep
->tx_pending_lock
);
684 err
= request_irq(ep
->irq
, ep93xx_irq
, IRQF_SHARED
, dev
->name
, dev
);
687 ep93xx_free_buffers(ep
);
691 wrl(ep
, REG_GIINTMSK
, REG_GIINTMSK_ENABLE
);
693 netif_start_queue(dev
);
698 static int ep93xx_close(struct net_device
*dev
)
700 struct ep93xx_priv
*ep
= netdev_priv(dev
);
702 netif_stop_queue(dev
);
704 wrl(ep
, REG_GIINTMSK
, 0);
705 free_irq(ep
->irq
, dev
);
707 ep93xx_free_buffers(ep
);
712 static int ep93xx_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
714 struct ep93xx_priv
*ep
= netdev_priv(dev
);
715 struct mii_ioctl_data
*data
= if_mii(ifr
);
717 return generic_mii_ioctl(&ep
->mii
, data
, cmd
, NULL
);
720 static int ep93xx_mdio_read(struct net_device
*dev
, int phy_id
, int reg
)
722 struct ep93xx_priv
*ep
= netdev_priv(dev
);
726 wrl(ep
, REG_MIICMD
, REG_MIICMD_READ
| (phy_id
<< 5) | reg
);
728 for (i
= 0; i
< 10; i
++) {
729 if ((rdl(ep
, REG_MIISTS
) & REG_MIISTS_BUSY
) == 0)
735 printk(KERN_INFO DRV_MODULE_NAME
": mdio read timed out\n");
738 data
= rdl(ep
, REG_MIIDATA
);
744 static void ep93xx_mdio_write(struct net_device
*dev
, int phy_id
, int reg
, int data
)
746 struct ep93xx_priv
*ep
= netdev_priv(dev
);
749 wrl(ep
, REG_MIIDATA
, data
);
750 wrl(ep
, REG_MIICMD
, REG_MIICMD_WRITE
| (phy_id
<< 5) | reg
);
752 for (i
= 0; i
< 10; i
++) {
753 if ((rdl(ep
, REG_MIISTS
) & REG_MIISTS_BUSY
) == 0)
759 printk(KERN_INFO DRV_MODULE_NAME
": mdio write timed out\n");
762 static void ep93xx_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
764 strcpy(info
->driver
, DRV_MODULE_NAME
);
765 strcpy(info
->version
, DRV_MODULE_VERSION
);
768 static int ep93xx_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
770 struct ep93xx_priv
*ep
= netdev_priv(dev
);
771 return mii_ethtool_gset(&ep
->mii
, cmd
);
774 static int ep93xx_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
776 struct ep93xx_priv
*ep
= netdev_priv(dev
);
777 return mii_ethtool_sset(&ep
->mii
, cmd
);
780 static int ep93xx_nway_reset(struct net_device
*dev
)
782 struct ep93xx_priv
*ep
= netdev_priv(dev
);
783 return mii_nway_restart(&ep
->mii
);
786 static u32
ep93xx_get_link(struct net_device
*dev
)
788 struct ep93xx_priv
*ep
= netdev_priv(dev
);
789 return mii_link_ok(&ep
->mii
);
792 static struct ethtool_ops ep93xx_ethtool_ops
= {
793 .get_drvinfo
= ep93xx_get_drvinfo
,
794 .get_settings
= ep93xx_get_settings
,
795 .set_settings
= ep93xx_set_settings
,
796 .nway_reset
= ep93xx_nway_reset
,
797 .get_link
= ep93xx_get_link
,
800 struct net_device
*ep93xx_dev_alloc(struct ep93xx_eth_data
*data
)
802 struct net_device
*dev
;
803 struct ep93xx_priv
*ep
;
805 dev
= alloc_etherdev(sizeof(struct ep93xx_priv
));
808 ep
= netdev_priv(dev
);
810 memcpy(dev
->dev_addr
, data
->dev_addr
, ETH_ALEN
);
812 dev
->get_stats
= ep93xx_get_stats
;
813 dev
->ethtool_ops
= &ep93xx_ethtool_ops
;
814 dev
->poll
= ep93xx_poll
;
815 dev
->hard_start_xmit
= ep93xx_xmit
;
816 dev
->open
= ep93xx_open
;
817 dev
->stop
= ep93xx_close
;
818 dev
->do_ioctl
= ep93xx_ioctl
;
820 dev
->features
|= NETIF_F_SG
| NETIF_F_HW_CSUM
;
827 static int ep93xx_eth_remove(struct platform_device
*pdev
)
829 struct net_device
*dev
;
830 struct ep93xx_priv
*ep
;
832 dev
= platform_get_drvdata(pdev
);
835 platform_set_drvdata(pdev
, NULL
);
837 ep
= netdev_priv(dev
);
839 /* @@@ Force down. */
840 unregister_netdev(dev
);
841 ep93xx_free_buffers(ep
);
843 if (ep
->base_addr
!= NULL
)
844 iounmap(ep
->base_addr
);
846 if (ep
->res
!= NULL
) {
847 release_resource(ep
->res
);
856 static int ep93xx_eth_probe(struct platform_device
*pdev
)
858 struct ep93xx_eth_data
*data
;
859 struct net_device
*dev
;
860 struct ep93xx_priv
*ep
;
863 data
= pdev
->dev
.platform_data
;
867 dev
= ep93xx_dev_alloc(data
);
872 ep
= netdev_priv(dev
);
874 platform_set_drvdata(pdev
, dev
);
876 ep
->res
= request_mem_region(pdev
->resource
[0].start
,
877 pdev
->resource
[0].end
- pdev
->resource
[0].start
+ 1,
879 if (ep
->res
== NULL
) {
880 dev_err(&pdev
->dev
, "Could not reserve memory region\n");
885 ep
->base_addr
= ioremap(pdev
->resource
[0].start
,
886 pdev
->resource
[0].end
- pdev
->resource
[0].start
);
887 if (ep
->base_addr
== NULL
) {
888 dev_err(&pdev
->dev
, "Failed to ioremap ethernet registers\n");
892 ep
->irq
= pdev
->resource
[1].start
;
894 ep
->mii
.phy_id
= data
->phy_id
;
895 ep
->mii
.phy_id_mask
= 0x1f;
896 ep
->mii
.reg_num_mask
= 0x1f;
898 ep
->mii
.mdio_read
= ep93xx_mdio_read
;
899 ep
->mii
.mdio_write
= ep93xx_mdio_write
;
900 ep
->mdc_divisor
= 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
902 err
= register_netdev(dev
);
904 dev_err(&pdev
->dev
, "Failed to register netdev\n");
908 printk(KERN_INFO
"%s: ep93xx on-chip ethernet, IRQ %d, "
909 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x.\n", dev
->name
,
910 ep
->irq
, data
->dev_addr
[0], data
->dev_addr
[1],
911 data
->dev_addr
[2], data
->dev_addr
[3],
912 data
->dev_addr
[4], data
->dev_addr
[5]);
917 ep93xx_eth_remove(pdev
);
922 static struct platform_driver ep93xx_eth_driver
= {
923 .probe
= ep93xx_eth_probe
,
924 .remove
= ep93xx_eth_remove
,
926 .name
= "ep93xx-eth",
930 static int __init
ep93xx_eth_init_module(void)
932 printk(KERN_INFO DRV_MODULE_NAME
" version " DRV_MODULE_VERSION
" loading\n");
933 return platform_driver_register(&ep93xx_eth_driver
);
936 static void __exit
ep93xx_eth_cleanup_module(void)
938 platform_driver_unregister(&ep93xx_eth_driver
);
941 module_init(ep93xx_eth_init_module
);
942 module_exit(ep93xx_eth_cleanup_module
);
943 MODULE_LICENSE("GPL");