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New 7.0 FW: bnx2x, cnic, bnx2i, bnx2fc
[mirror_ubuntu-zesty-kernel.git] / drivers / net / bnx2x / bnx2x_ethtool.c
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #include <linux/ethtool.h>
18 #include <linux/netdevice.h>
19 #include <linux/types.h>
20 #include <linux/sched.h>
21 #include <linux/crc32.h>
22
23
24 #include "bnx2x.h"
25 #include "bnx2x_cmn.h"
26 #include "bnx2x_dump.h"
27 #include "bnx2x_init.h"
28 #include "bnx2x_sp.h"
29
30 /* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34 #define MAX_QUEUE_NAME_LEN 4
35 static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39 } bnx2x_q_stats_arr[] = {
40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
66 };
67
68 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70 static const struct {
71 long offset;
72 int size;
73 u32 flags;
74 #define STATS_FLAGS_PORT 1
75 #define STATS_FLAGS_FUNC 2
76 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78 } bnx2x_stats_arr[] = {
79 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
107 { STATS_OFFSET32(brb_drop_hi),
108 8, STATS_FLAGS_PORT, "rx_brb_discard" },
109 { STATS_OFFSET32(brb_truncate_hi),
110 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
111 { STATS_OFFSET32(pause_frames_received_hi),
112 8, STATS_FLAGS_PORT, "rx_pause_frames" },
113 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
114 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
115 { STATS_OFFSET32(nig_timer_max),
116 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
117 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
118 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
119 { STATS_OFFSET32(rx_skb_alloc_failed),
120 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
121 { STATS_OFFSET32(hw_csum_err),
122 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
123
124 { STATS_OFFSET32(total_bytes_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_bytes" },
126 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
127 8, STATS_FLAGS_PORT, "tx_error_bytes" },
128 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
130 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
132 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
134 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
135 8, STATS_FLAGS_PORT, "tx_mac_errors" },
136 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
137 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
138 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
139 8, STATS_FLAGS_PORT, "tx_single_collisions" },
140 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
141 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
143 8, STATS_FLAGS_PORT, "tx_deferred" },
144 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
147 8, STATS_FLAGS_PORT, "tx_late_collisions" },
148 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_total_collisions" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
151 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
153 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
155 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
157 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
158 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
159 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
160 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
161 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
162 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
163 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
164 { STATS_OFFSET32(pause_frames_sent_hi),
165 8, STATS_FLAGS_PORT, "tx_pause_frames" },
166 { STATS_OFFSET32(total_tpa_aggregations_hi),
167 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
168 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
169 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
170 { STATS_OFFSET32(total_tpa_bytes_hi),
171 8, STATS_FLAGS_FUNC, "tpa_bytes"}
172 };
173
174 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
175 static int bnx2x_get_port_type(struct bnx2x *bp)
176 {
177 int port_type;
178 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
179 switch (bp->link_params.phy[phy_idx].media_type) {
180 case ETH_PHY_SFP_FIBER:
181 case ETH_PHY_XFP_FIBER:
182 case ETH_PHY_KR:
183 case ETH_PHY_CX4:
184 port_type = PORT_FIBRE;
185 break;
186 case ETH_PHY_DA_TWINAX:
187 port_type = PORT_DA;
188 break;
189 case ETH_PHY_BASE_T:
190 port_type = PORT_TP;
191 break;
192 case ETH_PHY_NOT_PRESENT:
193 port_type = PORT_NONE;
194 break;
195 case ETH_PHY_UNSPECIFIED:
196 default:
197 port_type = PORT_OTHER;
198 break;
199 }
200 return port_type;
201 }
202
203 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
204 {
205 struct bnx2x *bp = netdev_priv(dev);
206 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
207
208 /* Dual Media boards present all available port types */
209 cmd->supported = bp->port.supported[cfg_idx] |
210 (bp->port.supported[cfg_idx ^ 1] &
211 (SUPPORTED_TP | SUPPORTED_FIBRE));
212 cmd->advertising = bp->port.advertising[cfg_idx];
213
214 if ((bp->state == BNX2X_STATE_OPEN) &&
215 !(bp->flags & MF_FUNC_DIS) &&
216 (bp->link_vars.link_up)) {
217 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
218 cmd->duplex = bp->link_vars.duplex;
219 } else {
220 ethtool_cmd_speed_set(
221 cmd, bp->link_params.req_line_speed[cfg_idx]);
222 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
223 }
224
225 if (IS_MF(bp))
226 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
227
228 cmd->port = bnx2x_get_port_type(bp);
229
230 cmd->phy_address = bp->mdio.prtad;
231 cmd->transceiver = XCVR_INTERNAL;
232
233 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
234 cmd->autoneg = AUTONEG_ENABLE;
235 else
236 cmd->autoneg = AUTONEG_DISABLE;
237
238 cmd->maxtxpkt = 0;
239 cmd->maxrxpkt = 0;
240
241 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
242 DP_LEVEL " supported 0x%x advertising 0x%x speed %u\n"
243 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
244 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
245 cmd->cmd, cmd->supported, cmd->advertising,
246 ethtool_cmd_speed(cmd),
247 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
248 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
249
250 return 0;
251 }
252
253 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
254 {
255 struct bnx2x *bp = netdev_priv(dev);
256 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
257 u32 speed;
258
259 if (IS_MF_SD(bp))
260 return 0;
261
262 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
263 " supported 0x%x advertising 0x%x speed %u\n"
264 " duplex %d port %d phy_address %d transceiver %d\n"
265 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
266 cmd->cmd, cmd->supported, cmd->advertising,
267 ethtool_cmd_speed(cmd),
268 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
269 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
270
271 speed = ethtool_cmd_speed(cmd);
272
273 if (IS_MF_SI(bp)) {
274 u32 part;
275 u32 line_speed = bp->link_vars.line_speed;
276
277 /* use 10G if no link detected */
278 if (!line_speed)
279 line_speed = 10000;
280
281 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
282 BNX2X_DEV_INFO("To set speed BC %X or higher "
283 "is required, please upgrade BC\n",
284 REQ_BC_VER_4_SET_MF_BW);
285 return -EINVAL;
286 }
287
288 part = (speed * 100) / line_speed;
289
290 if (line_speed < speed || !part) {
291 BNX2X_DEV_INFO("Speed setting should be in a range "
292 "from 1%% to 100%% "
293 "of actual line speed\n");
294 return -EINVAL;
295 }
296
297 if (bp->state != BNX2X_STATE_OPEN)
298 /* store value for following "load" */
299 bp->pending_max = part;
300 else
301 bnx2x_update_max_mf_config(bp, part);
302
303 return 0;
304 }
305
306 cfg_idx = bnx2x_get_link_cfg_idx(bp);
307 old_multi_phy_config = bp->link_params.multi_phy_config;
308 switch (cmd->port) {
309 case PORT_TP:
310 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
311 break; /* no port change */
312
313 if (!(bp->port.supported[0] & SUPPORTED_TP ||
314 bp->port.supported[1] & SUPPORTED_TP)) {
315 DP(NETIF_MSG_LINK, "Unsupported port type\n");
316 return -EINVAL;
317 }
318 bp->link_params.multi_phy_config &=
319 ~PORT_HW_CFG_PHY_SELECTION_MASK;
320 if (bp->link_params.multi_phy_config &
321 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
322 bp->link_params.multi_phy_config |=
323 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
324 else
325 bp->link_params.multi_phy_config |=
326 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
327 break;
328 case PORT_FIBRE:
329 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
330 break; /* no port change */
331
332 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
333 bp->port.supported[1] & SUPPORTED_FIBRE)) {
334 DP(NETIF_MSG_LINK, "Unsupported port type\n");
335 return -EINVAL;
336 }
337 bp->link_params.multi_phy_config &=
338 ~PORT_HW_CFG_PHY_SELECTION_MASK;
339 if (bp->link_params.multi_phy_config &
340 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
341 bp->link_params.multi_phy_config |=
342 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
343 else
344 bp->link_params.multi_phy_config |=
345 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
346 break;
347 default:
348 DP(NETIF_MSG_LINK, "Unsupported port type\n");
349 return -EINVAL;
350 }
351 /* Save new config in case command complete successuly */
352 new_multi_phy_config = bp->link_params.multi_phy_config;
353 /* Get the new cfg_idx */
354 cfg_idx = bnx2x_get_link_cfg_idx(bp);
355 /* Restore old config in case command failed */
356 bp->link_params.multi_phy_config = old_multi_phy_config;
357 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
358
359 if (cmd->autoneg == AUTONEG_ENABLE) {
360 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
361 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
362 return -EINVAL;
363 }
364
365 /* advertise the requested speed and duplex if supported */
366 cmd->advertising &= bp->port.supported[cfg_idx];
367
368 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
369 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
370 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
371 cmd->advertising);
372
373 } else { /* forced speed */
374 /* advertise the requested speed and duplex if supported */
375 switch (speed) {
376 case SPEED_10:
377 if (cmd->duplex == DUPLEX_FULL) {
378 if (!(bp->port.supported[cfg_idx] &
379 SUPPORTED_10baseT_Full)) {
380 DP(NETIF_MSG_LINK,
381 "10M full not supported\n");
382 return -EINVAL;
383 }
384
385 advertising = (ADVERTISED_10baseT_Full |
386 ADVERTISED_TP);
387 } else {
388 if (!(bp->port.supported[cfg_idx] &
389 SUPPORTED_10baseT_Half)) {
390 DP(NETIF_MSG_LINK,
391 "10M half not supported\n");
392 return -EINVAL;
393 }
394
395 advertising = (ADVERTISED_10baseT_Half |
396 ADVERTISED_TP);
397 }
398 break;
399
400 case SPEED_100:
401 if (cmd->duplex == DUPLEX_FULL) {
402 if (!(bp->port.supported[cfg_idx] &
403 SUPPORTED_100baseT_Full)) {
404 DP(NETIF_MSG_LINK,
405 "100M full not supported\n");
406 return -EINVAL;
407 }
408
409 advertising = (ADVERTISED_100baseT_Full |
410 ADVERTISED_TP);
411 } else {
412 if (!(bp->port.supported[cfg_idx] &
413 SUPPORTED_100baseT_Half)) {
414 DP(NETIF_MSG_LINK,
415 "100M half not supported\n");
416 return -EINVAL;
417 }
418
419 advertising = (ADVERTISED_100baseT_Half |
420 ADVERTISED_TP);
421 }
422 break;
423
424 case SPEED_1000:
425 if (cmd->duplex != DUPLEX_FULL) {
426 DP(NETIF_MSG_LINK, "1G half not supported\n");
427 return -EINVAL;
428 }
429
430 if (!(bp->port.supported[cfg_idx] &
431 SUPPORTED_1000baseT_Full)) {
432 DP(NETIF_MSG_LINK, "1G full not supported\n");
433 return -EINVAL;
434 }
435
436 advertising = (ADVERTISED_1000baseT_Full |
437 ADVERTISED_TP);
438 break;
439
440 case SPEED_2500:
441 if (cmd->duplex != DUPLEX_FULL) {
442 DP(NETIF_MSG_LINK,
443 "2.5G half not supported\n");
444 return -EINVAL;
445 }
446
447 if (!(bp->port.supported[cfg_idx]
448 & SUPPORTED_2500baseX_Full)) {
449 DP(NETIF_MSG_LINK,
450 "2.5G full not supported\n");
451 return -EINVAL;
452 }
453
454 advertising = (ADVERTISED_2500baseX_Full |
455 ADVERTISED_TP);
456 break;
457
458 case SPEED_10000:
459 if (cmd->duplex != DUPLEX_FULL) {
460 DP(NETIF_MSG_LINK, "10G half not supported\n");
461 return -EINVAL;
462 }
463
464 if (!(bp->port.supported[cfg_idx]
465 & SUPPORTED_10000baseT_Full)) {
466 DP(NETIF_MSG_LINK, "10G full not supported\n");
467 return -EINVAL;
468 }
469
470 advertising = (ADVERTISED_10000baseT_Full |
471 ADVERTISED_FIBRE);
472 break;
473
474 default:
475 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
476 return -EINVAL;
477 }
478
479 bp->link_params.req_line_speed[cfg_idx] = speed;
480 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
481 bp->port.advertising[cfg_idx] = advertising;
482 }
483
484 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
485 DP_LEVEL " req_duplex %d advertising 0x%x\n",
486 bp->link_params.req_line_speed[cfg_idx],
487 bp->link_params.req_duplex[cfg_idx],
488 bp->port.advertising[cfg_idx]);
489
490 /* Set new config */
491 bp->link_params.multi_phy_config = new_multi_phy_config;
492 if (netif_running(dev)) {
493 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
494 bnx2x_link_set(bp);
495 }
496
497 return 0;
498 }
499
500 #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
501 #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
502 #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
503
504 static int bnx2x_get_regs_len(struct net_device *dev)
505 {
506 struct bnx2x *bp = netdev_priv(dev);
507 int regdump_len = 0;
508 int i, j, k;
509
510 if (CHIP_IS_E1(bp)) {
511 for (i = 0; i < REGS_COUNT; i++)
512 if (IS_E1_ONLINE(reg_addrs[i].info))
513 regdump_len += reg_addrs[i].size;
514
515 for (i = 0; i < WREGS_COUNT_E1; i++)
516 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
517 regdump_len += wreg_addrs_e1[i].size *
518 (1 + wreg_addrs_e1[i].read_regs_count);
519
520 } else if (CHIP_IS_E1H(bp)) {
521 for (i = 0; i < REGS_COUNT; i++)
522 if (IS_E1H_ONLINE(reg_addrs[i].info))
523 regdump_len += reg_addrs[i].size;
524
525 for (i = 0; i < WREGS_COUNT_E1H; i++)
526 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
527 regdump_len += wreg_addrs_e1h[i].size *
528 (1 + wreg_addrs_e1h[i].read_regs_count);
529 } else if (!CHIP_IS_E1x(bp)) {
530 for (i = 0; i < REGS_COUNT; i++)
531 if (IS_E2_ONLINE(reg_addrs[i].info))
532 regdump_len += reg_addrs[i].size;
533
534 for (i = 0; i < WREGS_COUNT_E2; i++)
535 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
536 regdump_len += wreg_addrs_e2[i].size *
537 (1 + wreg_addrs_e2[i].read_regs_count);
538
539 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
540 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
541 for (k = 0; k < PAGE_READ_REGS_E2; k++)
542 if (IS_E2_ONLINE(page_read_regs_e2[k].
543 info))
544 regdump_len +=
545 page_read_regs_e2[k].size;
546 }
547 }
548 regdump_len *= 4;
549 regdump_len += sizeof(struct dump_hdr);
550
551 return regdump_len;
552 }
553
554 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
555 {
556 u32 i, j, k, n;
557
558 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
559 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
560 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
561 for (k = 0; k < PAGE_READ_REGS_E2; k++)
562 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
563 for (n = 0; n <
564 page_read_regs_e2[k].size; n++)
565 *p++ = REG_RD(bp,
566 page_read_regs_e2[k].addr + n*4);
567 }
568 }
569 }
570
571 static void bnx2x_get_regs(struct net_device *dev,
572 struct ethtool_regs *regs, void *_p)
573 {
574 u32 *p = _p, i, j;
575 struct bnx2x *bp = netdev_priv(dev);
576 struct dump_hdr dump_hdr = {0};
577
578 regs->version = 0;
579 memset(p, 0, regs->len);
580
581 if (!netif_running(bp->dev))
582 return;
583
584 /* Disable parity attentions as long as following dump may
585 * cause false alarms by reading never written registers. We
586 * will re-enable parity attentions right after the dump.
587 */
588 bnx2x_disable_blocks_parity(bp);
589
590 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
591 dump_hdr.dump_sign = dump_sign_all;
592 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
593 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
594 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
595 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
596
597 if (CHIP_IS_E1(bp))
598 dump_hdr.info = RI_E1_ONLINE;
599 else if (CHIP_IS_E1H(bp))
600 dump_hdr.info = RI_E1H_ONLINE;
601 else if (!CHIP_IS_E1x(bp))
602 dump_hdr.info = RI_E2_ONLINE |
603 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
604
605 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
606 p += dump_hdr.hdr_size + 1;
607
608 if (CHIP_IS_E1(bp)) {
609 for (i = 0; i < REGS_COUNT; i++)
610 if (IS_E1_ONLINE(reg_addrs[i].info))
611 for (j = 0; j < reg_addrs[i].size; j++)
612 *p++ = REG_RD(bp,
613 reg_addrs[i].addr + j*4);
614
615 } else if (CHIP_IS_E1H(bp)) {
616 for (i = 0; i < REGS_COUNT; i++)
617 if (IS_E1H_ONLINE(reg_addrs[i].info))
618 for (j = 0; j < reg_addrs[i].size; j++)
619 *p++ = REG_RD(bp,
620 reg_addrs[i].addr + j*4);
621
622 } else if (!CHIP_IS_E1x(bp)) {
623 for (i = 0; i < REGS_COUNT; i++)
624 if (IS_E2_ONLINE(reg_addrs[i].info))
625 for (j = 0; j < reg_addrs[i].size; j++)
626 *p++ = REG_RD(bp,
627 reg_addrs[i].addr + j*4);
628
629 if (CHIP_IS_E2(bp))
630 bnx2x_read_pages_regs_e2(bp, p);
631 else
632 /* E3 paged registers read is unimplemented yet */
633 WARN_ON(1);
634 }
635 /* Re-enable parity attentions */
636 bnx2x_clear_blocks_parity(bp);
637 if (CHIP_PARITY_ENABLED(bp))
638 bnx2x_enable_blocks_parity(bp);
639 }
640
641 static void bnx2x_get_drvinfo(struct net_device *dev,
642 struct ethtool_drvinfo *info)
643 {
644 struct bnx2x *bp = netdev_priv(dev);
645 u8 phy_fw_ver[PHY_FW_VER_LEN];
646
647 strcpy(info->driver, DRV_MODULE_NAME);
648 strcpy(info->version, DRV_MODULE_VERSION);
649
650 phy_fw_ver[0] = '\0';
651 if (bp->port.pmf) {
652 bnx2x_acquire_phy_lock(bp);
653 bnx2x_get_ext_phy_fw_version(&bp->link_params,
654 (bp->state != BNX2X_STATE_CLOSED),
655 phy_fw_ver, PHY_FW_VER_LEN);
656 bnx2x_release_phy_lock(bp);
657 }
658
659 strncpy(info->fw_version, bp->fw_ver, 32);
660 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
661 "bc %d.%d.%d%s%s",
662 (bp->common.bc_ver & 0xff0000) >> 16,
663 (bp->common.bc_ver & 0xff00) >> 8,
664 (bp->common.bc_ver & 0xff),
665 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
666 strcpy(info->bus_info, pci_name(bp->pdev));
667 info->n_stats = BNX2X_NUM_STATS;
668 info->testinfo_len = BNX2X_NUM_TESTS;
669 info->eedump_len = bp->common.flash_size;
670 info->regdump_len = bnx2x_get_regs_len(dev);
671 }
672
673 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
674 {
675 struct bnx2x *bp = netdev_priv(dev);
676
677 if (bp->flags & NO_WOL_FLAG) {
678 wol->supported = 0;
679 wol->wolopts = 0;
680 } else {
681 wol->supported = WAKE_MAGIC;
682 if (bp->wol)
683 wol->wolopts = WAKE_MAGIC;
684 else
685 wol->wolopts = 0;
686 }
687 memset(&wol->sopass, 0, sizeof(wol->sopass));
688 }
689
690 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
691 {
692 struct bnx2x *bp = netdev_priv(dev);
693
694 if (wol->wolopts & ~WAKE_MAGIC)
695 return -EINVAL;
696
697 if (wol->wolopts & WAKE_MAGIC) {
698 if (bp->flags & NO_WOL_FLAG)
699 return -EINVAL;
700
701 bp->wol = 1;
702 } else
703 bp->wol = 0;
704
705 return 0;
706 }
707
708 static u32 bnx2x_get_msglevel(struct net_device *dev)
709 {
710 struct bnx2x *bp = netdev_priv(dev);
711
712 return bp->msg_enable;
713 }
714
715 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
716 {
717 struct bnx2x *bp = netdev_priv(dev);
718
719 if (capable(CAP_NET_ADMIN)) {
720 /* dump MCP trace */
721 if (level & BNX2X_MSG_MCP)
722 bnx2x_fw_dump_lvl(bp, KERN_INFO);
723 bp->msg_enable = level;
724 }
725 }
726
727 static int bnx2x_nway_reset(struct net_device *dev)
728 {
729 struct bnx2x *bp = netdev_priv(dev);
730
731 if (!bp->port.pmf)
732 return 0;
733
734 if (netif_running(dev)) {
735 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
736 bnx2x_link_set(bp);
737 }
738
739 return 0;
740 }
741
742 static u32 bnx2x_get_link(struct net_device *dev)
743 {
744 struct bnx2x *bp = netdev_priv(dev);
745
746 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
747 return 0;
748
749 return bp->link_vars.link_up;
750 }
751
752 static int bnx2x_get_eeprom_len(struct net_device *dev)
753 {
754 struct bnx2x *bp = netdev_priv(dev);
755
756 return bp->common.flash_size;
757 }
758
759 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
760 {
761 int port = BP_PORT(bp);
762 int count, i;
763 u32 val = 0;
764
765 /* adjust timeout for emulation/FPGA */
766 count = NVRAM_TIMEOUT_COUNT;
767 if (CHIP_REV_IS_SLOW(bp))
768 count *= 100;
769
770 /* request access to nvram interface */
771 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
772 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
773
774 for (i = 0; i < count*10; i++) {
775 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
776 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
777 break;
778
779 udelay(5);
780 }
781
782 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
783 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
784 return -EBUSY;
785 }
786
787 return 0;
788 }
789
790 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
791 {
792 int port = BP_PORT(bp);
793 int count, i;
794 u32 val = 0;
795
796 /* adjust timeout for emulation/FPGA */
797 count = NVRAM_TIMEOUT_COUNT;
798 if (CHIP_REV_IS_SLOW(bp))
799 count *= 100;
800
801 /* relinquish nvram interface */
802 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
803 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
804
805 for (i = 0; i < count*10; i++) {
806 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
807 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
808 break;
809
810 udelay(5);
811 }
812
813 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
814 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
815 return -EBUSY;
816 }
817
818 return 0;
819 }
820
821 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
822 {
823 u32 val;
824
825 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
826
827 /* enable both bits, even on read */
828 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
829 (val | MCPR_NVM_ACCESS_ENABLE_EN |
830 MCPR_NVM_ACCESS_ENABLE_WR_EN));
831 }
832
833 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
834 {
835 u32 val;
836
837 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
838
839 /* disable both bits, even after read */
840 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
841 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
842 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
843 }
844
845 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
846 u32 cmd_flags)
847 {
848 int count, i, rc;
849 u32 val;
850
851 /* build the command word */
852 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
853
854 /* need to clear DONE bit separately */
855 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
856
857 /* address of the NVRAM to read from */
858 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
859 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
860
861 /* issue a read command */
862 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
863
864 /* adjust timeout for emulation/FPGA */
865 count = NVRAM_TIMEOUT_COUNT;
866 if (CHIP_REV_IS_SLOW(bp))
867 count *= 100;
868
869 /* wait for completion */
870 *ret_val = 0;
871 rc = -EBUSY;
872 for (i = 0; i < count; i++) {
873 udelay(5);
874 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
875
876 if (val & MCPR_NVM_COMMAND_DONE) {
877 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
878 /* we read nvram data in cpu order
879 * but ethtool sees it as an array of bytes
880 * converting to big-endian will do the work */
881 *ret_val = cpu_to_be32(val);
882 rc = 0;
883 break;
884 }
885 }
886
887 return rc;
888 }
889
890 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
891 int buf_size)
892 {
893 int rc;
894 u32 cmd_flags;
895 __be32 val;
896
897 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
898 DP(BNX2X_MSG_NVM,
899 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
900 offset, buf_size);
901 return -EINVAL;
902 }
903
904 if (offset + buf_size > bp->common.flash_size) {
905 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
906 " buf_size (0x%x) > flash_size (0x%x)\n",
907 offset, buf_size, bp->common.flash_size);
908 return -EINVAL;
909 }
910
911 /* request access to nvram interface */
912 rc = bnx2x_acquire_nvram_lock(bp);
913 if (rc)
914 return rc;
915
916 /* enable access to nvram interface */
917 bnx2x_enable_nvram_access(bp);
918
919 /* read the first word(s) */
920 cmd_flags = MCPR_NVM_COMMAND_FIRST;
921 while ((buf_size > sizeof(u32)) && (rc == 0)) {
922 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
923 memcpy(ret_buf, &val, 4);
924
925 /* advance to the next dword */
926 offset += sizeof(u32);
927 ret_buf += sizeof(u32);
928 buf_size -= sizeof(u32);
929 cmd_flags = 0;
930 }
931
932 if (rc == 0) {
933 cmd_flags |= MCPR_NVM_COMMAND_LAST;
934 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
935 memcpy(ret_buf, &val, 4);
936 }
937
938 /* disable access to nvram interface */
939 bnx2x_disable_nvram_access(bp);
940 bnx2x_release_nvram_lock(bp);
941
942 return rc;
943 }
944
945 static int bnx2x_get_eeprom(struct net_device *dev,
946 struct ethtool_eeprom *eeprom, u8 *eebuf)
947 {
948 struct bnx2x *bp = netdev_priv(dev);
949 int rc;
950
951 if (!netif_running(dev))
952 return -EAGAIN;
953
954 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
955 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
956 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
957 eeprom->len, eeprom->len);
958
959 /* parameters already validated in ethtool_get_eeprom */
960
961 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
962
963 return rc;
964 }
965
966 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
967 u32 cmd_flags)
968 {
969 int count, i, rc;
970
971 /* build the command word */
972 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
973
974 /* need to clear DONE bit separately */
975 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
976
977 /* write the data */
978 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
979
980 /* address of the NVRAM to write to */
981 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
982 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
983
984 /* issue the write command */
985 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
986
987 /* adjust timeout for emulation/FPGA */
988 count = NVRAM_TIMEOUT_COUNT;
989 if (CHIP_REV_IS_SLOW(bp))
990 count *= 100;
991
992 /* wait for completion */
993 rc = -EBUSY;
994 for (i = 0; i < count; i++) {
995 udelay(5);
996 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
997 if (val & MCPR_NVM_COMMAND_DONE) {
998 rc = 0;
999 break;
1000 }
1001 }
1002
1003 return rc;
1004 }
1005
1006 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1007
1008 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1009 int buf_size)
1010 {
1011 int rc;
1012 u32 cmd_flags;
1013 u32 align_offset;
1014 __be32 val;
1015
1016 if (offset + buf_size > bp->common.flash_size) {
1017 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1018 " buf_size (0x%x) > flash_size (0x%x)\n",
1019 offset, buf_size, bp->common.flash_size);
1020 return -EINVAL;
1021 }
1022
1023 /* request access to nvram interface */
1024 rc = bnx2x_acquire_nvram_lock(bp);
1025 if (rc)
1026 return rc;
1027
1028 /* enable access to nvram interface */
1029 bnx2x_enable_nvram_access(bp);
1030
1031 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1032 align_offset = (offset & ~0x03);
1033 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1034
1035 if (rc == 0) {
1036 val &= ~(0xff << BYTE_OFFSET(offset));
1037 val |= (*data_buf << BYTE_OFFSET(offset));
1038
1039 /* nvram data is returned as an array of bytes
1040 * convert it back to cpu order */
1041 val = be32_to_cpu(val);
1042
1043 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1044 cmd_flags);
1045 }
1046
1047 /* disable access to nvram interface */
1048 bnx2x_disable_nvram_access(bp);
1049 bnx2x_release_nvram_lock(bp);
1050
1051 return rc;
1052 }
1053
1054 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1055 int buf_size)
1056 {
1057 int rc;
1058 u32 cmd_flags;
1059 u32 val;
1060 u32 written_so_far;
1061
1062 if (buf_size == 1) /* ethtool */
1063 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1064
1065 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1066 DP(BNX2X_MSG_NVM,
1067 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1068 offset, buf_size);
1069 return -EINVAL;
1070 }
1071
1072 if (offset + buf_size > bp->common.flash_size) {
1073 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1074 " buf_size (0x%x) > flash_size (0x%x)\n",
1075 offset, buf_size, bp->common.flash_size);
1076 return -EINVAL;
1077 }
1078
1079 /* request access to nvram interface */
1080 rc = bnx2x_acquire_nvram_lock(bp);
1081 if (rc)
1082 return rc;
1083
1084 /* enable access to nvram interface */
1085 bnx2x_enable_nvram_access(bp);
1086
1087 written_so_far = 0;
1088 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1089 while ((written_so_far < buf_size) && (rc == 0)) {
1090 if (written_so_far == (buf_size - sizeof(u32)))
1091 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1092 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1093 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1094 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1095 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1096
1097 memcpy(&val, data_buf, 4);
1098
1099 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1100
1101 /* advance to the next dword */
1102 offset += sizeof(u32);
1103 data_buf += sizeof(u32);
1104 written_so_far += sizeof(u32);
1105 cmd_flags = 0;
1106 }
1107
1108 /* disable access to nvram interface */
1109 bnx2x_disable_nvram_access(bp);
1110 bnx2x_release_nvram_lock(bp);
1111
1112 return rc;
1113 }
1114
1115 static int bnx2x_set_eeprom(struct net_device *dev,
1116 struct ethtool_eeprom *eeprom, u8 *eebuf)
1117 {
1118 struct bnx2x *bp = netdev_priv(dev);
1119 int port = BP_PORT(bp);
1120 int rc = 0;
1121 u32 ext_phy_config;
1122 if (!netif_running(dev))
1123 return -EAGAIN;
1124
1125 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1126 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1127 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1128 eeprom->len, eeprom->len);
1129
1130 /* parameters already validated in ethtool_set_eeprom */
1131
1132 /* PHY eeprom can be accessed only by the PMF */
1133 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1134 !bp->port.pmf)
1135 return -EINVAL;
1136
1137 ext_phy_config =
1138 SHMEM_RD(bp,
1139 dev_info.port_hw_config[port].external_phy_config);
1140
1141 if (eeprom->magic == 0x50485950) {
1142 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1143 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1144
1145 bnx2x_acquire_phy_lock(bp);
1146 rc |= bnx2x_link_reset(&bp->link_params,
1147 &bp->link_vars, 0);
1148 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1149 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1150 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1151 MISC_REGISTERS_GPIO_HIGH, port);
1152 bnx2x_release_phy_lock(bp);
1153 bnx2x_link_report(bp);
1154
1155 } else if (eeprom->magic == 0x50485952) {
1156 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1157 if (bp->state == BNX2X_STATE_OPEN) {
1158 bnx2x_acquire_phy_lock(bp);
1159 rc |= bnx2x_link_reset(&bp->link_params,
1160 &bp->link_vars, 1);
1161
1162 rc |= bnx2x_phy_init(&bp->link_params,
1163 &bp->link_vars);
1164 bnx2x_release_phy_lock(bp);
1165 bnx2x_calc_fc_adv(bp);
1166 }
1167 } else if (eeprom->magic == 0x53985943) {
1168 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1169 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1170 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1171
1172 /* DSP Remove Download Mode */
1173 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1174 MISC_REGISTERS_GPIO_LOW, port);
1175
1176 bnx2x_acquire_phy_lock(bp);
1177
1178 bnx2x_sfx7101_sp_sw_reset(bp,
1179 &bp->link_params.phy[EXT_PHY1]);
1180
1181 /* wait 0.5 sec to allow it to run */
1182 msleep(500);
1183 bnx2x_ext_phy_hw_reset(bp, port);
1184 msleep(500);
1185 bnx2x_release_phy_lock(bp);
1186 }
1187 } else
1188 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1189
1190 return rc;
1191 }
1192
1193 static int bnx2x_get_coalesce(struct net_device *dev,
1194 struct ethtool_coalesce *coal)
1195 {
1196 struct bnx2x *bp = netdev_priv(dev);
1197
1198 memset(coal, 0, sizeof(struct ethtool_coalesce));
1199
1200 coal->rx_coalesce_usecs = bp->rx_ticks;
1201 coal->tx_coalesce_usecs = bp->tx_ticks;
1202
1203 return 0;
1204 }
1205
1206 static int bnx2x_set_coalesce(struct net_device *dev,
1207 struct ethtool_coalesce *coal)
1208 {
1209 struct bnx2x *bp = netdev_priv(dev);
1210
1211 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1212 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1213 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1214
1215 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1216 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1217 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1218
1219 if (netif_running(dev))
1220 bnx2x_update_coalesce(bp);
1221
1222 return 0;
1223 }
1224
1225 static void bnx2x_get_ringparam(struct net_device *dev,
1226 struct ethtool_ringparam *ering)
1227 {
1228 struct bnx2x *bp = netdev_priv(dev);
1229
1230 ering->rx_max_pending = MAX_RX_AVAIL;
1231 ering->rx_mini_max_pending = 0;
1232 ering->rx_jumbo_max_pending = 0;
1233
1234 if (bp->rx_ring_size)
1235 ering->rx_pending = bp->rx_ring_size;
1236 else
1237 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1238 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1239 else
1240 ering->rx_pending = MAX_RX_AVAIL;
1241
1242 ering->rx_mini_pending = 0;
1243 ering->rx_jumbo_pending = 0;
1244
1245 ering->tx_max_pending = MAX_TX_AVAIL;
1246 ering->tx_pending = bp->tx_ring_size;
1247 }
1248
1249 static int bnx2x_set_ringparam(struct net_device *dev,
1250 struct ethtool_ringparam *ering)
1251 {
1252 struct bnx2x *bp = netdev_priv(dev);
1253
1254 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1255 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1256 return -EAGAIN;
1257 }
1258
1259 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1260 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1261 MIN_RX_SIZE_TPA)) ||
1262 (ering->tx_pending > MAX_TX_AVAIL) ||
1263 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1264 return -EINVAL;
1265
1266 bp->rx_ring_size = ering->rx_pending;
1267 bp->tx_ring_size = ering->tx_pending;
1268
1269 return bnx2x_reload_if_running(dev);
1270 }
1271
1272 static void bnx2x_get_pauseparam(struct net_device *dev,
1273 struct ethtool_pauseparam *epause)
1274 {
1275 struct bnx2x *bp = netdev_priv(dev);
1276 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1277 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1278 BNX2X_FLOW_CTRL_AUTO);
1279
1280 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1281 BNX2X_FLOW_CTRL_RX);
1282 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1283 BNX2X_FLOW_CTRL_TX);
1284
1285 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1286 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1287 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1288 }
1289
1290 static int bnx2x_set_pauseparam(struct net_device *dev,
1291 struct ethtool_pauseparam *epause)
1292 {
1293 struct bnx2x *bp = netdev_priv(dev);
1294 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1295 if (IS_MF(bp))
1296 return 0;
1297
1298 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1299 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1300 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1301
1302 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1303
1304 if (epause->rx_pause)
1305 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1306
1307 if (epause->tx_pause)
1308 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1309
1310 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1311 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1312
1313 if (epause->autoneg) {
1314 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1315 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1316 return -EINVAL;
1317 }
1318
1319 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1320 bp->link_params.req_flow_ctrl[cfg_idx] =
1321 BNX2X_FLOW_CTRL_AUTO;
1322 }
1323 }
1324
1325 DP(NETIF_MSG_LINK,
1326 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1327
1328 if (netif_running(dev)) {
1329 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1330 bnx2x_link_set(bp);
1331 }
1332
1333 return 0;
1334 }
1335
1336 static const struct {
1337 char string[ETH_GSTRING_LEN];
1338 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1339 { "register_test (offline)" },
1340 { "memory_test (offline)" },
1341 { "loopback_test (offline)" },
1342 { "nvram_test (online)" },
1343 { "interrupt_test (online)" },
1344 { "link_test (online)" },
1345 { "idle check (online)" }
1346 };
1347
1348 enum {
1349 BNX2X_CHIP_E1_OFST = 0,
1350 BNX2X_CHIP_E1H_OFST,
1351 BNX2X_CHIP_E2_OFST,
1352 BNX2X_CHIP_E3_OFST,
1353 BNX2X_CHIP_E3B0_OFST,
1354 BNX2X_CHIP_MAX_OFST
1355 };
1356
1357 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1358 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1359 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1360 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1361 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1362
1363 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1364 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1365
1366 static int bnx2x_test_registers(struct bnx2x *bp)
1367 {
1368 int idx, i, rc = -ENODEV;
1369 u32 wr_val = 0, hw;
1370 int port = BP_PORT(bp);
1371 static const struct {
1372 u32 hw;
1373 u32 offset0;
1374 u32 offset1;
1375 u32 mask;
1376 } reg_tbl[] = {
1377 /* 0 */ { BNX2X_CHIP_MASK_ALL,
1378 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1379 { BNX2X_CHIP_MASK_ALL,
1380 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1381 { BNX2X_CHIP_MASK_E1X,
1382 HC_REG_AGG_INT_0, 4, 0x000003ff },
1383 { BNX2X_CHIP_MASK_ALL,
1384 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1385 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1386 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1387 { BNX2X_CHIP_MASK_E3B0,
1388 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1389 { BNX2X_CHIP_MASK_ALL,
1390 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1391 { BNX2X_CHIP_MASK_ALL,
1392 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1393 { BNX2X_CHIP_MASK_ALL,
1394 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1395 { BNX2X_CHIP_MASK_ALL,
1396 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1397 /* 10 */ { BNX2X_CHIP_MASK_ALL,
1398 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1399 { BNX2X_CHIP_MASK_ALL,
1400 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1401 { BNX2X_CHIP_MASK_ALL,
1402 QM_REG_CONNNUM_0, 4, 0x000fffff },
1403 { BNX2X_CHIP_MASK_ALL,
1404 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1405 { BNX2X_CHIP_MASK_ALL,
1406 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1407 { BNX2X_CHIP_MASK_ALL,
1408 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1409 { BNX2X_CHIP_MASK_ALL,
1410 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1411 { BNX2X_CHIP_MASK_ALL,
1412 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1413 { BNX2X_CHIP_MASK_ALL,
1414 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1415 { BNX2X_CHIP_MASK_ALL,
1416 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1417 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1418 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1419 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1420 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1421 { BNX2X_CHIP_MASK_ALL,
1422 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1423 { BNX2X_CHIP_MASK_ALL,
1424 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1425 { BNX2X_CHIP_MASK_ALL,
1426 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1427 { BNX2X_CHIP_MASK_ALL,
1428 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1429 { BNX2X_CHIP_MASK_ALL,
1430 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1431 { BNX2X_CHIP_MASK_ALL,
1432 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1433 { BNX2X_CHIP_MASK_ALL,
1434 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1435 { BNX2X_CHIP_MASK_ALL,
1436 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1437 /* 30 */ { BNX2X_CHIP_MASK_ALL,
1438 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1439 { BNX2X_CHIP_MASK_ALL,
1440 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1441 { BNX2X_CHIP_MASK_ALL,
1442 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1443 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1444 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1445 { BNX2X_CHIP_MASK_ALL,
1446 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1447 { BNX2X_CHIP_MASK_ALL,
1448 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1449 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1450 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1451 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1452 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1453
1454 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1455 };
1456
1457 if (!netif_running(bp->dev))
1458 return rc;
1459
1460 if (CHIP_IS_E1(bp))
1461 hw = BNX2X_CHIP_MASK_E1;
1462 else if (CHIP_IS_E1H(bp))
1463 hw = BNX2X_CHIP_MASK_E1H;
1464 else if (CHIP_IS_E2(bp))
1465 hw = BNX2X_CHIP_MASK_E2;
1466 else if (CHIP_IS_E3B0(bp))
1467 hw = BNX2X_CHIP_MASK_E3B0;
1468 else /* e3 A0 */
1469 hw = BNX2X_CHIP_MASK_E3;
1470
1471 /* Repeat the test twice:
1472 First by writing 0x00000000, second by writing 0xffffffff */
1473 for (idx = 0; idx < 2; idx++) {
1474
1475 switch (idx) {
1476 case 0:
1477 wr_val = 0;
1478 break;
1479 case 1:
1480 wr_val = 0xffffffff;
1481 break;
1482 }
1483
1484 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1485 u32 offset, mask, save_val, val;
1486 if (!(hw & reg_tbl[i].hw))
1487 continue;
1488
1489 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1490 mask = reg_tbl[i].mask;
1491
1492 save_val = REG_RD(bp, offset);
1493
1494 REG_WR(bp, offset, wr_val & mask);
1495
1496 val = REG_RD(bp, offset);
1497
1498 /* Restore the original register's value */
1499 REG_WR(bp, offset, save_val);
1500
1501 /* verify value is as expected */
1502 if ((val & mask) != (wr_val & mask)) {
1503 DP(NETIF_MSG_HW,
1504 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1505 offset, val, wr_val, mask);
1506 goto test_reg_exit;
1507 }
1508 }
1509 }
1510
1511 rc = 0;
1512
1513 test_reg_exit:
1514 return rc;
1515 }
1516
1517 static int bnx2x_test_memory(struct bnx2x *bp)
1518 {
1519 int i, j, rc = -ENODEV;
1520 u32 val, index;
1521 static const struct {
1522 u32 offset;
1523 int size;
1524 } mem_tbl[] = {
1525 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1526 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1527 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1528 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1529 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1530 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1531 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1532
1533 { 0xffffffff, 0 }
1534 };
1535
1536 static const struct {
1537 char *name;
1538 u32 offset;
1539 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1540 } prty_tbl[] = {
1541 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1542 {0x3ffc0, 0, 0, 0} },
1543 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1544 {0x2, 0x2, 0, 0} },
1545 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1546 {0, 0, 0, 0} },
1547 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1548 {0x3ffc0, 0, 0, 0} },
1549 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1550 {0x3ffc0, 0, 0, 0} },
1551 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1552 {0x3ffc1, 0, 0, 0} },
1553
1554 { NULL, 0xffffffff, {0, 0, 0, 0} }
1555 };
1556
1557 if (!netif_running(bp->dev))
1558 return rc;
1559
1560 if (CHIP_IS_E1(bp))
1561 index = BNX2X_CHIP_E1_OFST;
1562 else if (CHIP_IS_E1H(bp))
1563 index = BNX2X_CHIP_E1H_OFST;
1564 else if (CHIP_IS_E2(bp))
1565 index = BNX2X_CHIP_E2_OFST;
1566 else /* e3 */
1567 index = BNX2X_CHIP_E3_OFST;
1568
1569 /* pre-Check the parity status */
1570 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1571 val = REG_RD(bp, prty_tbl[i].offset);
1572 if (val & ~(prty_tbl[i].hw_mask[index])) {
1573 DP(NETIF_MSG_HW,
1574 "%s is 0x%x\n", prty_tbl[i].name, val);
1575 goto test_mem_exit;
1576 }
1577 }
1578
1579 /* Go through all the memories */
1580 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1581 for (j = 0; j < mem_tbl[i].size; j++)
1582 REG_RD(bp, mem_tbl[i].offset + j*4);
1583
1584 /* Check the parity status */
1585 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1586 val = REG_RD(bp, prty_tbl[i].offset);
1587 if (val & ~(prty_tbl[i].hw_mask[index])) {
1588 DP(NETIF_MSG_HW,
1589 "%s is 0x%x\n", prty_tbl[i].name, val);
1590 goto test_mem_exit;
1591 }
1592 }
1593
1594 rc = 0;
1595
1596 test_mem_exit:
1597 return rc;
1598 }
1599
1600 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1601 {
1602 int cnt = 1400;
1603
1604 if (link_up) {
1605 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1606 msleep(20);
1607
1608 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1609 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1610 }
1611 }
1612
1613 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1614 {
1615 unsigned int pkt_size, num_pkts, i;
1616 struct sk_buff *skb;
1617 unsigned char *packet;
1618 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1619 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1620 u16 tx_start_idx, tx_idx;
1621 u16 rx_start_idx, rx_idx;
1622 u16 pkt_prod, bd_prod, rx_comp_cons;
1623 struct sw_tx_bd *tx_buf;
1624 struct eth_tx_start_bd *tx_start_bd;
1625 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1626 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
1627 dma_addr_t mapping;
1628 union eth_rx_cqe *cqe;
1629 u8 cqe_fp_flags, cqe_fp_type;
1630 struct sw_rx_bd *rx_buf;
1631 u16 len;
1632 int rc = -ENODEV;
1633
1634 /* check the loopback mode */
1635 switch (loopback_mode) {
1636 case BNX2X_PHY_LOOPBACK:
1637 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1638 return -EINVAL;
1639 break;
1640 case BNX2X_MAC_LOOPBACK:
1641 bp->link_params.loopback_mode = CHIP_IS_E3(bp) ?
1642 LOOPBACK_XMAC : LOOPBACK_BMAC;
1643 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1644 break;
1645 default:
1646 return -EINVAL;
1647 }
1648
1649 /* prepare the loopback packet */
1650 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1651 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1652 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1653 if (!skb) {
1654 rc = -ENOMEM;
1655 goto test_loopback_exit;
1656 }
1657 packet = skb_put(skb, pkt_size);
1658 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1659 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1660 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1661 for (i = ETH_HLEN; i < pkt_size; i++)
1662 packet[i] = (unsigned char) (i & 0xff);
1663 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1664 skb_headlen(skb), DMA_TO_DEVICE);
1665 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1666 rc = -ENOMEM;
1667 dev_kfree_skb(skb);
1668 BNX2X_ERR("Unable to map SKB\n");
1669 goto test_loopback_exit;
1670 }
1671
1672 /* send the loopback packet */
1673 num_pkts = 0;
1674 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1675 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1676
1677 pkt_prod = fp_tx->tx_pkt_prod++;
1678 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1679 tx_buf->first_bd = fp_tx->tx_bd_prod;
1680 tx_buf->skb = skb;
1681 tx_buf->flags = 0;
1682
1683 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1684 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1685 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1686 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1687 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1688 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1689 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1690 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1691 SET_FLAG(tx_start_bd->general_data,
1692 ETH_TX_START_BD_ETH_ADDR_TYPE,
1693 UNICAST_ADDRESS);
1694 SET_FLAG(tx_start_bd->general_data,
1695 ETH_TX_START_BD_HDR_NBDS,
1696 1);
1697
1698 /* turn on parsing and get a BD */
1699 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1700
1701 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1702 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1703
1704 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1705 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1706
1707 wmb();
1708
1709 fp_tx->tx_db.data.prod += 2;
1710 barrier();
1711 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1712
1713 mmiowb();
1714 barrier();
1715
1716 num_pkts++;
1717 fp_tx->tx_bd_prod += 2; /* start + pbd */
1718
1719 udelay(100);
1720
1721 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1722 if (tx_idx != tx_start_idx + num_pkts)
1723 goto test_loopback_exit;
1724
1725 /* Unlike HC IGU won't generate an interrupt for status block
1726 * updates that have been performed while interrupts were
1727 * disabled.
1728 */
1729 if (bp->common.int_block == INT_BLOCK_IGU) {
1730 /* Disable local BHes to prevent a dead-lock situation between
1731 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1732 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1733 */
1734 local_bh_disable();
1735 bnx2x_tx_int(fp_tx);
1736 local_bh_enable();
1737 }
1738
1739 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1740 if (rx_idx != rx_start_idx + num_pkts)
1741 goto test_loopback_exit;
1742
1743 rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1744 cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
1745 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1746 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1747 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1748 goto test_loopback_rx_exit;
1749
1750 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1751 if (len != pkt_size)
1752 goto test_loopback_rx_exit;
1753
1754 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1755 dma_sync_single_for_device(&bp->pdev->dev,
1756 dma_unmap_addr(rx_buf, mapping),
1757 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
1758 skb = rx_buf->skb;
1759 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1760 for (i = ETH_HLEN; i < pkt_size; i++)
1761 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1762 goto test_loopback_rx_exit;
1763
1764 rc = 0;
1765
1766 test_loopback_rx_exit:
1767
1768 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1769 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1770 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1771 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1772
1773 /* Update producers */
1774 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1775 fp_rx->rx_sge_prod);
1776
1777 test_loopback_exit:
1778 bp->link_params.loopback_mode = LOOPBACK_NONE;
1779
1780 return rc;
1781 }
1782
1783 static int bnx2x_test_loopback(struct bnx2x *bp)
1784 {
1785 int rc = 0, res;
1786
1787 if (BP_NOMCP(bp))
1788 return rc;
1789
1790 if (!netif_running(bp->dev))
1791 return BNX2X_LOOPBACK_FAILED;
1792
1793 bnx2x_netif_stop(bp, 1);
1794 bnx2x_acquire_phy_lock(bp);
1795
1796 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
1797 if (res) {
1798 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1799 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1800 }
1801
1802 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
1803 if (res) {
1804 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1805 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1806 }
1807
1808 bnx2x_release_phy_lock(bp);
1809 bnx2x_netif_start(bp);
1810
1811 return rc;
1812 }
1813
1814 #define CRC32_RESIDUAL 0xdebb20e3
1815
1816 static int bnx2x_test_nvram(struct bnx2x *bp)
1817 {
1818 static const struct {
1819 int offset;
1820 int size;
1821 } nvram_tbl[] = {
1822 { 0, 0x14 }, /* bootstrap */
1823 { 0x14, 0xec }, /* dir */
1824 { 0x100, 0x350 }, /* manuf_info */
1825 { 0x450, 0xf0 }, /* feature_info */
1826 { 0x640, 0x64 }, /* upgrade_key_info */
1827 { 0x708, 0x70 }, /* manuf_key_info */
1828 { 0, 0 }
1829 };
1830 __be32 buf[0x350 / 4];
1831 u8 *data = (u8 *)buf;
1832 int i, rc;
1833 u32 magic, crc;
1834
1835 if (BP_NOMCP(bp))
1836 return 0;
1837
1838 rc = bnx2x_nvram_read(bp, 0, data, 4);
1839 if (rc) {
1840 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1841 goto test_nvram_exit;
1842 }
1843
1844 magic = be32_to_cpu(buf[0]);
1845 if (magic != 0x669955aa) {
1846 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1847 rc = -ENODEV;
1848 goto test_nvram_exit;
1849 }
1850
1851 for (i = 0; nvram_tbl[i].size; i++) {
1852
1853 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1854 nvram_tbl[i].size);
1855 if (rc) {
1856 DP(NETIF_MSG_PROBE,
1857 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1858 goto test_nvram_exit;
1859 }
1860
1861 crc = ether_crc_le(nvram_tbl[i].size, data);
1862 if (crc != CRC32_RESIDUAL) {
1863 DP(NETIF_MSG_PROBE,
1864 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1865 rc = -ENODEV;
1866 goto test_nvram_exit;
1867 }
1868 }
1869
1870 test_nvram_exit:
1871 return rc;
1872 }
1873
1874 /* Send an EMPTY ramrod on the first queue */
1875 static int bnx2x_test_intr(struct bnx2x *bp)
1876 {
1877 struct bnx2x_queue_state_params params = {0};
1878
1879 if (!netif_running(bp->dev))
1880 return -ENODEV;
1881
1882 params.q_obj = &bp->fp->q_obj;
1883 params.cmd = BNX2X_Q_CMD_EMPTY;
1884
1885 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1886
1887 return bnx2x_queue_state_change(bp, &params);
1888 }
1889
1890 static void bnx2x_self_test(struct net_device *dev,
1891 struct ethtool_test *etest, u64 *buf)
1892 {
1893 struct bnx2x *bp = netdev_priv(dev);
1894 u8 is_serdes;
1895 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1896 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1897 etest->flags |= ETH_TEST_FL_FAILED;
1898 return;
1899 }
1900
1901 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1902
1903 if (!netif_running(dev))
1904 return;
1905
1906 /* offline tests are not supported in MF mode */
1907 if (IS_MF(bp))
1908 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1909 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1910
1911 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1912 int port = BP_PORT(bp);
1913 u32 val;
1914 u8 link_up;
1915
1916 /* save current value of input enable for TX port IF */
1917 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1918 /* disable input for TX port IF */
1919 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1920
1921 link_up = bp->link_vars.link_up;
1922
1923 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1924 bnx2x_nic_load(bp, LOAD_DIAG);
1925 /* wait until link state is restored */
1926 bnx2x_wait_for_link(bp, 1, is_serdes);
1927
1928 if (bnx2x_test_registers(bp) != 0) {
1929 buf[0] = 1;
1930 etest->flags |= ETH_TEST_FL_FAILED;
1931 }
1932 if (bnx2x_test_memory(bp) != 0) {
1933 buf[1] = 1;
1934 etest->flags |= ETH_TEST_FL_FAILED;
1935 }
1936
1937 buf[2] = bnx2x_test_loopback(bp);
1938 if (buf[2] != 0)
1939 etest->flags |= ETH_TEST_FL_FAILED;
1940
1941 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1942
1943 /* restore input for TX port IF */
1944 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1945
1946 bnx2x_nic_load(bp, LOAD_NORMAL);
1947 /* wait until link state is restored */
1948 bnx2x_wait_for_link(bp, link_up, is_serdes);
1949 }
1950 if (bnx2x_test_nvram(bp) != 0) {
1951 buf[3] = 1;
1952 etest->flags |= ETH_TEST_FL_FAILED;
1953 }
1954 if (bnx2x_test_intr(bp) != 0) {
1955 buf[4] = 1;
1956 etest->flags |= ETH_TEST_FL_FAILED;
1957 }
1958
1959 if (bnx2x_link_test(bp, is_serdes) != 0) {
1960 buf[5] = 1;
1961 etest->flags |= ETH_TEST_FL_FAILED;
1962 }
1963
1964 #ifdef BNX2X_EXTRA_DEBUG
1965 bnx2x_panic_dump(bp);
1966 #endif
1967 }
1968
1969 #define IS_PORT_STAT(i) \
1970 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1971 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1972 #define IS_MF_MODE_STAT(bp) \
1973 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1974
1975 /* ethtool statistics are displayed for all regular ethernet queues and the
1976 * fcoe L2 queue if not disabled
1977 */
1978 static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
1979 {
1980 return BNX2X_NUM_ETH_QUEUES(bp);
1981 }
1982
1983 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1984 {
1985 struct bnx2x *bp = netdev_priv(dev);
1986 int i, num_stats;
1987
1988 switch (stringset) {
1989 case ETH_SS_STATS:
1990 if (is_multi(bp)) {
1991 num_stats = bnx2x_num_stat_queues(bp) *
1992 BNX2X_NUM_Q_STATS;
1993 if (!IS_MF_MODE_STAT(bp))
1994 num_stats += BNX2X_NUM_STATS;
1995 } else {
1996 if (IS_MF_MODE_STAT(bp)) {
1997 num_stats = 0;
1998 for (i = 0; i < BNX2X_NUM_STATS; i++)
1999 if (IS_FUNC_STAT(i))
2000 num_stats++;
2001 } else
2002 num_stats = BNX2X_NUM_STATS;
2003 }
2004 return num_stats;
2005
2006 case ETH_SS_TEST:
2007 return BNX2X_NUM_TESTS;
2008
2009 default:
2010 return -EINVAL;
2011 }
2012 }
2013
2014 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2015 {
2016 struct bnx2x *bp = netdev_priv(dev);
2017 int i, j, k;
2018 char queue_name[MAX_QUEUE_NAME_LEN+1];
2019
2020 switch (stringset) {
2021 case ETH_SS_STATS:
2022 if (is_multi(bp)) {
2023 k = 0;
2024 for_each_eth_queue(bp, i) {
2025 memset(queue_name, 0, sizeof(queue_name));
2026 sprintf(queue_name, "%d", i);
2027 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2028 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2029 ETH_GSTRING_LEN,
2030 bnx2x_q_stats_arr[j].string,
2031 queue_name);
2032 k += BNX2X_NUM_Q_STATS;
2033 }
2034 if (IS_MF_MODE_STAT(bp))
2035 break;
2036 for (j = 0; j < BNX2X_NUM_STATS; j++)
2037 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2038 bnx2x_stats_arr[j].string);
2039 } else {
2040 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2041 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2042 continue;
2043 strcpy(buf + j*ETH_GSTRING_LEN,
2044 bnx2x_stats_arr[i].string);
2045 j++;
2046 }
2047 }
2048 break;
2049
2050 case ETH_SS_TEST:
2051 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2052 break;
2053 }
2054 }
2055
2056 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2057 struct ethtool_stats *stats, u64 *buf)
2058 {
2059 struct bnx2x *bp = netdev_priv(dev);
2060 u32 *hw_stats, *offset;
2061 int i, j, k;
2062
2063 if (is_multi(bp)) {
2064 k = 0;
2065 for_each_eth_queue(bp, i) {
2066 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2067 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2068 if (bnx2x_q_stats_arr[j].size == 0) {
2069 /* skip this counter */
2070 buf[k + j] = 0;
2071 continue;
2072 }
2073 offset = (hw_stats +
2074 bnx2x_q_stats_arr[j].offset);
2075 if (bnx2x_q_stats_arr[j].size == 4) {
2076 /* 4-byte counter */
2077 buf[k + j] = (u64) *offset;
2078 continue;
2079 }
2080 /* 8-byte counter */
2081 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2082 }
2083 k += BNX2X_NUM_Q_STATS;
2084 }
2085 if (IS_MF_MODE_STAT(bp))
2086 return;
2087 hw_stats = (u32 *)&bp->eth_stats;
2088 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2089 if (bnx2x_stats_arr[j].size == 0) {
2090 /* skip this counter */
2091 buf[k + j] = 0;
2092 continue;
2093 }
2094 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2095 if (bnx2x_stats_arr[j].size == 4) {
2096 /* 4-byte counter */
2097 buf[k + j] = (u64) *offset;
2098 continue;
2099 }
2100 /* 8-byte counter */
2101 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2102 }
2103 } else {
2104 hw_stats = (u32 *)&bp->eth_stats;
2105 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2106 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2107 continue;
2108 if (bnx2x_stats_arr[i].size == 0) {
2109 /* skip this counter */
2110 buf[j] = 0;
2111 j++;
2112 continue;
2113 }
2114 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2115 if (bnx2x_stats_arr[i].size == 4) {
2116 /* 4-byte counter */
2117 buf[j] = (u64) *offset;
2118 j++;
2119 continue;
2120 }
2121 /* 8-byte counter */
2122 buf[j] = HILO_U64(*offset, *(offset + 1));
2123 j++;
2124 }
2125 }
2126 }
2127
2128 static int bnx2x_set_phys_id(struct net_device *dev,
2129 enum ethtool_phys_id_state state)
2130 {
2131 struct bnx2x *bp = netdev_priv(dev);
2132
2133 if (!netif_running(dev))
2134 return -EAGAIN;
2135
2136 if (!bp->port.pmf)
2137 return -EOPNOTSUPP;
2138
2139 switch (state) {
2140 case ETHTOOL_ID_ACTIVE:
2141 return 1; /* cycle on/off once per second */
2142
2143 case ETHTOOL_ID_ON:
2144 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2145 LED_MODE_ON, SPEED_1000);
2146 break;
2147
2148 case ETHTOOL_ID_OFF:
2149 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2150 LED_MODE_FRONT_PANEL_OFF, 0);
2151
2152 break;
2153
2154 case ETHTOOL_ID_INACTIVE:
2155 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2156 LED_MODE_OPER,
2157 bp->link_vars.line_speed);
2158 }
2159
2160 return 0;
2161 }
2162
2163 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2164 void *rules __always_unused)
2165 {
2166 struct bnx2x *bp = netdev_priv(dev);
2167
2168 switch (info->cmd) {
2169 case ETHTOOL_GRXRINGS:
2170 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2171 return 0;
2172
2173 default:
2174 return -EOPNOTSUPP;
2175 }
2176 }
2177
2178 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2179 struct ethtool_rxfh_indir *indir)
2180 {
2181 struct bnx2x *bp = netdev_priv(dev);
2182 size_t copy_size =
2183 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE);
2184 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2185 size_t i;
2186
2187 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2188 return -EOPNOTSUPP;
2189
2190 /* Get the current configuration of the RSS indirection table */
2191 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2192
2193 /*
2194 * We can't use a memcpy() as an internal storage of an
2195 * indirection table is a u8 array while indir->ring_index
2196 * points to an array of u32.
2197 *
2198 * Indirection table contains the FW Client IDs, so we need to
2199 * align the returned table to the Client ID of the leading RSS
2200 * queue.
2201 */
2202 for (i = 0; i < copy_size; i++)
2203 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id;
2204
2205 indir->size = T_ETH_INDIRECTION_TABLE_SIZE;
2206
2207 return 0;
2208 }
2209
2210 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2211 const struct ethtool_rxfh_indir *indir)
2212 {
2213 struct bnx2x *bp = netdev_priv(dev);
2214 size_t i;
2215 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2216 u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2217
2218 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2219 return -EOPNOTSUPP;
2220
2221 /* validate the size */
2222 if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE)
2223 return -EINVAL;
2224
2225 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2226 /* validate the indices */
2227 if (indir->ring_index[i] >= num_eth_queues)
2228 return -EINVAL;
2229 /*
2230 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2231 * as an internal storage of an indirection table is a u8 array
2232 * while indir->ring_index points to an array of u32.
2233 *
2234 * Indirection table contains the FW Client IDs, so we need to
2235 * align the received table to the Client ID of the leading RSS
2236 * queue
2237 */
2238 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id;
2239 }
2240
2241 return bnx2x_config_rss_pf(bp, ind_table, false);
2242 }
2243
2244 static const struct ethtool_ops bnx2x_ethtool_ops = {
2245 .get_settings = bnx2x_get_settings,
2246 .set_settings = bnx2x_set_settings,
2247 .get_drvinfo = bnx2x_get_drvinfo,
2248 .get_regs_len = bnx2x_get_regs_len,
2249 .get_regs = bnx2x_get_regs,
2250 .get_wol = bnx2x_get_wol,
2251 .set_wol = bnx2x_set_wol,
2252 .get_msglevel = bnx2x_get_msglevel,
2253 .set_msglevel = bnx2x_set_msglevel,
2254 .nway_reset = bnx2x_nway_reset,
2255 .get_link = bnx2x_get_link,
2256 .get_eeprom_len = bnx2x_get_eeprom_len,
2257 .get_eeprom = bnx2x_get_eeprom,
2258 .set_eeprom = bnx2x_set_eeprom,
2259 .get_coalesce = bnx2x_get_coalesce,
2260 .set_coalesce = bnx2x_set_coalesce,
2261 .get_ringparam = bnx2x_get_ringparam,
2262 .set_ringparam = bnx2x_set_ringparam,
2263 .get_pauseparam = bnx2x_get_pauseparam,
2264 .set_pauseparam = bnx2x_set_pauseparam,
2265 .self_test = bnx2x_self_test,
2266 .get_sset_count = bnx2x_get_sset_count,
2267 .get_strings = bnx2x_get_strings,
2268 .set_phys_id = bnx2x_set_phys_id,
2269 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2270 .get_rxnfc = bnx2x_get_rxnfc,
2271 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2272 .set_rxfh_indir = bnx2x_set_rxfh_indir,
2273 };
2274
2275 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2276 {
2277 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2278 }
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