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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[mirror_ubuntu-zesty-kernel.git] / drivers / net / bnx2x / bnx2x_ethtool.c
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #include <linux/ethtool.h>
18 #include <linux/netdevice.h>
19 #include <linux/types.h>
20 #include <linux/sched.h>
21 #include <linux/crc32.h>
22
23
24 #include "bnx2x.h"
25 #include "bnx2x_cmn.h"
26 #include "bnx2x_dump.h"
27 #include "bnx2x_init.h"
28
29 /* Note: in the format strings below %s is replaced by the queue-name which is
30 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
31 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
32 */
33 #define MAX_QUEUE_NAME_LEN 4
34 static const struct {
35 long offset;
36 int size;
37 char string[ETH_GSTRING_LEN];
38 } bnx2x_q_stats_arr[] = {
39 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
40 { Q_STATS_OFFSET32(error_bytes_received_hi),
41 8, "[%s]: rx_error_bytes" },
42 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
43 8, "[%s]: rx_ucast_packets" },
44 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
45 8, "[%s]: rx_mcast_packets" },
46 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
47 8, "[%s]: rx_bcast_packets" },
48 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
49 { Q_STATS_OFFSET32(rx_err_discard_pkt),
50 4, "[%s]: rx_phy_ip_err_discards"},
51 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
52 4, "[%s]: rx_skb_alloc_discard" },
53 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
54
55 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
56 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
57 8, "[%s]: tx_ucast_packets" },
58 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
59 8, "[%s]: tx_mcast_packets" },
60 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
61 8, "[%s]: tx_bcast_packets" }
62 };
63
64 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
65
66 static const struct {
67 long offset;
68 int size;
69 u32 flags;
70 #define STATS_FLAGS_PORT 1
71 #define STATS_FLAGS_FUNC 2
72 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
73 char string[ETH_GSTRING_LEN];
74 } bnx2x_stats_arr[] = {
75 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
76 8, STATS_FLAGS_BOTH, "rx_bytes" },
77 { STATS_OFFSET32(error_bytes_received_hi),
78 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
79 { STATS_OFFSET32(total_unicast_packets_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
81 { STATS_OFFSET32(total_multicast_packets_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
83 { STATS_OFFSET32(total_broadcast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
85 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
86 8, STATS_FLAGS_PORT, "rx_crc_errors" },
87 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
88 8, STATS_FLAGS_PORT, "rx_align_errors" },
89 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
90 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
91 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
92 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
93 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
94 8, STATS_FLAGS_PORT, "rx_fragments" },
95 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
96 8, STATS_FLAGS_PORT, "rx_jabbers" },
97 { STATS_OFFSET32(no_buff_discard_hi),
98 8, STATS_FLAGS_BOTH, "rx_discards" },
99 { STATS_OFFSET32(mac_filter_discard),
100 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
101 { STATS_OFFSET32(xxoverflow_discard),
102 4, STATS_FLAGS_PORT, "rx_fw_discards" },
103 { STATS_OFFSET32(brb_drop_hi),
104 8, STATS_FLAGS_PORT, "rx_brb_discard" },
105 { STATS_OFFSET32(brb_truncate_hi),
106 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
107 { STATS_OFFSET32(pause_frames_received_hi),
108 8, STATS_FLAGS_PORT, "rx_pause_frames" },
109 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
110 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
111 { STATS_OFFSET32(nig_timer_max),
112 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
113 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
114 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
115 { STATS_OFFSET32(rx_skb_alloc_failed),
116 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
117 { STATS_OFFSET32(hw_csum_err),
118 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
119
120 { STATS_OFFSET32(total_bytes_transmitted_hi),
121 8, STATS_FLAGS_BOTH, "tx_bytes" },
122 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
123 8, STATS_FLAGS_PORT, "tx_error_bytes" },
124 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
126 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
127 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
128 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
130 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
131 8, STATS_FLAGS_PORT, "tx_mac_errors" },
132 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
133 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
134 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
135 8, STATS_FLAGS_PORT, "tx_single_collisions" },
136 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
137 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
138 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
139 8, STATS_FLAGS_PORT, "tx_deferred" },
140 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
141 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
143 8, STATS_FLAGS_PORT, "tx_late_collisions" },
144 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_total_collisions" },
146 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
147 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
148 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
149 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
151 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
153 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
154 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
155 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
156 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
157 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
158 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
159 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
160 { STATS_OFFSET32(pause_frames_sent_hi),
161 8, STATS_FLAGS_PORT, "tx_pause_frames" }
162 };
163
164 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
165 static int bnx2x_get_port_type(struct bnx2x *bp)
166 {
167 int port_type;
168 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
169 switch (bp->link_params.phy[phy_idx].media_type) {
170 case ETH_PHY_SFP_FIBER:
171 case ETH_PHY_XFP_FIBER:
172 case ETH_PHY_KR:
173 case ETH_PHY_CX4:
174 port_type = PORT_FIBRE;
175 break;
176 case ETH_PHY_DA_TWINAX:
177 port_type = PORT_DA;
178 break;
179 case ETH_PHY_BASE_T:
180 port_type = PORT_TP;
181 break;
182 case ETH_PHY_NOT_PRESENT:
183 port_type = PORT_NONE;
184 break;
185 case ETH_PHY_UNSPECIFIED:
186 default:
187 port_type = PORT_OTHER;
188 break;
189 }
190 return port_type;
191 }
192
193 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
194 {
195 struct bnx2x *bp = netdev_priv(dev);
196 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
197
198 /* Dual Media boards present all available port types */
199 cmd->supported = bp->port.supported[cfg_idx] |
200 (bp->port.supported[cfg_idx ^ 1] &
201 (SUPPORTED_TP | SUPPORTED_FIBRE));
202 cmd->advertising = bp->port.advertising[cfg_idx];
203
204 if ((bp->state == BNX2X_STATE_OPEN) &&
205 !(bp->flags & MF_FUNC_DIS) &&
206 (bp->link_vars.link_up)) {
207 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
208 cmd->duplex = bp->link_vars.duplex;
209 } else {
210 ethtool_cmd_speed_set(
211 cmd, bp->link_params.req_line_speed[cfg_idx]);
212 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
213 }
214
215 if (IS_MF(bp))
216 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
217
218 cmd->port = bnx2x_get_port_type(bp);
219
220 cmd->phy_address = bp->mdio.prtad;
221 cmd->transceiver = XCVR_INTERNAL;
222
223 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
224 cmd->autoneg = AUTONEG_ENABLE;
225 else
226 cmd->autoneg = AUTONEG_DISABLE;
227
228 cmd->maxtxpkt = 0;
229 cmd->maxrxpkt = 0;
230
231 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
232 DP_LEVEL " supported 0x%x advertising 0x%x speed %u\n"
233 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
234 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
235 cmd->cmd, cmd->supported, cmd->advertising,
236 ethtool_cmd_speed(cmd),
237 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
238 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
239
240 return 0;
241 }
242
243 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
244 {
245 struct bnx2x *bp = netdev_priv(dev);
246 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
247 u32 speed;
248
249 if (IS_MF_SD(bp))
250 return 0;
251
252 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
253 " supported 0x%x advertising 0x%x speed %u\n"
254 " duplex %d port %d phy_address %d transceiver %d\n"
255 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
256 cmd->cmd, cmd->supported, cmd->advertising,
257 ethtool_cmd_speed(cmd),
258 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
259 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
260
261 speed = ethtool_cmd_speed(cmd);
262
263 if (IS_MF_SI(bp)) {
264 u32 part;
265 u32 line_speed = bp->link_vars.line_speed;
266
267 /* use 10G if no link detected */
268 if (!line_speed)
269 line_speed = 10000;
270
271 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
272 BNX2X_DEV_INFO("To set speed BC %X or higher "
273 "is required, please upgrade BC\n",
274 REQ_BC_VER_4_SET_MF_BW);
275 return -EINVAL;
276 }
277
278 part = (speed * 100) / line_speed;
279
280 if (line_speed < speed || !part) {
281 BNX2X_DEV_INFO("Speed setting should be in a range "
282 "from 1%% to 100%% "
283 "of actual line speed\n");
284 return -EINVAL;
285 }
286
287 if (bp->state != BNX2X_STATE_OPEN)
288 /* store value for following "load" */
289 bp->pending_max = part;
290 else
291 bnx2x_update_max_mf_config(bp, part);
292
293 return 0;
294 }
295
296 cfg_idx = bnx2x_get_link_cfg_idx(bp);
297 old_multi_phy_config = bp->link_params.multi_phy_config;
298 switch (cmd->port) {
299 case PORT_TP:
300 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
301 break; /* no port change */
302
303 if (!(bp->port.supported[0] & SUPPORTED_TP ||
304 bp->port.supported[1] & SUPPORTED_TP)) {
305 DP(NETIF_MSG_LINK, "Unsupported port type\n");
306 return -EINVAL;
307 }
308 bp->link_params.multi_phy_config &=
309 ~PORT_HW_CFG_PHY_SELECTION_MASK;
310 if (bp->link_params.multi_phy_config &
311 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
312 bp->link_params.multi_phy_config |=
313 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
314 else
315 bp->link_params.multi_phy_config |=
316 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
317 break;
318 case PORT_FIBRE:
319 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
320 break; /* no port change */
321
322 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
323 bp->port.supported[1] & SUPPORTED_FIBRE)) {
324 DP(NETIF_MSG_LINK, "Unsupported port type\n");
325 return -EINVAL;
326 }
327 bp->link_params.multi_phy_config &=
328 ~PORT_HW_CFG_PHY_SELECTION_MASK;
329 if (bp->link_params.multi_phy_config &
330 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
331 bp->link_params.multi_phy_config |=
332 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
333 else
334 bp->link_params.multi_phy_config |=
335 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
336 break;
337 default:
338 DP(NETIF_MSG_LINK, "Unsupported port type\n");
339 return -EINVAL;
340 }
341 /* Save new config in case command complete successuly */
342 new_multi_phy_config = bp->link_params.multi_phy_config;
343 /* Get the new cfg_idx */
344 cfg_idx = bnx2x_get_link_cfg_idx(bp);
345 /* Restore old config in case command failed */
346 bp->link_params.multi_phy_config = old_multi_phy_config;
347 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
348
349 if (cmd->autoneg == AUTONEG_ENABLE) {
350 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
351 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
352 return -EINVAL;
353 }
354
355 /* advertise the requested speed and duplex if supported */
356 cmd->advertising &= bp->port.supported[cfg_idx];
357
358 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
359 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
360 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
361 cmd->advertising);
362
363 } else { /* forced speed */
364 /* advertise the requested speed and duplex if supported */
365 switch (speed) {
366 case SPEED_10:
367 if (cmd->duplex == DUPLEX_FULL) {
368 if (!(bp->port.supported[cfg_idx] &
369 SUPPORTED_10baseT_Full)) {
370 DP(NETIF_MSG_LINK,
371 "10M full not supported\n");
372 return -EINVAL;
373 }
374
375 advertising = (ADVERTISED_10baseT_Full |
376 ADVERTISED_TP);
377 } else {
378 if (!(bp->port.supported[cfg_idx] &
379 SUPPORTED_10baseT_Half)) {
380 DP(NETIF_MSG_LINK,
381 "10M half not supported\n");
382 return -EINVAL;
383 }
384
385 advertising = (ADVERTISED_10baseT_Half |
386 ADVERTISED_TP);
387 }
388 break;
389
390 case SPEED_100:
391 if (cmd->duplex == DUPLEX_FULL) {
392 if (!(bp->port.supported[cfg_idx] &
393 SUPPORTED_100baseT_Full)) {
394 DP(NETIF_MSG_LINK,
395 "100M full not supported\n");
396 return -EINVAL;
397 }
398
399 advertising = (ADVERTISED_100baseT_Full |
400 ADVERTISED_TP);
401 } else {
402 if (!(bp->port.supported[cfg_idx] &
403 SUPPORTED_100baseT_Half)) {
404 DP(NETIF_MSG_LINK,
405 "100M half not supported\n");
406 return -EINVAL;
407 }
408
409 advertising = (ADVERTISED_100baseT_Half |
410 ADVERTISED_TP);
411 }
412 break;
413
414 case SPEED_1000:
415 if (cmd->duplex != DUPLEX_FULL) {
416 DP(NETIF_MSG_LINK, "1G half not supported\n");
417 return -EINVAL;
418 }
419
420 if (!(bp->port.supported[cfg_idx] &
421 SUPPORTED_1000baseT_Full)) {
422 DP(NETIF_MSG_LINK, "1G full not supported\n");
423 return -EINVAL;
424 }
425
426 advertising = (ADVERTISED_1000baseT_Full |
427 ADVERTISED_TP);
428 break;
429
430 case SPEED_2500:
431 if (cmd->duplex != DUPLEX_FULL) {
432 DP(NETIF_MSG_LINK,
433 "2.5G half not supported\n");
434 return -EINVAL;
435 }
436
437 if (!(bp->port.supported[cfg_idx]
438 & SUPPORTED_2500baseX_Full)) {
439 DP(NETIF_MSG_LINK,
440 "2.5G full not supported\n");
441 return -EINVAL;
442 }
443
444 advertising = (ADVERTISED_2500baseX_Full |
445 ADVERTISED_TP);
446 break;
447
448 case SPEED_10000:
449 if (cmd->duplex != DUPLEX_FULL) {
450 DP(NETIF_MSG_LINK, "10G half not supported\n");
451 return -EINVAL;
452 }
453
454 if (!(bp->port.supported[cfg_idx]
455 & SUPPORTED_10000baseT_Full)) {
456 DP(NETIF_MSG_LINK, "10G full not supported\n");
457 return -EINVAL;
458 }
459
460 advertising = (ADVERTISED_10000baseT_Full |
461 ADVERTISED_FIBRE);
462 break;
463
464 default:
465 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
466 return -EINVAL;
467 }
468
469 bp->link_params.req_line_speed[cfg_idx] = speed;
470 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
471 bp->port.advertising[cfg_idx] = advertising;
472 }
473
474 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
475 DP_LEVEL " req_duplex %d advertising 0x%x\n",
476 bp->link_params.req_line_speed[cfg_idx],
477 bp->link_params.req_duplex[cfg_idx],
478 bp->port.advertising[cfg_idx]);
479
480 /* Set new config */
481 bp->link_params.multi_phy_config = new_multi_phy_config;
482 if (netif_running(dev)) {
483 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
484 bnx2x_link_set(bp);
485 }
486
487 return 0;
488 }
489
490 #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
491 #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
492 #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
493
494 static int bnx2x_get_regs_len(struct net_device *dev)
495 {
496 struct bnx2x *bp = netdev_priv(dev);
497 int regdump_len = 0;
498 int i, j, k;
499
500 if (CHIP_IS_E1(bp)) {
501 for (i = 0; i < REGS_COUNT; i++)
502 if (IS_E1_ONLINE(reg_addrs[i].info))
503 regdump_len += reg_addrs[i].size;
504
505 for (i = 0; i < WREGS_COUNT_E1; i++)
506 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
507 regdump_len += wreg_addrs_e1[i].size *
508 (1 + wreg_addrs_e1[i].read_regs_count);
509
510 } else if (CHIP_IS_E1H(bp)) {
511 for (i = 0; i < REGS_COUNT; i++)
512 if (IS_E1H_ONLINE(reg_addrs[i].info))
513 regdump_len += reg_addrs[i].size;
514
515 for (i = 0; i < WREGS_COUNT_E1H; i++)
516 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
517 regdump_len += wreg_addrs_e1h[i].size *
518 (1 + wreg_addrs_e1h[i].read_regs_count);
519 } else if (CHIP_IS_E2(bp)) {
520 for (i = 0; i < REGS_COUNT; i++)
521 if (IS_E2_ONLINE(reg_addrs[i].info))
522 regdump_len += reg_addrs[i].size;
523
524 for (i = 0; i < WREGS_COUNT_E2; i++)
525 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
526 regdump_len += wreg_addrs_e2[i].size *
527 (1 + wreg_addrs_e2[i].read_regs_count);
528
529 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
530 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
531 for (k = 0; k < PAGE_READ_REGS_E2; k++)
532 if (IS_E2_ONLINE(page_read_regs_e2[k].
533 info))
534 regdump_len +=
535 page_read_regs_e2[k].size;
536 }
537 }
538 regdump_len *= 4;
539 regdump_len += sizeof(struct dump_hdr);
540
541 return regdump_len;
542 }
543
544 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
545 {
546 u32 i, j, k, n;
547
548 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
549 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
550 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
551 for (k = 0; k < PAGE_READ_REGS_E2; k++)
552 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
553 for (n = 0; n <
554 page_read_regs_e2[k].size; n++)
555 *p++ = REG_RD(bp,
556 page_read_regs_e2[k].addr + n*4);
557 }
558 }
559 }
560
561 static void bnx2x_get_regs(struct net_device *dev,
562 struct ethtool_regs *regs, void *_p)
563 {
564 u32 *p = _p, i, j;
565 struct bnx2x *bp = netdev_priv(dev);
566 struct dump_hdr dump_hdr = {0};
567
568 regs->version = 0;
569 memset(p, 0, regs->len);
570
571 if (!netif_running(bp->dev))
572 return;
573
574 /* Disable parity attentions as long as following dump may
575 * cause false alarms by reading never written registers. We
576 * will re-enable parity attentions right after the dump.
577 */
578 bnx2x_disable_blocks_parity(bp);
579
580 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
581 dump_hdr.dump_sign = dump_sign_all;
582 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
583 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
584 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
585 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
586
587 if (CHIP_IS_E1(bp))
588 dump_hdr.info = RI_E1_ONLINE;
589 else if (CHIP_IS_E1H(bp))
590 dump_hdr.info = RI_E1H_ONLINE;
591 else if (CHIP_IS_E2(bp))
592 dump_hdr.info = RI_E2_ONLINE |
593 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
594
595 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
596 p += dump_hdr.hdr_size + 1;
597
598 if (CHIP_IS_E1(bp)) {
599 for (i = 0; i < REGS_COUNT; i++)
600 if (IS_E1_ONLINE(reg_addrs[i].info))
601 for (j = 0; j < reg_addrs[i].size; j++)
602 *p++ = REG_RD(bp,
603 reg_addrs[i].addr + j*4);
604
605 } else if (CHIP_IS_E1H(bp)) {
606 for (i = 0; i < REGS_COUNT; i++)
607 if (IS_E1H_ONLINE(reg_addrs[i].info))
608 for (j = 0; j < reg_addrs[i].size; j++)
609 *p++ = REG_RD(bp,
610 reg_addrs[i].addr + j*4);
611
612 } else if (CHIP_IS_E2(bp)) {
613 for (i = 0; i < REGS_COUNT; i++)
614 if (IS_E2_ONLINE(reg_addrs[i].info))
615 for (j = 0; j < reg_addrs[i].size; j++)
616 *p++ = REG_RD(bp,
617 reg_addrs[i].addr + j*4);
618
619 bnx2x_read_pages_regs_e2(bp, p);
620 }
621 /* Re-enable parity attentions */
622 bnx2x_clear_blocks_parity(bp);
623 if (CHIP_PARITY_ENABLED(bp))
624 bnx2x_enable_blocks_parity(bp);
625 }
626
627 #define PHY_FW_VER_LEN 20
628
629 static void bnx2x_get_drvinfo(struct net_device *dev,
630 struct ethtool_drvinfo *info)
631 {
632 struct bnx2x *bp = netdev_priv(dev);
633 u8 phy_fw_ver[PHY_FW_VER_LEN];
634
635 strcpy(info->driver, DRV_MODULE_NAME);
636 strcpy(info->version, DRV_MODULE_VERSION);
637
638 phy_fw_ver[0] = '\0';
639 if (bp->port.pmf) {
640 bnx2x_acquire_phy_lock(bp);
641 bnx2x_get_ext_phy_fw_version(&bp->link_params,
642 (bp->state != BNX2X_STATE_CLOSED),
643 phy_fw_ver, PHY_FW_VER_LEN);
644 bnx2x_release_phy_lock(bp);
645 }
646
647 strncpy(info->fw_version, bp->fw_ver, 32);
648 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
649 "bc %d.%d.%d%s%s",
650 (bp->common.bc_ver & 0xff0000) >> 16,
651 (bp->common.bc_ver & 0xff00) >> 8,
652 (bp->common.bc_ver & 0xff),
653 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
654 strcpy(info->bus_info, pci_name(bp->pdev));
655 info->n_stats = BNX2X_NUM_STATS;
656 info->testinfo_len = BNX2X_NUM_TESTS;
657 info->eedump_len = bp->common.flash_size;
658 info->regdump_len = bnx2x_get_regs_len(dev);
659 }
660
661 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
662 {
663 struct bnx2x *bp = netdev_priv(dev);
664
665 if (bp->flags & NO_WOL_FLAG) {
666 wol->supported = 0;
667 wol->wolopts = 0;
668 } else {
669 wol->supported = WAKE_MAGIC;
670 if (bp->wol)
671 wol->wolopts = WAKE_MAGIC;
672 else
673 wol->wolopts = 0;
674 }
675 memset(&wol->sopass, 0, sizeof(wol->sopass));
676 }
677
678 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
679 {
680 struct bnx2x *bp = netdev_priv(dev);
681
682 if (wol->wolopts & ~WAKE_MAGIC)
683 return -EINVAL;
684
685 if (wol->wolopts & WAKE_MAGIC) {
686 if (bp->flags & NO_WOL_FLAG)
687 return -EINVAL;
688
689 bp->wol = 1;
690 } else
691 bp->wol = 0;
692
693 return 0;
694 }
695
696 static u32 bnx2x_get_msglevel(struct net_device *dev)
697 {
698 struct bnx2x *bp = netdev_priv(dev);
699
700 return bp->msg_enable;
701 }
702
703 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
704 {
705 struct bnx2x *bp = netdev_priv(dev);
706
707 if (capable(CAP_NET_ADMIN))
708 bp->msg_enable = level;
709 }
710
711 static int bnx2x_nway_reset(struct net_device *dev)
712 {
713 struct bnx2x *bp = netdev_priv(dev);
714
715 if (!bp->port.pmf)
716 return 0;
717
718 if (netif_running(dev)) {
719 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
720 bnx2x_link_set(bp);
721 }
722
723 return 0;
724 }
725
726 static u32 bnx2x_get_link(struct net_device *dev)
727 {
728 struct bnx2x *bp = netdev_priv(dev);
729
730 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
731 return 0;
732
733 return bp->link_vars.link_up;
734 }
735
736 static int bnx2x_get_eeprom_len(struct net_device *dev)
737 {
738 struct bnx2x *bp = netdev_priv(dev);
739
740 return bp->common.flash_size;
741 }
742
743 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
744 {
745 int port = BP_PORT(bp);
746 int count, i;
747 u32 val = 0;
748
749 /* adjust timeout for emulation/FPGA */
750 count = NVRAM_TIMEOUT_COUNT;
751 if (CHIP_REV_IS_SLOW(bp))
752 count *= 100;
753
754 /* request access to nvram interface */
755 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
756 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
757
758 for (i = 0; i < count*10; i++) {
759 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
760 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
761 break;
762
763 udelay(5);
764 }
765
766 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
767 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
768 return -EBUSY;
769 }
770
771 return 0;
772 }
773
774 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
775 {
776 int port = BP_PORT(bp);
777 int count, i;
778 u32 val = 0;
779
780 /* adjust timeout for emulation/FPGA */
781 count = NVRAM_TIMEOUT_COUNT;
782 if (CHIP_REV_IS_SLOW(bp))
783 count *= 100;
784
785 /* relinquish nvram interface */
786 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
787 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
788
789 for (i = 0; i < count*10; i++) {
790 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
791 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
792 break;
793
794 udelay(5);
795 }
796
797 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
798 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
799 return -EBUSY;
800 }
801
802 return 0;
803 }
804
805 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
806 {
807 u32 val;
808
809 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
810
811 /* enable both bits, even on read */
812 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
813 (val | MCPR_NVM_ACCESS_ENABLE_EN |
814 MCPR_NVM_ACCESS_ENABLE_WR_EN));
815 }
816
817 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
818 {
819 u32 val;
820
821 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
822
823 /* disable both bits, even after read */
824 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
825 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
826 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
827 }
828
829 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
830 u32 cmd_flags)
831 {
832 int count, i, rc;
833 u32 val;
834
835 /* build the command word */
836 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
837
838 /* need to clear DONE bit separately */
839 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
840
841 /* address of the NVRAM to read from */
842 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
843 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
844
845 /* issue a read command */
846 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
847
848 /* adjust timeout for emulation/FPGA */
849 count = NVRAM_TIMEOUT_COUNT;
850 if (CHIP_REV_IS_SLOW(bp))
851 count *= 100;
852
853 /* wait for completion */
854 *ret_val = 0;
855 rc = -EBUSY;
856 for (i = 0; i < count; i++) {
857 udelay(5);
858 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
859
860 if (val & MCPR_NVM_COMMAND_DONE) {
861 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
862 /* we read nvram data in cpu order
863 * but ethtool sees it as an array of bytes
864 * converting to big-endian will do the work */
865 *ret_val = cpu_to_be32(val);
866 rc = 0;
867 break;
868 }
869 }
870
871 return rc;
872 }
873
874 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
875 int buf_size)
876 {
877 int rc;
878 u32 cmd_flags;
879 __be32 val;
880
881 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
882 DP(BNX2X_MSG_NVM,
883 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
884 offset, buf_size);
885 return -EINVAL;
886 }
887
888 if (offset + buf_size > bp->common.flash_size) {
889 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
890 " buf_size (0x%x) > flash_size (0x%x)\n",
891 offset, buf_size, bp->common.flash_size);
892 return -EINVAL;
893 }
894
895 /* request access to nvram interface */
896 rc = bnx2x_acquire_nvram_lock(bp);
897 if (rc)
898 return rc;
899
900 /* enable access to nvram interface */
901 bnx2x_enable_nvram_access(bp);
902
903 /* read the first word(s) */
904 cmd_flags = MCPR_NVM_COMMAND_FIRST;
905 while ((buf_size > sizeof(u32)) && (rc == 0)) {
906 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
907 memcpy(ret_buf, &val, 4);
908
909 /* advance to the next dword */
910 offset += sizeof(u32);
911 ret_buf += sizeof(u32);
912 buf_size -= sizeof(u32);
913 cmd_flags = 0;
914 }
915
916 if (rc == 0) {
917 cmd_flags |= MCPR_NVM_COMMAND_LAST;
918 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
919 memcpy(ret_buf, &val, 4);
920 }
921
922 /* disable access to nvram interface */
923 bnx2x_disable_nvram_access(bp);
924 bnx2x_release_nvram_lock(bp);
925
926 return rc;
927 }
928
929 static int bnx2x_get_eeprom(struct net_device *dev,
930 struct ethtool_eeprom *eeprom, u8 *eebuf)
931 {
932 struct bnx2x *bp = netdev_priv(dev);
933 int rc;
934
935 if (!netif_running(dev))
936 return -EAGAIN;
937
938 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
939 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
940 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
941 eeprom->len, eeprom->len);
942
943 /* parameters already validated in ethtool_get_eeprom */
944
945 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
946
947 return rc;
948 }
949
950 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
951 u32 cmd_flags)
952 {
953 int count, i, rc;
954
955 /* build the command word */
956 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
957
958 /* need to clear DONE bit separately */
959 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
960
961 /* write the data */
962 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
963
964 /* address of the NVRAM to write to */
965 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
966 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
967
968 /* issue the write command */
969 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
970
971 /* adjust timeout for emulation/FPGA */
972 count = NVRAM_TIMEOUT_COUNT;
973 if (CHIP_REV_IS_SLOW(bp))
974 count *= 100;
975
976 /* wait for completion */
977 rc = -EBUSY;
978 for (i = 0; i < count; i++) {
979 udelay(5);
980 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
981 if (val & MCPR_NVM_COMMAND_DONE) {
982 rc = 0;
983 break;
984 }
985 }
986
987 return rc;
988 }
989
990 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
991
992 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
993 int buf_size)
994 {
995 int rc;
996 u32 cmd_flags;
997 u32 align_offset;
998 __be32 val;
999
1000 if (offset + buf_size > bp->common.flash_size) {
1001 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1002 " buf_size (0x%x) > flash_size (0x%x)\n",
1003 offset, buf_size, bp->common.flash_size);
1004 return -EINVAL;
1005 }
1006
1007 /* request access to nvram interface */
1008 rc = bnx2x_acquire_nvram_lock(bp);
1009 if (rc)
1010 return rc;
1011
1012 /* enable access to nvram interface */
1013 bnx2x_enable_nvram_access(bp);
1014
1015 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1016 align_offset = (offset & ~0x03);
1017 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1018
1019 if (rc == 0) {
1020 val &= ~(0xff << BYTE_OFFSET(offset));
1021 val |= (*data_buf << BYTE_OFFSET(offset));
1022
1023 /* nvram data is returned as an array of bytes
1024 * convert it back to cpu order */
1025 val = be32_to_cpu(val);
1026
1027 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1028 cmd_flags);
1029 }
1030
1031 /* disable access to nvram interface */
1032 bnx2x_disable_nvram_access(bp);
1033 bnx2x_release_nvram_lock(bp);
1034
1035 return rc;
1036 }
1037
1038 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1039 int buf_size)
1040 {
1041 int rc;
1042 u32 cmd_flags;
1043 u32 val;
1044 u32 written_so_far;
1045
1046 if (buf_size == 1) /* ethtool */
1047 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1048
1049 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1050 DP(BNX2X_MSG_NVM,
1051 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1052 offset, buf_size);
1053 return -EINVAL;
1054 }
1055
1056 if (offset + buf_size > bp->common.flash_size) {
1057 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1058 " buf_size (0x%x) > flash_size (0x%x)\n",
1059 offset, buf_size, bp->common.flash_size);
1060 return -EINVAL;
1061 }
1062
1063 /* request access to nvram interface */
1064 rc = bnx2x_acquire_nvram_lock(bp);
1065 if (rc)
1066 return rc;
1067
1068 /* enable access to nvram interface */
1069 bnx2x_enable_nvram_access(bp);
1070
1071 written_so_far = 0;
1072 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1073 while ((written_so_far < buf_size) && (rc == 0)) {
1074 if (written_so_far == (buf_size - sizeof(u32)))
1075 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1076 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1077 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1078 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1079 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1080
1081 memcpy(&val, data_buf, 4);
1082
1083 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1084
1085 /* advance to the next dword */
1086 offset += sizeof(u32);
1087 data_buf += sizeof(u32);
1088 written_so_far += sizeof(u32);
1089 cmd_flags = 0;
1090 }
1091
1092 /* disable access to nvram interface */
1093 bnx2x_disable_nvram_access(bp);
1094 bnx2x_release_nvram_lock(bp);
1095
1096 return rc;
1097 }
1098
1099 static int bnx2x_set_eeprom(struct net_device *dev,
1100 struct ethtool_eeprom *eeprom, u8 *eebuf)
1101 {
1102 struct bnx2x *bp = netdev_priv(dev);
1103 int port = BP_PORT(bp);
1104 int rc = 0;
1105 u32 ext_phy_config;
1106 if (!netif_running(dev))
1107 return -EAGAIN;
1108
1109 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1110 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1111 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1112 eeprom->len, eeprom->len);
1113
1114 /* parameters already validated in ethtool_set_eeprom */
1115
1116 /* PHY eeprom can be accessed only by the PMF */
1117 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1118 !bp->port.pmf)
1119 return -EINVAL;
1120
1121 ext_phy_config =
1122 SHMEM_RD(bp,
1123 dev_info.port_hw_config[port].external_phy_config);
1124
1125 if (eeprom->magic == 0x50485950) {
1126 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1127 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1128
1129 bnx2x_acquire_phy_lock(bp);
1130 rc |= bnx2x_link_reset(&bp->link_params,
1131 &bp->link_vars, 0);
1132 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1133 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1134 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1135 MISC_REGISTERS_GPIO_HIGH, port);
1136 bnx2x_release_phy_lock(bp);
1137 bnx2x_link_report(bp);
1138
1139 } else if (eeprom->magic == 0x50485952) {
1140 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1141 if (bp->state == BNX2X_STATE_OPEN) {
1142 bnx2x_acquire_phy_lock(bp);
1143 rc |= bnx2x_link_reset(&bp->link_params,
1144 &bp->link_vars, 1);
1145
1146 rc |= bnx2x_phy_init(&bp->link_params,
1147 &bp->link_vars);
1148 bnx2x_release_phy_lock(bp);
1149 bnx2x_calc_fc_adv(bp);
1150 }
1151 } else if (eeprom->magic == 0x53985943) {
1152 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1153 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1154 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1155
1156 /* DSP Remove Download Mode */
1157 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1158 MISC_REGISTERS_GPIO_LOW, port);
1159
1160 bnx2x_acquire_phy_lock(bp);
1161
1162 bnx2x_sfx7101_sp_sw_reset(bp,
1163 &bp->link_params.phy[EXT_PHY1]);
1164
1165 /* wait 0.5 sec to allow it to run */
1166 msleep(500);
1167 bnx2x_ext_phy_hw_reset(bp, port);
1168 msleep(500);
1169 bnx2x_release_phy_lock(bp);
1170 }
1171 } else
1172 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1173
1174 return rc;
1175 }
1176
1177 static int bnx2x_get_coalesce(struct net_device *dev,
1178 struct ethtool_coalesce *coal)
1179 {
1180 struct bnx2x *bp = netdev_priv(dev);
1181
1182 memset(coal, 0, sizeof(struct ethtool_coalesce));
1183
1184 coal->rx_coalesce_usecs = bp->rx_ticks;
1185 coal->tx_coalesce_usecs = bp->tx_ticks;
1186
1187 return 0;
1188 }
1189
1190 static int bnx2x_set_coalesce(struct net_device *dev,
1191 struct ethtool_coalesce *coal)
1192 {
1193 struct bnx2x *bp = netdev_priv(dev);
1194
1195 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1196 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1197 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1198
1199 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1200 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1201 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1202
1203 if (netif_running(dev))
1204 bnx2x_update_coalesce(bp);
1205
1206 return 0;
1207 }
1208
1209 static void bnx2x_get_ringparam(struct net_device *dev,
1210 struct ethtool_ringparam *ering)
1211 {
1212 struct bnx2x *bp = netdev_priv(dev);
1213
1214 ering->rx_max_pending = MAX_RX_AVAIL;
1215 ering->rx_mini_max_pending = 0;
1216 ering->rx_jumbo_max_pending = 0;
1217
1218 if (bp->rx_ring_size)
1219 ering->rx_pending = bp->rx_ring_size;
1220 else
1221 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1222 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1223 else
1224 ering->rx_pending = MAX_RX_AVAIL;
1225
1226 ering->rx_mini_pending = 0;
1227 ering->rx_jumbo_pending = 0;
1228
1229 ering->tx_max_pending = MAX_TX_AVAIL;
1230 ering->tx_pending = bp->tx_ring_size;
1231 }
1232
1233 static int bnx2x_set_ringparam(struct net_device *dev,
1234 struct ethtool_ringparam *ering)
1235 {
1236 struct bnx2x *bp = netdev_priv(dev);
1237 int rc = 0;
1238
1239 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1240 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1241 return -EAGAIN;
1242 }
1243
1244 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1245 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1246 MIN_RX_SIZE_TPA)) ||
1247 (ering->tx_pending > MAX_TX_AVAIL) ||
1248 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1249 return -EINVAL;
1250
1251 bp->rx_ring_size = ering->rx_pending;
1252 bp->tx_ring_size = ering->tx_pending;
1253
1254 if (netif_running(dev)) {
1255 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1256 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1257 }
1258
1259 return rc;
1260 }
1261
1262 static void bnx2x_get_pauseparam(struct net_device *dev,
1263 struct ethtool_pauseparam *epause)
1264 {
1265 struct bnx2x *bp = netdev_priv(dev);
1266 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1267 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1268 BNX2X_FLOW_CTRL_AUTO);
1269
1270 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1271 BNX2X_FLOW_CTRL_RX);
1272 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1273 BNX2X_FLOW_CTRL_TX);
1274
1275 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1276 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1277 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1278 }
1279
1280 static int bnx2x_set_pauseparam(struct net_device *dev,
1281 struct ethtool_pauseparam *epause)
1282 {
1283 struct bnx2x *bp = netdev_priv(dev);
1284 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1285 if (IS_MF(bp))
1286 return 0;
1287
1288 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1289 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1290 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1291
1292 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1293
1294 if (epause->rx_pause)
1295 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1296
1297 if (epause->tx_pause)
1298 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1299
1300 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1301 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1302
1303 if (epause->autoneg) {
1304 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1305 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1306 return -EINVAL;
1307 }
1308
1309 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1310 bp->link_params.req_flow_ctrl[cfg_idx] =
1311 BNX2X_FLOW_CTRL_AUTO;
1312 }
1313 }
1314
1315 DP(NETIF_MSG_LINK,
1316 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1317
1318 if (netif_running(dev)) {
1319 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1320 bnx2x_link_set(bp);
1321 }
1322
1323 return 0;
1324 }
1325
1326 static const struct {
1327 char string[ETH_GSTRING_LEN];
1328 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1329 { "register_test (offline)" },
1330 { "memory_test (offline)" },
1331 { "loopback_test (offline)" },
1332 { "nvram_test (online)" },
1333 { "interrupt_test (online)" },
1334 { "link_test (online)" },
1335 { "idle check (online)" }
1336 };
1337
1338 static int bnx2x_test_registers(struct bnx2x *bp)
1339 {
1340 int idx, i, rc = -ENODEV;
1341 u32 wr_val = 0;
1342 int port = BP_PORT(bp);
1343 static const struct {
1344 u32 offset0;
1345 u32 offset1;
1346 u32 mask;
1347 } reg_tbl[] = {
1348 /* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1349 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1350 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1351 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1352 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1353 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1354 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1355 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1356 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1357 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1358 /* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1359 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1360 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1361 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1362 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1363 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1364 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1365 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1366 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1367 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1368 /* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1369 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1370 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1371 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1372 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1373 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1374 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1375 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1376 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1377 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1378 /* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1379 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1380 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1381 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1382 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1383 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1384 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1385
1386 { 0xffffffff, 0, 0x00000000 }
1387 };
1388
1389 if (!netif_running(bp->dev))
1390 return rc;
1391
1392 /* Repeat the test twice:
1393 First by writing 0x00000000, second by writing 0xffffffff */
1394 for (idx = 0; idx < 2; idx++) {
1395
1396 switch (idx) {
1397 case 0:
1398 wr_val = 0;
1399 break;
1400 case 1:
1401 wr_val = 0xffffffff;
1402 break;
1403 }
1404
1405 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1406 u32 offset, mask, save_val, val;
1407 if (CHIP_IS_E2(bp) &&
1408 reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1409 continue;
1410
1411 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1412 mask = reg_tbl[i].mask;
1413
1414 save_val = REG_RD(bp, offset);
1415
1416 REG_WR(bp, offset, wr_val & mask);
1417
1418 val = REG_RD(bp, offset);
1419
1420 /* Restore the original register's value */
1421 REG_WR(bp, offset, save_val);
1422
1423 /* verify value is as expected */
1424 if ((val & mask) != (wr_val & mask)) {
1425 DP(NETIF_MSG_PROBE,
1426 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1427 offset, val, wr_val, mask);
1428 goto test_reg_exit;
1429 }
1430 }
1431 }
1432
1433 rc = 0;
1434
1435 test_reg_exit:
1436 return rc;
1437 }
1438
1439 static int bnx2x_test_memory(struct bnx2x *bp)
1440 {
1441 int i, j, rc = -ENODEV;
1442 u32 val;
1443 static const struct {
1444 u32 offset;
1445 int size;
1446 } mem_tbl[] = {
1447 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1448 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1449 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1450 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1451 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1452 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1453 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1454
1455 { 0xffffffff, 0 }
1456 };
1457 static const struct {
1458 char *name;
1459 u32 offset;
1460 u32 e1_mask;
1461 u32 e1h_mask;
1462 u32 e2_mask;
1463 } prty_tbl[] = {
1464 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 },
1465 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 },
1466 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 },
1467 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 },
1468 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 },
1469 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 },
1470
1471 { NULL, 0xffffffff, 0, 0, 0 }
1472 };
1473
1474 if (!netif_running(bp->dev))
1475 return rc;
1476
1477 /* pre-Check the parity status */
1478 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1479 val = REG_RD(bp, prty_tbl[i].offset);
1480 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1481 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1482 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1483 DP(NETIF_MSG_HW,
1484 "%s is 0x%x\n", prty_tbl[i].name, val);
1485 goto test_mem_exit;
1486 }
1487 }
1488
1489 /* Go through all the memories */
1490 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1491 for (j = 0; j < mem_tbl[i].size; j++)
1492 REG_RD(bp, mem_tbl[i].offset + j*4);
1493
1494 /* Check the parity status */
1495 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1496 val = REG_RD(bp, prty_tbl[i].offset);
1497 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1498 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1499 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1500 DP(NETIF_MSG_HW,
1501 "%s is 0x%x\n", prty_tbl[i].name, val);
1502 goto test_mem_exit;
1503 }
1504 }
1505
1506 rc = 0;
1507
1508 test_mem_exit:
1509 return rc;
1510 }
1511
1512 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1513 {
1514 int cnt = 1400;
1515
1516 if (link_up)
1517 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1518 msleep(10);
1519 }
1520
1521 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1522 {
1523 unsigned int pkt_size, num_pkts, i;
1524 struct sk_buff *skb;
1525 unsigned char *packet;
1526 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1527 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1528 u16 tx_start_idx, tx_idx;
1529 u16 rx_start_idx, rx_idx;
1530 u16 pkt_prod, bd_prod;
1531 struct sw_tx_bd *tx_buf;
1532 struct eth_tx_start_bd *tx_start_bd;
1533 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1534 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
1535 dma_addr_t mapping;
1536 union eth_rx_cqe *cqe;
1537 u8 cqe_fp_flags;
1538 struct sw_rx_bd *rx_buf;
1539 u16 len;
1540 int rc = -ENODEV;
1541
1542 /* check the loopback mode */
1543 switch (loopback_mode) {
1544 case BNX2X_PHY_LOOPBACK:
1545 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1546 return -EINVAL;
1547 break;
1548 case BNX2X_MAC_LOOPBACK:
1549 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1550 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1551 break;
1552 default:
1553 return -EINVAL;
1554 }
1555
1556 /* prepare the loopback packet */
1557 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1558 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1559 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1560 if (!skb) {
1561 rc = -ENOMEM;
1562 goto test_loopback_exit;
1563 }
1564 packet = skb_put(skb, pkt_size);
1565 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1566 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1567 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1568 for (i = ETH_HLEN; i < pkt_size; i++)
1569 packet[i] = (unsigned char) (i & 0xff);
1570
1571 /* send the loopback packet */
1572 num_pkts = 0;
1573 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1574 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1575
1576 pkt_prod = fp_tx->tx_pkt_prod++;
1577 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1578 tx_buf->first_bd = fp_tx->tx_bd_prod;
1579 tx_buf->skb = skb;
1580 tx_buf->flags = 0;
1581
1582 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1583 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1584 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1585 skb_headlen(skb), DMA_TO_DEVICE);
1586 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1587 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1588 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1589 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1590 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1591 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1592 SET_FLAG(tx_start_bd->general_data,
1593 ETH_TX_START_BD_ETH_ADDR_TYPE,
1594 UNICAST_ADDRESS);
1595 SET_FLAG(tx_start_bd->general_data,
1596 ETH_TX_START_BD_HDR_NBDS,
1597 1);
1598
1599 /* turn on parsing and get a BD */
1600 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1601
1602 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1603 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1604
1605 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1606 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1607
1608 wmb();
1609
1610 fp_tx->tx_db.data.prod += 2;
1611 barrier();
1612 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1613
1614 mmiowb();
1615
1616 num_pkts++;
1617 fp_tx->tx_bd_prod += 2; /* start + pbd */
1618
1619 udelay(100);
1620
1621 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1622 if (tx_idx != tx_start_idx + num_pkts)
1623 goto test_loopback_exit;
1624
1625 /* Unlike HC IGU won't generate an interrupt for status block
1626 * updates that have been performed while interrupts were
1627 * disabled.
1628 */
1629 if (bp->common.int_block == INT_BLOCK_IGU) {
1630 /* Disable local BHes to prevent a dead-lock situation between
1631 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1632 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1633 */
1634 local_bh_disable();
1635 bnx2x_tx_int(fp_tx);
1636 local_bh_enable();
1637 }
1638
1639 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1640 if (rx_idx != rx_start_idx + num_pkts)
1641 goto test_loopback_exit;
1642
1643 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1644 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1645 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1646 goto test_loopback_rx_exit;
1647
1648 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1649 if (len != pkt_size)
1650 goto test_loopback_rx_exit;
1651
1652 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1653 skb = rx_buf->skb;
1654 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1655 for (i = ETH_HLEN; i < pkt_size; i++)
1656 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1657 goto test_loopback_rx_exit;
1658
1659 rc = 0;
1660
1661 test_loopback_rx_exit:
1662
1663 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1664 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1665 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1666 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1667
1668 /* Update producers */
1669 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1670 fp_rx->rx_sge_prod);
1671
1672 test_loopback_exit:
1673 bp->link_params.loopback_mode = LOOPBACK_NONE;
1674
1675 return rc;
1676 }
1677
1678 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1679 {
1680 int rc = 0, res;
1681
1682 if (BP_NOMCP(bp))
1683 return rc;
1684
1685 if (!netif_running(bp->dev))
1686 return BNX2X_LOOPBACK_FAILED;
1687
1688 bnx2x_netif_stop(bp, 1);
1689 bnx2x_acquire_phy_lock(bp);
1690
1691 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1692 if (res) {
1693 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1694 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1695 }
1696
1697 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1698 if (res) {
1699 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1700 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1701 }
1702
1703 bnx2x_release_phy_lock(bp);
1704 bnx2x_netif_start(bp);
1705
1706 return rc;
1707 }
1708
1709 #define CRC32_RESIDUAL 0xdebb20e3
1710
1711 static int bnx2x_test_nvram(struct bnx2x *bp)
1712 {
1713 static const struct {
1714 int offset;
1715 int size;
1716 } nvram_tbl[] = {
1717 { 0, 0x14 }, /* bootstrap */
1718 { 0x14, 0xec }, /* dir */
1719 { 0x100, 0x350 }, /* manuf_info */
1720 { 0x450, 0xf0 }, /* feature_info */
1721 { 0x640, 0x64 }, /* upgrade_key_info */
1722 { 0x708, 0x70 }, /* manuf_key_info */
1723 { 0, 0 }
1724 };
1725 __be32 buf[0x350 / 4];
1726 u8 *data = (u8 *)buf;
1727 int i, rc;
1728 u32 magic, crc;
1729
1730 if (BP_NOMCP(bp))
1731 return 0;
1732
1733 rc = bnx2x_nvram_read(bp, 0, data, 4);
1734 if (rc) {
1735 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1736 goto test_nvram_exit;
1737 }
1738
1739 magic = be32_to_cpu(buf[0]);
1740 if (magic != 0x669955aa) {
1741 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1742 rc = -ENODEV;
1743 goto test_nvram_exit;
1744 }
1745
1746 for (i = 0; nvram_tbl[i].size; i++) {
1747
1748 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1749 nvram_tbl[i].size);
1750 if (rc) {
1751 DP(NETIF_MSG_PROBE,
1752 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1753 goto test_nvram_exit;
1754 }
1755
1756 crc = ether_crc_le(nvram_tbl[i].size, data);
1757 if (crc != CRC32_RESIDUAL) {
1758 DP(NETIF_MSG_PROBE,
1759 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1760 rc = -ENODEV;
1761 goto test_nvram_exit;
1762 }
1763 }
1764
1765 test_nvram_exit:
1766 return rc;
1767 }
1768
1769 static int bnx2x_test_intr(struct bnx2x *bp)
1770 {
1771 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1772 int i, rc;
1773
1774 if (!netif_running(bp->dev))
1775 return -ENODEV;
1776
1777 config->hdr.length = 0;
1778 if (CHIP_IS_E1(bp))
1779 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1780 else
1781 config->hdr.offset = BP_FUNC(bp);
1782 config->hdr.client_id = bp->fp->cl_id;
1783 config->hdr.reserved1 = 0;
1784
1785 bp->set_mac_pending = 1;
1786 smp_wmb();
1787 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1788 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1789 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1790 if (rc == 0) {
1791 for (i = 0; i < 10; i++) {
1792 if (!bp->set_mac_pending)
1793 break;
1794 smp_rmb();
1795 msleep_interruptible(10);
1796 }
1797 if (i == 10)
1798 rc = -ENODEV;
1799 }
1800
1801 return rc;
1802 }
1803
1804 static void bnx2x_self_test(struct net_device *dev,
1805 struct ethtool_test *etest, u64 *buf)
1806 {
1807 struct bnx2x *bp = netdev_priv(dev);
1808 u8 is_serdes;
1809 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1810 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1811 etest->flags |= ETH_TEST_FL_FAILED;
1812 return;
1813 }
1814
1815 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1816
1817 if (!netif_running(dev))
1818 return;
1819
1820 /* offline tests are not supported in MF mode */
1821 if (IS_MF(bp))
1822 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1823 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1824
1825 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1826 int port = BP_PORT(bp);
1827 u32 val;
1828 u8 link_up;
1829
1830 /* save current value of input enable for TX port IF */
1831 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1832 /* disable input for TX port IF */
1833 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1834
1835 link_up = bp->link_vars.link_up;
1836
1837 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1838 bnx2x_nic_load(bp, LOAD_DIAG);
1839 /* wait until link state is restored */
1840 bnx2x_wait_for_link(bp, link_up, is_serdes);
1841
1842 if (bnx2x_test_registers(bp) != 0) {
1843 buf[0] = 1;
1844 etest->flags |= ETH_TEST_FL_FAILED;
1845 }
1846 if (bnx2x_test_memory(bp) != 0) {
1847 buf[1] = 1;
1848 etest->flags |= ETH_TEST_FL_FAILED;
1849 }
1850
1851 buf[2] = bnx2x_test_loopback(bp, link_up);
1852 if (buf[2] != 0)
1853 etest->flags |= ETH_TEST_FL_FAILED;
1854
1855 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1856
1857 /* restore input for TX port IF */
1858 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1859
1860 bnx2x_nic_load(bp, LOAD_NORMAL);
1861 /* wait until link state is restored */
1862 bnx2x_wait_for_link(bp, link_up, is_serdes);
1863 }
1864 if (bnx2x_test_nvram(bp) != 0) {
1865 buf[3] = 1;
1866 etest->flags |= ETH_TEST_FL_FAILED;
1867 }
1868 if (bnx2x_test_intr(bp) != 0) {
1869 buf[4] = 1;
1870 etest->flags |= ETH_TEST_FL_FAILED;
1871 }
1872
1873 if (bnx2x_link_test(bp, is_serdes) != 0) {
1874 buf[5] = 1;
1875 etest->flags |= ETH_TEST_FL_FAILED;
1876 }
1877
1878 #ifdef BNX2X_EXTRA_DEBUG
1879 bnx2x_panic_dump(bp);
1880 #endif
1881 }
1882
1883 #define IS_PORT_STAT(i) \
1884 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1885 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1886 #define IS_MF_MODE_STAT(bp) \
1887 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1888
1889 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1890 {
1891 struct bnx2x *bp = netdev_priv(dev);
1892 int i, num_stats;
1893
1894 switch (stringset) {
1895 case ETH_SS_STATS:
1896 if (is_multi(bp)) {
1897 num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1898 BNX2X_NUM_Q_STATS;
1899 if (!IS_MF_MODE_STAT(bp))
1900 num_stats += BNX2X_NUM_STATS;
1901 } else {
1902 if (IS_MF_MODE_STAT(bp)) {
1903 num_stats = 0;
1904 for (i = 0; i < BNX2X_NUM_STATS; i++)
1905 if (IS_FUNC_STAT(i))
1906 num_stats++;
1907 } else
1908 num_stats = BNX2X_NUM_STATS;
1909 }
1910 return num_stats;
1911
1912 case ETH_SS_TEST:
1913 return BNX2X_NUM_TESTS;
1914
1915 default:
1916 return -EINVAL;
1917 }
1918 }
1919
1920 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1921 {
1922 struct bnx2x *bp = netdev_priv(dev);
1923 int i, j, k;
1924 char queue_name[MAX_QUEUE_NAME_LEN+1];
1925
1926 switch (stringset) {
1927 case ETH_SS_STATS:
1928 if (is_multi(bp)) {
1929 k = 0;
1930 for_each_napi_queue(bp, i) {
1931 memset(queue_name, 0, sizeof(queue_name));
1932
1933 if (IS_FCOE_IDX(i))
1934 sprintf(queue_name, "fcoe");
1935 else
1936 sprintf(queue_name, "%d", i);
1937
1938 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1939 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
1940 ETH_GSTRING_LEN,
1941 bnx2x_q_stats_arr[j].string,
1942 queue_name);
1943 k += BNX2X_NUM_Q_STATS;
1944 }
1945 if (IS_MF_MODE_STAT(bp))
1946 break;
1947 for (j = 0; j < BNX2X_NUM_STATS; j++)
1948 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1949 bnx2x_stats_arr[j].string);
1950 } else {
1951 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1952 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
1953 continue;
1954 strcpy(buf + j*ETH_GSTRING_LEN,
1955 bnx2x_stats_arr[i].string);
1956 j++;
1957 }
1958 }
1959 break;
1960
1961 case ETH_SS_TEST:
1962 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1963 break;
1964 }
1965 }
1966
1967 static void bnx2x_get_ethtool_stats(struct net_device *dev,
1968 struct ethtool_stats *stats, u64 *buf)
1969 {
1970 struct bnx2x *bp = netdev_priv(dev);
1971 u32 *hw_stats, *offset;
1972 int i, j, k;
1973
1974 if (is_multi(bp)) {
1975 k = 0;
1976 for_each_napi_queue(bp, i) {
1977 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1978 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1979 if (bnx2x_q_stats_arr[j].size == 0) {
1980 /* skip this counter */
1981 buf[k + j] = 0;
1982 continue;
1983 }
1984 offset = (hw_stats +
1985 bnx2x_q_stats_arr[j].offset);
1986 if (bnx2x_q_stats_arr[j].size == 4) {
1987 /* 4-byte counter */
1988 buf[k + j] = (u64) *offset;
1989 continue;
1990 }
1991 /* 8-byte counter */
1992 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1993 }
1994 k += BNX2X_NUM_Q_STATS;
1995 }
1996 if (IS_MF_MODE_STAT(bp))
1997 return;
1998 hw_stats = (u32 *)&bp->eth_stats;
1999 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2000 if (bnx2x_stats_arr[j].size == 0) {
2001 /* skip this counter */
2002 buf[k + j] = 0;
2003 continue;
2004 }
2005 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2006 if (bnx2x_stats_arr[j].size == 4) {
2007 /* 4-byte counter */
2008 buf[k + j] = (u64) *offset;
2009 continue;
2010 }
2011 /* 8-byte counter */
2012 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2013 }
2014 } else {
2015 hw_stats = (u32 *)&bp->eth_stats;
2016 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2017 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2018 continue;
2019 if (bnx2x_stats_arr[i].size == 0) {
2020 /* skip this counter */
2021 buf[j] = 0;
2022 j++;
2023 continue;
2024 }
2025 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2026 if (bnx2x_stats_arr[i].size == 4) {
2027 /* 4-byte counter */
2028 buf[j] = (u64) *offset;
2029 j++;
2030 continue;
2031 }
2032 /* 8-byte counter */
2033 buf[j] = HILO_U64(*offset, *(offset + 1));
2034 j++;
2035 }
2036 }
2037 }
2038
2039 static int bnx2x_set_phys_id(struct net_device *dev,
2040 enum ethtool_phys_id_state state)
2041 {
2042 struct bnx2x *bp = netdev_priv(dev);
2043
2044 if (!netif_running(dev))
2045 return -EAGAIN;
2046
2047 if (!bp->port.pmf)
2048 return -EOPNOTSUPP;
2049
2050 switch (state) {
2051 case ETHTOOL_ID_ACTIVE:
2052 return 1; /* cycle on/off once per second */
2053
2054 case ETHTOOL_ID_ON:
2055 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2056 LED_MODE_ON, SPEED_1000);
2057 break;
2058
2059 case ETHTOOL_ID_OFF:
2060 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2061 LED_MODE_FRONT_PANEL_OFF, 0);
2062
2063 break;
2064
2065 case ETHTOOL_ID_INACTIVE:
2066 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2067 LED_MODE_OPER,
2068 bp->link_vars.line_speed);
2069 }
2070
2071 return 0;
2072 }
2073
2074 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2075 void *rules __always_unused)
2076 {
2077 struct bnx2x *bp = netdev_priv(dev);
2078
2079 switch (info->cmd) {
2080 case ETHTOOL_GRXRINGS:
2081 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2082 return 0;
2083
2084 default:
2085 return -EOPNOTSUPP;
2086 }
2087 }
2088
2089 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2090 struct ethtool_rxfh_indir *indir)
2091 {
2092 struct bnx2x *bp = netdev_priv(dev);
2093 size_t copy_size =
2094 min_t(size_t, indir->size, TSTORM_INDIRECTION_TABLE_SIZE);
2095
2096 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2097 return -EOPNOTSUPP;
2098
2099 indir->size = TSTORM_INDIRECTION_TABLE_SIZE;
2100 memcpy(indir->ring_index, bp->rx_indir_table,
2101 copy_size * sizeof(bp->rx_indir_table[0]));
2102 return 0;
2103 }
2104
2105 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2106 const struct ethtool_rxfh_indir *indir)
2107 {
2108 struct bnx2x *bp = netdev_priv(dev);
2109 size_t i;
2110
2111 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2112 return -EOPNOTSUPP;
2113
2114 /* Validate size and indices */
2115 if (indir->size != TSTORM_INDIRECTION_TABLE_SIZE)
2116 return -EINVAL;
2117 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
2118 if (indir->ring_index[i] >= BNX2X_NUM_ETH_QUEUES(bp))
2119 return -EINVAL;
2120
2121 memcpy(bp->rx_indir_table, indir->ring_index,
2122 indir->size * sizeof(bp->rx_indir_table[0]));
2123 bnx2x_push_indir_table(bp);
2124 return 0;
2125 }
2126
2127 static const struct ethtool_ops bnx2x_ethtool_ops = {
2128 .get_settings = bnx2x_get_settings,
2129 .set_settings = bnx2x_set_settings,
2130 .get_drvinfo = bnx2x_get_drvinfo,
2131 .get_regs_len = bnx2x_get_regs_len,
2132 .get_regs = bnx2x_get_regs,
2133 .get_wol = bnx2x_get_wol,
2134 .set_wol = bnx2x_set_wol,
2135 .get_msglevel = bnx2x_get_msglevel,
2136 .set_msglevel = bnx2x_set_msglevel,
2137 .nway_reset = bnx2x_nway_reset,
2138 .get_link = bnx2x_get_link,
2139 .get_eeprom_len = bnx2x_get_eeprom_len,
2140 .get_eeprom = bnx2x_get_eeprom,
2141 .set_eeprom = bnx2x_set_eeprom,
2142 .get_coalesce = bnx2x_get_coalesce,
2143 .set_coalesce = bnx2x_set_coalesce,
2144 .get_ringparam = bnx2x_get_ringparam,
2145 .set_ringparam = bnx2x_set_ringparam,
2146 .get_pauseparam = bnx2x_get_pauseparam,
2147 .set_pauseparam = bnx2x_set_pauseparam,
2148 .self_test = bnx2x_self_test,
2149 .get_sset_count = bnx2x_get_sset_count,
2150 .get_strings = bnx2x_get_strings,
2151 .set_phys_id = bnx2x_set_phys_id,
2152 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2153 .get_rxnfc = bnx2x_get_rxnfc,
2154 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2155 .set_rxfh_indir = bnx2x_set_rxfh_indir,
2156 };
2157
2158 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2159 {
2160 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2161 }
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