1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
13 #if defined(__BIG_ENDIAN)
14 u16 max_iscsi_init_conn
;
15 u16 max_iscsi_trgt_conn
;
16 #elif defined(__LITTLE_ENDIAN)
17 u16 max_iscsi_trgt_conn
;
18 u16 max_iscsi_init_conn
;
29 /****************************************************************************
30 * Shared HW configuration *
31 ****************************************************************************/
32 struct shared_hw_cfg
{ /* NVRAM Offset */
33 /* Up to 16 bytes of NULL-terminated string */
34 u8 part_num
[16]; /* 0x104 */
36 u32 config
; /* 0x114 */
37 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
38 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
39 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
40 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
41 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
43 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
45 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
47 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
48 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
49 /* Whatever MFW found in NVM
50 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
51 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
52 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
53 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
54 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
55 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
56 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
57 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
58 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
59 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
60 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
61 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
62 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
63 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
65 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
66 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
67 #define SHARED_HW_CFG_LED_MAC1 0x00000000
68 #define SHARED_HW_CFG_LED_PHY1 0x00010000
69 #define SHARED_HW_CFG_LED_PHY2 0x00020000
70 #define SHARED_HW_CFG_LED_PHY3 0x00030000
71 #define SHARED_HW_CFG_LED_MAC2 0x00040000
72 #define SHARED_HW_CFG_LED_PHY4 0x00050000
73 #define SHARED_HW_CFG_LED_PHY5 0x00060000
74 #define SHARED_HW_CFG_LED_PHY6 0x00070000
75 #define SHARED_HW_CFG_LED_MAC3 0x00080000
76 #define SHARED_HW_CFG_LED_PHY7 0x00090000
77 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
78 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
79 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
80 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
81 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
84 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
85 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
86 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
87 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
88 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
89 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
90 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
91 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
93 u32 config2
; /* 0x118 */
94 /* one time auto detect grace period (in sec) */
95 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
96 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
98 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
100 /* The default value for the core clock is 250MHz and it is
101 achieved by setting the clock change to 4 */
102 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
103 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
105 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
106 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
108 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
110 /* The fan failure mechanism is usually related to the PHY type
111 since the power consumption of the board is determined by the PHY.
112 Currently, fan is required for most designs with SFX7101, BCM8727
113 and BCM8481. If a fan is not required for a board which uses one
114 of those PHYs, this field should be set to "Disabled". If a fan is
115 required for a different PHY type, this option should be set to
117 The fan failure indication is expected on
119 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
120 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
121 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
122 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
123 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
125 /* Set the MDC/MDIO access for the first external phy */
126 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
127 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
128 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
129 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
130 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
131 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
132 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
134 /* Set the MDC/MDIO access for the second external phy */
135 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
136 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
137 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
138 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
139 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
140 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
141 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
142 u32 power_dissipated
; /* 0x11c */
143 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
144 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
146 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
147 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
148 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
149 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
150 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
151 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
153 u32 ump_nc_si_config
; /* 0x120 */
154 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
155 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
156 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
157 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
158 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
159 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
161 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
162 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
164 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
165 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
166 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
167 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
169 u32 board
; /* 0x124 */
170 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
171 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
173 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
174 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
176 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
177 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
179 u32 reserved
; /* 0x128 */
184 /****************************************************************************
185 * Port HW configuration *
186 ****************************************************************************/
187 struct port_hw_cfg
{ /* port 0: 0x12c port 1: 0x2bc */
190 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
191 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
194 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
195 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
197 u32 power_dissipated
;
198 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
199 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
200 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
201 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
202 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
203 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
204 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
205 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
208 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
209 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
210 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
211 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
212 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
213 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
214 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
215 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
218 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
219 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
222 u32 iscsi_mac_upper
; /* Upper 16 bits are always zeroes */
225 u32 rdma_mac_upper
; /* Upper 16 bits are always zeroes */
229 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
230 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
232 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
233 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
236 u32 Reserved0
[16]; /* 0x158 */
238 /* for external PHY, or forced mode or during AN */
239 u16 xgxs_config_rx
[4]; /* 0x198 */
241 u16 xgxs_config_tx
[4]; /* 0x1A0 */
243 u32 Reserved1
[57]; /* 0x1A8 */
244 u32 speed_capability_mask2
; /* 0x28C */
245 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
246 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
247 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
248 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
249 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
250 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
251 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
252 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
253 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
254 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G 0x00000080
255 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G 0x00000100
256 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G 0x00000200
257 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G 0x00000400
258 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G 0x00000800
260 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
261 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
262 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
263 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
264 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
265 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
266 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
267 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
268 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
269 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G 0x00800000
270 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G 0x01000000
271 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G 0x02000000
272 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G 0x04000000
273 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G 0x08000000
275 /* In the case where two media types (e.g. copper and fiber) are
276 present and electrically active at the same time, PHY Selection
277 will determine which of the two PHYs will be designated as the
278 Active PHY and used for a connection to the network. */
279 u32 multi_phy_config
; /* 0x290 */
280 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
281 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
282 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
283 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
284 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
285 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
286 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
288 /* When enabled, all second phy nvram parameters will be swapped
289 with the first phy parameters */
290 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
291 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
292 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
293 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
296 /* Address of the second external phy */
297 u32 external_phy_config2
; /* 0x294 */
298 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
299 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
301 /* The second XGXS external PHY type */
302 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
303 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
304 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
305 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
306 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
307 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
308 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
309 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
310 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
311 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
312 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
313 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
314 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
315 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
316 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
317 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
318 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
319 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
321 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
322 8706, 8726 and 8727) not all 4 values are needed. */
323 u16 xgxs_config2_rx
[4]; /* 0x296 */
324 u16 xgxs_config2_tx
[4]; /* 0x2A0 */
327 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
328 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
329 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
330 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
331 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
332 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
333 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
334 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
336 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
338 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
340 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
342 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
344 u32 external_phy_config
;
345 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
346 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
347 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
348 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
349 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
351 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
352 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
354 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
355 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
356 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
357 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
358 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
359 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
360 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
361 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
362 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
363 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
364 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
365 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
366 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
367 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
368 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
369 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
371 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
372 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
374 u32 speed_capability_mask
;
375 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
376 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
377 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
378 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
379 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
380 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
381 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
382 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
383 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
384 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
385 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
386 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
387 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
388 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
389 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
391 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
392 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
393 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
394 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
395 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
396 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
397 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
398 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
399 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
400 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
401 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
402 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
403 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
404 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
405 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
412 /****************************************************************************
413 * Shared Feature configuration *
414 ****************************************************************************/
415 struct shared_feat_cfg
{ /* NVRAM Offset */
417 u32 config
; /* 0x450 */
418 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
420 /* Use the values from options 47 and 48 instead of the HW default
422 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
423 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
425 #define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
430 /****************************************************************************
431 * Port Feature configuration *
432 ****************************************************************************/
433 struct port_feat_cfg
{ /* port 0: 0x454 port 1: 0x4c8 */
436 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
437 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
438 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
439 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
440 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
441 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
442 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
443 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
444 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
445 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
446 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
447 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
448 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
449 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
450 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
451 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
452 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
453 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
454 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
455 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
456 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
457 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
458 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
459 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
460 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
461 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
462 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
463 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
464 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
465 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
466 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
467 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
468 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
469 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
470 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
471 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
472 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
473 #define PORT_FEATURE_EN_SIZE_SHIFT 24
474 #define PORT_FEATURE_WOL_ENABLED 0x01000000
475 #define PORT_FEATURE_MBA_ENABLED 0x02000000
476 #define PORT_FEATURE_MFW_ENABLED 0x04000000
478 /* Reserved bits: 28-29 */
479 /* Check the optic vendor via i2c against a list of approved modules
480 in a separate nvram image */
481 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
482 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
483 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000
484 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000
485 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
486 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
490 /* Default is used when driver sets to "auto" mode */
491 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
492 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
493 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
494 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
495 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
496 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
497 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
498 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
499 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
502 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
503 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
504 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
505 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
506 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
507 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
508 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
509 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
510 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
511 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
512 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
513 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
514 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
515 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
516 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
517 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
518 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
519 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
520 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
521 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
522 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
523 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
524 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
525 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
526 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
527 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
528 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
529 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
530 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
531 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
532 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
533 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
534 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
535 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
536 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
537 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
538 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
539 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
540 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
541 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
542 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
543 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
544 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
545 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
546 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
547 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
548 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
549 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
550 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
551 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
552 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
553 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
554 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
555 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
558 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
559 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
562 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
563 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
564 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
567 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
568 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
569 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
570 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
571 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
575 #define PORT_FEATURE_SMBUS_EN 0x00000001
576 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
577 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
581 u32 link_config
; /* Used as HW defaults for the driver */
582 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
583 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
584 /* (forced) low speed switch (< 10G) */
585 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
586 /* (forced) high speed switch (>= 10G) */
587 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
588 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
589 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
591 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
592 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
593 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
594 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
595 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
596 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
597 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
598 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
599 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
600 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
601 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
602 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
603 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
604 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
605 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
606 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
607 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
609 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
610 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
611 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
612 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
613 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
614 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
615 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
617 /* The default for MCP link configuration,
618 uses the same defines as link_config */
619 u32 mfw_wol_link_cfg
;
620 /* The default for the driver of the second external phy,
621 uses the same defines as link_config */
622 u32 link_config2
; /* 0x47C */
624 /* The default for MCP of the second external phy,
625 uses the same defines as link_config */
626 u32 mfw_wol_link_cfg2
; /* 0x480 */
628 u32 Reserved2
[17]; /* 0x484 */
633 /****************************************************************************
634 * Device Information *
635 ****************************************************************************/
636 struct shm_dev_info
{ /* size */
638 u32 bc_rev
; /* 8 bits each: major, minor, build */ /* 4 */
640 struct shared_hw_cfg shared_hw_config
; /* 40 */
642 struct port_hw_cfg port_hw_config
[PORT_MAX
]; /* 400*2=800 */
644 struct shared_feat_cfg shared_feature_config
; /* 4 */
646 struct port_feat_cfg port_feature_config
[PORT_MAX
];/* 116*2=232 */
659 #define E1_FUNC_MAX 2
660 #define E1H_FUNC_MAX 8
670 /* This value (in milliseconds) determines the frequency of the driver
671 * issuing the PULSE message code. The firmware monitors this periodic
672 * pulse to determine when to switch to an OS-absent mode. */
673 #define DRV_PULSE_PERIOD_MS 250
675 /* This value (in milliseconds) determines how long the driver should
676 * wait for an acknowledgement from the firmware before timing out. Once
677 * the firmware has timed out, the driver will assume there is no firmware
678 * running and there won't be any firmware-driver synchronization during a
680 #define FW_ACK_TIME_OUT_MS 5000
682 #define FW_ACK_POLL_TIME_MS 1
684 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
686 /* LED Blink rate that will achieve ~15.9Hz */
687 #define LED_BLINK_RATE_VAL 480
689 /****************************************************************************
690 * Driver <-> FW Mailbox *
691 ****************************************************************************/
695 /* Driver should update this field on any link change event */
697 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
698 #define LINK_STATUS_LINK_UP 0x00000001
699 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
700 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
701 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
702 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
703 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
704 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
705 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
706 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
707 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
708 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
709 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
710 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
711 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
712 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
713 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
714 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
715 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
716 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
717 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
718 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
719 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
720 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
721 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
722 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
723 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
725 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
726 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
728 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
729 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
730 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
732 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
733 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
734 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
735 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
736 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
737 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
738 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
740 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
741 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
743 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
744 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
746 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
747 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
748 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
749 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
750 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
752 #define LINK_STATUS_SERDES_LINK 0x00100000
754 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
755 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
756 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
757 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
758 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
759 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
760 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
761 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
767 /* MCP firmware does not use this field */
768 u32 ext_phy_fw_version
;
776 #define DRV_MSG_CODE_MASK 0xffff0000
777 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
778 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
779 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
780 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
781 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
782 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
783 #define DRV_MSG_CODE_DCC_OK 0x30000000
784 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
785 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
786 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
787 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
788 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
789 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
790 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
791 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
793 * The optic module verification commands require bootcode
796 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
797 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
799 * The specific optic module verification command requires bootcode
802 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
803 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
805 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
806 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
807 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
808 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
810 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
815 #define FW_MSG_CODE_MASK 0xffff0000
816 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
817 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
818 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
819 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
820 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
821 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
822 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
823 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
824 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
825 #define FW_MSG_CODE_DCC_DONE 0x30100000
826 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
827 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
828 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
829 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
830 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
831 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
832 #define FW_MSG_CODE_NO_KEY 0x80f00000
833 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
834 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
835 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
836 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
837 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
838 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
839 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
840 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
841 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
843 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
844 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
845 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
846 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
848 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
853 #define DRV_PULSE_SEQ_MASK 0x00007fff
854 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
855 /* The system time is in the format of
856 * (year-2001)*12*32 + month*32 + day. */
857 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
858 /* Indicate to the firmware not to go into the
859 * OS-absent when it is not getting driver pulse.
860 * This is used for debugging as well for PXE(MBA). */
863 #define MCP_PULSE_SEQ_MASK 0x00007fff
864 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
865 /* Indicates to the driver not to assert due to lack
867 #define MCP_EVENT_MASK 0xffff0000
868 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
870 u32 iscsi_boot_signature
;
871 u32 iscsi_boot_block_offset
;
874 #define DRV_STATUS_PMF 0x00000001
876 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
877 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
878 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
879 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
880 #define DRV_STATUS_DCC_RESERVED1 0x00000800
881 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
882 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
885 #define VIRT_MAC_SIGN_MASK 0xffff0000
886 #define VIRT_MAC_SIGNATURE 0x564d0000
892 /****************************************************************************
893 * Management firmware state *
894 ****************************************************************************/
895 /* Allocate 440 bytes for management firmware */
896 #define MGMTFW_STATE_WORD_SIZE 110
898 struct mgmtfw_state
{
899 u32 opaque
[MGMTFW_STATE_WORD_SIZE
];
903 /****************************************************************************
904 * Multi-Function configuration *
905 ****************************************************************************/
906 struct shared_mf_cfg
{
909 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
911 #define SHARED_MF_CLP_EXIT 0x00000001
913 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
919 u32 dynamic_cfg
; /* device control channel */
920 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
921 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
922 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
932 /* function 0 of each port cannot be hidden */
933 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
935 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
936 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
937 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
938 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
939 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
940 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
942 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
945 /* 0 - low priority, 3 - high priority */
946 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
947 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
948 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
951 /* value range - 0..100, increments in 100Mbps */
952 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
953 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
954 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
955 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
956 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
957 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
959 u32 mac_upper
; /* MAC */
960 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
961 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
962 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
964 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
966 u32 e1hov_tag
; /* VNI */
967 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
968 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
969 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
977 struct shared_mf_cfg shared_mf_config
;
978 struct port_mf_cfg port_mf_config
[PORT_MAX
];
979 struct func_mf_cfg func_mf_config
[E1H_FUNC_MAX
];
984 /****************************************************************************
985 * Shared Memory Region *
986 ****************************************************************************/
987 struct shmem_region
{ /* SharedMem Offset (size) */
989 u32 validity_map
[PORT_MAX
]; /* 0x0 (4*2 = 0x8) */
990 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
991 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
993 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
994 #define SHR_MEM_VALIDITY_MB 0x00200000
995 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
996 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
997 /* One licensing bit should be set */
998 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
999 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1000 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1001 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1003 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1004 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1005 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1006 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1007 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1008 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1010 struct shm_dev_info dev_info
; /* 0x8 (0x438) */
1012 struct license_key drv_lic_key
[PORT_MAX
]; /* 0x440 (52*2=0x68) */
1014 /* FW information (for internal FW use) */
1015 u32 fw_info_fio_offset
; /* 0x4a8 (0x4) */
1016 struct mgmtfw_state mgmtfw_state
; /* 0x4ac (0x1b8) */
1018 struct drv_port_mb port_mb
[PORT_MAX
]; /* 0x664 (16*2=0x20) */
1019 struct drv_func_mb func_mb
[E1H_FUNC_MAX
];
1021 struct mf_cfg mf_cfg
;
1026 struct shmem2_region
{
1031 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1032 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1033 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1034 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1035 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1036 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1037 #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
1038 u32 ext_phy_fw_version2
[PORT_MAX
];
1040 * For backwards compatibility, if the mf_cfg_addr does not exist
1041 * (the size filed is smaller than 0xc) the mf_cfg resides at the
1042 * end of struct shmem_region
1048 u32 rx_stat_ifhcinoctets
;
1049 u32 rx_stat_ifhcinbadoctets
;
1050 u32 rx_stat_etherstatsfragments
;
1051 u32 rx_stat_ifhcinucastpkts
;
1052 u32 rx_stat_ifhcinmulticastpkts
;
1053 u32 rx_stat_ifhcinbroadcastpkts
;
1054 u32 rx_stat_dot3statsfcserrors
;
1055 u32 rx_stat_dot3statsalignmenterrors
;
1056 u32 rx_stat_dot3statscarriersenseerrors
;
1057 u32 rx_stat_xonpauseframesreceived
;
1058 u32 rx_stat_xoffpauseframesreceived
;
1059 u32 rx_stat_maccontrolframesreceived
;
1060 u32 rx_stat_xoffstateentered
;
1061 u32 rx_stat_dot3statsframestoolong
;
1062 u32 rx_stat_etherstatsjabbers
;
1063 u32 rx_stat_etherstatsundersizepkts
;
1064 u32 rx_stat_etherstatspkts64octets
;
1065 u32 rx_stat_etherstatspkts65octetsto127octets
;
1066 u32 rx_stat_etherstatspkts128octetsto255octets
;
1067 u32 rx_stat_etherstatspkts256octetsto511octets
;
1068 u32 rx_stat_etherstatspkts512octetsto1023octets
;
1069 u32 rx_stat_etherstatspkts1024octetsto1522octets
;
1070 u32 rx_stat_etherstatspktsover1522octets
;
1072 u32 rx_stat_falsecarriererrors
;
1074 u32 tx_stat_ifhcoutoctets
;
1075 u32 tx_stat_ifhcoutbadoctets
;
1076 u32 tx_stat_etherstatscollisions
;
1077 u32 tx_stat_outxonsent
;
1078 u32 tx_stat_outxoffsent
;
1079 u32 tx_stat_flowcontroldone
;
1080 u32 tx_stat_dot3statssinglecollisionframes
;
1081 u32 tx_stat_dot3statsmultiplecollisionframes
;
1082 u32 tx_stat_dot3statsdeferredtransmissions
;
1083 u32 tx_stat_dot3statsexcessivecollisions
;
1084 u32 tx_stat_dot3statslatecollisions
;
1085 u32 tx_stat_ifhcoutucastpkts
;
1086 u32 tx_stat_ifhcoutmulticastpkts
;
1087 u32 tx_stat_ifhcoutbroadcastpkts
;
1088 u32 tx_stat_etherstatspkts64octets
;
1089 u32 tx_stat_etherstatspkts65octetsto127octets
;
1090 u32 tx_stat_etherstatspkts128octetsto255octets
;
1091 u32 tx_stat_etherstatspkts256octetsto511octets
;
1092 u32 tx_stat_etherstatspkts512octetsto1023octets
;
1093 u32 tx_stat_etherstatspkts1024octetsto1522octets
;
1094 u32 tx_stat_etherstatspktsover1522octets
;
1095 u32 tx_stat_dot3statsinternalmactransmiterrors
;
1100 u32 tx_stat_gtpkt_lo
;
1101 u32 tx_stat_gtpkt_hi
;
1102 u32 tx_stat_gtxpf_lo
;
1103 u32 tx_stat_gtxpf_hi
;
1104 u32 tx_stat_gtfcs_lo
;
1105 u32 tx_stat_gtfcs_hi
;
1106 u32 tx_stat_gtmca_lo
;
1107 u32 tx_stat_gtmca_hi
;
1108 u32 tx_stat_gtbca_lo
;
1109 u32 tx_stat_gtbca_hi
;
1110 u32 tx_stat_gtfrg_lo
;
1111 u32 tx_stat_gtfrg_hi
;
1112 u32 tx_stat_gtovr_lo
;
1113 u32 tx_stat_gtovr_hi
;
1114 u32 tx_stat_gt64_lo
;
1115 u32 tx_stat_gt64_hi
;
1116 u32 tx_stat_gt127_lo
;
1117 u32 tx_stat_gt127_hi
;
1118 u32 tx_stat_gt255_lo
;
1119 u32 tx_stat_gt255_hi
;
1120 u32 tx_stat_gt511_lo
;
1121 u32 tx_stat_gt511_hi
;
1122 u32 tx_stat_gt1023_lo
;
1123 u32 tx_stat_gt1023_hi
;
1124 u32 tx_stat_gt1518_lo
;
1125 u32 tx_stat_gt1518_hi
;
1126 u32 tx_stat_gt2047_lo
;
1127 u32 tx_stat_gt2047_hi
;
1128 u32 tx_stat_gt4095_lo
;
1129 u32 tx_stat_gt4095_hi
;
1130 u32 tx_stat_gt9216_lo
;
1131 u32 tx_stat_gt9216_hi
;
1132 u32 tx_stat_gt16383_lo
;
1133 u32 tx_stat_gt16383_hi
;
1134 u32 tx_stat_gtmax_lo
;
1135 u32 tx_stat_gtmax_hi
;
1136 u32 tx_stat_gtufl_lo
;
1137 u32 tx_stat_gtufl_hi
;
1138 u32 tx_stat_gterr_lo
;
1139 u32 tx_stat_gterr_hi
;
1140 u32 tx_stat_gtbyt_lo
;
1141 u32 tx_stat_gtbyt_hi
;
1143 u32 rx_stat_gr64_lo
;
1144 u32 rx_stat_gr64_hi
;
1145 u32 rx_stat_gr127_lo
;
1146 u32 rx_stat_gr127_hi
;
1147 u32 rx_stat_gr255_lo
;
1148 u32 rx_stat_gr255_hi
;
1149 u32 rx_stat_gr511_lo
;
1150 u32 rx_stat_gr511_hi
;
1151 u32 rx_stat_gr1023_lo
;
1152 u32 rx_stat_gr1023_hi
;
1153 u32 rx_stat_gr1518_lo
;
1154 u32 rx_stat_gr1518_hi
;
1155 u32 rx_stat_gr2047_lo
;
1156 u32 rx_stat_gr2047_hi
;
1157 u32 rx_stat_gr4095_lo
;
1158 u32 rx_stat_gr4095_hi
;
1159 u32 rx_stat_gr9216_lo
;
1160 u32 rx_stat_gr9216_hi
;
1161 u32 rx_stat_gr16383_lo
;
1162 u32 rx_stat_gr16383_hi
;
1163 u32 rx_stat_grmax_lo
;
1164 u32 rx_stat_grmax_hi
;
1165 u32 rx_stat_grpkt_lo
;
1166 u32 rx_stat_grpkt_hi
;
1167 u32 rx_stat_grfcs_lo
;
1168 u32 rx_stat_grfcs_hi
;
1169 u32 rx_stat_grmca_lo
;
1170 u32 rx_stat_grmca_hi
;
1171 u32 rx_stat_grbca_lo
;
1172 u32 rx_stat_grbca_hi
;
1173 u32 rx_stat_grxcf_lo
;
1174 u32 rx_stat_grxcf_hi
;
1175 u32 rx_stat_grxpf_lo
;
1176 u32 rx_stat_grxpf_hi
;
1177 u32 rx_stat_grxuo_lo
;
1178 u32 rx_stat_grxuo_hi
;
1179 u32 rx_stat_grjbr_lo
;
1180 u32 rx_stat_grjbr_hi
;
1181 u32 rx_stat_grovr_lo
;
1182 u32 rx_stat_grovr_hi
;
1183 u32 rx_stat_grflr_lo
;
1184 u32 rx_stat_grflr_hi
;
1185 u32 rx_stat_grmeg_lo
;
1186 u32 rx_stat_grmeg_hi
;
1187 u32 rx_stat_grmeb_lo
;
1188 u32 rx_stat_grmeb_hi
;
1189 u32 rx_stat_grbyt_lo
;
1190 u32 rx_stat_grbyt_hi
;
1191 u32 rx_stat_grund_lo
;
1192 u32 rx_stat_grund_hi
;
1193 u32 rx_stat_grfrg_lo
;
1194 u32 rx_stat_grfrg_hi
;
1195 u32 rx_stat_grerb_lo
;
1196 u32 rx_stat_grerb_hi
;
1197 u32 rx_stat_grfre_lo
;
1198 u32 rx_stat_grfre_hi
;
1199 u32 rx_stat_gripj_lo
;
1200 u32 rx_stat_gripj_hi
;
1205 struct emac_stats emac_stats
;
1206 struct bmac_stats bmac_stats
;
1212 u32 rx_stat_ifhcinbadoctets_hi
;
1213 u32 rx_stat_ifhcinbadoctets_lo
;
1215 /* out_bad_octets */
1216 u32 tx_stat_ifhcoutbadoctets_hi
;
1217 u32 tx_stat_ifhcoutbadoctets_lo
;
1219 /* crc_receive_errors */
1220 u32 rx_stat_dot3statsfcserrors_hi
;
1221 u32 rx_stat_dot3statsfcserrors_lo
;
1222 /* alignment_errors */
1223 u32 rx_stat_dot3statsalignmenterrors_hi
;
1224 u32 rx_stat_dot3statsalignmenterrors_lo
;
1225 /* carrier_sense_errors */
1226 u32 rx_stat_dot3statscarriersenseerrors_hi
;
1227 u32 rx_stat_dot3statscarriersenseerrors_lo
;
1228 /* false_carrier_detections */
1229 u32 rx_stat_falsecarriererrors_hi
;
1230 u32 rx_stat_falsecarriererrors_lo
;
1232 /* runt_packets_received */
1233 u32 rx_stat_etherstatsundersizepkts_hi
;
1234 u32 rx_stat_etherstatsundersizepkts_lo
;
1235 /* jabber_packets_received */
1236 u32 rx_stat_dot3statsframestoolong_hi
;
1237 u32 rx_stat_dot3statsframestoolong_lo
;
1239 /* error_runt_packets_received */
1240 u32 rx_stat_etherstatsfragments_hi
;
1241 u32 rx_stat_etherstatsfragments_lo
;
1242 /* error_jabber_packets_received */
1243 u32 rx_stat_etherstatsjabbers_hi
;
1244 u32 rx_stat_etherstatsjabbers_lo
;
1246 /* control_frames_received */
1247 u32 rx_stat_maccontrolframesreceived_hi
;
1248 u32 rx_stat_maccontrolframesreceived_lo
;
1249 u32 rx_stat_bmac_xpf_hi
;
1250 u32 rx_stat_bmac_xpf_lo
;
1251 u32 rx_stat_bmac_xcf_hi
;
1252 u32 rx_stat_bmac_xcf_lo
;
1254 /* xoff_state_entered */
1255 u32 rx_stat_xoffstateentered_hi
;
1256 u32 rx_stat_xoffstateentered_lo
;
1257 /* pause_xon_frames_received */
1258 u32 rx_stat_xonpauseframesreceived_hi
;
1259 u32 rx_stat_xonpauseframesreceived_lo
;
1260 /* pause_xoff_frames_received */
1261 u32 rx_stat_xoffpauseframesreceived_hi
;
1262 u32 rx_stat_xoffpauseframesreceived_lo
;
1263 /* pause_xon_frames_transmitted */
1264 u32 tx_stat_outxonsent_hi
;
1265 u32 tx_stat_outxonsent_lo
;
1266 /* pause_xoff_frames_transmitted */
1267 u32 tx_stat_outxoffsent_hi
;
1268 u32 tx_stat_outxoffsent_lo
;
1269 /* flow_control_done */
1270 u32 tx_stat_flowcontroldone_hi
;
1271 u32 tx_stat_flowcontroldone_lo
;
1273 /* ether_stats_collisions */
1274 u32 tx_stat_etherstatscollisions_hi
;
1275 u32 tx_stat_etherstatscollisions_lo
;
1276 /* single_collision_transmit_frames */
1277 u32 tx_stat_dot3statssinglecollisionframes_hi
;
1278 u32 tx_stat_dot3statssinglecollisionframes_lo
;
1279 /* multiple_collision_transmit_frames */
1280 u32 tx_stat_dot3statsmultiplecollisionframes_hi
;
1281 u32 tx_stat_dot3statsmultiplecollisionframes_lo
;
1282 /* deferred_transmissions */
1283 u32 tx_stat_dot3statsdeferredtransmissions_hi
;
1284 u32 tx_stat_dot3statsdeferredtransmissions_lo
;
1285 /* excessive_collision_frames */
1286 u32 tx_stat_dot3statsexcessivecollisions_hi
;
1287 u32 tx_stat_dot3statsexcessivecollisions_lo
;
1288 /* late_collision_frames */
1289 u32 tx_stat_dot3statslatecollisions_hi
;
1290 u32 tx_stat_dot3statslatecollisions_lo
;
1292 /* frames_transmitted_64_bytes */
1293 u32 tx_stat_etherstatspkts64octets_hi
;
1294 u32 tx_stat_etherstatspkts64octets_lo
;
1295 /* frames_transmitted_65_127_bytes */
1296 u32 tx_stat_etherstatspkts65octetsto127octets_hi
;
1297 u32 tx_stat_etherstatspkts65octetsto127octets_lo
;
1298 /* frames_transmitted_128_255_bytes */
1299 u32 tx_stat_etherstatspkts128octetsto255octets_hi
;
1300 u32 tx_stat_etherstatspkts128octetsto255octets_lo
;
1301 /* frames_transmitted_256_511_bytes */
1302 u32 tx_stat_etherstatspkts256octetsto511octets_hi
;
1303 u32 tx_stat_etherstatspkts256octetsto511octets_lo
;
1304 /* frames_transmitted_512_1023_bytes */
1305 u32 tx_stat_etherstatspkts512octetsto1023octets_hi
;
1306 u32 tx_stat_etherstatspkts512octetsto1023octets_lo
;
1307 /* frames_transmitted_1024_1522_bytes */
1308 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi
;
1309 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo
;
1310 /* frames_transmitted_1523_9022_bytes */
1311 u32 tx_stat_etherstatspktsover1522octets_hi
;
1312 u32 tx_stat_etherstatspktsover1522octets_lo
;
1313 u32 tx_stat_bmac_2047_hi
;
1314 u32 tx_stat_bmac_2047_lo
;
1315 u32 tx_stat_bmac_4095_hi
;
1316 u32 tx_stat_bmac_4095_lo
;
1317 u32 tx_stat_bmac_9216_hi
;
1318 u32 tx_stat_bmac_9216_lo
;
1319 u32 tx_stat_bmac_16383_hi
;
1320 u32 tx_stat_bmac_16383_lo
;
1322 /* internal_mac_transmit_errors */
1323 u32 tx_stat_dot3statsinternalmactransmiterrors_hi
;
1324 u32 tx_stat_dot3statsinternalmactransmiterrors_lo
;
1326 /* if_out_discards */
1327 u32 tx_stat_bmac_ufl_hi
;
1328 u32 tx_stat_bmac_ufl_lo
;
1332 #define MAC_STX_IDX_MAX 2
1334 struct host_port_stats
{
1335 u32 host_port_stats_start
;
1337 struct mac_stx mac_stx
[MAC_STX_IDX_MAX
];
1342 u32 host_port_stats_end
;
1346 struct host_func_stats
{
1347 u32 host_func_stats_start
;
1349 u32 total_bytes_received_hi
;
1350 u32 total_bytes_received_lo
;
1352 u32 total_bytes_transmitted_hi
;
1353 u32 total_bytes_transmitted_lo
;
1355 u32 total_unicast_packets_received_hi
;
1356 u32 total_unicast_packets_received_lo
;
1358 u32 total_multicast_packets_received_hi
;
1359 u32 total_multicast_packets_received_lo
;
1361 u32 total_broadcast_packets_received_hi
;
1362 u32 total_broadcast_packets_received_lo
;
1364 u32 total_unicast_packets_transmitted_hi
;
1365 u32 total_unicast_packets_transmitted_lo
;
1367 u32 total_multicast_packets_transmitted_hi
;
1368 u32 total_multicast_packets_transmitted_lo
;
1370 u32 total_broadcast_packets_transmitted_hi
;
1371 u32 total_broadcast_packets_transmitted_lo
;
1373 u32 valid_bytes_received_hi
;
1374 u32 valid_bytes_received_lo
;
1376 u32 host_func_stats_end
;
1380 #define BCM_5710_FW_MAJOR_VERSION 5
1381 #define BCM_5710_FW_MINOR_VERSION 2
1382 #define BCM_5710_FW_REVISION_VERSION 13
1383 #define BCM_5710_FW_ENGINEERING_VERSION 0
1384 #define BCM_5710_FW_COMPILE_FLAGS 1
1390 struct atten_def_status_block
{
1392 __le32 attn_bits_ack
;
1395 __le16 attn_bits_index
;
1401 * common data for all protocols
1403 struct doorbell_hdr
{
1405 #define DOORBELL_HDR_RX (0x1<<0)
1406 #define DOORBELL_HDR_RX_SHIFT 0
1407 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1408 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1409 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1410 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1411 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1412 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1416 * doorbell message sent to the chip
1419 #if defined(__BIG_ENDIAN)
1422 struct doorbell_hdr header
;
1423 #elif defined(__LITTLE_ENDIAN)
1424 struct doorbell_hdr header
;
1432 * doorbell message sent to the chip
1434 struct doorbell_set_prod
{
1435 #if defined(__BIG_ENDIAN)
1438 struct doorbell_hdr header
;
1439 #elif defined(__LITTLE_ENDIAN)
1440 struct doorbell_hdr header
;
1448 * IGU driver acknowledgement register
1450 struct igu_ack_register
{
1451 #if defined(__BIG_ENDIAN)
1452 u16 sb_id_and_flags
;
1453 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1454 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1455 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1456 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1457 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1458 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1459 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1460 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1461 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1462 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1463 u16 status_block_index
;
1464 #elif defined(__LITTLE_ENDIAN)
1465 u16 status_block_index
;
1466 u16 sb_id_and_flags
;
1467 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1468 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1469 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1470 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1471 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1472 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1473 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1474 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1475 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1476 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1482 * IGU driver acknowledgement register
1484 struct igu_backward_compatible
{
1485 u32 sb_id_and_flags
;
1486 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
1487 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
1488 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
1489 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
1490 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
1491 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
1492 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
1493 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
1494 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
1495 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
1496 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
1497 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
1503 * IGU driver acknowledgement register
1505 struct igu_regular
{
1506 u32 sb_id_and_flags
;
1507 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
1508 #define IGU_REGULAR_SB_INDEX_SHIFT 0
1509 #define IGU_REGULAR_RESERVED0 (0x1<<20)
1510 #define IGU_REGULAR_RESERVED0_SHIFT 20
1511 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
1512 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
1513 #define IGU_REGULAR_BUPDATE (0x1<<24)
1514 #define IGU_REGULAR_BUPDATE_SHIFT 24
1515 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
1516 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
1517 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
1518 #define IGU_REGULAR_RESERVED_1_SHIFT 27
1519 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
1520 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
1521 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
1522 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
1523 #define IGU_REGULAR_BCLEANUP (0x1<<31)
1524 #define IGU_REGULAR_BCLEANUP_SHIFT 31
1529 * IGU driver acknowledgement register
1531 union igu_consprod_reg
{
1532 struct igu_regular regular
;
1533 struct igu_backward_compatible backward_compatible
;
1538 * Parser parsing flags field
1540 struct parsing_flags
{
1542 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1543 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1544 #define PARSING_FLAGS_VLAN (0x1<<1)
1545 #define PARSING_FLAGS_VLAN_SHIFT 1
1546 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1547 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1548 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1549 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1550 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1551 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1552 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1553 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1554 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1555 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1556 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1557 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1558 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1559 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1560 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1561 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1562 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1563 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1564 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1565 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1566 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1567 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1578 * dmae command structure
1580 struct dmae_command
{
1582 #define DMAE_COMMAND_SRC (0x1<<0)
1583 #define DMAE_COMMAND_SRC_SHIFT 0
1584 #define DMAE_COMMAND_DST (0x3<<1)
1585 #define DMAE_COMMAND_DST_SHIFT 1
1586 #define DMAE_COMMAND_C_DST (0x1<<3)
1587 #define DMAE_COMMAND_C_DST_SHIFT 3
1588 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1589 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1590 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1591 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1592 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1593 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1594 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1595 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1596 #define DMAE_COMMAND_PORT (0x1<<11)
1597 #define DMAE_COMMAND_PORT_SHIFT 11
1598 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1599 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1600 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1601 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1602 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1603 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1604 #define DMAE_COMMAND_E1HVN (0x3<<15)
1605 #define DMAE_COMMAND_E1HVN_SHIFT 15
1606 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1607 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1612 #if defined(__BIG_ENDIAN)
1615 #elif defined(__LITTLE_ENDIAN)
1624 #if defined(__BIG_ENDIAN)
1627 #elif defined(__LITTLE_ENDIAN)
1631 #if defined(__BIG_ENDIAN)
1634 #elif defined(__LITTLE_ENDIAN)
1638 #if defined(__BIG_ENDIAN)
1641 #elif defined(__LITTLE_ENDIAN)
1648 struct double_regpair
{
1657 * The eth storm context of Ustorm (configuration part)
1659 struct ustorm_eth_st_context_config
{
1660 #if defined(__BIG_ENDIAN)
1662 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1663 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1664 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1665 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1666 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1667 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1668 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
1669 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
1670 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1671 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1674 u8 sb_index_numbers
;
1675 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1676 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1677 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1678 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1679 #elif defined(__LITTLE_ENDIAN)
1680 u8 sb_index_numbers
;
1681 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1682 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1683 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1684 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1688 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1689 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1690 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1691 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1692 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1693 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1694 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
1695 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
1696 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1697 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1699 #if defined(__BIG_ENDIAN)
1701 u8 statistics_counter_id
;
1702 u8 mc_alignment_log_size
;
1703 #elif defined(__LITTLE_ENDIAN)
1704 u8 mc_alignment_log_size
;
1705 u8 statistics_counter_id
;
1708 #if defined(__BIG_ENDIAN)
1709 u8 __local_sge_prod
;
1712 #elif defined(__LITTLE_ENDIAN)
1715 u8 __local_sge_prod
;
1717 #if defined(__BIG_ENDIAN)
1718 u16 __sdm_bd_expected_counter
;
1720 u8 __expected_bds_on_ram
;
1721 #elif defined(__LITTLE_ENDIAN)
1722 u8 __expected_bds_on_ram
;
1724 u16 __sdm_bd_expected_counter
;
1726 #if defined(__BIG_ENDIAN)
1727 u16 __ring_data_ram_addr
;
1728 u16 __hc_cstorm_ram_addr
;
1729 #elif defined(__LITTLE_ENDIAN)
1730 u16 __hc_cstorm_ram_addr
;
1731 u16 __ring_data_ram_addr
;
1733 #if defined(__BIG_ENDIAN)
1735 u8 max_sges_for_packet
;
1736 u16 __bd_ring_ram_addr
;
1737 #elif defined(__LITTLE_ENDIAN)
1738 u16 __bd_ring_ram_addr
;
1739 u8 max_sges_for_packet
;
1742 u32 bd_page_base_lo
;
1743 u32 bd_page_base_hi
;
1744 u32 sge_page_base_lo
;
1745 u32 sge_page_base_hi
;
1746 struct regpair reserved2
;
1750 * The eth Rx Buffer Descriptor
1758 * The eth Rx SGE Descriptor
1766 * Local BDs and SGEs rings (in ETH)
1768 struct eth_local_rx_rings
{
1769 struct eth_rx_bd __local_bd_ring
[8];
1770 struct eth_rx_sge __local_sge_ring
[10];
1774 * The eth storm context of Ustorm
1776 struct ustorm_eth_st_context
{
1777 struct ustorm_eth_st_context_config common
;
1778 struct eth_local_rx_rings __rings
;
1782 * The eth storm context of Tstorm
1784 struct tstorm_eth_st_context
{
1785 u32 __reserved0
[28];
1789 * The eth aggregative context section of Xstorm
1791 struct xstorm_eth_extra_ag_context_section
{
1792 #if defined(__BIG_ENDIAN)
1796 #elif defined(__LITTLE_ENDIAN)
1805 #if defined(__BIG_ENDIAN)
1808 u16 __tcp_agg_vars2
;
1809 #elif defined(__LITTLE_ENDIAN)
1810 u16 __tcp_agg_vars2
;
1818 #if defined(__BIG_ENDIAN)
1821 #elif defined(__LITTLE_ENDIAN)
1825 #if defined(__BIG_ENDIAN)
1830 #elif defined(__LITTLE_ENDIAN)
1836 u32 __tcp_agg_vars6
;
1837 #if defined(__BIG_ENDIAN)
1839 u16 __tcp_agg_vars7
;
1840 #elif defined(__LITTLE_ENDIAN)
1841 u16 __tcp_agg_vars7
;
1846 #if defined(__BIG_ENDIAN)
1850 #elif defined(__LITTLE_ENDIAN)
1858 * The eth aggregative context of Xstorm
1860 struct xstorm_eth_ag_context
{
1861 #if defined(__BIG_ENDIAN)
1865 #elif defined(__LITTLE_ENDIAN)
1870 #if defined(__BIG_ENDIAN)
1875 #elif defined(__LITTLE_ENDIAN)
1882 #if defined(__BIG_ENDIAN)
1885 #elif defined(__LITTLE_ENDIAN)
1889 struct xstorm_eth_extra_ag_context_section __extra_section
;
1890 #if defined(__BIG_ENDIAN)
1894 #elif defined(__LITTLE_ENDIAN)
1899 #if defined(__BIG_ENDIAN)
1902 #elif defined(__LITTLE_ENDIAN)
1906 #if defined(__BIG_ENDIAN)
1910 #elif defined(__LITTLE_ENDIAN)
1915 #if defined(__BIG_ENDIAN)
1918 #elif defined(__LITTLE_ENDIAN)
1923 #if defined(__BIG_ENDIAN)
1926 #elif defined(__LITTLE_ENDIAN)
1930 #if defined(__BIG_ENDIAN)
1935 #elif defined(__LITTLE_ENDIAN)
1941 #if defined(__BIG_ENDIAN)
1943 u16 __bd_ind_max_val
;
1944 #elif defined(__LITTLE_ENDIAN)
1945 u16 __bd_ind_max_val
;
1954 * The eth extra aggregative context section of Tstorm
1956 struct tstorm_eth_extra_ag_context_section
{
1958 #if defined(__BIG_ENDIAN)
1962 #elif defined(__LITTLE_ENDIAN)
1967 #if defined(__BIG_ENDIAN)
1971 #elif defined(__LITTLE_ENDIAN)
1981 u32 __tcp_agg_vars1
;
1988 * The eth aggregative context of Tstorm
1990 struct tstorm_eth_ag_context
{
1991 #if defined(__BIG_ENDIAN)
1995 #elif defined(__LITTLE_ENDIAN)
2000 #if defined(__BIG_ENDIAN)
2003 #elif defined(__LITTLE_ENDIAN)
2007 struct tstorm_eth_extra_ag_context_section __extra_section
;
2011 * The eth aggregative context of Cstorm
2013 struct cstorm_eth_ag_context
{
2015 #if defined(__BIG_ENDIAN)
2019 #elif defined(__LITTLE_ENDIAN)
2024 u32 __num_of_treated_packet
;
2025 u32 __last_packet_treated
;
2026 #if defined(__BIG_ENDIAN)
2029 #elif defined(__LITTLE_ENDIAN)
2033 #if defined(__BIG_ENDIAN)
2038 #elif defined(__LITTLE_ENDIAN)
2044 #if defined(__BIG_ENDIAN)
2047 #elif defined(__LITTLE_ENDIAN)
2052 #if defined(__BIG_ENDIAN)
2055 #elif defined(__LITTLE_ENDIAN)
2059 #if defined(__BIG_ENDIAN)
2060 u16 __packet_index_th
;
2062 #elif defined(__LITTLE_ENDIAN)
2064 u16 __packet_index_th
;
2069 * The eth aggregative context of Ustorm
2071 struct ustorm_eth_ag_context
{
2072 #if defined(__BIG_ENDIAN)
2073 u8 __aux_counter_flags
;
2077 #elif defined(__LITTLE_ENDIAN)
2081 u8 __aux_counter_flags
;
2083 #if defined(__BIG_ENDIAN)
2087 #elif defined(__LITTLE_ENDIAN)
2093 #if defined(__BIG_ENDIAN)
2097 #elif defined(__LITTLE_ENDIAN)
2104 #if defined(__BIG_ENDIAN)
2107 #elif defined(__LITTLE_ENDIAN)
2111 #if defined(__BIG_ENDIAN)
2113 u8 __decision_rules
;
2114 u8 __decision_rule_enable_bits
;
2115 #elif defined(__LITTLE_ENDIAN)
2116 u8 __decision_rule_enable_bits
;
2117 u8 __decision_rules
;
2123 * Timers connection context
2125 struct timers_block_context
{
2130 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
2131 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
2132 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
2133 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
2134 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
2135 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
2139 * structure for easy accessibility to assembler
2141 struct eth_tx_bd_flags
{
2143 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
2144 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
2145 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
2146 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
2147 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<2)
2148 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 2
2149 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
2150 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
2151 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
2152 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2153 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
2154 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
2155 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
2156 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2157 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
2158 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2162 * The eth Tx Buffer Descriptor
2164 struct eth_tx_start_bd
{
2170 struct eth_tx_bd_flags bd_flags
;
2172 #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
2173 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2174 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
2175 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2179 * Tx regular BD structure
2184 u16 total_pkt_bytes
;
2190 * Tx parsing BD structure for ETH,Relevant in START
2192 struct eth_tx_parse_bd
{
2194 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
2195 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
2196 #define ETH_TX_PARSE_BD_UDP_CS_FLG (0x1<<4)
2197 #define ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT 4
2198 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
2199 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2200 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
2201 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
2202 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
2203 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
2205 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
2206 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
2207 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
2208 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
2209 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
2210 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
2211 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
2212 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
2213 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
2214 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
2215 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
2216 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
2217 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
2218 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
2219 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
2220 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
2224 __le16 tcp_pseudo_csum
;
2227 __le32 tcp_send_seq
;
2231 * The last BD in the BD memory will hold a pointer to the next BD memory
2233 struct eth_tx_next_bd
{
2240 * union for 4 Bd types
2242 union eth_tx_bd_types
{
2243 struct eth_tx_start_bd start_bd
;
2244 struct eth_tx_bd reg_bd
;
2245 struct eth_tx_parse_bd parse_bd
;
2246 struct eth_tx_next_bd next_bd
;
2250 * The eth storm context of Xstorm
2252 struct xstorm_eth_st_context
{
2253 u32 tx_bd_page_base_lo
;
2254 u32 tx_bd_page_base_hi
;
2255 #if defined(__BIG_ENDIAN)
2258 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
2259 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
2260 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
2261 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2262 u8 __local_tx_bd_prod
;
2263 #elif defined(__LITTLE_ENDIAN)
2264 u8 __local_tx_bd_prod
;
2266 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
2267 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
2268 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
2269 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2274 #if defined(__BIG_ENDIAN)
2275 u8 __ram_cache_index
;
2276 u8 __double_buffer_client
;
2278 #elif defined(__LITTLE_ENDIAN)
2280 u8 __double_buffer_client
;
2281 u8 __ram_cache_index
;
2283 #if defined(__BIG_ENDIAN)
2284 u16 __statistics_address
;
2286 #elif defined(__LITTLE_ENDIAN)
2288 u16 __statistics_address
;
2290 #if defined(__BIG_ENDIAN)
2291 u8 __local_tx_bd_cons
;
2295 #elif defined(__LITTLE_ENDIAN)
2299 u8 __local_tx_bd_cons
;
2301 union eth_tx_bd_types __bds
[13];
2305 * The eth storm context of Cstorm
2307 struct cstorm_eth_st_context
{
2308 #if defined(__BIG_ENDIAN)
2312 #elif defined(__LITTLE_ENDIAN)
2321 * Ethernet connection context
2323 struct eth_context
{
2324 struct ustorm_eth_st_context ustorm_st_context
;
2325 struct tstorm_eth_st_context tstorm_st_context
;
2326 struct xstorm_eth_ag_context xstorm_ag_context
;
2327 struct tstorm_eth_ag_context tstorm_ag_context
;
2328 struct cstorm_eth_ag_context cstorm_ag_context
;
2329 struct ustorm_eth_ag_context ustorm_ag_context
;
2330 struct timers_block_context timers_context
;
2331 struct xstorm_eth_st_context xstorm_st_context
;
2332 struct cstorm_eth_st_context cstorm_st_context
;
2339 struct eth_tx_doorbell
{
2340 #if defined(__BIG_ENDIAN)
2343 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2344 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2345 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2346 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2347 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2348 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2349 struct doorbell_hdr hdr
;
2350 #elif defined(__LITTLE_ENDIAN)
2351 struct doorbell_hdr hdr
;
2353 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2354 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2355 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2356 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2357 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2358 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2365 * cstorm default status block, generated by ustorm
2367 struct cstorm_def_status_block_u
{
2368 __le16 index_values
[HC_USTORM_DEF_SB_NUM_INDICES
];
2369 __le16 status_block_index
;
2376 * cstorm default status block, generated by cstorm
2378 struct cstorm_def_status_block_c
{
2379 __le16 index_values
[HC_CSTORM_DEF_SB_NUM_INDICES
];
2380 __le16 status_block_index
;
2387 * xstorm status block
2389 struct xstorm_def_status_block
{
2390 __le16 index_values
[HC_XSTORM_DEF_SB_NUM_INDICES
];
2391 __le16 status_block_index
;
2398 * tstorm status block
2400 struct tstorm_def_status_block
{
2401 __le16 index_values
[HC_TSTORM_DEF_SB_NUM_INDICES
];
2402 __le16 status_block_index
;
2411 struct host_def_status_block
{
2412 struct atten_def_status_block atten_status_block
;
2413 struct cstorm_def_status_block_u u_def_status_block
;
2414 struct cstorm_def_status_block_c c_def_status_block
;
2415 struct xstorm_def_status_block x_def_status_block
;
2416 struct tstorm_def_status_block t_def_status_block
;
2421 * cstorm status block, generated by ustorm
2423 struct cstorm_status_block_u
{
2424 __le16 index_values
[HC_USTORM_SB_NUM_INDICES
];
2425 __le16 status_block_index
;
2432 * cstorm status block, generated by cstorm
2434 struct cstorm_status_block_c
{
2435 __le16 index_values
[HC_CSTORM_SB_NUM_INDICES
];
2436 __le16 status_block_index
;
2445 struct host_status_block
{
2446 struct cstorm_status_block_u u_status_block
;
2447 struct cstorm_status_block_c c_status_block
;
2452 * The data for RSS setup ramrod
2454 struct eth_client_setup_ramrod_data
{
2463 * regular eth FP CQE parameters struct
2465 struct eth_fast_path_rx_cqe
{
2466 u8 type_error_flags
;
2467 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2468 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2469 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2470 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2471 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2472 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2473 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2474 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2475 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2476 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2477 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2478 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2479 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2480 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2482 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2483 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2484 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2485 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2486 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2487 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2488 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2489 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2490 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2491 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2492 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2493 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2494 u8 placement_offset
;
2496 __le32 rss_hash_result
;
2500 struct parsing_flags pars_flags
;
2506 * The data for RSS setup ramrod
2508 struct eth_halt_ramrod_data
{
2515 * The data for statistics query ramrod
2517 struct eth_query_ramrod_data
{
2518 #if defined(__BIG_ENDIAN)
2522 #elif defined(__LITTLE_ENDIAN)
2532 * Place holder for ramrods protocol specific data
2534 struct ramrod_data
{
2540 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2542 union eth_ramrod_data
{
2543 struct ramrod_data general
;
2548 * Eth Rx Cqe structure- general structure for ramrods
2550 struct common_ramrod_eth_rx_cqe
{
2552 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2553 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2554 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1)
2555 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2556 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2)
2557 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2560 __le32 conn_and_cmd_data
;
2561 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2562 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2563 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2564 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2565 struct ramrod_data protocol_data
;
2566 __le32 reserved2
[4];
2570 * Rx Last CQE in page (in ETH)
2572 struct eth_rx_cqe_next_page
{
2579 * union for all eth rx cqe types (fix their sizes)
2582 struct eth_fast_path_rx_cqe fast_path_cqe
;
2583 struct common_ramrod_eth_rx_cqe ramrod_cqe
;
2584 struct eth_rx_cqe_next_page next_page_cqe
;
2589 * common data for all protocols
2592 __le32 conn_and_cmd_data
;
2593 #define SPE_HDR_CID (0xFFFFFF<<0)
2594 #define SPE_HDR_CID_SHIFT 0
2595 #define SPE_HDR_CMD_ID (0xFF<<24)
2596 #define SPE_HDR_CMD_ID_SHIFT 24
2598 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2599 #define SPE_HDR_CONN_TYPE_SHIFT 0
2600 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2601 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2606 * Ethernet slow path element
2608 union eth_specific_data
{
2609 u8 protocol_data
[8];
2610 struct regpair mac_config_addr
;
2611 struct eth_client_setup_ramrod_data client_setup_ramrod_data
;
2612 struct eth_halt_ramrod_data halt_ramrod_data
;
2613 struct regpair leading_cqe_addr
;
2614 struct regpair update_data_addr
;
2615 struct eth_query_ramrod_data query_ramrod_data
;
2619 * Ethernet slow path element
2623 union eth_specific_data data
;
2628 * array of 13 bds as appears in the eth xstorm context
2630 struct eth_tx_bds_array
{
2631 union eth_tx_bd_types bds
[13];
2636 * Common configuration parameters per function in Tstorm
2638 struct tstorm_eth_function_common_config
{
2639 #if defined(__BIG_ENDIAN)
2640 u8 leading_client_id
;
2643 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2644 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2645 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2646 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2647 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2648 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2649 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2650 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2651 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2652 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2653 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2654 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2655 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2656 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2657 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2658 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2659 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
2660 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
2661 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
2662 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
2663 #elif defined(__LITTLE_ENDIAN)
2665 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2666 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2667 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2668 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2669 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2670 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2671 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2672 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2673 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2674 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2675 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2676 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2677 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2678 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2679 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2680 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2681 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
2682 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
2683 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
2684 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
2686 u8 leading_client_id
;
2692 * RSS idirection table update configuration
2694 struct rss_update_config
{
2695 #if defined(__BIG_ENDIAN)
2698 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2699 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2700 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2701 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2702 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2703 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2704 #elif defined(__LITTLE_ENDIAN)
2706 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2707 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2708 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2709 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2710 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2711 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2718 * parameters for eth update ramrod
2720 struct eth_update_ramrod_data
{
2721 struct tstorm_eth_function_common_config func_config
;
2722 u8 indirectionTable
[128];
2723 struct rss_update_config rss_config
;
2728 * MAC filtering configuration command header
2730 struct mac_configuration_hdr
{
2738 * MAC address in list for ramrod
2740 struct tstorm_cam_entry
{
2741 __le16 lsb_mac_addr
;
2742 __le16 middle_mac_addr
;
2743 __le16 msb_mac_addr
;
2745 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2746 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2747 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2748 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2749 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2750 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2754 * MAC filtering: CAM target table entry
2756 struct tstorm_cam_target_table_entry
{
2758 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2759 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2760 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2761 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2762 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2763 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2764 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2765 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2766 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2767 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2770 u32 clients_bit_vector
;
2774 * MAC address in list for ramrod
2776 struct mac_configuration_entry
{
2777 struct tstorm_cam_entry cam_entry
;
2778 struct tstorm_cam_target_table_entry target_table_entry
;
2782 * MAC filtering configuration command
2784 struct mac_configuration_cmd
{
2785 struct mac_configuration_hdr hdr
;
2786 struct mac_configuration_entry config_table
[64];
2791 * MAC address in list for ramrod
2793 struct mac_configuration_entry_e1h
{
2794 __le16 lsb_mac_addr
;
2795 __le16 middle_mac_addr
;
2796 __le16 msb_mac_addr
;
2801 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2802 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2803 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2804 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2805 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2806 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2807 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1 (0x1F<<3)
2808 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT 3
2809 u32 clients_bit_vector
;
2813 * MAC filtering configuration command
2815 struct mac_configuration_cmd_e1h
{
2816 struct mac_configuration_hdr hdr
;
2817 struct mac_configuration_entry_e1h config_table
[32];
2822 * approximate-match multicast filtering for E1H per function in Tstorm
2824 struct tstorm_eth_approximate_match_multicast_filtering
{
2825 u32 mcast_add_hash_bit_array
[8];
2830 * Configuration parameters per client in Tstorm
2832 struct tstorm_eth_client_config
{
2833 #if defined(__BIG_ENDIAN)
2835 u8 statistics_counter_id
;
2837 #elif defined(__LITTLE_ENDIAN)
2839 u8 statistics_counter_id
;
2842 #if defined(__BIG_ENDIAN)
2844 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2845 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2846 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2847 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2848 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2849 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2850 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2851 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2852 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
2853 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
2855 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2856 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2857 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2858 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2859 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2860 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2861 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
2862 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
2863 #elif defined(__LITTLE_ENDIAN)
2865 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2866 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2867 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2868 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2869 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2870 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2871 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
2872 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
2874 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2875 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2876 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2877 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2878 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2879 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2880 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2881 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2882 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
2883 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
2889 * MAC filtering configuration parameters per port in Tstorm
2891 struct tstorm_eth_mac_filter_config
{
2893 u32 ucast_accept_all
;
2895 u32 mcast_accept_all
;
2897 u32 bcast_accept_all
;
2905 * common flag to indicate existance of TPA.
2907 struct tstorm_eth_tpa_exist
{
2908 #if defined(__BIG_ENDIAN)
2912 #elif defined(__LITTLE_ENDIAN)
2922 * rx rings pause data for E1h only
2924 struct ustorm_eth_rx_pause_data_e1h
{
2925 #if defined(__BIG_ENDIAN)
2928 #elif defined(__LITTLE_ENDIAN)
2932 #if defined(__BIG_ENDIAN)
2935 #elif defined(__LITTLE_ENDIAN)
2939 #if defined(__BIG_ENDIAN)
2942 #elif defined(__LITTLE_ENDIAN)
2946 #if defined(__BIG_ENDIAN)
2949 #elif defined(__LITTLE_ENDIAN)
2957 * Three RX producers for ETH
2959 struct ustorm_eth_rx_producers
{
2960 #if defined(__BIG_ENDIAN)
2963 #elif defined(__LITTLE_ENDIAN)
2967 #if defined(__BIG_ENDIAN)
2970 #elif defined(__LITTLE_ENDIAN)
2978 * per-port SAFC demo variables
2980 struct cmng_flags_per_port
{
2981 u8 con_number
[NUM_OF_PROTOCOLS
];
2983 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2984 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2985 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2986 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2987 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2988 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2989 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2990 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2991 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2992 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2993 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
2994 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2999 * per-port rate shaping variables
3001 struct rate_shaping_vars_per_port
{
3002 u32 rs_periodic_timeout
;
3007 * per-port fairness variables
3009 struct fairness_vars_per_port
{
3012 u32 fairness_timeout
;
3016 * per-port SAFC variables
3018 struct safc_struct_per_port
{
3019 #if defined(__BIG_ENDIAN)
3022 u8 safc_timeout_usec
;
3023 #elif defined(__LITTLE_ENDIAN)
3024 u8 safc_timeout_usec
;
3028 u16 cos_to_pause_mask
[NUM_OF_SAFC_BITS
];
3032 * Per-port congestion management variables
3034 struct cmng_struct_per_port
{
3035 struct rate_shaping_vars_per_port rs_vars
;
3036 struct fairness_vars_per_port fair_vars
;
3037 struct safc_struct_per_port safc_vars
;
3038 struct cmng_flags_per_port flags
;
3043 * Dynamic host coalescing init parameters
3045 struct dynamic_hc_config
{
3047 u8 shift_per_protocol
[HC_USTORM_SB_NUM_INDICES
];
3048 u8 hc_timeout0
[HC_USTORM_SB_NUM_INDICES
];
3049 u8 hc_timeout1
[HC_USTORM_SB_NUM_INDICES
];
3050 u8 hc_timeout2
[HC_USTORM_SB_NUM_INDICES
];
3051 u8 hc_timeout3
[HC_USTORM_SB_NUM_INDICES
];
3056 * Protocol-common statistics collected by the Xstorm (per client)
3058 struct xstorm_per_client_stats
{
3060 __le32 unicast_pkts_sent
;
3061 struct regpair unicast_bytes_sent
;
3062 struct regpair multicast_bytes_sent
;
3063 __le32 multicast_pkts_sent
;
3064 __le32 broadcast_pkts_sent
;
3065 struct regpair broadcast_bytes_sent
;
3066 __le16 stats_counter
;
3072 * Common statistics collected by the Xstorm (per port)
3074 struct xstorm_common_stats
{
3075 struct xstorm_per_client_stats client_statistics
[MAX_X_STAT_COUNTER_ID
];
3079 * Protocol-common statistics collected by the Tstorm (per port)
3081 struct tstorm_per_port_stats
{
3082 __le32 mac_filter_discard
;
3083 __le32 xxoverflow_discard
;
3084 __le32 brb_truncate_discard
;
3089 * Protocol-common statistics collected by the Tstorm (per client)
3091 struct tstorm_per_client_stats
{
3092 struct regpair rcv_unicast_bytes
;
3093 struct regpair rcv_broadcast_bytes
;
3094 struct regpair rcv_multicast_bytes
;
3095 struct regpair rcv_error_bytes
;
3096 __le32 checksum_discard
;
3097 __le32 packets_too_big_discard
;
3098 __le32 rcv_unicast_pkts
;
3099 __le32 rcv_broadcast_pkts
;
3100 __le32 rcv_multicast_pkts
;
3101 __le32 no_buff_discard
;
3102 __le32 ttl0_discard
;
3103 __le16 stats_counter
;
3108 * Protocol-common statistics collected by the Tstorm
3110 struct tstorm_common_stats
{
3111 struct tstorm_per_port_stats port_statistics
;
3112 struct tstorm_per_client_stats client_statistics
[MAX_T_STAT_COUNTER_ID
];
3116 * Protocol-common statistics collected by the Ustorm (per client)
3118 struct ustorm_per_client_stats
{
3119 struct regpair ucast_no_buff_bytes
;
3120 struct regpair mcast_no_buff_bytes
;
3121 struct regpair bcast_no_buff_bytes
;
3122 __le32 ucast_no_buff_pkts
;
3123 __le32 mcast_no_buff_pkts
;
3124 __le32 bcast_no_buff_pkts
;
3125 __le16 stats_counter
;
3130 * Protocol-common statistics collected by the Ustorm
3132 struct ustorm_common_stats
{
3133 struct ustorm_per_client_stats client_statistics
[MAX_U_STAT_COUNTER_ID
];
3137 * Eth statistics query structure for the eth_stats_query ramrod
3139 struct eth_stats_query
{
3140 struct xstorm_common_stats xstorm_common
;
3141 struct tstorm_common_stats tstorm_common
;
3142 struct ustorm_common_stats ustorm_common
;
3147 * per-vnic fairness variables
3149 struct fairness_vars_per_vn
{
3150 u32 cos_credit_delta
[MAX_COS_NUMBER
];
3151 u32 protocol_credit_delta
[NUM_OF_PROTOCOLS
];
3152 u32 vn_credit_delta
;
3158 * FW version stored in the Xstorm RAM
3161 #if defined(__BIG_ENDIAN)
3166 #elif defined(__LITTLE_ENDIAN)
3173 #define FW_VERSION_OPTIMIZED (0x1<<0)
3174 #define FW_VERSION_OPTIMIZED_SHIFT 0
3175 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
3176 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
3177 #define FW_VERSION_CHIP_VERSION (0x3<<2)
3178 #define FW_VERSION_CHIP_VERSION_SHIFT 2
3179 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
3180 #define __FW_VERSION_RESERVED_SHIFT 4
3185 * FW version stored in first line of pram
3187 struct pram_fw_version
{
3193 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
3194 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3195 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
3196 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3197 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
3198 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3199 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
3200 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3201 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
3202 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3207 * The send queue element
3209 struct protocol_common_spe
{
3211 struct regpair phy_address
;
3216 * a single rate shaping counter. can be used as protocol or vnic counter
3218 struct rate_shaping_counter
{
3220 #if defined(__BIG_ENDIAN)
3223 #elif defined(__LITTLE_ENDIAN)
3231 * per-vnic rate shaping variables
3233 struct rate_shaping_vars_per_vn
{
3234 struct rate_shaping_counter protocol_counters
[NUM_OF_PROTOCOLS
];
3235 struct rate_shaping_counter vn_counter
;
3240 * The send queue element
3242 struct slow_path_element
{
3244 u8 protocol_data
[8];
3249 * eth/toe flags that indicate if to query
3251 struct stats_indication_flags
{