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bnx2x: Fix potential link issue In BCM8727 based boards
[mirror_ubuntu-bionic-kernel.git] / drivers / net / bnx2x / bnx2x_link.c
1 /* Copyright 2008-2009 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
26
27 #include "bnx2x.h"
28
29 /********************************************************/
30 #define ETH_HLEN 14
31 #define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
32 #define ETH_MIN_PACKET_SIZE 60
33 #define ETH_MAX_PACKET_SIZE 1500
34 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
35 #define MDIO_ACCESS_TIMEOUT 1000
36 #define BMAC_CONTROL_RX_ENABLE 2
37
38 /***********************************************************/
39 /* Shortcut definitions */
40 /***********************************************************/
41
42 #define NIG_LATCH_BC_ENABLE_MI_INT 0
43
44 #define NIG_STATUS_EMAC0_MI_INT \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
46 #define NIG_STATUS_XGXS0_LINK10G \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
48 #define NIG_STATUS_XGXS0_LINK_STATUS \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
50 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
52 #define NIG_STATUS_SERDES0_LINK_STATUS \
53 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
54 #define NIG_MASK_MI_INT \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
56 #define NIG_MASK_XGXS0_LINK10G \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
58 #define NIG_MASK_XGXS0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
60 #define NIG_MASK_SERDES0_LINK_STATUS \
61 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
62
63 #define MDIO_AN_CL73_OR_37_COMPLETE \
64 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
65 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
66
67 #define XGXS_RESET_BITS \
68 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
73
74 #define SERDES_RESET_BITS \
75 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
79
80 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
81 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
82 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
83 #define AUTONEG_PARALLEL \
84 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
85 #define AUTONEG_SGMII_FIBER_AUTODET \
86 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
87 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
88
89 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
91 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
93 #define GP_STATUS_SPEED_MASK \
94 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
95 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
96 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
97 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
98 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
99 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
100 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
101 #define GP_STATUS_10G_HIG \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
103 #define GP_STATUS_10G_CX4 \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
105 #define GP_STATUS_12G_HIG \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
107 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
108 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
109 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
110 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
111 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
112 #define GP_STATUS_10G_KX4 \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
114
115 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
116 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
117 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
118 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
119 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
120 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
121 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
122 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
123 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
124 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
125 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
126 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
127 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
128 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
129 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
130 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
131 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
132 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
133 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
134 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
135 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
136 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
137 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
138
139 #define PHY_XGXS_FLAG 0x1
140 #define PHY_SGMII_FLAG 0x2
141 #define PHY_SERDES_FLAG 0x4
142
143 /* */
144 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
145 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
146 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147
148
149 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
150 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
151 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
152 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
153
154 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
157
158 #define SFP_EEPROM_OPTIONS_ADDR 0x40
159 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
160 #define SFP_EEPROM_OPTIONS_SIZE 2
161
162 #define EDC_MODE_LINEAR 0x0022
163 #define EDC_MODE_LIMITING 0x0044
164 #define EDC_MODE_PASSIVE_DAC 0x0055
165
166
167
168 /**********************************************************/
169 /* INTERFACE */
170 /**********************************************************/
171 #define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
172 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
173 DEFAULT_PHY_DEV_ADDR, \
174 (_bank + (_addr & 0xf)), \
175 _val)
176
177 #define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
178 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
179 DEFAULT_PHY_DEV_ADDR, \
180 (_bank + (_addr & 0xf)), \
181 _val)
182
183 static void bnx2x_set_serdes_access(struct link_params *params)
184 {
185 struct bnx2x *bp = params->bp;
186 u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
187
188 /* Set Clause 22 */
189 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
190 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
191 udelay(500);
192 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
193 udelay(500);
194 /* Set Clause 45 */
195 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
196 }
197 static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
198 {
199 struct bnx2x *bp = params->bp;
200
201 if (phy_flags & PHY_XGXS_FLAG) {
202 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
203 params->port*0x18, 0);
204 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
205 DEFAULT_PHY_DEV_ADDR);
206 } else {
207 bnx2x_set_serdes_access(params);
208
209 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
210 params->port*0x10,
211 DEFAULT_PHY_DEV_ADDR);
212 }
213 }
214
215 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
216 {
217 u32 val = REG_RD(bp, reg);
218
219 val |= bits;
220 REG_WR(bp, reg, val);
221 return val;
222 }
223
224 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
225 {
226 u32 val = REG_RD(bp, reg);
227
228 val &= ~bits;
229 REG_WR(bp, reg, val);
230 return val;
231 }
232
233 static void bnx2x_emac_init(struct link_params *params,
234 struct link_vars *vars)
235 {
236 /* reset and unreset the emac core */
237 struct bnx2x *bp = params->bp;
238 u8 port = params->port;
239 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
240 u32 val;
241 u16 timeout;
242
243 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
244 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
245 udelay(5);
246 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
247 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
248
249 /* init emac - use read-modify-write */
250 /* self clear reset */
251 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
252 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
253
254 timeout = 200;
255 do {
256 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
257 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
258 if (!timeout) {
259 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
260 return;
261 }
262 timeout--;
263 } while (val & EMAC_MODE_RESET);
264
265 /* Set mac address */
266 val = ((params->mac_addr[0] << 8) |
267 params->mac_addr[1]);
268 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
269
270 val = ((params->mac_addr[2] << 24) |
271 (params->mac_addr[3] << 16) |
272 (params->mac_addr[4] << 8) |
273 params->mac_addr[5]);
274 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
275 }
276
277 static u8 bnx2x_emac_enable(struct link_params *params,
278 struct link_vars *vars, u8 lb)
279 {
280 struct bnx2x *bp = params->bp;
281 u8 port = params->port;
282 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
283 u32 val;
284
285 DP(NETIF_MSG_LINK, "enabling EMAC\n");
286
287 /* enable emac and not bmac */
288 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
289
290 /* for paladium */
291 if (CHIP_REV_IS_EMUL(bp)) {
292 /* Use lane 1 (of lanes 0-3) */
293 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
294 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
295 port*4, 1);
296 }
297 /* for fpga */
298 else
299
300 if (CHIP_REV_IS_FPGA(bp)) {
301 /* Use lane 1 (of lanes 0-3) */
302 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
303
304 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
305 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
306 0);
307 } else
308 /* ASIC */
309 if (vars->phy_flags & PHY_XGXS_FLAG) {
310 u32 ser_lane = ((params->lane_config &
311 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
312 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
313
314 DP(NETIF_MSG_LINK, "XGXS\n");
315 /* select the master lanes (out of 0-3) */
316 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
317 port*4, ser_lane);
318 /* select XGXS */
319 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
320 port*4, 1);
321
322 } else { /* SerDes */
323 DP(NETIF_MSG_LINK, "SerDes\n");
324 /* select SerDes */
325 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
326 port*4, 0);
327 }
328
329 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
330 EMAC_RX_MODE_RESET);
331 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
332 EMAC_TX_MODE_RESET);
333
334 if (CHIP_REV_IS_SLOW(bp)) {
335 /* config GMII mode */
336 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
337 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
338 (val | EMAC_MODE_PORT_GMII));
339 } else { /* ASIC */
340 /* pause enable/disable */
341 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
342 EMAC_RX_MODE_FLOW_EN);
343 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
344 bnx2x_bits_en(bp, emac_base +
345 EMAC_REG_EMAC_RX_MODE,
346 EMAC_RX_MODE_FLOW_EN);
347
348 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
349 (EMAC_TX_MODE_EXT_PAUSE_EN |
350 EMAC_TX_MODE_FLOW_EN));
351 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
352 bnx2x_bits_en(bp, emac_base +
353 EMAC_REG_EMAC_TX_MODE,
354 (EMAC_TX_MODE_EXT_PAUSE_EN |
355 EMAC_TX_MODE_FLOW_EN));
356 }
357
358 /* KEEP_VLAN_TAG, promiscuous */
359 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
360 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
361 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
362
363 /* Set Loopback */
364 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
365 if (lb)
366 val |= 0x810;
367 else
368 val &= ~0x810;
369 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
370
371 /* enable emac */
372 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
373
374 /* enable emac for jumbo packets */
375 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
376 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
377 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
378
379 /* strip CRC */
380 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
381
382 /* disable the NIG in/out to the bmac */
383 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
384 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
385 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
386
387 /* enable the NIG in/out to the emac */
388 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
389 val = 0;
390 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
391 val = 1;
392
393 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
394 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
395
396 if (CHIP_REV_IS_EMUL(bp)) {
397 /* take the BigMac out of reset */
398 REG_WR(bp,
399 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
400 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
401
402 /* enable access for bmac registers */
403 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
404 } else
405 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
406
407 vars->mac_type = MAC_TYPE_EMAC;
408 return 0;
409 }
410
411
412
413 static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
414 u8 is_lb)
415 {
416 struct bnx2x *bp = params->bp;
417 u8 port = params->port;
418 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
419 NIG_REG_INGRESS_BMAC0_MEM;
420 u32 wb_data[2];
421 u32 val;
422
423 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
424 /* reset and unreset the BigMac */
425 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
426 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
427 msleep(1);
428
429 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
430 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
431
432 /* enable access for bmac registers */
433 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
434
435 /* XGXS control */
436 wb_data[0] = 0x3c;
437 wb_data[1] = 0;
438 REG_WR_DMAE(bp, bmac_addr +
439 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
440 wb_data, 2);
441
442 /* tx MAC SA */
443 wb_data[0] = ((params->mac_addr[2] << 24) |
444 (params->mac_addr[3] << 16) |
445 (params->mac_addr[4] << 8) |
446 params->mac_addr[5]);
447 wb_data[1] = ((params->mac_addr[0] << 8) |
448 params->mac_addr[1]);
449 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
450 wb_data, 2);
451
452 /* tx control */
453 val = 0xc0;
454 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
455 val |= 0x800000;
456 wb_data[0] = val;
457 wb_data[1] = 0;
458 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
459 wb_data, 2);
460
461 /* mac control */
462 val = 0x3;
463 if (is_lb) {
464 val |= 0x4;
465 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
466 }
467 wb_data[0] = val;
468 wb_data[1] = 0;
469 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
470 wb_data, 2);
471
472 /* set rx mtu */
473 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
474 wb_data[1] = 0;
475 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
476 wb_data, 2);
477
478 /* rx control set to don't strip crc */
479 val = 0x14;
480 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
481 val |= 0x20;
482 wb_data[0] = val;
483 wb_data[1] = 0;
484 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
485 wb_data, 2);
486
487 /* set tx mtu */
488 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
489 wb_data[1] = 0;
490 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
491 wb_data, 2);
492
493 /* set cnt max size */
494 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
495 wb_data[1] = 0;
496 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
497 wb_data, 2);
498
499 /* configure safc */
500 wb_data[0] = 0x1000200;
501 wb_data[1] = 0;
502 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
503 wb_data, 2);
504 /* fix for emulation */
505 if (CHIP_REV_IS_EMUL(bp)) {
506 wb_data[0] = 0xf000;
507 wb_data[1] = 0;
508 REG_WR_DMAE(bp,
509 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
510 wb_data, 2);
511 }
512
513 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
514 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
515 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
516 val = 0;
517 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
518 val = 1;
519 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
520 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
521 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
522 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
523 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
524 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
525
526 vars->mac_type = MAC_TYPE_BMAC;
527 return 0;
528 }
529
530 static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
531 {
532 struct bnx2x *bp = params->bp;
533 u32 val;
534
535 if (phy_flags & PHY_XGXS_FLAG) {
536 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
537 val = XGXS_RESET_BITS;
538
539 } else { /* SerDes */
540 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
541 val = SERDES_RESET_BITS;
542 }
543
544 val = val << (params->port*16);
545
546 /* reset and unreset the SerDes/XGXS */
547 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
548 val);
549 udelay(500);
550 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
551 val);
552 bnx2x_set_phy_mdio(params, phy_flags);
553 }
554
555 void bnx2x_link_status_update(struct link_params *params,
556 struct link_vars *vars)
557 {
558 struct bnx2x *bp = params->bp;
559 u8 link_10g;
560 u8 port = params->port;
561
562 if (params->switch_cfg == SWITCH_CFG_1G)
563 vars->phy_flags = PHY_SERDES_FLAG;
564 else
565 vars->phy_flags = PHY_XGXS_FLAG;
566 vars->link_status = REG_RD(bp, params->shmem_base +
567 offsetof(struct shmem_region,
568 port_mb[port].link_status));
569
570 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
571
572 if (vars->link_up) {
573 DP(NETIF_MSG_LINK, "phy link up\n");
574
575 vars->phy_link_up = 1;
576 vars->duplex = DUPLEX_FULL;
577 switch (vars->link_status &
578 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
579 case LINK_10THD:
580 vars->duplex = DUPLEX_HALF;
581 /* fall thru */
582 case LINK_10TFD:
583 vars->line_speed = SPEED_10;
584 break;
585
586 case LINK_100TXHD:
587 vars->duplex = DUPLEX_HALF;
588 /* fall thru */
589 case LINK_100T4:
590 case LINK_100TXFD:
591 vars->line_speed = SPEED_100;
592 break;
593
594 case LINK_1000THD:
595 vars->duplex = DUPLEX_HALF;
596 /* fall thru */
597 case LINK_1000TFD:
598 vars->line_speed = SPEED_1000;
599 break;
600
601 case LINK_2500THD:
602 vars->duplex = DUPLEX_HALF;
603 /* fall thru */
604 case LINK_2500TFD:
605 vars->line_speed = SPEED_2500;
606 break;
607
608 case LINK_10GTFD:
609 vars->line_speed = SPEED_10000;
610 break;
611
612 case LINK_12GTFD:
613 vars->line_speed = SPEED_12000;
614 break;
615
616 case LINK_12_5GTFD:
617 vars->line_speed = SPEED_12500;
618 break;
619
620 case LINK_13GTFD:
621 vars->line_speed = SPEED_13000;
622 break;
623
624 case LINK_15GTFD:
625 vars->line_speed = SPEED_15000;
626 break;
627
628 case LINK_16GTFD:
629 vars->line_speed = SPEED_16000;
630 break;
631
632 default:
633 break;
634 }
635
636 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
637 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
638 else
639 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX;
640
641 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
642 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
643 else
644 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX;
645
646 if (vars->phy_flags & PHY_XGXS_FLAG) {
647 if (vars->line_speed &&
648 ((vars->line_speed == SPEED_10) ||
649 (vars->line_speed == SPEED_100))) {
650 vars->phy_flags |= PHY_SGMII_FLAG;
651 } else {
652 vars->phy_flags &= ~PHY_SGMII_FLAG;
653 }
654 }
655
656 /* anything 10 and over uses the bmac */
657 link_10g = ((vars->line_speed == SPEED_10000) ||
658 (vars->line_speed == SPEED_12000) ||
659 (vars->line_speed == SPEED_12500) ||
660 (vars->line_speed == SPEED_13000) ||
661 (vars->line_speed == SPEED_15000) ||
662 (vars->line_speed == SPEED_16000));
663 if (link_10g)
664 vars->mac_type = MAC_TYPE_BMAC;
665 else
666 vars->mac_type = MAC_TYPE_EMAC;
667
668 } else { /* link down */
669 DP(NETIF_MSG_LINK, "phy link down\n");
670
671 vars->phy_link_up = 0;
672
673 vars->line_speed = 0;
674 vars->duplex = DUPLEX_FULL;
675 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
676
677 /* indicate no mac active */
678 vars->mac_type = MAC_TYPE_NONE;
679 }
680
681 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
682 vars->link_status, vars->phy_link_up);
683 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
684 vars->line_speed, vars->duplex, vars->flow_ctrl);
685 }
686
687 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
688 {
689 struct bnx2x *bp = params->bp;
690
691 REG_WR(bp, params->shmem_base +
692 offsetof(struct shmem_region,
693 port_mb[params->port].link_status),
694 link_status);
695 }
696
697 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
698 {
699 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
700 NIG_REG_INGRESS_BMAC0_MEM;
701 u32 wb_data[2];
702 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
703
704 /* Only if the bmac is out of reset */
705 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
706 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
707 nig_bmac_enable) {
708
709 /* Clear Rx Enable bit in BMAC_CONTROL register */
710 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
711 wb_data, 2);
712 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
713 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
714 wb_data, 2);
715
716 msleep(1);
717 }
718 }
719
720 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
721 u32 line_speed)
722 {
723 struct bnx2x *bp = params->bp;
724 u8 port = params->port;
725 u32 init_crd, crd;
726 u32 count = 1000;
727
728 /* disable port */
729 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
730
731 /* wait for init credit */
732 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
733 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
734 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
735
736 while ((init_crd != crd) && count) {
737 msleep(5);
738
739 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
740 count--;
741 }
742 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
743 if (init_crd != crd) {
744 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
745 init_crd, crd);
746 return -EINVAL;
747 }
748
749 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
750 line_speed == SPEED_10 ||
751 line_speed == SPEED_100 ||
752 line_speed == SPEED_1000 ||
753 line_speed == SPEED_2500) {
754 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
755 /* update threshold */
756 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
757 /* update init credit */
758 init_crd = 778; /* (800-18-4) */
759
760 } else {
761 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
762 ETH_OVREHEAD)/16;
763 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
764 /* update threshold */
765 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
766 /* update init credit */
767 switch (line_speed) {
768 case SPEED_10000:
769 init_crd = thresh + 553 - 22;
770 break;
771
772 case SPEED_12000:
773 init_crd = thresh + 664 - 22;
774 break;
775
776 case SPEED_13000:
777 init_crd = thresh + 742 - 22;
778 break;
779
780 case SPEED_16000:
781 init_crd = thresh + 778 - 22;
782 break;
783 default:
784 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
785 line_speed);
786 return -EINVAL;
787 }
788 }
789 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
790 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
791 line_speed, init_crd);
792
793 /* probe the credit changes */
794 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
795 msleep(5);
796 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
797
798 /* enable port */
799 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
800 return 0;
801 }
802
803 static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
804 {
805 u32 emac_base;
806
807 switch (ext_phy_type) {
808 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
809 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
810 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
811 /* All MDC/MDIO is directed through single EMAC */
812 if (REG_RD(bp, NIG_REG_PORT_SWAP))
813 emac_base = GRCBASE_EMAC0;
814 else
815 emac_base = GRCBASE_EMAC1;
816 break;
817 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
818 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
819 break;
820 default:
821 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
822 break;
823 }
824 return emac_base;
825
826 }
827
828 u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
829 u8 phy_addr, u8 devad, u16 reg, u16 val)
830 {
831 u32 tmp, saved_mode;
832 u8 i, rc = 0;
833 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
834
835 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
836 * (a value of 49==0x31) and make sure that the AUTO poll is off
837 */
838
839 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
840 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
841 EMAC_MDIO_MODE_CLOCK_CNT);
842 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
843 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
844 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
845 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
846 udelay(40);
847
848 /* address */
849
850 tmp = ((phy_addr << 21) | (devad << 16) | reg |
851 EMAC_MDIO_COMM_COMMAND_ADDRESS |
852 EMAC_MDIO_COMM_START_BUSY);
853 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
854
855 for (i = 0; i < 50; i++) {
856 udelay(10);
857
858 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
859 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
860 udelay(5);
861 break;
862 }
863 }
864 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
865 DP(NETIF_MSG_LINK, "write phy register failed\n");
866 rc = -EFAULT;
867 } else {
868 /* data */
869 tmp = ((phy_addr << 21) | (devad << 16) | val |
870 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
871 EMAC_MDIO_COMM_START_BUSY);
872 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
873
874 for (i = 0; i < 50; i++) {
875 udelay(10);
876
877 tmp = REG_RD(bp, mdio_ctrl +
878 EMAC_REG_EMAC_MDIO_COMM);
879 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
880 udelay(5);
881 break;
882 }
883 }
884 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
885 DP(NETIF_MSG_LINK, "write phy register failed\n");
886 rc = -EFAULT;
887 }
888 }
889
890 /* Restore the saved mode */
891 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
892
893 return rc;
894 }
895
896 u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
897 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
898 {
899 u32 val, saved_mode;
900 u16 i;
901 u8 rc = 0;
902
903 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
904 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
905 * (a value of 49==0x31) and make sure that the AUTO poll is off
906 */
907
908 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
909 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
910 EMAC_MDIO_MODE_CLOCK_CNT));
911 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
912 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
913 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
914 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
915 udelay(40);
916
917 /* address */
918 val = ((phy_addr << 21) | (devad << 16) | reg |
919 EMAC_MDIO_COMM_COMMAND_ADDRESS |
920 EMAC_MDIO_COMM_START_BUSY);
921 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
922
923 for (i = 0; i < 50; i++) {
924 udelay(10);
925
926 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
927 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
928 udelay(5);
929 break;
930 }
931 }
932 if (val & EMAC_MDIO_COMM_START_BUSY) {
933 DP(NETIF_MSG_LINK, "read phy register failed\n");
934
935 *ret_val = 0;
936 rc = -EFAULT;
937
938 } else {
939 /* data */
940 val = ((phy_addr << 21) | (devad << 16) |
941 EMAC_MDIO_COMM_COMMAND_READ_45 |
942 EMAC_MDIO_COMM_START_BUSY);
943 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
944
945 for (i = 0; i < 50; i++) {
946 udelay(10);
947
948 val = REG_RD(bp, mdio_ctrl +
949 EMAC_REG_EMAC_MDIO_COMM);
950 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
951 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
952 break;
953 }
954 }
955 if (val & EMAC_MDIO_COMM_START_BUSY) {
956 DP(NETIF_MSG_LINK, "read phy register failed\n");
957
958 *ret_val = 0;
959 rc = -EFAULT;
960 }
961 }
962
963 /* Restore the saved mode */
964 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
965
966 return rc;
967 }
968
969 static void bnx2x_set_aer_mmd(struct link_params *params,
970 struct link_vars *vars)
971 {
972 struct bnx2x *bp = params->bp;
973 u32 ser_lane;
974 u16 offset;
975
976 ser_lane = ((params->lane_config &
977 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
978 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
979
980 offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
981 (params->phy_addr + ser_lane) : 0;
982
983 CL45_WR_OVER_CL22(bp, params->port,
984 params->phy_addr,
985 MDIO_REG_BANK_AER_BLOCK,
986 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
987 }
988
989 static void bnx2x_set_master_ln(struct link_params *params)
990 {
991 struct bnx2x *bp = params->bp;
992 u16 new_master_ln, ser_lane;
993 ser_lane = ((params->lane_config &
994 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
995 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
996
997 /* set the master_ln for AN */
998 CL45_RD_OVER_CL22(bp, params->port,
999 params->phy_addr,
1000 MDIO_REG_BANK_XGXS_BLOCK2,
1001 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1002 &new_master_ln);
1003
1004 CL45_WR_OVER_CL22(bp, params->port,
1005 params->phy_addr,
1006 MDIO_REG_BANK_XGXS_BLOCK2 ,
1007 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1008 (new_master_ln | ser_lane));
1009 }
1010
1011 static u8 bnx2x_reset_unicore(struct link_params *params)
1012 {
1013 struct bnx2x *bp = params->bp;
1014 u16 mii_control;
1015 u16 i;
1016
1017 CL45_RD_OVER_CL22(bp, params->port,
1018 params->phy_addr,
1019 MDIO_REG_BANK_COMBO_IEEE0,
1020 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1021
1022 /* reset the unicore */
1023 CL45_WR_OVER_CL22(bp, params->port,
1024 params->phy_addr,
1025 MDIO_REG_BANK_COMBO_IEEE0,
1026 MDIO_COMBO_IEEE0_MII_CONTROL,
1027 (mii_control |
1028 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1029 if (params->switch_cfg == SWITCH_CFG_1G)
1030 bnx2x_set_serdes_access(params);
1031
1032 /* wait for the reset to self clear */
1033 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1034 udelay(5);
1035
1036 /* the reset erased the previous bank value */
1037 CL45_RD_OVER_CL22(bp, params->port,
1038 params->phy_addr,
1039 MDIO_REG_BANK_COMBO_IEEE0,
1040 MDIO_COMBO_IEEE0_MII_CONTROL,
1041 &mii_control);
1042
1043 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1044 udelay(5);
1045 return 0;
1046 }
1047 }
1048
1049 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1050 return -EINVAL;
1051
1052 }
1053
1054 static void bnx2x_set_swap_lanes(struct link_params *params)
1055 {
1056 struct bnx2x *bp = params->bp;
1057 /* Each two bits represents a lane number:
1058 No swap is 0123 => 0x1b no need to enable the swap */
1059 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1060
1061 ser_lane = ((params->lane_config &
1062 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1063 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1064 rx_lane_swap = ((params->lane_config &
1065 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1066 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1067 tx_lane_swap = ((params->lane_config &
1068 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1069 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1070
1071 if (rx_lane_swap != 0x1b) {
1072 CL45_WR_OVER_CL22(bp, params->port,
1073 params->phy_addr,
1074 MDIO_REG_BANK_XGXS_BLOCK2,
1075 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1076 (rx_lane_swap |
1077 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1078 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1079 } else {
1080 CL45_WR_OVER_CL22(bp, params->port,
1081 params->phy_addr,
1082 MDIO_REG_BANK_XGXS_BLOCK2,
1083 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1084 }
1085
1086 if (tx_lane_swap != 0x1b) {
1087 CL45_WR_OVER_CL22(bp, params->port,
1088 params->phy_addr,
1089 MDIO_REG_BANK_XGXS_BLOCK2,
1090 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1091 (tx_lane_swap |
1092 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1093 } else {
1094 CL45_WR_OVER_CL22(bp, params->port,
1095 params->phy_addr,
1096 MDIO_REG_BANK_XGXS_BLOCK2,
1097 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1098 }
1099 }
1100
1101 static void bnx2x_set_parallel_detection(struct link_params *params,
1102 u8 phy_flags)
1103 {
1104 struct bnx2x *bp = params->bp;
1105 u16 control2;
1106
1107 CL45_RD_OVER_CL22(bp, params->port,
1108 params->phy_addr,
1109 MDIO_REG_BANK_SERDES_DIGITAL,
1110 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1111 &control2);
1112 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1113 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1114 else
1115 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1116 DP(NETIF_MSG_LINK, "params->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1117 params->speed_cap_mask, control2);
1118 CL45_WR_OVER_CL22(bp, params->port,
1119 params->phy_addr,
1120 MDIO_REG_BANK_SERDES_DIGITAL,
1121 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1122 control2);
1123
1124 if ((phy_flags & PHY_XGXS_FLAG) &&
1125 (params->speed_cap_mask &
1126 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1127 DP(NETIF_MSG_LINK, "XGXS\n");
1128
1129 CL45_WR_OVER_CL22(bp, params->port,
1130 params->phy_addr,
1131 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1132 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1133 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1134
1135 CL45_RD_OVER_CL22(bp, params->port,
1136 params->phy_addr,
1137 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1138 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1139 &control2);
1140
1141
1142 control2 |=
1143 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1144
1145 CL45_WR_OVER_CL22(bp, params->port,
1146 params->phy_addr,
1147 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1148 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1149 control2);
1150
1151 /* Disable parallel detection of HiG */
1152 CL45_WR_OVER_CL22(bp, params->port,
1153 params->phy_addr,
1154 MDIO_REG_BANK_XGXS_BLOCK2,
1155 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1156 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1157 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1158 }
1159 }
1160
1161 static void bnx2x_set_autoneg(struct link_params *params,
1162 struct link_vars *vars,
1163 u8 enable_cl73)
1164 {
1165 struct bnx2x *bp = params->bp;
1166 u16 reg_val;
1167
1168 /* CL37 Autoneg */
1169
1170 CL45_RD_OVER_CL22(bp, params->port,
1171 params->phy_addr,
1172 MDIO_REG_BANK_COMBO_IEEE0,
1173 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1174
1175 /* CL37 Autoneg Enabled */
1176 if (vars->line_speed == SPEED_AUTO_NEG)
1177 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1178 else /* CL37 Autoneg Disabled */
1179 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1180 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1181
1182 CL45_WR_OVER_CL22(bp, params->port,
1183 params->phy_addr,
1184 MDIO_REG_BANK_COMBO_IEEE0,
1185 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1186
1187 /* Enable/Disable Autodetection */
1188
1189 CL45_RD_OVER_CL22(bp, params->port,
1190 params->phy_addr,
1191 MDIO_REG_BANK_SERDES_DIGITAL,
1192 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1193 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1194 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1195 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
1196 if (vars->line_speed == SPEED_AUTO_NEG)
1197 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1198 else
1199 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1200
1201 CL45_WR_OVER_CL22(bp, params->port,
1202 params->phy_addr,
1203 MDIO_REG_BANK_SERDES_DIGITAL,
1204 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1205
1206 /* Enable TetonII and BAM autoneg */
1207 CL45_RD_OVER_CL22(bp, params->port,
1208 params->phy_addr,
1209 MDIO_REG_BANK_BAM_NEXT_PAGE,
1210 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1211 &reg_val);
1212 if (vars->line_speed == SPEED_AUTO_NEG) {
1213 /* Enable BAM aneg Mode and TetonII aneg Mode */
1214 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1215 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1216 } else {
1217 /* TetonII and BAM Autoneg Disabled */
1218 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1219 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1220 }
1221 CL45_WR_OVER_CL22(bp, params->port,
1222 params->phy_addr,
1223 MDIO_REG_BANK_BAM_NEXT_PAGE,
1224 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1225 reg_val);
1226
1227 if (enable_cl73) {
1228 /* Enable Cl73 FSM status bits */
1229 CL45_WR_OVER_CL22(bp, params->port,
1230 params->phy_addr,
1231 MDIO_REG_BANK_CL73_USERB0,
1232 MDIO_CL73_USERB0_CL73_UCTRL,
1233 0xe);
1234
1235 /* Enable BAM Station Manager*/
1236 CL45_WR_OVER_CL22(bp, params->port,
1237 params->phy_addr,
1238 MDIO_REG_BANK_CL73_USERB0,
1239 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1240 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1241 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1242 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1243
1244 /* Advertise CL73 link speeds */
1245 CL45_RD_OVER_CL22(bp, params->port,
1246 params->phy_addr,
1247 MDIO_REG_BANK_CL73_IEEEB1,
1248 MDIO_CL73_IEEEB1_AN_ADV2,
1249 &reg_val);
1250 if (params->speed_cap_mask &
1251 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1252 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1253 if (params->speed_cap_mask &
1254 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1255 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1256
1257 CL45_WR_OVER_CL22(bp, params->port,
1258 params->phy_addr,
1259 MDIO_REG_BANK_CL73_IEEEB1,
1260 MDIO_CL73_IEEEB1_AN_ADV2,
1261 reg_val);
1262
1263 /* CL73 Autoneg Enabled */
1264 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1265
1266 } else /* CL73 Autoneg Disabled */
1267 reg_val = 0;
1268
1269 CL45_WR_OVER_CL22(bp, params->port,
1270 params->phy_addr,
1271 MDIO_REG_BANK_CL73_IEEEB0,
1272 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1273 }
1274
1275 /* program SerDes, forced speed */
1276 static void bnx2x_program_serdes(struct link_params *params,
1277 struct link_vars *vars)
1278 {
1279 struct bnx2x *bp = params->bp;
1280 u16 reg_val;
1281
1282 /* program duplex, disable autoneg and sgmii*/
1283 CL45_RD_OVER_CL22(bp, params->port,
1284 params->phy_addr,
1285 MDIO_REG_BANK_COMBO_IEEE0,
1286 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1287 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
1288 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1289 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
1290 if (params->req_duplex == DUPLEX_FULL)
1291 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1292 CL45_WR_OVER_CL22(bp, params->port,
1293 params->phy_addr,
1294 MDIO_REG_BANK_COMBO_IEEE0,
1295 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1296
1297 /* program speed
1298 - needed only if the speed is greater than 1G (2.5G or 10G) */
1299 CL45_RD_OVER_CL22(bp, params->port,
1300 params->phy_addr,
1301 MDIO_REG_BANK_SERDES_DIGITAL,
1302 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
1303 /* clearing the speed value before setting the right speed */
1304 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1305
1306 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1307 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1308
1309 if (!((vars->line_speed == SPEED_1000) ||
1310 (vars->line_speed == SPEED_100) ||
1311 (vars->line_speed == SPEED_10))) {
1312
1313 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1314 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1315 if (vars->line_speed == SPEED_10000)
1316 reg_val |=
1317 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
1318 if (vars->line_speed == SPEED_13000)
1319 reg_val |=
1320 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1321 }
1322
1323 CL45_WR_OVER_CL22(bp, params->port,
1324 params->phy_addr,
1325 MDIO_REG_BANK_SERDES_DIGITAL,
1326 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1327
1328 }
1329
1330 static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1331 {
1332 struct bnx2x *bp = params->bp;
1333 u16 val = 0;
1334
1335 /* configure the 48 bits for BAM AN */
1336
1337 /* set extended capabilities */
1338 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1339 val |= MDIO_OVER_1G_UP1_2_5G;
1340 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1341 val |= MDIO_OVER_1G_UP1_10G;
1342 CL45_WR_OVER_CL22(bp, params->port,
1343 params->phy_addr,
1344 MDIO_REG_BANK_OVER_1G,
1345 MDIO_OVER_1G_UP1, val);
1346
1347 CL45_WR_OVER_CL22(bp, params->port,
1348 params->phy_addr,
1349 MDIO_REG_BANK_OVER_1G,
1350 MDIO_OVER_1G_UP3, 0x400);
1351 }
1352
1353 static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u16 *ieee_fc)
1354 {
1355 struct bnx2x *bp = params->bp;
1356 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1357 /* resolve pause mode and advertisement
1358 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1359
1360 switch (params->req_flow_ctrl) {
1361 case BNX2X_FLOW_CTRL_AUTO:
1362 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
1363 *ieee_fc |=
1364 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1365 } else {
1366 *ieee_fc |=
1367 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1368 }
1369 break;
1370 case BNX2X_FLOW_CTRL_TX:
1371 *ieee_fc |=
1372 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1373 break;
1374
1375 case BNX2X_FLOW_CTRL_RX:
1376 case BNX2X_FLOW_CTRL_BOTH:
1377 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1378 break;
1379
1380 case BNX2X_FLOW_CTRL_NONE:
1381 default:
1382 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1383 break;
1384 }
1385 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
1386 }
1387
1388 static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1389 u16 ieee_fc)
1390 {
1391 struct bnx2x *bp = params->bp;
1392 u16 val;
1393 /* for AN, we are always publishing full duplex */
1394
1395 CL45_WR_OVER_CL22(bp, params->port,
1396 params->phy_addr,
1397 MDIO_REG_BANK_COMBO_IEEE0,
1398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
1399 CL45_RD_OVER_CL22(bp, params->port,
1400 params->phy_addr,
1401 MDIO_REG_BANK_CL73_IEEEB1,
1402 MDIO_CL73_IEEEB1_AN_ADV1, &val);
1403 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
1404 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
1405 CL45_WR_OVER_CL22(bp, params->port,
1406 params->phy_addr,
1407 MDIO_REG_BANK_CL73_IEEEB1,
1408 MDIO_CL73_IEEEB1_AN_ADV1, val);
1409 }
1410
1411 static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
1412 {
1413 struct bnx2x *bp = params->bp;
1414 u16 mii_control;
1415
1416 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
1417 /* Enable and restart BAM/CL37 aneg */
1418
1419 if (enable_cl73) {
1420 CL45_RD_OVER_CL22(bp, params->port,
1421 params->phy_addr,
1422 MDIO_REG_BANK_CL73_IEEEB0,
1423 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1424 &mii_control);
1425
1426 CL45_WR_OVER_CL22(bp, params->port,
1427 params->phy_addr,
1428 MDIO_REG_BANK_CL73_IEEEB0,
1429 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1430 (mii_control |
1431 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1432 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1433 } else {
1434
1435 CL45_RD_OVER_CL22(bp, params->port,
1436 params->phy_addr,
1437 MDIO_REG_BANK_COMBO_IEEE0,
1438 MDIO_COMBO_IEEE0_MII_CONTROL,
1439 &mii_control);
1440 DP(NETIF_MSG_LINK,
1441 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1442 mii_control);
1443 CL45_WR_OVER_CL22(bp, params->port,
1444 params->phy_addr,
1445 MDIO_REG_BANK_COMBO_IEEE0,
1446 MDIO_COMBO_IEEE0_MII_CONTROL,
1447 (mii_control |
1448 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1449 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1450 }
1451 }
1452
1453 static void bnx2x_initialize_sgmii_process(struct link_params *params,
1454 struct link_vars *vars)
1455 {
1456 struct bnx2x *bp = params->bp;
1457 u16 control1;
1458
1459 /* in SGMII mode, the unicore is always slave */
1460
1461 CL45_RD_OVER_CL22(bp, params->port,
1462 params->phy_addr,
1463 MDIO_REG_BANK_SERDES_DIGITAL,
1464 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1465 &control1);
1466 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1467 /* set sgmii mode (and not fiber) */
1468 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1469 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1470 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1471 CL45_WR_OVER_CL22(bp, params->port,
1472 params->phy_addr,
1473 MDIO_REG_BANK_SERDES_DIGITAL,
1474 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1475 control1);
1476
1477 /* if forced speed */
1478 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
1479 /* set speed, disable autoneg */
1480 u16 mii_control;
1481
1482 CL45_RD_OVER_CL22(bp, params->port,
1483 params->phy_addr,
1484 MDIO_REG_BANK_COMBO_IEEE0,
1485 MDIO_COMBO_IEEE0_MII_CONTROL,
1486 &mii_control);
1487 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1488 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1489 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1490
1491 switch (vars->line_speed) {
1492 case SPEED_100:
1493 mii_control |=
1494 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1495 break;
1496 case SPEED_1000:
1497 mii_control |=
1498 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1499 break;
1500 case SPEED_10:
1501 /* there is nothing to set for 10M */
1502 break;
1503 default:
1504 /* invalid speed for SGMII */
1505 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1506 vars->line_speed);
1507 break;
1508 }
1509
1510 /* setting the full duplex */
1511 if (params->req_duplex == DUPLEX_FULL)
1512 mii_control |=
1513 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1514 CL45_WR_OVER_CL22(bp, params->port,
1515 params->phy_addr,
1516 MDIO_REG_BANK_COMBO_IEEE0,
1517 MDIO_COMBO_IEEE0_MII_CONTROL,
1518 mii_control);
1519
1520 } else { /* AN mode */
1521 /* enable and restart AN */
1522 bnx2x_restart_autoneg(params, 0);
1523 }
1524 }
1525
1526
1527 /*
1528 * link management
1529 */
1530
1531 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1532 { /* LD LP */
1533 switch (pause_result) { /* ASYM P ASYM P */
1534 case 0xb: /* 1 0 1 1 */
1535 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
1536 break;
1537
1538 case 0xe: /* 1 1 1 0 */
1539 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
1540 break;
1541
1542 case 0x5: /* 0 1 0 1 */
1543 case 0x7: /* 0 1 1 1 */
1544 case 0xd: /* 1 1 0 1 */
1545 case 0xf: /* 1 1 1 1 */
1546 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
1547 break;
1548
1549 default:
1550 break;
1551 }
1552 }
1553
1554 static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params,
1555 struct link_vars *vars)
1556 {
1557 struct bnx2x *bp = params->bp;
1558 u8 ext_phy_addr;
1559 u16 ld_pause; /* local */
1560 u16 lp_pause; /* link partner */
1561 u16 an_complete; /* AN complete */
1562 u16 pause_result;
1563 u8 ret = 0;
1564 u32 ext_phy_type;
1565 u8 port = params->port;
1566 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
1567 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1568 /* read twice */
1569
1570 bnx2x_cl45_read(bp, port,
1571 ext_phy_type,
1572 ext_phy_addr,
1573 MDIO_AN_DEVAD,
1574 MDIO_AN_REG_STATUS, &an_complete);
1575 bnx2x_cl45_read(bp, port,
1576 ext_phy_type,
1577 ext_phy_addr,
1578 MDIO_AN_DEVAD,
1579 MDIO_AN_REG_STATUS, &an_complete);
1580
1581 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1582 ret = 1;
1583 bnx2x_cl45_read(bp, port,
1584 ext_phy_type,
1585 ext_phy_addr,
1586 MDIO_AN_DEVAD,
1587 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1588 bnx2x_cl45_read(bp, port,
1589 ext_phy_type,
1590 ext_phy_addr,
1591 MDIO_AN_DEVAD,
1592 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1593 pause_result = (ld_pause &
1594 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1595 pause_result |= (lp_pause &
1596 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1597 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
1598 pause_result);
1599 bnx2x_pause_resolve(vars, pause_result);
1600 if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE &&
1601 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1602 bnx2x_cl45_read(bp, port,
1603 ext_phy_type,
1604 ext_phy_addr,
1605 MDIO_AN_DEVAD,
1606 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1607
1608 bnx2x_cl45_read(bp, port,
1609 ext_phy_type,
1610 ext_phy_addr,
1611 MDIO_AN_DEVAD,
1612 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1613 pause_result = (ld_pause &
1614 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1615 pause_result |= (lp_pause &
1616 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1617
1618 bnx2x_pause_resolve(vars, pause_result);
1619 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
1620 pause_result);
1621 }
1622 }
1623 return ret;
1624 }
1625
1626 static u8 bnx2x_direct_parallel_detect_used(struct link_params *params)
1627 {
1628 struct bnx2x *bp = params->bp;
1629 u16 pd_10g, status2_1000x;
1630 CL45_RD_OVER_CL22(bp, params->port,
1631 params->phy_addr,
1632 MDIO_REG_BANK_SERDES_DIGITAL,
1633 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1634 &status2_1000x);
1635 CL45_RD_OVER_CL22(bp, params->port,
1636 params->phy_addr,
1637 MDIO_REG_BANK_SERDES_DIGITAL,
1638 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1639 &status2_1000x);
1640 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
1641 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
1642 params->port);
1643 return 1;
1644 }
1645
1646 CL45_RD_OVER_CL22(bp, params->port,
1647 params->phy_addr,
1648 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1649 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
1650 &pd_10g);
1651
1652 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
1653 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
1654 params->port);
1655 return 1;
1656 }
1657 return 0;
1658 }
1659
1660 static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1661 struct link_vars *vars,
1662 u32 gp_status)
1663 {
1664 struct bnx2x *bp = params->bp;
1665 u16 ld_pause; /* local driver */
1666 u16 lp_pause; /* link partner */
1667 u16 pause_result;
1668
1669 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1670
1671 /* resolve from gp_status in case of AN complete and not sgmii */
1672 if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1673 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1674 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1675 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1676 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1677 if (bnx2x_direct_parallel_detect_used(params)) {
1678 vars->flow_ctrl = params->req_fc_auto_adv;
1679 return;
1680 }
1681 if ((gp_status &
1682 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1683 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
1684 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1685 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
1686
1687 CL45_RD_OVER_CL22(bp, params->port,
1688 params->phy_addr,
1689 MDIO_REG_BANK_CL73_IEEEB1,
1690 MDIO_CL73_IEEEB1_AN_ADV1,
1691 &ld_pause);
1692 CL45_RD_OVER_CL22(bp, params->port,
1693 params->phy_addr,
1694 MDIO_REG_BANK_CL73_IEEEB1,
1695 MDIO_CL73_IEEEB1_AN_LP_ADV1,
1696 &lp_pause);
1697 pause_result = (ld_pause &
1698 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
1699 >> 8;
1700 pause_result |= (lp_pause &
1701 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
1702 >> 10;
1703 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
1704 pause_result);
1705 } else {
1706
1707 CL45_RD_OVER_CL22(bp, params->port,
1708 params->phy_addr,
1709 MDIO_REG_BANK_COMBO_IEEE0,
1710 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1711 &ld_pause);
1712 CL45_RD_OVER_CL22(bp, params->port,
1713 params->phy_addr,
1714 MDIO_REG_BANK_COMBO_IEEE0,
1715 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1716 &lp_pause);
1717 pause_result = (ld_pause &
1718 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1719 pause_result |= (lp_pause &
1720 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1721 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
1722 pause_result);
1723 }
1724 bnx2x_pause_resolve(vars, pause_result);
1725 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1726 (bnx2x_ext_phy_resolve_fc(params, vars))) {
1727 return;
1728 } else {
1729 if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
1730 vars->flow_ctrl = params->req_fc_auto_adv;
1731 else
1732 vars->flow_ctrl = params->req_flow_ctrl;
1733 }
1734 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1735 }
1736
1737 static void bnx2x_check_fallback_to_cl37(struct link_params *params)
1738 {
1739 struct bnx2x *bp = params->bp;
1740 u16 rx_status, ustat_val, cl37_fsm_recieved;
1741 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
1742 /* Step 1: Make sure signal is detected */
1743 CL45_RD_OVER_CL22(bp, params->port,
1744 params->phy_addr,
1745 MDIO_REG_BANK_RX0,
1746 MDIO_RX0_RX_STATUS,
1747 &rx_status);
1748 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
1749 (MDIO_RX0_RX_STATUS_SIGDET)) {
1750 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
1751 "rx_status(0x80b0) = 0x%x\n", rx_status);
1752 CL45_WR_OVER_CL22(bp, params->port,
1753 params->phy_addr,
1754 MDIO_REG_BANK_CL73_IEEEB0,
1755 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1756 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
1757 return;
1758 }
1759 /* Step 2: Check CL73 state machine */
1760 CL45_RD_OVER_CL22(bp, params->port,
1761 params->phy_addr,
1762 MDIO_REG_BANK_CL73_USERB0,
1763 MDIO_CL73_USERB0_CL73_USTAT1,
1764 &ustat_val);
1765 if ((ustat_val &
1766 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1767 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
1768 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1769 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
1770 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
1771 "ustat_val(0x8371) = 0x%x\n", ustat_val);
1772 return;
1773 }
1774 /* Step 3: Check CL37 Message Pages received to indicate LP
1775 supports only CL37 */
1776 CL45_RD_OVER_CL22(bp, params->port,
1777 params->phy_addr,
1778 MDIO_REG_BANK_REMOTE_PHY,
1779 MDIO_REMOTE_PHY_MISC_RX_STATUS,
1780 &cl37_fsm_recieved);
1781 if ((cl37_fsm_recieved &
1782 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1783 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
1784 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1785 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
1786 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
1787 "misc_rx_status(0x8330) = 0x%x\n",
1788 cl37_fsm_recieved);
1789 return;
1790 }
1791 /* The combined cl37/cl73 fsm state information indicating that we are
1792 connected to a device which does not support cl73, but does support
1793 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1794 /* Disable CL73 */
1795 CL45_WR_OVER_CL22(bp, params->port,
1796 params->phy_addr,
1797 MDIO_REG_BANK_CL73_IEEEB0,
1798 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1799 0);
1800 /* Restart CL37 autoneg */
1801 bnx2x_restart_autoneg(params, 0);
1802 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
1803 }
1804 static u8 bnx2x_link_settings_status(struct link_params *params,
1805 struct link_vars *vars,
1806 u32 gp_status,
1807 u8 ext_phy_link_up)
1808 {
1809 struct bnx2x *bp = params->bp;
1810 u16 new_line_speed;
1811 u8 rc = 0;
1812 vars->link_status = 0;
1813
1814 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1815 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1816 gp_status);
1817
1818 vars->phy_link_up = 1;
1819 vars->link_status |= LINK_STATUS_LINK_UP;
1820
1821 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1822 vars->duplex = DUPLEX_FULL;
1823 else
1824 vars->duplex = DUPLEX_HALF;
1825
1826 bnx2x_flow_ctrl_resolve(params, vars, gp_status);
1827
1828 switch (gp_status & GP_STATUS_SPEED_MASK) {
1829 case GP_STATUS_10M:
1830 new_line_speed = SPEED_10;
1831 if (vars->duplex == DUPLEX_FULL)
1832 vars->link_status |= LINK_10TFD;
1833 else
1834 vars->link_status |= LINK_10THD;
1835 break;
1836
1837 case GP_STATUS_100M:
1838 new_line_speed = SPEED_100;
1839 if (vars->duplex == DUPLEX_FULL)
1840 vars->link_status |= LINK_100TXFD;
1841 else
1842 vars->link_status |= LINK_100TXHD;
1843 break;
1844
1845 case GP_STATUS_1G:
1846 case GP_STATUS_1G_KX:
1847 new_line_speed = SPEED_1000;
1848 if (vars->duplex == DUPLEX_FULL)
1849 vars->link_status |= LINK_1000TFD;
1850 else
1851 vars->link_status |= LINK_1000THD;
1852 break;
1853
1854 case GP_STATUS_2_5G:
1855 new_line_speed = SPEED_2500;
1856 if (vars->duplex == DUPLEX_FULL)
1857 vars->link_status |= LINK_2500TFD;
1858 else
1859 vars->link_status |= LINK_2500THD;
1860 break;
1861
1862 case GP_STATUS_5G:
1863 case GP_STATUS_6G:
1864 DP(NETIF_MSG_LINK,
1865 "link speed unsupported gp_status 0x%x\n",
1866 gp_status);
1867 return -EINVAL;
1868
1869 case GP_STATUS_10G_KX4:
1870 case GP_STATUS_10G_HIG:
1871 case GP_STATUS_10G_CX4:
1872 new_line_speed = SPEED_10000;
1873 vars->link_status |= LINK_10GTFD;
1874 break;
1875
1876 case GP_STATUS_12G_HIG:
1877 new_line_speed = SPEED_12000;
1878 vars->link_status |= LINK_12GTFD;
1879 break;
1880
1881 case GP_STATUS_12_5G:
1882 new_line_speed = SPEED_12500;
1883 vars->link_status |= LINK_12_5GTFD;
1884 break;
1885
1886 case GP_STATUS_13G:
1887 new_line_speed = SPEED_13000;
1888 vars->link_status |= LINK_13GTFD;
1889 break;
1890
1891 case GP_STATUS_15G:
1892 new_line_speed = SPEED_15000;
1893 vars->link_status |= LINK_15GTFD;
1894 break;
1895
1896 case GP_STATUS_16G:
1897 new_line_speed = SPEED_16000;
1898 vars->link_status |= LINK_16GTFD;
1899 break;
1900
1901 default:
1902 DP(NETIF_MSG_LINK,
1903 "link speed unsupported gp_status 0x%x\n",
1904 gp_status);
1905 return -EINVAL;
1906 }
1907
1908 /* Upon link speed change set the NIG into drain mode.
1909 Comes to deals with possible FIFO glitch due to clk change
1910 when speed is decreased without link down indicator */
1911 if (new_line_speed != vars->line_speed) {
1912 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
1913 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
1914 ext_phy_link_up) {
1915 DP(NETIF_MSG_LINK, "Internal link speed %d is"
1916 " different than the external"
1917 " link speed %d\n", new_line_speed,
1918 vars->line_speed);
1919 vars->phy_link_up = 0;
1920 return 0;
1921 }
1922 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
1923 + params->port*4, 0);
1924 msleep(1);
1925 }
1926 vars->line_speed = new_line_speed;
1927 vars->link_status |= LINK_STATUS_SERDES_LINK;
1928
1929 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1930 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1931 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1932 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1933 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1934 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1935 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
1936 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1937 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
1938 vars->autoneg = AUTO_NEG_ENABLED;
1939
1940 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
1941 vars->autoneg |= AUTO_NEG_COMPLETE;
1942 vars->link_status |=
1943 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1944 }
1945
1946 vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
1947 vars->link_status |=
1948 LINK_STATUS_PARALLEL_DETECTION_USED;
1949
1950 }
1951 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1952 vars->link_status |=
1953 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1954
1955 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1956 vars->link_status |=
1957 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1958
1959 } else { /* link_down */
1960 DP(NETIF_MSG_LINK, "phy link down\n");
1961
1962 vars->phy_link_up = 0;
1963
1964 vars->duplex = DUPLEX_FULL;
1965 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1966 vars->autoneg = AUTO_NEG_DISABLED;
1967 vars->mac_type = MAC_TYPE_NONE;
1968
1969 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1970 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1971 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT))) {
1972 /* Check signal is detected */
1973 bnx2x_check_fallback_to_cl37(params);
1974 }
1975 }
1976
1977 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
1978 gp_status, vars->phy_link_up, vars->line_speed);
1979 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1980 " autoneg 0x%x\n",
1981 vars->duplex,
1982 vars->flow_ctrl, vars->autoneg);
1983 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1984
1985 return rc;
1986 }
1987
1988 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
1989 {
1990 struct bnx2x *bp = params->bp;
1991 u16 lp_up2;
1992 u16 tx_driver;
1993 u16 bank;
1994
1995 /* read precomp */
1996 CL45_RD_OVER_CL22(bp, params->port,
1997 params->phy_addr,
1998 MDIO_REG_BANK_OVER_1G,
1999 MDIO_OVER_1G_LP_UP2, &lp_up2);
2000
2001 /* bits [10:7] at lp_up2, positioned at [15:12] */
2002 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2003 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2004 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2005
2006 if (lp_up2 == 0)
2007 return;
2008
2009 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2010 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2011 CL45_RD_OVER_CL22(bp, params->port,
2012 params->phy_addr,
2013 bank,
2014 MDIO_TX0_TX_DRIVER, &tx_driver);
2015
2016 /* replace tx_driver bits [15:12] */
2017 if (lp_up2 !=
2018 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2019 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2020 tx_driver |= lp_up2;
2021 CL45_WR_OVER_CL22(bp, params->port,
2022 params->phy_addr,
2023 bank,
2024 MDIO_TX0_TX_DRIVER, tx_driver);
2025 }
2026 }
2027 }
2028
2029 static u8 bnx2x_emac_program(struct link_params *params,
2030 u32 line_speed, u32 duplex)
2031 {
2032 struct bnx2x *bp = params->bp;
2033 u8 port = params->port;
2034 u16 mode = 0;
2035
2036 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2037 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2038 EMAC_REG_EMAC_MODE,
2039 (EMAC_MODE_25G_MODE |
2040 EMAC_MODE_PORT_MII_10M |
2041 EMAC_MODE_HALF_DUPLEX));
2042 switch (line_speed) {
2043 case SPEED_10:
2044 mode |= EMAC_MODE_PORT_MII_10M;
2045 break;
2046
2047 case SPEED_100:
2048 mode |= EMAC_MODE_PORT_MII;
2049 break;
2050
2051 case SPEED_1000:
2052 mode |= EMAC_MODE_PORT_GMII;
2053 break;
2054
2055 case SPEED_2500:
2056 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2057 break;
2058
2059 default:
2060 /* 10G not valid for EMAC */
2061 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
2062 return -EINVAL;
2063 }
2064
2065 if (duplex == DUPLEX_HALF)
2066 mode |= EMAC_MODE_HALF_DUPLEX;
2067 bnx2x_bits_en(bp,
2068 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2069 mode);
2070
2071 bnx2x_set_led(params, LED_MODE_OPER, line_speed);
2072 return 0;
2073 }
2074
2075 /*****************************************************************************/
2076 /* External Phy section */
2077 /*****************************************************************************/
2078 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
2079 {
2080 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2081 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2082 msleep(1);
2083 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2084 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
2085 }
2086
2087 static void bnx2x_ext_phy_reset(struct link_params *params,
2088 struct link_vars *vars)
2089 {
2090 struct bnx2x *bp = params->bp;
2091 u32 ext_phy_type;
2092 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2093
2094 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
2095 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2096 /* The PHY reset is controled by GPIO 1
2097 * Give it 1ms of reset pulse
2098 */
2099 if (vars->phy_flags & PHY_XGXS_FLAG) {
2100
2101 switch (ext_phy_type) {
2102 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2103 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2104 break;
2105
2106 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2107 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2108 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
2109
2110 /* Restore normal power mode*/
2111 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2112 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2113 params->port);
2114
2115 /* HW reset */
2116 bnx2x_ext_phy_hw_reset(bp, params->port);
2117
2118 bnx2x_cl45_write(bp, params->port,
2119 ext_phy_type,
2120 ext_phy_addr,
2121 MDIO_PMA_DEVAD,
2122 MDIO_PMA_REG_CTRL, 0xa040);
2123 break;
2124
2125 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
2126 break;
2127
2128 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
2129
2130 /* Restore normal power mode*/
2131 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2132 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2133 params->port);
2134
2135 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2136 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2137 params->port);
2138
2139 bnx2x_cl45_write(bp, params->port,
2140 ext_phy_type,
2141 ext_phy_addr,
2142 MDIO_PMA_DEVAD,
2143 MDIO_PMA_REG_CTRL,
2144 1<<15);
2145 break;
2146
2147 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2148 DP(NETIF_MSG_LINK, "XGXS 8072\n");
2149
2150 /* Unset Low Power Mode and SW reset */
2151 /* Restore normal power mode*/
2152 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2153 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2154 params->port);
2155
2156 bnx2x_cl45_write(bp, params->port,
2157 ext_phy_type,
2158 ext_phy_addr,
2159 MDIO_PMA_DEVAD,
2160 MDIO_PMA_REG_CTRL,
2161 1<<15);
2162 break;
2163
2164 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2165 DP(NETIF_MSG_LINK, "XGXS 8073\n");
2166
2167 /* Restore normal power mode*/
2168 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2169 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2170 params->port);
2171
2172 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2173 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2174 params->port);
2175 break;
2176
2177 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2178 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
2179
2180 /* Restore normal power mode*/
2181 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2182 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2183 params->port);
2184
2185 /* HW reset */
2186 bnx2x_ext_phy_hw_reset(bp, params->port);
2187 break;
2188
2189 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
2190 /* Restore normal power mode*/
2191 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2192 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2193 params->port);
2194
2195 /* HW reset */
2196 bnx2x_ext_phy_hw_reset(bp, params->port);
2197
2198 bnx2x_cl45_write(bp, params->port,
2199 ext_phy_type,
2200 ext_phy_addr,
2201 MDIO_PMA_DEVAD,
2202 MDIO_PMA_REG_CTRL,
2203 1<<15);
2204 break;
2205 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
2206 break;
2207 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2208 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2209 break;
2210
2211 default:
2212 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2213 params->ext_phy_config);
2214 break;
2215 }
2216
2217 } else { /* SerDes */
2218 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2219 switch (ext_phy_type) {
2220 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2221 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2222 break;
2223
2224 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2225 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2226 bnx2x_ext_phy_hw_reset(bp, params->port);
2227 break;
2228
2229 default:
2230 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2231 params->ext_phy_config);
2232 break;
2233 }
2234 }
2235 }
2236
2237 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
2238 u32 shmem_base, u32 spirom_ver)
2239 {
2240 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
2241 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
2242 REG_WR(bp, shmem_base +
2243 offsetof(struct shmem_region,
2244 port_mb[port].ext_phy_fw_version),
2245 spirom_ver);
2246 }
2247
2248 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
2249 u32 ext_phy_type, u8 ext_phy_addr,
2250 u32 shmem_base)
2251 {
2252 u16 fw_ver1, fw_ver2;
2253
2254 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2255 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2256 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2257 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2258 bnx2x_save_spirom_version(bp, port, shmem_base,
2259 (u32)(fw_ver1<<16 | fw_ver2));
2260 }
2261
2262
2263 static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
2264 u8 ext_phy_addr, u32 shmem_base)
2265 {
2266 u16 val, fw_ver1, fw_ver2, cnt;
2267 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
2268 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2269 bnx2x_cl45_write(bp, port,
2270 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2271 ext_phy_addr, MDIO_PMA_DEVAD,
2272 0xA819, 0x0014);
2273 bnx2x_cl45_write(bp, port,
2274 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2275 ext_phy_addr,
2276 MDIO_PMA_DEVAD,
2277 0xA81A,
2278 0xc200);
2279 bnx2x_cl45_write(bp, port,
2280 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2281 ext_phy_addr,
2282 MDIO_PMA_DEVAD,
2283 0xA81B,
2284 0x0000);
2285 bnx2x_cl45_write(bp, port,
2286 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2287 ext_phy_addr,
2288 MDIO_PMA_DEVAD,
2289 0xA81C,
2290 0x0300);
2291 bnx2x_cl45_write(bp, port,
2292 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2293 ext_phy_addr,
2294 MDIO_PMA_DEVAD,
2295 0xA817,
2296 0x0009);
2297
2298 for (cnt = 0; cnt < 100; cnt++) {
2299 bnx2x_cl45_read(bp, port,
2300 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2301 ext_phy_addr,
2302 MDIO_PMA_DEVAD,
2303 0xA818,
2304 &val);
2305 if (val & 1)
2306 break;
2307 udelay(5);
2308 }
2309 if (cnt == 100) {
2310 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
2311 bnx2x_save_spirom_version(bp, port,
2312 shmem_base, 0);
2313 return;
2314 }
2315
2316
2317 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2318 bnx2x_cl45_write(bp, port,
2319 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2320 ext_phy_addr, MDIO_PMA_DEVAD,
2321 0xA819, 0x0000);
2322 bnx2x_cl45_write(bp, port,
2323 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2324 ext_phy_addr, MDIO_PMA_DEVAD,
2325 0xA81A, 0xc200);
2326 bnx2x_cl45_write(bp, port,
2327 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2328 ext_phy_addr, MDIO_PMA_DEVAD,
2329 0xA817, 0x000A);
2330 for (cnt = 0; cnt < 100; cnt++) {
2331 bnx2x_cl45_read(bp, port,
2332 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2333 ext_phy_addr,
2334 MDIO_PMA_DEVAD,
2335 0xA818,
2336 &val);
2337 if (val & 1)
2338 break;
2339 udelay(5);
2340 }
2341 if (cnt == 100) {
2342 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
2343 bnx2x_save_spirom_version(bp, port,
2344 shmem_base, 0);
2345 return;
2346 }
2347
2348 /* lower 16 bits of the register SPI_FW_STATUS */
2349 bnx2x_cl45_read(bp, port,
2350 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2351 ext_phy_addr,
2352 MDIO_PMA_DEVAD,
2353 0xA81B,
2354 &fw_ver1);
2355 /* upper 16 bits of register SPI_FW_STATUS */
2356 bnx2x_cl45_read(bp, port,
2357 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2358 ext_phy_addr,
2359 MDIO_PMA_DEVAD,
2360 0xA81C,
2361 &fw_ver2);
2362
2363 bnx2x_save_spirom_version(bp, port,
2364 shmem_base, (fw_ver2<<16) | fw_ver1);
2365 }
2366
2367 static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
2368 {
2369 struct bnx2x *bp = params->bp;
2370 u8 port = params->port;
2371 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2372 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2373
2374 /* Need to wait 200ms after reset */
2375 msleep(200);
2376 /* Boot port from external ROM
2377 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2378 */
2379 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2380 MDIO_PMA_DEVAD,
2381 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2382
2383 /* Reset internal microprocessor */
2384 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2385 MDIO_PMA_DEVAD,
2386 MDIO_PMA_REG_GEN_CTRL,
2387 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2388 /* set micro reset = 0 */
2389 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2390 MDIO_PMA_DEVAD,
2391 MDIO_PMA_REG_GEN_CTRL,
2392 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2393 /* Reset internal microprocessor */
2394 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2395 MDIO_PMA_DEVAD,
2396 MDIO_PMA_REG_GEN_CTRL,
2397 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2398 /* wait for 100ms for code download via SPI port */
2399 msleep(100);
2400
2401 /* Clear ser_boot_ctl bit */
2402 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2403 MDIO_PMA_DEVAD,
2404 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2405 /* Wait 100ms */
2406 msleep(100);
2407
2408 bnx2x_save_bcm_spirom_ver(bp, port,
2409 ext_phy_type,
2410 ext_phy_addr,
2411 params->shmem_base);
2412 }
2413
2414 static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2415 {
2416 /* This is only required for 8073A1, version 102 only */
2417
2418 struct bnx2x *bp = params->bp;
2419 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2420 u16 val;
2421
2422 /* Read 8073 HW revision*/
2423 bnx2x_cl45_read(bp, params->port,
2424 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2425 ext_phy_addr,
2426 MDIO_PMA_DEVAD,
2427 MDIO_PMA_REG_8073_CHIP_REV, &val);
2428
2429 if (val != 1) {
2430 /* No need to workaround in 8073 A1 */
2431 return 0;
2432 }
2433
2434 bnx2x_cl45_read(bp, params->port,
2435 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2436 ext_phy_addr,
2437 MDIO_PMA_DEVAD,
2438 MDIO_PMA_REG_ROM_VER2, &val);
2439
2440 /* SNR should be applied only for version 0x102 */
2441 if (val != 0x102)
2442 return 0;
2443
2444 return 1;
2445 }
2446
2447 static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2448 {
2449 struct bnx2x *bp = params->bp;
2450 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2451 u16 val, cnt, cnt1 ;
2452
2453 bnx2x_cl45_read(bp, params->port,
2454 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2455 ext_phy_addr,
2456 MDIO_PMA_DEVAD,
2457 MDIO_PMA_REG_8073_CHIP_REV, &val);
2458
2459 if (val > 0) {
2460 /* No need to workaround in 8073 A1 */
2461 return 0;
2462 }
2463 /* XAUI workaround in 8073 A0: */
2464
2465 /* After loading the boot ROM and restarting Autoneg,
2466 poll Dev1, Reg $C820: */
2467
2468 for (cnt = 0; cnt < 1000; cnt++) {
2469 bnx2x_cl45_read(bp, params->port,
2470 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2471 ext_phy_addr,
2472 MDIO_PMA_DEVAD,
2473 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2474 &val);
2475 /* If bit [14] = 0 or bit [13] = 0, continue on with
2476 system initialization (XAUI work-around not required,
2477 as these bits indicate 2.5G or 1G link up). */
2478 if (!(val & (1<<14)) || !(val & (1<<13))) {
2479 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2480 return 0;
2481 } else if (!(val & (1<<15))) {
2482 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2483 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2484 it's MSB (bit 15) goes to 1 (indicating that the
2485 XAUI workaround has completed),
2486 then continue on with system initialization.*/
2487 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2488 bnx2x_cl45_read(bp, params->port,
2489 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2490 ext_phy_addr,
2491 MDIO_PMA_DEVAD,
2492 MDIO_PMA_REG_8073_XAUI_WA, &val);
2493 if (val & (1<<15)) {
2494 DP(NETIF_MSG_LINK,
2495 "XAUI workaround has completed\n");
2496 return 0;
2497 }
2498 msleep(3);
2499 }
2500 break;
2501 }
2502 msleep(3);
2503 }
2504 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2505 return -EINVAL;
2506 }
2507
2508 static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2509 u8 ext_phy_addr,
2510 u32 ext_phy_type,
2511 u32 shmem_base)
2512 {
2513 /* Boot port from external ROM */
2514 /* EDC grst */
2515 bnx2x_cl45_write(bp, port,
2516 ext_phy_type,
2517 ext_phy_addr,
2518 MDIO_PMA_DEVAD,
2519 MDIO_PMA_REG_GEN_CTRL,
2520 0x0001);
2521
2522 /* ucode reboot and rst */
2523 bnx2x_cl45_write(bp, port,
2524 ext_phy_type,
2525 ext_phy_addr,
2526 MDIO_PMA_DEVAD,
2527 MDIO_PMA_REG_GEN_CTRL,
2528 0x008c);
2529
2530 bnx2x_cl45_write(bp, port,
2531 ext_phy_type,
2532 ext_phy_addr,
2533 MDIO_PMA_DEVAD,
2534 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2535
2536 /* Reset internal microprocessor */
2537 bnx2x_cl45_write(bp, port,
2538 ext_phy_type,
2539 ext_phy_addr,
2540 MDIO_PMA_DEVAD,
2541 MDIO_PMA_REG_GEN_CTRL,
2542 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2543
2544 /* Release srst bit */
2545 bnx2x_cl45_write(bp, port,
2546 ext_phy_type,
2547 ext_phy_addr,
2548 MDIO_PMA_DEVAD,
2549 MDIO_PMA_REG_GEN_CTRL,
2550 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2551
2552 /* wait for 120ms for code download via SPI port */
2553 msleep(120);
2554
2555 /* Clear ser_boot_ctl bit */
2556 bnx2x_cl45_write(bp, port,
2557 ext_phy_type,
2558 ext_phy_addr,
2559 MDIO_PMA_DEVAD,
2560 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2561
2562 bnx2x_save_bcm_spirom_ver(bp, port,
2563 ext_phy_type,
2564 ext_phy_addr,
2565 shmem_base);
2566 }
2567
2568 static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
2569 u8 ext_phy_addr,
2570 u32 shmem_base)
2571 {
2572 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2573 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2574 shmem_base);
2575 }
2576
2577 static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2578 u8 ext_phy_addr,
2579 u32 shmem_base)
2580 {
2581 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2582 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2583 shmem_base);
2584
2585 }
2586
2587 static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2588 {
2589 struct bnx2x *bp = params->bp;
2590 u8 port = params->port;
2591 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2592 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2593
2594 /* Need to wait 100ms after reset */
2595 msleep(100);
2596
2597 /* Micro controller re-boot */
2598 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2599 MDIO_PMA_DEVAD,
2600 MDIO_PMA_REG_GEN_CTRL,
2601 0x018B);
2602
2603 /* Set soft reset */
2604 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2605 MDIO_PMA_DEVAD,
2606 MDIO_PMA_REG_GEN_CTRL,
2607 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2608
2609 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2610 MDIO_PMA_DEVAD,
2611 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2612
2613 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2614 MDIO_PMA_DEVAD,
2615 MDIO_PMA_REG_GEN_CTRL,
2616 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2617
2618 /* wait for 150ms for microcode load */
2619 msleep(150);
2620
2621 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2622 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2623 MDIO_PMA_DEVAD,
2624 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2625
2626 msleep(200);
2627 bnx2x_save_bcm_spirom_ver(bp, port,
2628 ext_phy_type,
2629 ext_phy_addr,
2630 params->shmem_base);
2631 }
2632
2633 static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
2634 u32 ext_phy_type, u8 ext_phy_addr,
2635 u8 tx_en)
2636 {
2637 u16 val;
2638
2639 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
2640 tx_en, port);
2641 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2642 bnx2x_cl45_read(bp, port,
2643 ext_phy_type,
2644 ext_phy_addr,
2645 MDIO_PMA_DEVAD,
2646 MDIO_PMA_REG_PHY_IDENTIFIER,
2647 &val);
2648
2649 if (tx_en)
2650 val &= ~(1<<15);
2651 else
2652 val |= (1<<15);
2653
2654 bnx2x_cl45_write(bp, port,
2655 ext_phy_type,
2656 ext_phy_addr,
2657 MDIO_PMA_DEVAD,
2658 MDIO_PMA_REG_PHY_IDENTIFIER,
2659 val);
2660 }
2661
2662 static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
2663 u16 addr, u8 byte_cnt, u8 *o_buf)
2664 {
2665 struct bnx2x *bp = params->bp;
2666 u16 val = 0;
2667 u16 i;
2668 u8 port = params->port;
2669 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2670 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2671
2672 if (byte_cnt > 16) {
2673 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2674 " is limited to 0xf\n");
2675 return -EINVAL;
2676 }
2677 /* Set the read command byte count */
2678 bnx2x_cl45_write(bp, port,
2679 ext_phy_type,
2680 ext_phy_addr,
2681 MDIO_PMA_DEVAD,
2682 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2683 (byte_cnt | 0xa000));
2684
2685 /* Set the read command address */
2686 bnx2x_cl45_write(bp, port,
2687 ext_phy_type,
2688 ext_phy_addr,
2689 MDIO_PMA_DEVAD,
2690 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2691 addr);
2692
2693 /* Activate read command */
2694 bnx2x_cl45_write(bp, port,
2695 ext_phy_type,
2696 ext_phy_addr,
2697 MDIO_PMA_DEVAD,
2698 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2699 0x2c0f);
2700
2701 /* Wait up to 500us for command complete status */
2702 for (i = 0; i < 100; i++) {
2703 bnx2x_cl45_read(bp, port,
2704 ext_phy_type,
2705 ext_phy_addr,
2706 MDIO_PMA_DEVAD,
2707 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2708 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2709 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2710 break;
2711 udelay(5);
2712 }
2713
2714 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2715 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2716 DP(NETIF_MSG_LINK,
2717 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2718 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2719 return -EINVAL;
2720 }
2721
2722 /* Read the buffer */
2723 for (i = 0; i < byte_cnt; i++) {
2724 bnx2x_cl45_read(bp, port,
2725 ext_phy_type,
2726 ext_phy_addr,
2727 MDIO_PMA_DEVAD,
2728 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
2729 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
2730 }
2731
2732 for (i = 0; i < 100; i++) {
2733 bnx2x_cl45_read(bp, port,
2734 ext_phy_type,
2735 ext_phy_addr,
2736 MDIO_PMA_DEVAD,
2737 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2738 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2739 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2740 return 0;;
2741 msleep(1);
2742 }
2743 return -EINVAL;
2744 }
2745
2746 static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2747 u16 addr, u8 byte_cnt, u8 *o_buf)
2748 {
2749 struct bnx2x *bp = params->bp;
2750 u16 val, i;
2751 u8 port = params->port;
2752 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
2753 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2754
2755 if (byte_cnt > 16) {
2756 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2757 " is limited to 0xf\n");
2758 return -EINVAL;
2759 }
2760
2761 /* Need to read from 1.8000 to clear it */
2762 bnx2x_cl45_read(bp, port,
2763 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2764 ext_phy_addr,
2765 MDIO_PMA_DEVAD,
2766 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2767 &val);
2768
2769 /* Set the read command byte count */
2770 bnx2x_cl45_write(bp, port,
2771 ext_phy_type,
2772 ext_phy_addr,
2773 MDIO_PMA_DEVAD,
2774 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2775 ((byte_cnt < 2) ? 2 : byte_cnt));
2776
2777 /* Set the read command address */
2778 bnx2x_cl45_write(bp, port,
2779 ext_phy_type,
2780 ext_phy_addr,
2781 MDIO_PMA_DEVAD,
2782 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2783 addr);
2784 /* Set the destination address */
2785 bnx2x_cl45_write(bp, port,
2786 ext_phy_type,
2787 ext_phy_addr,
2788 MDIO_PMA_DEVAD,
2789 0x8004,
2790 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
2791
2792 /* Activate read command */
2793 bnx2x_cl45_write(bp, port,
2794 ext_phy_type,
2795 ext_phy_addr,
2796 MDIO_PMA_DEVAD,
2797 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2798 0x8002);
2799 /* Wait appropriate time for two-wire command to finish before
2800 polling the status register */
2801 msleep(1);
2802
2803 /* Wait up to 500us for command complete status */
2804 for (i = 0; i < 100; i++) {
2805 bnx2x_cl45_read(bp, port,
2806 ext_phy_type,
2807 ext_phy_addr,
2808 MDIO_PMA_DEVAD,
2809 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2810 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2811 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2812 break;
2813 udelay(5);
2814 }
2815
2816 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2817 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2818 DP(NETIF_MSG_LINK,
2819 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2820 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2821 return -EINVAL;
2822 }
2823
2824 /* Read the buffer */
2825 for (i = 0; i < byte_cnt; i++) {
2826 bnx2x_cl45_read(bp, port,
2827 ext_phy_type,
2828 ext_phy_addr,
2829 MDIO_PMA_DEVAD,
2830 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
2831 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
2832 }
2833
2834 for (i = 0; i < 100; i++) {
2835 bnx2x_cl45_read(bp, port,
2836 ext_phy_type,
2837 ext_phy_addr,
2838 MDIO_PMA_DEVAD,
2839 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2840 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2841 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2842 return 0;;
2843 msleep(1);
2844 }
2845
2846 return -EINVAL;
2847 }
2848
2849 u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
2850 u8 byte_cnt, u8 *o_buf)
2851 {
2852 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2853
2854 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2855 return bnx2x_8726_read_sfp_module_eeprom(params, addr,
2856 byte_cnt, o_buf);
2857 else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2858 return bnx2x_8727_read_sfp_module_eeprom(params, addr,
2859 byte_cnt, o_buf);
2860 return -EINVAL;
2861 }
2862
2863 static u8 bnx2x_get_edc_mode(struct link_params *params,
2864 u16 *edc_mode)
2865 {
2866 struct bnx2x *bp = params->bp;
2867 u8 val, check_limiting_mode = 0;
2868 *edc_mode = EDC_MODE_LIMITING;
2869
2870 /* First check for copper cable */
2871 if (bnx2x_read_sfp_module_eeprom(params,
2872 SFP_EEPROM_CON_TYPE_ADDR,
2873 1,
2874 &val) != 0) {
2875 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
2876 return -EINVAL;
2877 }
2878
2879 switch (val) {
2880 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
2881 {
2882 u8 copper_module_type;
2883
2884 /* Check if its active cable( includes SFP+ module)
2885 of passive cable*/
2886 if (bnx2x_read_sfp_module_eeprom(params,
2887 SFP_EEPROM_FC_TX_TECH_ADDR,
2888 1,
2889 &copper_module_type) !=
2890 0) {
2891 DP(NETIF_MSG_LINK,
2892 "Failed to read copper-cable-type"
2893 " from SFP+ EEPROM\n");
2894 return -EINVAL;
2895 }
2896
2897 if (copper_module_type &
2898 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
2899 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
2900 check_limiting_mode = 1;
2901 } else if (copper_module_type &
2902 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
2903 DP(NETIF_MSG_LINK, "Passive Copper"
2904 " cable detected\n");
2905 *edc_mode =
2906 EDC_MODE_PASSIVE_DAC;
2907 } else {
2908 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
2909 "type 0x%x !!!\n", copper_module_type);
2910 return -EINVAL;
2911 }
2912 break;
2913 }
2914 case SFP_EEPROM_CON_TYPE_VAL_LC:
2915 DP(NETIF_MSG_LINK, "Optic module detected\n");
2916 check_limiting_mode = 1;
2917 break;
2918 default:
2919 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
2920 val);
2921 return -EINVAL;
2922 }
2923
2924 if (check_limiting_mode) {
2925 u8 options[SFP_EEPROM_OPTIONS_SIZE];
2926 if (bnx2x_read_sfp_module_eeprom(params,
2927 SFP_EEPROM_OPTIONS_ADDR,
2928 SFP_EEPROM_OPTIONS_SIZE,
2929 options) != 0) {
2930 DP(NETIF_MSG_LINK, "Failed to read Option"
2931 " field from module EEPROM\n");
2932 return -EINVAL;
2933 }
2934 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
2935 *edc_mode = EDC_MODE_LINEAR;
2936 else
2937 *edc_mode = EDC_MODE_LIMITING;
2938 }
2939 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
2940 return 0;
2941 }
2942
2943 /* This function read the relevant field from the module ( SFP+ ),
2944 and verify it is compliant with this board */
2945 static u8 bnx2x_verify_sfp_module(struct link_params *params)
2946 {
2947 struct bnx2x *bp = params->bp;
2948 u32 val;
2949 u32 fw_resp;
2950 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
2951 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
2952
2953 val = REG_RD(bp, params->shmem_base +
2954 offsetof(struct shmem_region, dev_info.
2955 port_feature_config[params->port].config));
2956 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2957 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
2958 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
2959 return 0;
2960 }
2961
2962 /* Ask the FW to validate the module */
2963 if (!(params->feature_config_flags &
2964 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
2965 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
2966 "verification\n");
2967 return -EINVAL;
2968 }
2969
2970 fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL);
2971 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
2972 DP(NETIF_MSG_LINK, "Approved module\n");
2973 return 0;
2974 }
2975
2976 /* format the warning message */
2977 if (bnx2x_read_sfp_module_eeprom(params,
2978 SFP_EEPROM_VENDOR_NAME_ADDR,
2979 SFP_EEPROM_VENDOR_NAME_SIZE,
2980 (u8 *)vendor_name))
2981 vendor_name[0] = '\0';
2982 else
2983 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
2984 if (bnx2x_read_sfp_module_eeprom(params,
2985 SFP_EEPROM_PART_NO_ADDR,
2986 SFP_EEPROM_PART_NO_SIZE,
2987 (u8 *)vendor_pn))
2988 vendor_pn[0] = '\0';
2989 else
2990 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
2991
2992 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected, Port %d from %s part number %s\n",
2993 params->port, vendor_name, vendor_pn);
2994 return -EINVAL;
2995 }
2996
2997 static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
2998 u16 edc_mode)
2999 {
3000 struct bnx2x *bp = params->bp;
3001 u8 port = params->port;
3002 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3003 u16 cur_limiting_mode;
3004
3005 bnx2x_cl45_read(bp, port,
3006 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3007 ext_phy_addr,
3008 MDIO_PMA_DEVAD,
3009 MDIO_PMA_REG_ROM_VER2,
3010 &cur_limiting_mode);
3011 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
3012 cur_limiting_mode);
3013
3014 if (edc_mode == EDC_MODE_LIMITING) {
3015 DP(NETIF_MSG_LINK,
3016 "Setting LIMITING MODE\n");
3017 bnx2x_cl45_write(bp, port,
3018 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3019 ext_phy_addr,
3020 MDIO_PMA_DEVAD,
3021 MDIO_PMA_REG_ROM_VER2,
3022 EDC_MODE_LIMITING);
3023 } else { /* LRM mode ( default )*/
3024
3025 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
3026
3027 /* Changing to LRM mode takes quite few seconds.
3028 So do it only if current mode is limiting
3029 ( default is LRM )*/
3030 if (cur_limiting_mode != EDC_MODE_LIMITING)
3031 return 0;
3032
3033 bnx2x_cl45_write(bp, port,
3034 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3035 ext_phy_addr,
3036 MDIO_PMA_DEVAD,
3037 MDIO_PMA_REG_LRM_MODE,
3038 0);
3039 bnx2x_cl45_write(bp, port,
3040 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3041 ext_phy_addr,
3042 MDIO_PMA_DEVAD,
3043 MDIO_PMA_REG_ROM_VER2,
3044 0x128);
3045 bnx2x_cl45_write(bp, port,
3046 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3047 ext_phy_addr,
3048 MDIO_PMA_DEVAD,
3049 MDIO_PMA_REG_MISC_CTRL0,
3050 0x4008);
3051 bnx2x_cl45_write(bp, port,
3052 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3053 ext_phy_addr,
3054 MDIO_PMA_DEVAD,
3055 MDIO_PMA_REG_LRM_MODE,
3056 0xaaaa);
3057 }
3058 return 0;
3059 }
3060
3061 static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
3062 u16 edc_mode)
3063 {
3064 struct bnx2x *bp = params->bp;
3065 u8 port = params->port;
3066 u16 phy_identifier;
3067 u16 rom_ver2_val;
3068 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3069
3070 bnx2x_cl45_read(bp, port,
3071 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3072 ext_phy_addr,
3073 MDIO_PMA_DEVAD,
3074 MDIO_PMA_REG_PHY_IDENTIFIER,
3075 &phy_identifier);
3076
3077 bnx2x_cl45_write(bp, port,
3078 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3079 ext_phy_addr,
3080 MDIO_PMA_DEVAD,
3081 MDIO_PMA_REG_PHY_IDENTIFIER,
3082 (phy_identifier & ~(1<<9)));
3083
3084 bnx2x_cl45_read(bp, port,
3085 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3086 ext_phy_addr,
3087 MDIO_PMA_DEVAD,
3088 MDIO_PMA_REG_ROM_VER2,
3089 &rom_ver2_val);
3090 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
3091 bnx2x_cl45_write(bp, port,
3092 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3093 ext_phy_addr,
3094 MDIO_PMA_DEVAD,
3095 MDIO_PMA_REG_ROM_VER2,
3096 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
3097
3098 bnx2x_cl45_write(bp, port,
3099 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3100 ext_phy_addr,
3101 MDIO_PMA_DEVAD,
3102 MDIO_PMA_REG_PHY_IDENTIFIER,
3103 (phy_identifier | (1<<9)));
3104
3105 return 0;
3106 }
3107
3108
3109 static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
3110 {
3111 u8 val;
3112 struct bnx2x *bp = params->bp;
3113 u16 timeout;
3114 /* Initialization time after hot-plug may take up to 300ms for some
3115 phys type ( e.g. JDSU ) */
3116 for (timeout = 0; timeout < 60; timeout++) {
3117 if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val)
3118 == 0) {
3119 DP(NETIF_MSG_LINK, "SFP+ module initialization "
3120 "took %d ms\n", timeout * 5);
3121 return 0;
3122 }
3123 msleep(5);
3124 }
3125 return -EINVAL;
3126 }
3127
3128 static void bnx2x_8727_power_module(struct bnx2x *bp,
3129 struct link_params *params,
3130 u8 ext_phy_addr, u8 is_power_up) {
3131 /* Make sure GPIOs are not using for LED mode */
3132 u16 val;
3133 u8 port = params->port;
3134 /*
3135 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
3136 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
3137 * output
3138 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
3139 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
3140 * where the 1st bit is the over-current(only input), and 2nd bit is
3141 * for power( only output )
3142 */
3143
3144 /*
3145 * In case of NOC feature is disabled and power is up, set GPIO control
3146 * as input to enable listening of over-current indication
3147 */
3148
3149 if (!(params->feature_config_flags &
3150 FEATURE_CONFIG_BCM8727_NOC) && is_power_up)
3151 val = (1<<4);
3152 else
3153 /*
3154 * Set GPIO control to OUTPUT, and set the power bit
3155 * to according to the is_power_up
3156 */
3157 val = ((!(is_power_up)) << 1);
3158
3159 bnx2x_cl45_write(bp, port,
3160 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3161 ext_phy_addr,
3162 MDIO_PMA_DEVAD,
3163 MDIO_PMA_REG_8727_GPIO_CTRL,
3164 val);
3165 }
3166
3167 static u8 bnx2x_sfp_module_detection(struct link_params *params)
3168 {
3169 struct bnx2x *bp = params->bp;
3170 u16 edc_mode;
3171 u8 rc = 0;
3172 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3173 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3174 u32 val = REG_RD(bp, params->shmem_base +
3175 offsetof(struct shmem_region, dev_info.
3176 port_feature_config[params->port].config));
3177
3178 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
3179 params->port);
3180
3181 if (bnx2x_get_edc_mode(params, &edc_mode) != 0) {
3182 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
3183 return -EINVAL;
3184 } else if (bnx2x_verify_sfp_module(params) !=
3185 0) {
3186 /* check SFP+ module compatibility */
3187 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
3188 rc = -EINVAL;
3189 /* Turn on fault module-detected led */
3190 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3191 MISC_REGISTERS_GPIO_HIGH,
3192 params->port);
3193 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
3194 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3195 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
3196 /* Shutdown SFP+ module */
3197 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
3198 bnx2x_8727_power_module(bp, params,
3199 ext_phy_addr, 0);
3200 return rc;
3201 }
3202 } else {
3203 /* Turn off fault module-detected led */
3204 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
3205 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3206 MISC_REGISTERS_GPIO_LOW,
3207 params->port);
3208 }
3209
3210 /* power up the SFP module */
3211 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
3212 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
3213
3214 /* Check and set limiting mode / LRM mode on 8726.
3215 On 8727 it is done automatically */
3216 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
3217 bnx2x_bcm8726_set_limiting_mode(params, edc_mode);
3218 else
3219 bnx2x_bcm8727_set_limiting_mode(params, edc_mode);
3220 /*
3221 * Enable transmit for this module if the module is approved, or
3222 * if unapproved modules should also enable the Tx laser
3223 */
3224 if (rc == 0 ||
3225 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
3226 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3227 bnx2x_sfp_set_transmitter(bp, params->port,
3228 ext_phy_type, ext_phy_addr, 1);
3229 else
3230 bnx2x_sfp_set_transmitter(bp, params->port,
3231 ext_phy_type, ext_phy_addr, 0);
3232
3233 return rc;
3234 }
3235
3236 void bnx2x_handle_module_detect_int(struct link_params *params)
3237 {
3238 struct bnx2x *bp = params->bp;
3239 u32 gpio_val;
3240 u8 port = params->port;
3241
3242 /* Set valid module led off */
3243 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3244 MISC_REGISTERS_GPIO_HIGH,
3245 params->port);
3246
3247 /* Get current gpio val refelecting module plugged in / out*/
3248 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
3249
3250 /* Call the handling function in case module is detected */
3251 if (gpio_val == 0) {
3252
3253 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3254 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3255 port);
3256
3257 if (bnx2x_wait_for_sfp_module_initialized(params) ==
3258 0)
3259 bnx2x_sfp_module_detection(params);
3260 else
3261 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
3262 } else {
3263 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3264
3265 u32 ext_phy_type =
3266 XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3267 u32 val = REG_RD(bp, params->shmem_base +
3268 offsetof(struct shmem_region, dev_info.
3269 port_feature_config[params->port].
3270 config));
3271
3272 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3273 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
3274 port);
3275 /* Module was plugged out. */
3276 /* Disable transmit for this module */
3277 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3278 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3279 bnx2x_sfp_set_transmitter(bp, params->port,
3280 ext_phy_type, ext_phy_addr, 0);
3281 }
3282 }
3283
3284 static void bnx2x_bcm807x_force_10G(struct link_params *params)
3285 {
3286 struct bnx2x *bp = params->bp;
3287 u8 port = params->port;
3288 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3289 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3290
3291 /* Force KR or KX */
3292 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3293 MDIO_PMA_DEVAD,
3294 MDIO_PMA_REG_CTRL,
3295 0x2040);
3296 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3297 MDIO_PMA_DEVAD,
3298 MDIO_PMA_REG_10G_CTRL2,
3299 0x000b);
3300 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3301 MDIO_PMA_DEVAD,
3302 MDIO_PMA_REG_BCM_CTRL,
3303 0x0000);
3304 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3305 MDIO_AN_DEVAD,
3306 MDIO_AN_REG_CTRL,
3307 0x0000);
3308 }
3309
3310 static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
3311 {
3312 struct bnx2x *bp = params->bp;
3313 u8 port = params->port;
3314 u16 val;
3315 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3316 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3317
3318 bnx2x_cl45_read(bp, params->port,
3319 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3320 ext_phy_addr,
3321 MDIO_PMA_DEVAD,
3322 MDIO_PMA_REG_8073_CHIP_REV, &val);
3323
3324 if (val == 0) {
3325 /* Mustn't set low power mode in 8073 A0 */
3326 return;
3327 }
3328
3329 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3330 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3331 MDIO_XS_DEVAD,
3332 MDIO_XS_PLL_SEQUENCER, &val);
3333 val &= ~(1<<13);
3334 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3335 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3336
3337 /* PLL controls */
3338 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3339 MDIO_XS_DEVAD, 0x805E, 0x1077);
3340 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3341 MDIO_XS_DEVAD, 0x805D, 0x0000);
3342 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3343 MDIO_XS_DEVAD, 0x805C, 0x030B);
3344 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3345 MDIO_XS_DEVAD, 0x805B, 0x1240);
3346 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3347 MDIO_XS_DEVAD, 0x805A, 0x2490);
3348
3349 /* Tx Controls */
3350 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3351 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3352 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3353 MDIO_XS_DEVAD, 0x80A6, 0x9041);
3354 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3355 MDIO_XS_DEVAD, 0x80A5, 0x4640);
3356
3357 /* Rx Controls */
3358 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3359 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3360 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3361 MDIO_XS_DEVAD, 0x80FD, 0x9249);
3362 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3363 MDIO_XS_DEVAD, 0x80FC, 0x2015);
3364
3365 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3366 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3367 MDIO_XS_DEVAD,
3368 MDIO_XS_PLL_SEQUENCER, &val);
3369 val |= (1<<13);
3370 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3371 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3372 }
3373
3374 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3375 struct link_vars *vars)
3376 {
3377 struct bnx2x *bp = params->bp;
3378 u16 cl37_val;
3379 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3380 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3381
3382 bnx2x_cl45_read(bp, params->port,
3383 ext_phy_type,
3384 ext_phy_addr,
3385 MDIO_AN_DEVAD,
3386 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3387
3388 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3389 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3390
3391 if ((vars->ieee_fc &
3392 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3393 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
3394 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
3395 }
3396 if ((vars->ieee_fc &
3397 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3399 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3400 }
3401 if ((vars->ieee_fc &
3402 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3403 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3404 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3405 }
3406 DP(NETIF_MSG_LINK,
3407 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3408
3409 bnx2x_cl45_write(bp, params->port,
3410 ext_phy_type,
3411 ext_phy_addr,
3412 MDIO_AN_DEVAD,
3413 MDIO_AN_REG_CL37_FC_LD, cl37_val);
3414 msleep(500);
3415 }
3416
3417 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3418 struct link_vars *vars)
3419 {
3420 struct bnx2x *bp = params->bp;
3421 u16 val;
3422 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3423 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3424
3425 /* read modify write pause advertizing */
3426 bnx2x_cl45_read(bp, params->port,
3427 ext_phy_type,
3428 ext_phy_addr,
3429 MDIO_AN_DEVAD,
3430 MDIO_AN_REG_ADV_PAUSE, &val);
3431
3432 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3433
3434 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3435
3436 if ((vars->ieee_fc &
3437 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3438 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3439 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3440 }
3441 if ((vars->ieee_fc &
3442 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3443 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3444 val |=
3445 MDIO_AN_REG_ADV_PAUSE_PAUSE;
3446 }
3447 DP(NETIF_MSG_LINK,
3448 "Ext phy AN advertize 0x%x\n", val);
3449 bnx2x_cl45_write(bp, params->port,
3450 ext_phy_type,
3451 ext_phy_addr,
3452 MDIO_AN_DEVAD,
3453 MDIO_AN_REG_ADV_PAUSE, val);
3454 }
3455 static void bnx2x_set_preemphasis(struct link_params *params)
3456 {
3457 u16 bank, i = 0;
3458 struct bnx2x *bp = params->bp;
3459
3460 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3461 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3462 CL45_WR_OVER_CL22(bp, params->port,
3463 params->phy_addr,
3464 bank,
3465 MDIO_RX0_RX_EQ_BOOST,
3466 params->xgxs_config_rx[i]);
3467 }
3468
3469 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3470 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3471 CL45_WR_OVER_CL22(bp, params->port,
3472 params->phy_addr,
3473 bank,
3474 MDIO_TX0_TX_DRIVER,
3475 params->xgxs_config_tx[i]);
3476 }
3477 }
3478
3479
3480 static void bnx2x_8481_set_led4(struct link_params *params,
3481 u32 ext_phy_type, u8 ext_phy_addr)
3482 {
3483 struct bnx2x *bp = params->bp;
3484
3485 /* PHYC_CTL_LED_CTL */
3486 bnx2x_cl45_write(bp, params->port,
3487 ext_phy_type,
3488 ext_phy_addr,
3489 MDIO_PMA_DEVAD,
3490 MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
3491
3492 /* Unmask LED4 for 10G link */
3493 bnx2x_cl45_write(bp, params->port,
3494 ext_phy_type,
3495 ext_phy_addr,
3496 MDIO_PMA_DEVAD,
3497 MDIO_PMA_REG_8481_SIGNAL_MASK, (1<<6));
3498 /* 'Interrupt Mask' */
3499 bnx2x_cl45_write(bp, params->port,
3500 ext_phy_type,
3501 ext_phy_addr,
3502 MDIO_AN_DEVAD,
3503 0xFFFB, 0xFFFD);
3504 }
3505 static void bnx2x_8481_set_legacy_led_mode(struct link_params *params,
3506 u32 ext_phy_type, u8 ext_phy_addr)
3507 {
3508 struct bnx2x *bp = params->bp;
3509
3510 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3511 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3512 bnx2x_cl45_write(bp, params->port,
3513 ext_phy_type,
3514 ext_phy_addr,
3515 MDIO_AN_DEVAD,
3516 MDIO_AN_REG_8481_LEGACY_SHADOW,
3517 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3518 }
3519
3520 static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3521 u32 ext_phy_type, u8 ext_phy_addr)
3522 {
3523 struct bnx2x *bp = params->bp;
3524 u16 val1;
3525
3526 /* LED1 (10G Link) */
3527 /* Enable continuse based on source 7(10G-link) */
3528 bnx2x_cl45_read(bp, params->port,
3529 ext_phy_type,
3530 ext_phy_addr,
3531 MDIO_PMA_DEVAD,
3532 MDIO_PMA_REG_8481_LINK_SIGNAL,
3533 &val1);
3534 /* Set bit 2 to 0, and bits [1:0] to 10 */
3535 val1 &= ~((1<<0) | (1<<2) | (1<<7)); /* Clear bits 0,2,7*/
3536 val1 |= ((1<<1) | (1<<6)); /* Set bit 1, 6 */
3537
3538 bnx2x_cl45_write(bp, params->port,
3539 ext_phy_type,
3540 ext_phy_addr,
3541 MDIO_PMA_DEVAD,
3542 MDIO_PMA_REG_8481_LINK_SIGNAL,
3543 val1);
3544
3545 /* Unmask LED1 for 10G link */
3546 bnx2x_cl45_read(bp, params->port,
3547 ext_phy_type,
3548 ext_phy_addr,
3549 MDIO_PMA_DEVAD,
3550 MDIO_PMA_REG_8481_LED1_MASK,
3551 &val1);
3552 /* Set bit 2 to 0, and bits [1:0] to 10 */
3553 val1 |= (1<<7);
3554 bnx2x_cl45_write(bp, params->port,
3555 ext_phy_type,
3556 ext_phy_addr,
3557 MDIO_PMA_DEVAD,
3558 MDIO_PMA_REG_8481_LED1_MASK,
3559 val1);
3560
3561 /* LED2 (1G/100/10G Link) */
3562 /* Mask LED2 for 10G link */
3563 bnx2x_cl45_write(bp, params->port,
3564 ext_phy_type,
3565 ext_phy_addr,
3566 MDIO_PMA_DEVAD,
3567 MDIO_PMA_REG_8481_LED2_MASK,
3568 0);
3569
3570 /* Unmask LED3 for 10G link */
3571 bnx2x_cl45_write(bp, params->port,
3572 ext_phy_type,
3573 ext_phy_addr,
3574 MDIO_PMA_DEVAD,
3575 MDIO_PMA_REG_8481_LED3_MASK,
3576 0x6);
3577 bnx2x_cl45_write(bp, params->port,
3578 ext_phy_type,
3579 ext_phy_addr,
3580 MDIO_PMA_DEVAD,
3581 MDIO_PMA_REG_8481_LED3_BLINK,
3582 0);
3583 }
3584
3585
3586 static void bnx2x_init_internal_phy(struct link_params *params,
3587 struct link_vars *vars,
3588 u8 enable_cl73)
3589 {
3590 struct bnx2x *bp = params->bp;
3591
3592 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
3593 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3594 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3595 (params->feature_config_flags &
3596 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
3597 bnx2x_set_preemphasis(params);
3598
3599 /* forced speed requested? */
3600 if (vars->line_speed != SPEED_AUTO_NEG ||
3601 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3602 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3603 params->loopback_mode == LOOPBACK_EXT)) {
3604 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3605
3606 /* disable autoneg */
3607 bnx2x_set_autoneg(params, vars, 0);
3608
3609 /* program speed and duplex */
3610 bnx2x_program_serdes(params, vars);
3611
3612 } else { /* AN_mode */
3613 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3614
3615 /* AN enabled */
3616 bnx2x_set_brcm_cl37_advertisment(params);
3617
3618 /* program duplex & pause advertisement (for aneg) */
3619 bnx2x_set_ieee_aneg_advertisment(params,
3620 vars->ieee_fc);
3621
3622 /* enable autoneg */
3623 bnx2x_set_autoneg(params, vars, enable_cl73);
3624
3625 /* enable and restart AN */
3626 bnx2x_restart_autoneg(params, enable_cl73);
3627 }
3628
3629 } else { /* SGMII mode */
3630 DP(NETIF_MSG_LINK, "SGMII\n");
3631
3632 bnx2x_initialize_sgmii_process(params, vars);
3633 }
3634 }
3635
3636 static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3637 {
3638 struct bnx2x *bp = params->bp;
3639 u32 ext_phy_type;
3640 u8 ext_phy_addr;
3641 u16 cnt;
3642 u16 ctrl = 0;
3643 u16 val = 0;
3644 u8 rc = 0;
3645
3646 if (vars->phy_flags & PHY_XGXS_FLAG) {
3647 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
3648
3649 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3650 /* Make sure that the soft reset is off (expect for the 8072:
3651 * due to the lock, it will be done inside the specific
3652 * handling)
3653 */
3654 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3655 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3656 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3657 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
3658 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
3659 /* Wait for soft reset to get cleared upto 1 sec */
3660 for (cnt = 0; cnt < 1000; cnt++) {
3661 bnx2x_cl45_read(bp, params->port,
3662 ext_phy_type,
3663 ext_phy_addr,
3664 MDIO_PMA_DEVAD,
3665 MDIO_PMA_REG_CTRL, &ctrl);
3666 if (!(ctrl & (1<<15)))
3667 break;
3668 msleep(1);
3669 }
3670 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
3671 ctrl, cnt);
3672 }
3673
3674 switch (ext_phy_type) {
3675 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3676 break;
3677
3678 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3679 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3680
3681 bnx2x_cl45_write(bp, params->port,
3682 ext_phy_type,
3683 ext_phy_addr,
3684 MDIO_PMA_DEVAD,
3685 MDIO_PMA_REG_MISC_CTRL,
3686 0x8288);
3687 bnx2x_cl45_write(bp, params->port,
3688 ext_phy_type,
3689 ext_phy_addr,
3690 MDIO_PMA_DEVAD,
3691 MDIO_PMA_REG_PHY_IDENTIFIER,
3692 0x7fbf);
3693 bnx2x_cl45_write(bp, params->port,
3694 ext_phy_type,
3695 ext_phy_addr,
3696 MDIO_PMA_DEVAD,
3697 MDIO_PMA_REG_CMU_PLL_BYPASS,
3698 0x0100);
3699 bnx2x_cl45_write(bp, params->port,
3700 ext_phy_type,
3701 ext_phy_addr,
3702 MDIO_WIS_DEVAD,
3703 MDIO_WIS_REG_LASI_CNTL, 0x1);
3704
3705 /* BCM8705 doesn't have microcode, hence the 0 */
3706 bnx2x_save_spirom_version(bp, params->port,
3707 params->shmem_base, 0);
3708 break;
3709
3710 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3711 /* Wait until fw is loaded */
3712 for (cnt = 0; cnt < 100; cnt++) {
3713 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3714 ext_phy_addr, MDIO_PMA_DEVAD,
3715 MDIO_PMA_REG_ROM_VER1, &val);
3716 if (val)
3717 break;
3718 msleep(10);
3719 }
3720 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
3721 "after %d ms\n", cnt);
3722 if ((params->feature_config_flags &
3723 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3724 u8 i;
3725 u16 reg;
3726 for (i = 0; i < 4; i++) {
3727 reg = MDIO_XS_8706_REG_BANK_RX0 +
3728 i*(MDIO_XS_8706_REG_BANK_RX1 -
3729 MDIO_XS_8706_REG_BANK_RX0);
3730 bnx2x_cl45_read(bp, params->port,
3731 ext_phy_type,
3732 ext_phy_addr,
3733 MDIO_XS_DEVAD,
3734 reg, &val);
3735 /* Clear first 3 bits of the control */
3736 val &= ~0x7;
3737 /* Set control bits according to
3738 configuation */
3739 val |= (params->xgxs_config_rx[i] &
3740 0x7);
3741 DP(NETIF_MSG_LINK, "Setting RX"
3742 "Equalizer to BCM8706 reg 0x%x"
3743 " <-- val 0x%x\n", reg, val);
3744 bnx2x_cl45_write(bp, params->port,
3745 ext_phy_type,
3746 ext_phy_addr,
3747 MDIO_XS_DEVAD,
3748 reg, val);
3749 }
3750 }
3751 /* Force speed */
3752 if (params->req_line_speed == SPEED_10000) {
3753 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3754
3755 bnx2x_cl45_write(bp, params->port,
3756 ext_phy_type,
3757 ext_phy_addr,
3758 MDIO_PMA_DEVAD,
3759 MDIO_PMA_REG_DIGITAL_CTRL,
3760 0x400);
3761 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3762 ext_phy_addr, MDIO_PMA_DEVAD,
3763 MDIO_PMA_REG_LASI_CTRL, 1);
3764 } else {
3765 /* Force 1Gbps using autoneg with 1G
3766 advertisment */
3767
3768 /* Allow CL37 through CL73 */
3769 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3770 bnx2x_cl45_write(bp, params->port,
3771 ext_phy_type,
3772 ext_phy_addr,
3773 MDIO_AN_DEVAD,
3774 MDIO_AN_REG_CL37_CL73,
3775 0x040c);
3776
3777 /* Enable Full-Duplex advertisment on CL37 */
3778 bnx2x_cl45_write(bp, params->port,
3779 ext_phy_type,
3780 ext_phy_addr,
3781 MDIO_AN_DEVAD,
3782 MDIO_AN_REG_CL37_FC_LP,
3783 0x0020);
3784 /* Enable CL37 AN */
3785 bnx2x_cl45_write(bp, params->port,
3786 ext_phy_type,
3787 ext_phy_addr,
3788 MDIO_AN_DEVAD,
3789 MDIO_AN_REG_CL37_AN,
3790 0x1000);
3791 /* 1G support */
3792 bnx2x_cl45_write(bp, params->port,
3793 ext_phy_type,
3794 ext_phy_addr,
3795 MDIO_AN_DEVAD,
3796 MDIO_AN_REG_ADV, (1<<5));
3797
3798 /* Enable clause 73 AN */
3799 bnx2x_cl45_write(bp, params->port,
3800 ext_phy_type,
3801 ext_phy_addr,
3802 MDIO_AN_DEVAD,
3803 MDIO_AN_REG_CTRL,
3804 0x1200);
3805 bnx2x_cl45_write(bp, params->port,
3806 ext_phy_type,
3807 ext_phy_addr,
3808 MDIO_PMA_DEVAD,
3809 MDIO_PMA_REG_RX_ALARM_CTRL,
3810 0x0400);
3811 bnx2x_cl45_write(bp, params->port,
3812 ext_phy_type,
3813 ext_phy_addr,
3814 MDIO_PMA_DEVAD,
3815 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3816
3817 }
3818 bnx2x_save_bcm_spirom_ver(bp, params->port,
3819 ext_phy_type,
3820 ext_phy_addr,
3821 params->shmem_base);
3822 break;
3823 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3824 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3825 bnx2x_bcm8726_external_rom_boot(params);
3826
3827 /* Need to call module detected on initialization since
3828 the module detection triggered by actual module
3829 insertion might occur before driver is loaded, and when
3830 driver is loaded, it reset all registers, including the
3831 transmitter */
3832 bnx2x_sfp_module_detection(params);
3833
3834 /* Set Flow control */
3835 bnx2x_ext_phy_set_pause(params, vars);
3836 if (params->req_line_speed == SPEED_1000) {
3837 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3838 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3839 ext_phy_addr, MDIO_PMA_DEVAD,
3840 MDIO_PMA_REG_CTRL, 0x40);
3841 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3842 ext_phy_addr, MDIO_PMA_DEVAD,
3843 MDIO_PMA_REG_10G_CTRL2, 0xD);
3844 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3845 ext_phy_addr, MDIO_PMA_DEVAD,
3846 MDIO_PMA_REG_LASI_CTRL, 0x5);
3847 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3848 ext_phy_addr, MDIO_PMA_DEVAD,
3849 MDIO_PMA_REG_RX_ALARM_CTRL,
3850 0x400);
3851 } else if ((params->req_line_speed ==
3852 SPEED_AUTO_NEG) &&
3853 ((params->speed_cap_mask &
3854 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
3855 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
3856 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3857 ext_phy_addr, MDIO_AN_DEVAD,
3858 MDIO_AN_REG_ADV, 0x20);
3859 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3860 ext_phy_addr, MDIO_AN_DEVAD,
3861 MDIO_AN_REG_CL37_CL73, 0x040c);
3862 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3863 ext_phy_addr, MDIO_AN_DEVAD,
3864 MDIO_AN_REG_CL37_FC_LD, 0x0020);
3865 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3866 ext_phy_addr, MDIO_AN_DEVAD,
3867 MDIO_AN_REG_CL37_AN, 0x1000);
3868 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3869 ext_phy_addr, MDIO_AN_DEVAD,
3870 MDIO_AN_REG_CTRL, 0x1200);
3871
3872 /* Enable RX-ALARM control to receive
3873 interrupt for 1G speed change */
3874 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3875 ext_phy_addr, MDIO_PMA_DEVAD,
3876 MDIO_PMA_REG_LASI_CTRL, 0x4);
3877 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3878 ext_phy_addr, MDIO_PMA_DEVAD,
3879 MDIO_PMA_REG_RX_ALARM_CTRL,
3880 0x400);
3881
3882 } else { /* Default 10G. Set only LASI control */
3883 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3884 ext_phy_addr, MDIO_PMA_DEVAD,
3885 MDIO_PMA_REG_LASI_CTRL, 1);
3886 }
3887
3888 /* Set TX PreEmphasis if needed */
3889 if ((params->feature_config_flags &
3890 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3891 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3892 "TX_CTRL2 0x%x\n",
3893 params->xgxs_config_tx[0],
3894 params->xgxs_config_tx[1]);
3895 bnx2x_cl45_write(bp, params->port,
3896 ext_phy_type,
3897 ext_phy_addr,
3898 MDIO_PMA_DEVAD,
3899 MDIO_PMA_REG_8726_TX_CTRL1,
3900 params->xgxs_config_tx[0]);
3901
3902 bnx2x_cl45_write(bp, params->port,
3903 ext_phy_type,
3904 ext_phy_addr,
3905 MDIO_PMA_DEVAD,
3906 MDIO_PMA_REG_8726_TX_CTRL2,
3907 params->xgxs_config_tx[1]);
3908 }
3909 break;
3910 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3911 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3912 {
3913 u16 tmp1;
3914 u16 rx_alarm_ctrl_val;
3915 u16 lasi_ctrl_val;
3916 if (ext_phy_type ==
3917 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
3918 rx_alarm_ctrl_val = 0x400;
3919 lasi_ctrl_val = 0x0004;
3920 } else {
3921 rx_alarm_ctrl_val = (1<<2);
3922 lasi_ctrl_val = 0x0004;
3923 }
3924
3925 /* enable LASI */
3926 bnx2x_cl45_write(bp, params->port,
3927 ext_phy_type,
3928 ext_phy_addr,
3929 MDIO_PMA_DEVAD,
3930 MDIO_PMA_REG_RX_ALARM_CTRL,
3931 rx_alarm_ctrl_val);
3932
3933 bnx2x_cl45_write(bp, params->port,
3934 ext_phy_type,
3935 ext_phy_addr,
3936 MDIO_PMA_DEVAD,
3937 MDIO_PMA_REG_LASI_CTRL,
3938 lasi_ctrl_val);
3939
3940 bnx2x_8073_set_pause_cl37(params, vars);
3941
3942 if (ext_phy_type ==
3943 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)
3944 bnx2x_bcm8072_external_rom_boot(params);
3945 else
3946 /* In case of 8073 with long xaui lines,
3947 don't set the 8073 xaui low power*/
3948 bnx2x_bcm8073_set_xaui_low_power_mode(params);
3949
3950 bnx2x_cl45_read(bp, params->port,
3951 ext_phy_type,
3952 ext_phy_addr,
3953 MDIO_PMA_DEVAD,
3954 MDIO_PMA_REG_M8051_MSGOUT_REG,
3955 &tmp1);
3956
3957 bnx2x_cl45_read(bp, params->port,
3958 ext_phy_type,
3959 ext_phy_addr,
3960 MDIO_PMA_DEVAD,
3961 MDIO_PMA_REG_RX_ALARM, &tmp1);
3962
3963 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
3964 "0x%x\n", tmp1);
3965
3966 /* If this is forced speed, set to KR or KX
3967 * (all other are not supported)
3968 */
3969 if (params->loopback_mode == LOOPBACK_EXT) {
3970 bnx2x_bcm807x_force_10G(params);
3971 DP(NETIF_MSG_LINK,
3972 "Forced speed 10G on 807X\n");
3973 break;
3974 } else {
3975 bnx2x_cl45_write(bp, params->port,
3976 ext_phy_type, ext_phy_addr,
3977 MDIO_PMA_DEVAD,
3978 MDIO_PMA_REG_BCM_CTRL,
3979 0x0002);
3980 }
3981 if (params->req_line_speed != SPEED_AUTO_NEG) {
3982 if (params->req_line_speed == SPEED_10000) {
3983 val = (1<<7);
3984 } else if (params->req_line_speed ==
3985 SPEED_2500) {
3986 val = (1<<5);
3987 /* Note that 2.5G works only
3988 when used with 1G advertisment */
3989 } else
3990 val = (1<<5);
3991 } else {
3992
3993 val = 0;
3994 if (params->speed_cap_mask &
3995 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3996 val |= (1<<7);
3997
3998 /* Note that 2.5G works only when
3999 used with 1G advertisment */
4000 if (params->speed_cap_mask &
4001 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4002 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4003 val |= (1<<5);
4004 DP(NETIF_MSG_LINK,
4005 "807x autoneg val = 0x%x\n", val);
4006 }
4007
4008 bnx2x_cl45_write(bp, params->port,
4009 ext_phy_type,
4010 ext_phy_addr,
4011 MDIO_AN_DEVAD,
4012 MDIO_AN_REG_ADV, val);
4013 if (ext_phy_type ==
4014 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
4015 bnx2x_cl45_read(bp, params->port,
4016 ext_phy_type,
4017 ext_phy_addr,
4018 MDIO_AN_DEVAD,
4019 MDIO_AN_REG_8073_2_5G, &tmp1);
4020
4021 if (((params->speed_cap_mask &
4022 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4023 (params->req_line_speed ==
4024 SPEED_AUTO_NEG)) ||
4025 (params->req_line_speed ==
4026 SPEED_2500)) {
4027 u16 phy_ver;
4028 /* Allow 2.5G for A1 and above */
4029 bnx2x_cl45_read(bp, params->port,
4030 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4031 ext_phy_addr,
4032 MDIO_PMA_DEVAD,
4033 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
4034 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4035 if (phy_ver > 0)
4036 tmp1 |= 1;
4037 else
4038 tmp1 &= 0xfffe;
4039 } else {
4040 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4041 tmp1 &= 0xfffe;
4042 }
4043
4044 bnx2x_cl45_write(bp, params->port,
4045 ext_phy_type,
4046 ext_phy_addr,
4047 MDIO_AN_DEVAD,
4048 MDIO_AN_REG_8073_2_5G, tmp1);
4049 }
4050
4051 /* Add support for CL37 (passive mode) II */
4052
4053 bnx2x_cl45_read(bp, params->port,
4054 ext_phy_type,
4055 ext_phy_addr,
4056 MDIO_AN_DEVAD,
4057 MDIO_AN_REG_CL37_FC_LD,
4058 &tmp1);
4059
4060 bnx2x_cl45_write(bp, params->port,
4061 ext_phy_type,
4062 ext_phy_addr,
4063 MDIO_AN_DEVAD,
4064 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
4065 ((params->req_duplex == DUPLEX_FULL) ?
4066 0x20 : 0x40)));
4067
4068 /* Add support for CL37 (passive mode) III */
4069 bnx2x_cl45_write(bp, params->port,
4070 ext_phy_type,
4071 ext_phy_addr,
4072 MDIO_AN_DEVAD,
4073 MDIO_AN_REG_CL37_AN, 0x1000);
4074
4075 if (ext_phy_type ==
4076 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
4077 /* The SNR will improve about 2db by changing
4078 BW and FEE main tap. Rest commands are executed
4079 after link is up*/
4080 /*Change FFE main cursor to 5 in EDC register*/
4081 if (bnx2x_8073_is_snr_needed(params))
4082 bnx2x_cl45_write(bp, params->port,
4083 ext_phy_type,
4084 ext_phy_addr,
4085 MDIO_PMA_DEVAD,
4086 MDIO_PMA_REG_EDC_FFE_MAIN,
4087 0xFB0C);
4088
4089 /* Enable FEC (Forware Error Correction)
4090 Request in the AN */
4091 bnx2x_cl45_read(bp, params->port,
4092 ext_phy_type,
4093 ext_phy_addr,
4094 MDIO_AN_DEVAD,
4095 MDIO_AN_REG_ADV2, &tmp1);
4096
4097 tmp1 |= (1<<15);
4098
4099 bnx2x_cl45_write(bp, params->port,
4100 ext_phy_type,
4101 ext_phy_addr,
4102 MDIO_AN_DEVAD,
4103 MDIO_AN_REG_ADV2, tmp1);
4104
4105 }
4106
4107 bnx2x_ext_phy_set_pause(params, vars);
4108
4109 /* Restart autoneg */
4110 msleep(500);
4111 bnx2x_cl45_write(bp, params->port,
4112 ext_phy_type,
4113 ext_phy_addr,
4114 MDIO_AN_DEVAD,
4115 MDIO_AN_REG_CTRL, 0x1200);
4116 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
4117 "Advertise 1G=%x, 10G=%x\n",
4118 ((val & (1<<5)) > 0),
4119 ((val & (1<<7)) > 0));
4120 break;
4121 }
4122
4123 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4124 {
4125 u16 tmp1;
4126 u16 rx_alarm_ctrl_val;
4127 u16 lasi_ctrl_val;
4128
4129 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
4130
4131 u16 mod_abs;
4132 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
4133 lasi_ctrl_val = 0x0004;
4134
4135 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
4136 /* enable LASI */
4137 bnx2x_cl45_write(bp, params->port,
4138 ext_phy_type,
4139 ext_phy_addr,
4140 MDIO_PMA_DEVAD,
4141 MDIO_PMA_REG_RX_ALARM_CTRL,
4142 rx_alarm_ctrl_val);
4143
4144 bnx2x_cl45_write(bp, params->port,
4145 ext_phy_type,
4146 ext_phy_addr,
4147 MDIO_PMA_DEVAD,
4148 MDIO_PMA_REG_LASI_CTRL,
4149 lasi_ctrl_val);
4150
4151 /* Initially configure MOD_ABS to interrupt when
4152 module is presence( bit 8) */
4153 bnx2x_cl45_read(bp, params->port,
4154 ext_phy_type,
4155 ext_phy_addr,
4156 MDIO_PMA_DEVAD,
4157 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4158 /* Set EDC off by setting OPTXLOS signal input to low
4159 (bit 9).
4160 When the EDC is off it locks onto a reference clock and
4161 avoids becoming 'lost'.*/
4162 mod_abs &= ~((1<<8) | (1<<9));
4163 bnx2x_cl45_write(bp, params->port,
4164 ext_phy_type,
4165 ext_phy_addr,
4166 MDIO_PMA_DEVAD,
4167 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4168
4169 /* Make MOD_ABS give interrupt on change */
4170 bnx2x_cl45_read(bp, params->port,
4171 ext_phy_type,
4172 ext_phy_addr,
4173 MDIO_PMA_DEVAD,
4174 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4175 &val);
4176 val |= (1<<12);
4177 bnx2x_cl45_write(bp, params->port,
4178 ext_phy_type,
4179 ext_phy_addr,
4180 MDIO_PMA_DEVAD,
4181 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4182 val);
4183
4184 /* Set 8727 GPIOs to input to allow reading from the
4185 8727 GPIO0 status which reflect SFP+ module
4186 over-current */
4187
4188 bnx2x_cl45_read(bp, params->port,
4189 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4190 ext_phy_addr,
4191 MDIO_PMA_DEVAD,
4192 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4193 &val);
4194 val &= 0xff8f; /* Reset bits 4-6 */
4195 bnx2x_cl45_write(bp, params->port,
4196 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4197 ext_phy_addr,
4198 MDIO_PMA_DEVAD,
4199 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4200 val);
4201
4202 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
4203 bnx2x_bcm8073_set_xaui_low_power_mode(params);
4204
4205 bnx2x_cl45_read(bp, params->port,
4206 ext_phy_type,
4207 ext_phy_addr,
4208 MDIO_PMA_DEVAD,
4209 MDIO_PMA_REG_M8051_MSGOUT_REG,
4210 &tmp1);
4211
4212 bnx2x_cl45_read(bp, params->port,
4213 ext_phy_type,
4214 ext_phy_addr,
4215 MDIO_PMA_DEVAD,
4216 MDIO_PMA_REG_RX_ALARM, &tmp1);
4217
4218 /* Set option 1G speed */
4219 if (params->req_line_speed == SPEED_1000) {
4220
4221 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4222 bnx2x_cl45_write(bp, params->port,
4223 ext_phy_type,
4224 ext_phy_addr,
4225 MDIO_PMA_DEVAD,
4226 MDIO_PMA_REG_CTRL, 0x40);
4227 bnx2x_cl45_write(bp, params->port,
4228 ext_phy_type,
4229 ext_phy_addr,
4230 MDIO_PMA_DEVAD,
4231 MDIO_PMA_REG_10G_CTRL2, 0xD);
4232 bnx2x_cl45_read(bp, params->port,
4233 ext_phy_type,
4234 ext_phy_addr,
4235 MDIO_PMA_DEVAD,
4236 MDIO_PMA_REG_10G_CTRL2, &tmp1);
4237 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
4238
4239 } else if ((params->req_line_speed ==
4240 SPEED_AUTO_NEG) &&
4241 ((params->speed_cap_mask &
4242 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
4243 ((params->speed_cap_mask &
4244 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
4245 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4246 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
4247 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4248 ext_phy_addr, MDIO_AN_DEVAD,
4249 MDIO_PMA_REG_8727_MISC_CTRL, 0);
4250 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4251 ext_phy_addr, MDIO_AN_DEVAD,
4252 MDIO_AN_REG_CL37_AN, 0x1300);
4253 } else {
4254 /* Since the 8727 has only single reset pin,
4255 need to set the 10G registers although it is
4256 default */
4257 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4258 ext_phy_addr, MDIO_AN_DEVAD,
4259 MDIO_AN_REG_8727_MISC_CTRL,
4260 0x0020);
4261 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4262 ext_phy_addr, MDIO_AN_DEVAD,
4263 MDIO_AN_REG_CL37_AN, 0x0100);
4264 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4265 ext_phy_addr, MDIO_PMA_DEVAD,
4266 MDIO_PMA_REG_CTRL, 0x2040);
4267 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4268 ext_phy_addr, MDIO_PMA_DEVAD,
4269 MDIO_PMA_REG_10G_CTRL2, 0x0008);
4270 }
4271
4272 /* Set 2-wire transfer rate of SFP+ module EEPROM
4273 * to 100Khz since some DACs(direct attached cables) do
4274 * not work at 400Khz.
4275 */
4276 bnx2x_cl45_write(bp, params->port,
4277 ext_phy_type,
4278 ext_phy_addr,
4279 MDIO_PMA_DEVAD,
4280 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
4281 0xa001);
4282
4283 /* Set TX PreEmphasis if needed */
4284 if ((params->feature_config_flags &
4285 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4286 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
4287 "TX_CTRL2 0x%x\n",
4288 params->xgxs_config_tx[0],
4289 params->xgxs_config_tx[1]);
4290 bnx2x_cl45_write(bp, params->port,
4291 ext_phy_type,
4292 ext_phy_addr,
4293 MDIO_PMA_DEVAD,
4294 MDIO_PMA_REG_8727_TX_CTRL1,
4295 params->xgxs_config_tx[0]);
4296
4297 bnx2x_cl45_write(bp, params->port,
4298 ext_phy_type,
4299 ext_phy_addr,
4300 MDIO_PMA_DEVAD,
4301 MDIO_PMA_REG_8727_TX_CTRL2,
4302 params->xgxs_config_tx[1]);
4303 }
4304
4305 break;
4306 }
4307
4308 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4309 {
4310 u16 fw_ver1, fw_ver2;
4311 DP(NETIF_MSG_LINK,
4312 "Setting the SFX7101 LASI indication\n");
4313
4314 bnx2x_cl45_write(bp, params->port,
4315 ext_phy_type,
4316 ext_phy_addr,
4317 MDIO_PMA_DEVAD,
4318 MDIO_PMA_REG_LASI_CTRL, 0x1);
4319 DP(NETIF_MSG_LINK,
4320 "Setting the SFX7101 LED to blink on traffic\n");
4321 bnx2x_cl45_write(bp, params->port,
4322 ext_phy_type,
4323 ext_phy_addr,
4324 MDIO_PMA_DEVAD,
4325 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
4326
4327 bnx2x_ext_phy_set_pause(params, vars);
4328 /* Restart autoneg */
4329 bnx2x_cl45_read(bp, params->port,
4330 ext_phy_type,
4331 ext_phy_addr,
4332 MDIO_AN_DEVAD,
4333 MDIO_AN_REG_CTRL, &val);
4334 val |= 0x200;
4335 bnx2x_cl45_write(bp, params->port,
4336 ext_phy_type,
4337 ext_phy_addr,
4338 MDIO_AN_DEVAD,
4339 MDIO_AN_REG_CTRL, val);
4340
4341 /* Save spirom version */
4342 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4343 ext_phy_addr, MDIO_PMA_DEVAD,
4344 MDIO_PMA_REG_7101_VER1, &fw_ver1);
4345
4346 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4347 ext_phy_addr, MDIO_PMA_DEVAD,
4348 MDIO_PMA_REG_7101_VER2, &fw_ver2);
4349
4350 bnx2x_save_spirom_version(params->bp, params->port,
4351 params->shmem_base,
4352 (u32)(fw_ver1<<16 | fw_ver2));
4353 break;
4354 }
4355 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
4356 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
4357 /* This phy uses the NIG latch mechanism since link
4358 indication arrives through its LED4 and not via
4359 its LASI signal, so we get steady signal
4360 instead of clear on read */
4361 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4362 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4363
4364 bnx2x_cl45_write(bp, params->port,
4365 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
4366 ext_phy_addr,
4367 MDIO_PMA_DEVAD,
4368 MDIO_PMA_REG_CTRL, 0x0000);
4369
4370 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4371 if (params->req_line_speed == SPEED_AUTO_NEG) {
4372
4373 u16 autoneg_val, an_1000_val, an_10_100_val;
4374 /* set 1000 speed advertisement */
4375 bnx2x_cl45_read(bp, params->port,
4376 ext_phy_type,
4377 ext_phy_addr,
4378 MDIO_AN_DEVAD,
4379 MDIO_AN_REG_8481_1000T_CTRL,
4380 &an_1000_val);
4381
4382 if (params->speed_cap_mask &
4383 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
4384 an_1000_val |= (1<<8);
4385 if (params->req_duplex == DUPLEX_FULL)
4386 an_1000_val |= (1<<9);
4387 DP(NETIF_MSG_LINK, "Advertising 1G\n");
4388 } else
4389 an_1000_val &= ~((1<<8) | (1<<9));
4390
4391 bnx2x_cl45_write(bp, params->port,
4392 ext_phy_type,
4393 ext_phy_addr,
4394 MDIO_AN_DEVAD,
4395 MDIO_AN_REG_8481_1000T_CTRL,
4396 an_1000_val);
4397
4398 /* set 100 speed advertisement */
4399 bnx2x_cl45_read(bp, params->port,
4400 ext_phy_type,
4401 ext_phy_addr,
4402 MDIO_AN_DEVAD,
4403 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4404 &an_10_100_val);
4405
4406 if (params->speed_cap_mask &
4407 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
4408 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
4409 an_10_100_val |= (1<<7);
4410 if (params->req_duplex == DUPLEX_FULL)
4411 an_10_100_val |= (1<<8);
4412 DP(NETIF_MSG_LINK,
4413 "Advertising 100M\n");
4414 } else
4415 an_10_100_val &= ~((1<<7) | (1<<8));
4416
4417 /* set 10 speed advertisement */
4418 if (params->speed_cap_mask &
4419 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
4420 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
4421 an_10_100_val |= (1<<5);
4422 if (params->req_duplex == DUPLEX_FULL)
4423 an_10_100_val |= (1<<6);
4424 DP(NETIF_MSG_LINK, "Advertising 10M\n");
4425 }
4426 else
4427 an_10_100_val &= ~((1<<5) | (1<<6));
4428
4429 bnx2x_cl45_write(bp, params->port,
4430 ext_phy_type,
4431 ext_phy_addr,
4432 MDIO_AN_DEVAD,
4433 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4434 an_10_100_val);
4435
4436 bnx2x_cl45_read(bp, params->port,
4437 ext_phy_type,
4438 ext_phy_addr,
4439 MDIO_AN_DEVAD,
4440 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4441 &autoneg_val);
4442
4443 /* Disable forced speed */
4444 autoneg_val &= ~(1<<6|1<<13);
4445
4446 /* Enable autoneg and restart autoneg
4447 for legacy speeds */
4448 autoneg_val |= (1<<9|1<<12);
4449
4450 if (params->req_duplex == DUPLEX_FULL)
4451 autoneg_val |= (1<<8);
4452 else
4453 autoneg_val &= ~(1<<8);
4454
4455 bnx2x_cl45_write(bp, params->port,
4456 ext_phy_type,
4457 ext_phy_addr,
4458 MDIO_AN_DEVAD,
4459 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4460 autoneg_val);
4461
4462 if (params->speed_cap_mask &
4463 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
4464 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4465 /* Restart autoneg for 10G*/
4466
4467 bnx2x_cl45_write(bp, params->port,
4468 ext_phy_type,
4469 ext_phy_addr,
4470 MDIO_AN_DEVAD,
4471 MDIO_AN_REG_CTRL, 0x3200);
4472 }
4473 } else {
4474 /* Force speed */
4475 u16 autoneg_ctrl, pma_ctrl;
4476 bnx2x_cl45_read(bp, params->port,
4477 ext_phy_type,
4478 ext_phy_addr,
4479 MDIO_AN_DEVAD,
4480 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4481 &autoneg_ctrl);
4482
4483 /* Disable autoneg */
4484 autoneg_ctrl &= ~(1<<12);
4485
4486 /* Set 1000 force */
4487 switch (params->req_line_speed) {
4488 case SPEED_10000:
4489 DP(NETIF_MSG_LINK,
4490 "Unable to set 10G force !\n");
4491 break;
4492 case SPEED_1000:
4493 bnx2x_cl45_read(bp, params->port,
4494 ext_phy_type,
4495 ext_phy_addr,
4496 MDIO_PMA_DEVAD,
4497 MDIO_PMA_REG_CTRL,
4498 &pma_ctrl);
4499 autoneg_ctrl &= ~(1<<13);
4500 autoneg_ctrl |= (1<<6);
4501 pma_ctrl &= ~(1<<13);
4502 pma_ctrl |= (1<<6);
4503 DP(NETIF_MSG_LINK,
4504 "Setting 1000M force\n");
4505 bnx2x_cl45_write(bp, params->port,
4506 ext_phy_type,
4507 ext_phy_addr,
4508 MDIO_PMA_DEVAD,
4509 MDIO_PMA_REG_CTRL,
4510 pma_ctrl);
4511 break;
4512 case SPEED_100:
4513 autoneg_ctrl |= (1<<13);
4514 autoneg_ctrl &= ~(1<<6);
4515 DP(NETIF_MSG_LINK,
4516 "Setting 100M force\n");
4517 break;
4518 case SPEED_10:
4519 autoneg_ctrl &= ~(1<<13);
4520 autoneg_ctrl &= ~(1<<6);
4521 DP(NETIF_MSG_LINK,
4522 "Setting 10M force\n");
4523 break;
4524 }
4525
4526 /* Duplex mode */
4527 if (params->req_duplex == DUPLEX_FULL) {
4528 autoneg_ctrl |= (1<<8);
4529 DP(NETIF_MSG_LINK,
4530 "Setting full duplex\n");
4531 } else
4532 autoneg_ctrl &= ~(1<<8);
4533
4534 /* Update autoneg ctrl and pma ctrl */
4535 bnx2x_cl45_write(bp, params->port,
4536 ext_phy_type,
4537 ext_phy_addr,
4538 MDIO_AN_DEVAD,
4539 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4540 autoneg_ctrl);
4541 }
4542
4543 /* Save spirom version */
4544 bnx2x_save_8481_spirom_version(bp, params->port,
4545 ext_phy_addr,
4546 params->shmem_base);
4547 break;
4548 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4549 DP(NETIF_MSG_LINK,
4550 "XGXS PHY Failure detected 0x%x\n",
4551 params->ext_phy_config);
4552 rc = -EINVAL;
4553 break;
4554 default:
4555 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
4556 params->ext_phy_config);
4557 rc = -EINVAL;
4558 break;
4559 }
4560
4561 } else { /* SerDes */
4562
4563 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
4564 switch (ext_phy_type) {
4565 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
4566 DP(NETIF_MSG_LINK, "SerDes Direct\n");
4567 break;
4568
4569 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
4570 DP(NETIF_MSG_LINK, "SerDes 5482\n");
4571 break;
4572
4573 default:
4574 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
4575 params->ext_phy_config);
4576 break;
4577 }
4578 }
4579 return rc;
4580 }
4581
4582 static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4583 {
4584 struct bnx2x *bp = params->bp;
4585 u16 mod_abs, rx_alarm_status;
4586 u8 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
4587 u32 val = REG_RD(bp, params->shmem_base +
4588 offsetof(struct shmem_region, dev_info.
4589 port_feature_config[params->port].
4590 config));
4591 bnx2x_cl45_read(bp, params->port,
4592 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4593 ext_phy_addr,
4594 MDIO_PMA_DEVAD,
4595 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4596 if (mod_abs & (1<<8)) {
4597
4598 /* Module is absent */
4599 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4600 "show module is absent\n");
4601
4602 /* 1. Set mod_abs to detect next module
4603 presence event
4604 2. Set EDC off by setting OPTXLOS signal input to low
4605 (bit 9).
4606 When the EDC is off it locks onto a reference clock and
4607 avoids becoming 'lost'.*/
4608 mod_abs &= ~((1<<8)|(1<<9));
4609 bnx2x_cl45_write(bp, params->port,
4610 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4611 ext_phy_addr,
4612 MDIO_PMA_DEVAD,
4613 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4614
4615 /* Clear RX alarm since it stays up as long as
4616 the mod_abs wasn't changed */
4617 bnx2x_cl45_read(bp, params->port,
4618 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4619 ext_phy_addr,
4620 MDIO_PMA_DEVAD,
4621 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4622
4623 } else {
4624 /* Module is present */
4625 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4626 "show module is present\n");
4627 /* First thing, disable transmitter,
4628 and if the module is ok, the
4629 module_detection will enable it*/
4630
4631 /* 1. Set mod_abs to detect next module
4632 absent event ( bit 8)
4633 2. Restore the default polarity of the OPRXLOS signal and
4634 this signal will then correctly indicate the presence or
4635 absence of the Rx signal. (bit 9) */
4636 mod_abs |= ((1<<8)|(1<<9));
4637 bnx2x_cl45_write(bp, params->port,
4638 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4639 ext_phy_addr,
4640 MDIO_PMA_DEVAD,
4641 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4642
4643 /* Clear RX alarm since it stays up as long as
4644 the mod_abs wasn't changed. This is need to be done
4645 before calling the module detection, otherwise it will clear
4646 the link update alarm */
4647 bnx2x_cl45_read(bp, params->port,
4648 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4649 ext_phy_addr,
4650 MDIO_PMA_DEVAD,
4651 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4652
4653
4654 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4655 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4656 bnx2x_sfp_set_transmitter(bp, params->port,
4657 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4658 ext_phy_addr, 0);
4659
4660 if (bnx2x_wait_for_sfp_module_initialized(params)
4661 == 0)
4662 bnx2x_sfp_module_detection(params);
4663 else
4664 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4665 }
4666
4667 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4668 rx_alarm_status);
4669 /* No need to check link status in case of
4670 module plugged in/out */
4671 }
4672
4673
4674 static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4675 struct link_vars *vars,
4676 u8 is_mi_int)
4677 {
4678 struct bnx2x *bp = params->bp;
4679 u32 ext_phy_type;
4680 u8 ext_phy_addr;
4681 u16 val1 = 0, val2;
4682 u16 rx_sd, pcs_status;
4683 u8 ext_phy_link_up = 0;
4684 u8 port = params->port;
4685
4686 if (vars->phy_flags & PHY_XGXS_FLAG) {
4687 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
4688 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4689 switch (ext_phy_type) {
4690 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4691 DP(NETIF_MSG_LINK, "XGXS Direct\n");
4692 ext_phy_link_up = 1;
4693 break;
4694
4695 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4696 DP(NETIF_MSG_LINK, "XGXS 8705\n");
4697 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4698 ext_phy_addr,
4699 MDIO_WIS_DEVAD,
4700 MDIO_WIS_REG_LASI_STATUS, &val1);
4701 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4702
4703 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4704 ext_phy_addr,
4705 MDIO_WIS_DEVAD,
4706 MDIO_WIS_REG_LASI_STATUS, &val1);
4707 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4708
4709 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4710 ext_phy_addr,
4711 MDIO_PMA_DEVAD,
4712 MDIO_PMA_REG_RX_SD, &rx_sd);
4713
4714 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4715 ext_phy_addr,
4716 1,
4717 0xc809, &val1);
4718 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4719 ext_phy_addr,
4720 1,
4721 0xc809, &val1);
4722
4723 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4724 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) &&
4725 ((val1 & (1<<8)) == 0));
4726 if (ext_phy_link_up)
4727 vars->line_speed = SPEED_10000;
4728 break;
4729
4730 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
4731 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4732 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4733 /* Clear RX Alarm*/
4734 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4735 ext_phy_addr,
4736 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4737 &val2);
4738 /* clear LASI indication*/
4739 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4740 ext_phy_addr,
4741 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4742 &val1);
4743 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4744 ext_phy_addr,
4745 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4746 &val2);
4747 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
4748 "0x%x\n", val1, val2);
4749
4750 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4751 ext_phy_addr,
4752 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
4753 &rx_sd);
4754 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4755 ext_phy_addr,
4756 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
4757 &pcs_status);
4758 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4759 ext_phy_addr,
4760 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4761 &val2);
4762 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4763 ext_phy_addr,
4764 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4765 &val2);
4766
4767 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x"
4768 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
4769 rx_sd, pcs_status, val2);
4770 /* link is up if both bit 0 of pmd_rx_sd and
4771 * bit 0 of pcs_status are set, or if the autoneg bit
4772 1 is set
4773 */
4774 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
4775 (val2 & (1<<1)));
4776 if (ext_phy_link_up) {
4777 if (ext_phy_type ==
4778 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
4779 /* If transmitter is disabled,
4780 ignore false link up indication */
4781 bnx2x_cl45_read(bp, params->port,
4782 ext_phy_type,
4783 ext_phy_addr,
4784 MDIO_PMA_DEVAD,
4785 MDIO_PMA_REG_PHY_IDENTIFIER,
4786 &val1);
4787 if (val1 & (1<<15)) {
4788 DP(NETIF_MSG_LINK, "Tx is "
4789 "disabled\n");
4790 ext_phy_link_up = 0;
4791 break;
4792 }
4793 }
4794 if (val2 & (1<<1))
4795 vars->line_speed = SPEED_1000;
4796 else
4797 vars->line_speed = SPEED_10000;
4798 }
4799 break;
4800
4801 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4802 {
4803 u16 link_status = 0;
4804 u16 rx_alarm_status;
4805 /* Check the LASI */
4806 bnx2x_cl45_read(bp, params->port,
4807 ext_phy_type,
4808 ext_phy_addr,
4809 MDIO_PMA_DEVAD,
4810 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4811
4812 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4813 rx_alarm_status);
4814
4815 bnx2x_cl45_read(bp, params->port,
4816 ext_phy_type,
4817 ext_phy_addr,
4818 MDIO_PMA_DEVAD,
4819 MDIO_PMA_REG_LASI_STATUS, &val1);
4820
4821 DP(NETIF_MSG_LINK,
4822 "8727 LASI status 0x%x\n",
4823 val1);
4824
4825 /* Clear MSG-OUT */
4826 bnx2x_cl45_read(bp, params->port,
4827 ext_phy_type,
4828 ext_phy_addr,
4829 MDIO_PMA_DEVAD,
4830 MDIO_PMA_REG_M8051_MSGOUT_REG,
4831 &val1);
4832
4833 /*
4834 * If a module is present and there is need to check
4835 * for over current
4836 */
4837 if (!(params->feature_config_flags &
4838 FEATURE_CONFIG_BCM8727_NOC) &&
4839 !(rx_alarm_status & (1<<5))) {
4840 /* Check over-current using 8727 GPIO0 input*/
4841 bnx2x_cl45_read(bp, params->port,
4842 ext_phy_type,
4843 ext_phy_addr,
4844 MDIO_PMA_DEVAD,
4845 MDIO_PMA_REG_8727_GPIO_CTRL,
4846 &val1);
4847
4848 if ((val1 & (1<<8)) == 0) {
4849 DP(NETIF_MSG_LINK, "8727 Power fault"
4850 " has been detected on "
4851 "port %d\n",
4852 params->port);
4853 netdev_err(bp->dev, "Error: Power fault on Port %d has been detected and the power to that SFP+ module has been removed to prevent failure of the card. Please remove the SFP+ module and restart the system to clear this error.\n",
4854 params->port);
4855 /*
4856 * Disable all RX_ALARMs except for
4857 * mod_abs
4858 */
4859 bnx2x_cl45_write(bp, params->port,
4860 ext_phy_type,
4861 ext_phy_addr,
4862 MDIO_PMA_DEVAD,
4863 MDIO_PMA_REG_RX_ALARM_CTRL,
4864 (1<<5));
4865
4866 bnx2x_cl45_read(bp, params->port,
4867 ext_phy_type,
4868 ext_phy_addr,
4869 MDIO_PMA_DEVAD,
4870 MDIO_PMA_REG_PHY_IDENTIFIER,
4871 &val1);
4872 /* Wait for module_absent_event */
4873 val1 |= (1<<8);
4874 bnx2x_cl45_write(bp, params->port,
4875 ext_phy_type,
4876 ext_phy_addr,
4877 MDIO_PMA_DEVAD,
4878 MDIO_PMA_REG_PHY_IDENTIFIER,
4879 val1);
4880 /* Clear RX alarm */
4881 bnx2x_cl45_read(bp, params->port,
4882 ext_phy_type,
4883 ext_phy_addr,
4884 MDIO_PMA_DEVAD,
4885 MDIO_PMA_REG_RX_ALARM,
4886 &rx_alarm_status);
4887 break;
4888 }
4889 } /* Over current check */
4890
4891 /* When module absent bit is set, check module */
4892 if (rx_alarm_status & (1<<5)) {
4893 bnx2x_8727_handle_mod_abs(params);
4894 /* Enable all mod_abs and link detection bits */
4895 bnx2x_cl45_write(bp, params->port,
4896 ext_phy_type,
4897 ext_phy_addr,
4898 MDIO_PMA_DEVAD,
4899 MDIO_PMA_REG_RX_ALARM_CTRL,
4900 ((1<<5) | (1<<2)));
4901 }
4902
4903 /* If transmitter is disabled,
4904 ignore false link up indication */
4905 bnx2x_cl45_read(bp, params->port,
4906 ext_phy_type,
4907 ext_phy_addr,
4908 MDIO_PMA_DEVAD,
4909 MDIO_PMA_REG_PHY_IDENTIFIER,
4910 &val1);
4911 if (val1 & (1<<15)) {
4912 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4913 ext_phy_link_up = 0;
4914 break;
4915 }
4916
4917 bnx2x_cl45_read(bp, params->port,
4918 ext_phy_type,
4919 ext_phy_addr,
4920 MDIO_PMA_DEVAD,
4921 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4922 &link_status);
4923
4924 /* Bits 0..2 --> speed detected,
4925 bits 13..15--> link is down */
4926 if ((link_status & (1<<2)) &&
4927 (!(link_status & (1<<15)))) {
4928 ext_phy_link_up = 1;
4929 vars->line_speed = SPEED_10000;
4930 } else if ((link_status & (1<<0)) &&
4931 (!(link_status & (1<<13)))) {
4932 ext_phy_link_up = 1;
4933 vars->line_speed = SPEED_1000;
4934 DP(NETIF_MSG_LINK,
4935 "port %x: External link"
4936 " up in 1G\n", params->port);
4937 } else {
4938 ext_phy_link_up = 0;
4939 DP(NETIF_MSG_LINK,
4940 "port %x: External link"
4941 " is down\n", params->port);
4942 }
4943 break;
4944 }
4945
4946 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4947 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4948 {
4949 u16 link_status = 0;
4950 u16 an1000_status = 0;
4951
4952 if (ext_phy_type ==
4953 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
4954 bnx2x_cl45_read(bp, params->port,
4955 ext_phy_type,
4956 ext_phy_addr,
4957 MDIO_PCS_DEVAD,
4958 MDIO_PCS_REG_LASI_STATUS, &val1);
4959 bnx2x_cl45_read(bp, params->port,
4960 ext_phy_type,
4961 ext_phy_addr,
4962 MDIO_PCS_DEVAD,
4963 MDIO_PCS_REG_LASI_STATUS, &val2);
4964 DP(NETIF_MSG_LINK,
4965 "870x LASI status 0x%x->0x%x\n",
4966 val1, val2);
4967 } else {
4968 /* In 8073, port1 is directed through emac0 and
4969 * port0 is directed through emac1
4970 */
4971 bnx2x_cl45_read(bp, params->port,
4972 ext_phy_type,
4973 ext_phy_addr,
4974 MDIO_PMA_DEVAD,
4975 MDIO_PMA_REG_LASI_STATUS, &val1);
4976
4977 DP(NETIF_MSG_LINK,
4978 "8703 LASI status 0x%x\n",
4979 val1);
4980 }
4981
4982 /* clear the interrupt LASI status register */
4983 bnx2x_cl45_read(bp, params->port,
4984 ext_phy_type,
4985 ext_phy_addr,
4986 MDIO_PCS_DEVAD,
4987 MDIO_PCS_REG_STATUS, &val2);
4988 bnx2x_cl45_read(bp, params->port,
4989 ext_phy_type,
4990 ext_phy_addr,
4991 MDIO_PCS_DEVAD,
4992 MDIO_PCS_REG_STATUS, &val1);
4993 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
4994 val2, val1);
4995 /* Clear MSG-OUT */
4996 bnx2x_cl45_read(bp, params->port,
4997 ext_phy_type,
4998 ext_phy_addr,
4999 MDIO_PMA_DEVAD,
5000 MDIO_PMA_REG_M8051_MSGOUT_REG,
5001 &val1);
5002
5003 /* Check the LASI */
5004 bnx2x_cl45_read(bp, params->port,
5005 ext_phy_type,
5006 ext_phy_addr,
5007 MDIO_PMA_DEVAD,
5008 MDIO_PMA_REG_RX_ALARM, &val2);
5009
5010 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
5011
5012 /* Check the link status */
5013 bnx2x_cl45_read(bp, params->port,
5014 ext_phy_type,
5015 ext_phy_addr,
5016 MDIO_PCS_DEVAD,
5017 MDIO_PCS_REG_STATUS, &val2);
5018 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
5019
5020 bnx2x_cl45_read(bp, params->port,
5021 ext_phy_type,
5022 ext_phy_addr,
5023 MDIO_PMA_DEVAD,
5024 MDIO_PMA_REG_STATUS, &val2);
5025 bnx2x_cl45_read(bp, params->port,
5026 ext_phy_type,
5027 ext_phy_addr,
5028 MDIO_PMA_DEVAD,
5029 MDIO_PMA_REG_STATUS, &val1);
5030 ext_phy_link_up = ((val1 & 4) == 4);
5031 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
5032 if (ext_phy_type ==
5033 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
5034
5035 if (ext_phy_link_up &&
5036 ((params->req_line_speed !=
5037 SPEED_10000))) {
5038 if (bnx2x_bcm8073_xaui_wa(params)
5039 != 0) {
5040 ext_phy_link_up = 0;
5041 break;
5042 }
5043 }
5044 bnx2x_cl45_read(bp, params->port,
5045 ext_phy_type,
5046 ext_phy_addr,
5047 MDIO_AN_DEVAD,
5048 MDIO_AN_REG_LINK_STATUS,
5049 &an1000_status);
5050 bnx2x_cl45_read(bp, params->port,
5051 ext_phy_type,
5052 ext_phy_addr,
5053 MDIO_AN_DEVAD,
5054 MDIO_AN_REG_LINK_STATUS,
5055 &an1000_status);
5056
5057 /* Check the link status on 1.1.2 */
5058 bnx2x_cl45_read(bp, params->port,
5059 ext_phy_type,
5060 ext_phy_addr,
5061 MDIO_PMA_DEVAD,
5062 MDIO_PMA_REG_STATUS, &val2);
5063 bnx2x_cl45_read(bp, params->port,
5064 ext_phy_type,
5065 ext_phy_addr,
5066 MDIO_PMA_DEVAD,
5067 MDIO_PMA_REG_STATUS, &val1);
5068 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
5069 "an_link_status=0x%x\n",
5070 val2, val1, an1000_status);
5071
5072 ext_phy_link_up = (((val1 & 4) == 4) ||
5073 (an1000_status & (1<<1)));
5074 if (ext_phy_link_up &&
5075 bnx2x_8073_is_snr_needed(params)) {
5076 /* The SNR will improve about 2dbby
5077 changing the BW and FEE main tap.*/
5078
5079 /* The 1st write to change FFE main
5080 tap is set before restart AN */
5081 /* Change PLL Bandwidth in EDC
5082 register */
5083 bnx2x_cl45_write(bp, port, ext_phy_type,
5084 ext_phy_addr,
5085 MDIO_PMA_DEVAD,
5086 MDIO_PMA_REG_PLL_BANDWIDTH,
5087 0x26BC);
5088
5089 /* Change CDR Bandwidth in EDC
5090 register */
5091 bnx2x_cl45_write(bp, port, ext_phy_type,
5092 ext_phy_addr,
5093 MDIO_PMA_DEVAD,
5094 MDIO_PMA_REG_CDR_BANDWIDTH,
5095 0x0333);
5096 }
5097 bnx2x_cl45_read(bp, params->port,
5098 ext_phy_type,
5099 ext_phy_addr,
5100 MDIO_PMA_DEVAD,
5101 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
5102 &link_status);
5103
5104 /* Bits 0..2 --> speed detected,
5105 bits 13..15--> link is down */
5106 if ((link_status & (1<<2)) &&
5107 (!(link_status & (1<<15)))) {
5108 ext_phy_link_up = 1;
5109 vars->line_speed = SPEED_10000;
5110 DP(NETIF_MSG_LINK,
5111 "port %x: External link"
5112 " up in 10G\n", params->port);
5113 } else if ((link_status & (1<<1)) &&
5114 (!(link_status & (1<<14)))) {
5115 ext_phy_link_up = 1;
5116 vars->line_speed = SPEED_2500;
5117 DP(NETIF_MSG_LINK,
5118 "port %x: External link"
5119 " up in 2.5G\n", params->port);
5120 } else if ((link_status & (1<<0)) &&
5121 (!(link_status & (1<<13)))) {
5122 ext_phy_link_up = 1;
5123 vars->line_speed = SPEED_1000;
5124 DP(NETIF_MSG_LINK,
5125 "port %x: External link"
5126 " up in 1G\n", params->port);
5127 } else {
5128 ext_phy_link_up = 0;
5129 DP(NETIF_MSG_LINK,
5130 "port %x: External link"
5131 " is down\n", params->port);
5132 }
5133 } else {
5134 /* See if 1G link is up for the 8072 */
5135 bnx2x_cl45_read(bp, params->port,
5136 ext_phy_type,
5137 ext_phy_addr,
5138 MDIO_AN_DEVAD,
5139 MDIO_AN_REG_LINK_STATUS,
5140 &an1000_status);
5141 bnx2x_cl45_read(bp, params->port,
5142 ext_phy_type,
5143 ext_phy_addr,
5144 MDIO_AN_DEVAD,
5145 MDIO_AN_REG_LINK_STATUS,
5146 &an1000_status);
5147 if (an1000_status & (1<<1)) {
5148 ext_phy_link_up = 1;
5149 vars->line_speed = SPEED_1000;
5150 DP(NETIF_MSG_LINK,
5151 "port %x: External link"
5152 " up in 1G\n", params->port);
5153 } else if (ext_phy_link_up) {
5154 ext_phy_link_up = 1;
5155 vars->line_speed = SPEED_10000;
5156 DP(NETIF_MSG_LINK,
5157 "port %x: External link"
5158 " up in 10G\n", params->port);
5159 }
5160 }
5161
5162
5163 break;
5164 }
5165 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5166 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5167 ext_phy_addr,
5168 MDIO_PMA_DEVAD,
5169 MDIO_PMA_REG_LASI_STATUS, &val2);
5170 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5171 ext_phy_addr,
5172 MDIO_PMA_DEVAD,
5173 MDIO_PMA_REG_LASI_STATUS, &val1);
5174 DP(NETIF_MSG_LINK,
5175 "10G-base-T LASI status 0x%x->0x%x\n",
5176 val2, val1);
5177 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5178 ext_phy_addr,
5179 MDIO_PMA_DEVAD,
5180 MDIO_PMA_REG_STATUS, &val2);
5181 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5182 ext_phy_addr,
5183 MDIO_PMA_DEVAD,
5184 MDIO_PMA_REG_STATUS, &val1);
5185 DP(NETIF_MSG_LINK,
5186 "10G-base-T PMA status 0x%x->0x%x\n",
5187 val2, val1);
5188 ext_phy_link_up = ((val1 & 4) == 4);
5189 /* if link is up
5190 * print the AN outcome of the SFX7101 PHY
5191 */
5192 if (ext_phy_link_up) {
5193 bnx2x_cl45_read(bp, params->port,
5194 ext_phy_type,
5195 ext_phy_addr,
5196 MDIO_AN_DEVAD,
5197 MDIO_AN_REG_MASTER_STATUS,
5198 &val2);
5199 vars->line_speed = SPEED_10000;
5200 DP(NETIF_MSG_LINK,
5201 "SFX7101 AN status 0x%x->Master=%x\n",
5202 val2,
5203 (val2 & (1<<14)));
5204 }
5205 break;
5206 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5207 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5208 /* Check 10G-BaseT link status */
5209 /* Check PMD signal ok */
5210 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5211 ext_phy_addr,
5212 MDIO_AN_DEVAD,
5213 0xFFFA,
5214 &val1);
5215 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5216 ext_phy_addr,
5217 MDIO_PMA_DEVAD,
5218 MDIO_PMA_REG_8481_PMD_SIGNAL,
5219 &val2);
5220 DP(NETIF_MSG_LINK, "PMD_SIGNAL 1.a811 = 0x%x\n", val2);
5221
5222 /* Check link 10G */
5223 if (val2 & (1<<11)) {
5224 vars->line_speed = SPEED_10000;
5225 ext_phy_link_up = 1;
5226 bnx2x_8481_set_10G_led_mode(params,
5227 ext_phy_type,
5228 ext_phy_addr);
5229 } else { /* Check Legacy speed link */
5230 u16 legacy_status, legacy_speed;
5231
5232 /* Enable expansion register 0x42
5233 (Operation mode status) */
5234 bnx2x_cl45_write(bp, params->port,
5235 ext_phy_type,
5236 ext_phy_addr,
5237 MDIO_AN_DEVAD,
5238 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
5239 0xf42);
5240
5241 /* Get legacy speed operation status */
5242 bnx2x_cl45_read(bp, params->port,
5243 ext_phy_type,
5244 ext_phy_addr,
5245 MDIO_AN_DEVAD,
5246 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5247 &legacy_status);
5248
5249 DP(NETIF_MSG_LINK, "Legacy speed status"
5250 " = 0x%x\n", legacy_status);
5251 ext_phy_link_up = ((legacy_status & (1<<11))
5252 == (1<<11));
5253 if (ext_phy_link_up) {
5254 legacy_speed = (legacy_status & (3<<9));
5255 if (legacy_speed == (0<<9))
5256 vars->line_speed = SPEED_10;
5257 else if (legacy_speed == (1<<9))
5258 vars->line_speed =
5259 SPEED_100;
5260 else if (legacy_speed == (2<<9))
5261 vars->line_speed =
5262 SPEED_1000;
5263 else /* Should not happen */
5264 vars->line_speed = 0;
5265
5266 if (legacy_status & (1<<8))
5267 vars->duplex = DUPLEX_FULL;
5268 else
5269 vars->duplex = DUPLEX_HALF;
5270
5271 DP(NETIF_MSG_LINK, "Link is up "
5272 "in %dMbps, is_duplex_full"
5273 "= %d\n",
5274 vars->line_speed,
5275 (vars->duplex == DUPLEX_FULL));
5276 bnx2x_8481_set_legacy_led_mode(params,
5277 ext_phy_type,
5278 ext_phy_addr);
5279 }
5280 }
5281 break;
5282 default:
5283 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
5284 params->ext_phy_config);
5285 ext_phy_link_up = 0;
5286 break;
5287 }
5288 /* Set SGMII mode for external phy */
5289 if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5290 if (vars->line_speed < SPEED_1000)
5291 vars->phy_flags |= PHY_SGMII_FLAG;
5292 else
5293 vars->phy_flags &= ~PHY_SGMII_FLAG;
5294 }
5295
5296 } else { /* SerDes */
5297 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5298 switch (ext_phy_type) {
5299 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
5300 DP(NETIF_MSG_LINK, "SerDes Direct\n");
5301 ext_phy_link_up = 1;
5302 break;
5303
5304 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
5305 DP(NETIF_MSG_LINK, "SerDes 5482\n");
5306 ext_phy_link_up = 1;
5307 break;
5308
5309 default:
5310 DP(NETIF_MSG_LINK,
5311 "BAD SerDes ext_phy_config 0x%x\n",
5312 params->ext_phy_config);
5313 ext_phy_link_up = 0;
5314 break;
5315 }
5316 }
5317
5318 return ext_phy_link_up;
5319 }
5320
5321 static void bnx2x_link_int_enable(struct link_params *params)
5322 {
5323 u8 port = params->port;
5324 u32 ext_phy_type;
5325 u32 mask;
5326 struct bnx2x *bp = params->bp;
5327
5328 /* setting the status to report on link up
5329 for either XGXS or SerDes */
5330
5331 if (params->switch_cfg == SWITCH_CFG_10G) {
5332 mask = (NIG_MASK_XGXS0_LINK10G |
5333 NIG_MASK_XGXS0_LINK_STATUS);
5334 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5335 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5336 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5337 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
5338 (ext_phy_type !=
5339 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
5340 mask |= NIG_MASK_MI_INT;
5341 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5342 }
5343
5344 } else { /* SerDes */
5345 mask = NIG_MASK_SERDES0_LINK_STATUS;
5346 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5347 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5348 if ((ext_phy_type !=
5349 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
5350 (ext_phy_type !=
5351 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
5352 mask |= NIG_MASK_MI_INT;
5353 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5354 }
5355 }
5356 bnx2x_bits_en(bp,
5357 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5358 mask);
5359
5360 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5361 (params->switch_cfg == SWITCH_CFG_10G),
5362 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5363 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5364 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5365 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5366 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5367 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5368 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5369 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5370 }
5371
5372 static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
5373 u8 is_mi_int)
5374 {
5375 u32 latch_status = 0, is_mi_int_status;
5376 /* Disable the MI INT ( external phy int )
5377 * by writing 1 to the status register. Link down indication
5378 * is high-active-signal, so in this case we need to write the
5379 * status to clear the XOR
5380 */
5381 /* Read Latched signals */
5382 latch_status = REG_RD(bp,
5383 NIG_REG_LATCH_STATUS_0 + port*8);
5384 is_mi_int_status = REG_RD(bp,
5385 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
5386 DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
5387 "latch_status = 0x%x\n",
5388 is_mi_int, is_mi_int_status, latch_status);
5389 /* Handle only those with latched-signal=up.*/
5390 if (latch_status & 1) {
5391 /* For all latched-signal=up,Write original_signal to status */
5392 if (is_mi_int)
5393 bnx2x_bits_en(bp,
5394 NIG_REG_STATUS_INTERRUPT_PORT0
5395 + port*4,
5396 NIG_STATUS_EMAC0_MI_INT);
5397 else
5398 bnx2x_bits_dis(bp,
5399 NIG_REG_STATUS_INTERRUPT_PORT0
5400 + port*4,
5401 NIG_STATUS_EMAC0_MI_INT);
5402 /* For all latched-signal=up : Re-Arm Latch signals */
5403 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5404 (latch_status & 0xfffe) | (latch_status & 1));
5405 }
5406 }
5407 /*
5408 * link management
5409 */
5410 static void bnx2x_link_int_ack(struct link_params *params,
5411 struct link_vars *vars, u8 is_10g,
5412 u8 is_mi_int)
5413 {
5414 struct bnx2x *bp = params->bp;
5415 u8 port = params->port;
5416
5417 /* first reset all status
5418 * we assume only one line will be change at a time */
5419 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5420 (NIG_STATUS_XGXS0_LINK10G |
5421 NIG_STATUS_XGXS0_LINK_STATUS |
5422 NIG_STATUS_SERDES0_LINK_STATUS));
5423 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5424 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
5425 (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5426 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823)) {
5427 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5428 }
5429 if (vars->phy_link_up) {
5430 if (is_10g) {
5431 /* Disable the 10G link interrupt
5432 * by writing 1 to the status register
5433 */
5434 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
5435 bnx2x_bits_en(bp,
5436 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5437 NIG_STATUS_XGXS0_LINK10G);
5438
5439 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5440 /* Disable the link interrupt
5441 * by writing 1 to the relevant lane
5442 * in the status register
5443 */
5444 u32 ser_lane = ((params->lane_config &
5445 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5446 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5447
5448 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
5449 vars->line_speed);
5450 bnx2x_bits_en(bp,
5451 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5452 ((1 << ser_lane) <<
5453 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
5454
5455 } else { /* SerDes */
5456 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
5457 /* Disable the link interrupt
5458 * by writing 1 to the status register
5459 */
5460 bnx2x_bits_en(bp,
5461 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5462 NIG_STATUS_SERDES0_LINK_STATUS);
5463 }
5464
5465 } else { /* link_down */
5466 }
5467 }
5468
5469 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
5470 {
5471 u8 *str_ptr = str;
5472 u32 mask = 0xf0000000;
5473 u8 shift = 8*4;
5474 u8 digit;
5475 if (len < 10) {
5476 /* Need more than 10chars for this format */
5477 *str_ptr = '\0';
5478 return -EINVAL;
5479 }
5480 while (shift > 0) {
5481
5482 shift -= 4;
5483 digit = ((num & mask) >> shift);
5484 if (digit < 0xa)
5485 *str_ptr = digit + '0';
5486 else
5487 *str_ptr = digit - 0xa + 'a';
5488 str_ptr++;
5489 mask = mask >> 4;
5490 if (shift == 4*4) {
5491 *str_ptr = ':';
5492 str_ptr++;
5493 }
5494 }
5495 *str_ptr = '\0';
5496 return 0;
5497 }
5498
5499 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5500 u8 *version, u16 len)
5501 {
5502 struct bnx2x *bp;
5503 u32 ext_phy_type = 0;
5504 u32 spirom_ver = 0;
5505 u8 status;
5506
5507 if (version == NULL || params == NULL)
5508 return -EINVAL;
5509 bp = params->bp;
5510
5511 spirom_ver = REG_RD(bp, params->shmem_base +
5512 offsetof(struct shmem_region,
5513 port_mb[params->port].ext_phy_fw_version));
5514
5515 status = 0;
5516 /* reset the returned value to zero */
5517 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5518 switch (ext_phy_type) {
5519 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5520
5521 if (len < 5)
5522 return -EINVAL;
5523
5524 version[0] = (spirom_ver & 0xFF);
5525 version[1] = (spirom_ver & 0xFF00) >> 8;
5526 version[2] = (spirom_ver & 0xFF0000) >> 16;
5527 version[3] = (spirom_ver & 0xFF000000) >> 24;
5528 version[4] = '\0';
5529
5530 break;
5531 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5532 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
5533 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5534 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5535 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5536 status = bnx2x_format_ver(spirom_ver, version, len);
5537 break;
5538 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5539 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5540 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5541 (spirom_ver & 0x7F);
5542 status = bnx2x_format_ver(spirom_ver, version, len);
5543 break;
5544 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5545 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5546 version[0] = '\0';
5547 break;
5548
5549 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5550 DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
5551 " type is FAILURE!\n");
5552 status = -EINVAL;
5553 break;
5554
5555 default:
5556 break;
5557 }
5558 return status;
5559 }
5560
5561 static void bnx2x_set_xgxs_loopback(struct link_params *params,
5562 struct link_vars *vars,
5563 u8 is_10g)
5564 {
5565 u8 port = params->port;
5566 struct bnx2x *bp = params->bp;
5567
5568 if (is_10g) {
5569 u32 md_devad;
5570
5571 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5572
5573 /* change the uni_phy_addr in the nig */
5574 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5575 port*0x18));
5576
5577 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
5578
5579 bnx2x_cl45_write(bp, port, 0,
5580 params->phy_addr,
5581 5,
5582 (MDIO_REG_BANK_AER_BLOCK +
5583 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5584 0x2800);
5585
5586 bnx2x_cl45_write(bp, port, 0,
5587 params->phy_addr,
5588 5,
5589 (MDIO_REG_BANK_CL73_IEEEB0 +
5590 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5591 0x6041);
5592 msleep(200);
5593 /* set aer mmd back */
5594 bnx2x_set_aer_mmd(params, vars);
5595
5596 /* and md_devad */
5597 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5598 md_devad);
5599
5600 } else {
5601 u16 mii_control;
5602
5603 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5604
5605 CL45_RD_OVER_CL22(bp, port,
5606 params->phy_addr,
5607 MDIO_REG_BANK_COMBO_IEEE0,
5608 MDIO_COMBO_IEEE0_MII_CONTROL,
5609 &mii_control);
5610
5611 CL45_WR_OVER_CL22(bp, port,
5612 params->phy_addr,
5613 MDIO_REG_BANK_COMBO_IEEE0,
5614 MDIO_COMBO_IEEE0_MII_CONTROL,
5615 (mii_control |
5616 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
5617 }
5618 }
5619
5620
5621 static void bnx2x_ext_phy_loopback(struct link_params *params)
5622 {
5623 struct bnx2x *bp = params->bp;
5624 u8 ext_phy_addr;
5625 u32 ext_phy_type;
5626
5627 if (params->switch_cfg == SWITCH_CFG_10G) {
5628 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5629 ext_phy_addr = XGXS_EXT_PHY_ADDR(params->ext_phy_config);
5630 /* CL37 Autoneg Enabled */
5631 switch (ext_phy_type) {
5632 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5633 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
5634 DP(NETIF_MSG_LINK,
5635 "ext_phy_loopback: We should not get here\n");
5636 break;
5637 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5638 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
5639 break;
5640 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5641 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
5642 break;
5643 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5644 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5645 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5646 ext_phy_addr,
5647 MDIO_PMA_DEVAD,
5648 MDIO_PMA_REG_CTRL,
5649 0x0001);
5650 break;
5651 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5652 /* SFX7101_XGXS_TEST1 */
5653 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5654 ext_phy_addr,
5655 MDIO_XS_DEVAD,
5656 MDIO_XS_SFX7101_XGXS_TEST1,
5657 0x100);
5658 DP(NETIF_MSG_LINK,
5659 "ext_phy_loopback: set ext phy loopback\n");
5660 break;
5661 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5662
5663 break;
5664 } /* switch external PHY type */
5665 } else {
5666 /* serdes */
5667 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5668 ext_phy_addr = (params->ext_phy_config &
5669 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
5670 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
5671 }
5672 }
5673
5674
5675 /*
5676 *------------------------------------------------------------------------
5677 * bnx2x_override_led_value -
5678 *
5679 * Override the led value of the requsted led
5680 *
5681 *------------------------------------------------------------------------
5682 */
5683 u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
5684 u32 led_idx, u32 value)
5685 {
5686 u32 reg_val;
5687
5688 /* If port 0 then use EMAC0, else use EMAC1*/
5689 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5690
5691 DP(NETIF_MSG_LINK,
5692 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
5693 port, led_idx, value);
5694
5695 switch (led_idx) {
5696 case 0: /* 10MB led */
5697 /* Read the current value of the LED register in
5698 the EMAC block */
5699 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5700 /* Set the OVERRIDE bit to 1 */
5701 reg_val |= EMAC_LED_OVERRIDE;
5702 /* If value is 1, set the 10M_OVERRIDE bit,
5703 otherwise reset it.*/
5704 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
5705 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
5706 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5707 break;
5708 case 1: /*100MB led */
5709 /*Read the current value of the LED register in
5710 the EMAC block */
5711 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5712 /* Set the OVERRIDE bit to 1 */
5713 reg_val |= EMAC_LED_OVERRIDE;
5714 /* If value is 1, set the 100M_OVERRIDE bit,
5715 otherwise reset it.*/
5716 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
5717 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
5718 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5719 break;
5720 case 2: /* 1000MB led */
5721 /* Read the current value of the LED register in the
5722 EMAC block */
5723 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5724 /* Set the OVERRIDE bit to 1 */
5725 reg_val |= EMAC_LED_OVERRIDE;
5726 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
5727 reset it. */
5728 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
5729 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
5730 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5731 break;
5732 case 3: /* 2500MB led */
5733 /* Read the current value of the LED register in the
5734 EMAC block*/
5735 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5736 /* Set the OVERRIDE bit to 1 */
5737 reg_val |= EMAC_LED_OVERRIDE;
5738 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
5739 reset it.*/
5740 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
5741 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
5742 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5743 break;
5744 case 4: /*10G led */
5745 if (port == 0) {
5746 REG_WR(bp, NIG_REG_LED_10G_P0,
5747 value);
5748 } else {
5749 REG_WR(bp, NIG_REG_LED_10G_P1,
5750 value);
5751 }
5752 break;
5753 case 5: /* TRAFFIC led */
5754 /* Find if the traffic control is via BMAC or EMAC */
5755 if (port == 0)
5756 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
5757 else
5758 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
5759
5760 /* Override the traffic led in the EMAC:*/
5761 if (reg_val == 1) {
5762 /* Read the current value of the LED register in
5763 the EMAC block */
5764 reg_val = REG_RD(bp, emac_base +
5765 EMAC_REG_EMAC_LED);
5766 /* Set the TRAFFIC_OVERRIDE bit to 1 */
5767 reg_val |= EMAC_LED_OVERRIDE;
5768 /* If value is 1, set the TRAFFIC bit, otherwise
5769 reset it.*/
5770 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
5771 (reg_val & ~EMAC_LED_TRAFFIC);
5772 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5773 } else { /* Override the traffic led in the BMAC: */
5774 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5775 + port*4, 1);
5776 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
5777 value);
5778 }
5779 break;
5780 default:
5781 DP(NETIF_MSG_LINK,
5782 "bnx2x_override_led_value() unknown led index %d "
5783 "(should be 0-5)\n", led_idx);
5784 return -EINVAL;
5785 }
5786
5787 return 0;
5788 }
5789
5790
5791 u8 bnx2x_set_led(struct link_params *params, u8 mode, u32 speed)
5792 {
5793 u8 port = params->port;
5794 u16 hw_led_mode = params->hw_led_mode;
5795 u8 rc = 0;
5796 u32 tmp;
5797 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5798 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5799 struct bnx2x *bp = params->bp;
5800 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5801 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5802 speed, hw_led_mode);
5803 switch (mode) {
5804 case LED_MODE_OFF:
5805 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5806 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5807 SHARED_HW_CFG_LED_MAC1);
5808
5809 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5810 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5811 break;
5812
5813 case LED_MODE_OPER:
5814 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5815 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5816 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5817 } else {
5818 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5819 hw_led_mode);
5820 }
5821
5822 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
5823 port*4, 0);
5824 /* Set blinking rate to ~15.9Hz */
5825 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5826 LED_BLINK_RATE_VAL);
5827 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5828 port*4, 1);
5829 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5830 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5831 (tmp & (~EMAC_LED_OVERRIDE)));
5832
5833 if (CHIP_IS_E1(bp) &&
5834 ((speed == SPEED_2500) ||
5835 (speed == SPEED_1000) ||
5836 (speed == SPEED_100) ||
5837 (speed == SPEED_10))) {
5838 /* On Everest 1 Ax chip versions for speeds less than
5839 10G LED scheme is different */
5840 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5841 + port*4, 1);
5842 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5843 port*4, 0);
5844 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5845 port*4, 1);
5846 }
5847 break;
5848
5849 default:
5850 rc = -EINVAL;
5851 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5852 mode);
5853 break;
5854 }
5855 return rc;
5856
5857 }
5858
5859 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
5860 {
5861 struct bnx2x *bp = params->bp;
5862 u16 gp_status = 0;
5863
5864 CL45_RD_OVER_CL22(bp, params->port,
5865 params->phy_addr,
5866 MDIO_REG_BANK_GP_STATUS,
5867 MDIO_GP_STATUS_TOP_AN_STATUS1,
5868 &gp_status);
5869 /* link is up only if both local phy and external phy are up */
5870 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
5871 bnx2x_ext_phy_is_link_up(params, vars, 1))
5872 return 0;
5873
5874 return -ESRCH;
5875 }
5876
5877 static u8 bnx2x_link_initialize(struct link_params *params,
5878 struct link_vars *vars)
5879 {
5880 struct bnx2x *bp = params->bp;
5881 u8 port = params->port;
5882 u8 rc = 0;
5883 u8 non_ext_phy;
5884 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5885
5886 /* Activate the external PHY */
5887 bnx2x_ext_phy_reset(params, vars);
5888
5889 bnx2x_set_aer_mmd(params, vars);
5890
5891 if (vars->phy_flags & PHY_XGXS_FLAG)
5892 bnx2x_set_master_ln(params);
5893
5894 rc = bnx2x_reset_unicore(params);
5895 /* reset the SerDes and wait for reset bit return low */
5896 if (rc != 0)
5897 return rc;
5898
5899 bnx2x_set_aer_mmd(params, vars);
5900
5901 /* setting the masterLn_def again after the reset */
5902 if (vars->phy_flags & PHY_XGXS_FLAG) {
5903 bnx2x_set_master_ln(params);
5904 bnx2x_set_swap_lanes(params);
5905 }
5906
5907 if (vars->phy_flags & PHY_XGXS_FLAG) {
5908 if ((params->req_line_speed &&
5909 ((params->req_line_speed == SPEED_100) ||
5910 (params->req_line_speed == SPEED_10))) ||
5911 (!params->req_line_speed &&
5912 (params->speed_cap_mask >=
5913 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5914 (params->speed_cap_mask <
5915 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5916 )) {
5917 vars->phy_flags |= PHY_SGMII_FLAG;
5918 } else {
5919 vars->phy_flags &= ~PHY_SGMII_FLAG;
5920 }
5921 }
5922 /* In case of external phy existance, the line speed would be the
5923 line speed linked up by the external phy. In case it is direct only,
5924 then the line_speed during initialization will be equal to the
5925 req_line_speed*/
5926 vars->line_speed = params->req_line_speed;
5927
5928 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
5929
5930 /* init ext phy and enable link state int */
5931 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
5932 (params->loopback_mode == LOOPBACK_XGXS_10));
5933
5934 if (non_ext_phy ||
5935 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
5936 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) ||
5937 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
5938 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5939 if (params->req_line_speed == SPEED_AUTO_NEG)
5940 bnx2x_set_parallel_detection(params, vars->phy_flags);
5941 bnx2x_init_internal_phy(params, vars, non_ext_phy);
5942 }
5943
5944 if (!non_ext_phy)
5945 rc |= bnx2x_ext_phy_init(params, vars);
5946
5947 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5948 (NIG_STATUS_XGXS0_LINK10G |
5949 NIG_STATUS_XGXS0_LINK_STATUS |
5950 NIG_STATUS_SERDES0_LINK_STATUS));
5951
5952 return rc;
5953
5954 }
5955
5956
5957 u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5958 {
5959 struct bnx2x *bp = params->bp;
5960 u32 val;
5961
5962 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
5963 DP(NETIF_MSG_LINK, "req_speed %d, req_flowctrl %d\n",
5964 params->req_line_speed, params->req_flow_ctrl);
5965 vars->link_status = 0;
5966 vars->phy_link_up = 0;
5967 vars->link_up = 0;
5968 vars->line_speed = 0;
5969 vars->duplex = DUPLEX_FULL;
5970 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5971 vars->mac_type = MAC_TYPE_NONE;
5972
5973 if (params->switch_cfg == SWITCH_CFG_1G)
5974 vars->phy_flags = PHY_SERDES_FLAG;
5975 else
5976 vars->phy_flags = PHY_XGXS_FLAG;
5977
5978 /* disable attentions */
5979 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
5980 (NIG_MASK_XGXS0_LINK_STATUS |
5981 NIG_MASK_XGXS0_LINK10G |
5982 NIG_MASK_SERDES0_LINK_STATUS |
5983 NIG_MASK_MI_INT));
5984
5985 bnx2x_emac_init(params, vars);
5986
5987 if (CHIP_REV_IS_FPGA(bp)) {
5988
5989 vars->link_up = 1;
5990 vars->line_speed = SPEED_10000;
5991 vars->duplex = DUPLEX_FULL;
5992 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5993 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
5994 /* enable on E1.5 FPGA */
5995 if (CHIP_IS_E1H(bp)) {
5996 vars->flow_ctrl |=
5997 (BNX2X_FLOW_CTRL_TX |
5998 BNX2X_FLOW_CTRL_RX);
5999 vars->link_status |=
6000 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
6001 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
6002 }
6003
6004 bnx2x_emac_enable(params, vars, 0);
6005 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
6006 /* disable drain */
6007 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
6008
6009 /* update shared memory */
6010 bnx2x_update_mng(params, vars->link_status);
6011
6012 return 0;
6013
6014 } else
6015 if (CHIP_REV_IS_EMUL(bp)) {
6016
6017 vars->link_up = 1;
6018 vars->line_speed = SPEED_10000;
6019 vars->duplex = DUPLEX_FULL;
6020 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6021 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
6022
6023 bnx2x_bmac_enable(params, vars, 0);
6024
6025 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
6026 /* Disable drain */
6027 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
6028 + params->port*4, 0);
6029
6030 /* update shared memory */
6031 bnx2x_update_mng(params, vars->link_status);
6032
6033 return 0;
6034
6035 } else
6036 if (params->loopback_mode == LOOPBACK_BMAC) {
6037
6038 vars->link_up = 1;
6039 vars->line_speed = SPEED_10000;
6040 vars->duplex = DUPLEX_FULL;
6041 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6042 vars->mac_type = MAC_TYPE_BMAC;
6043
6044 vars->phy_flags = PHY_XGXS_FLAG;
6045
6046 bnx2x_phy_deassert(params, vars->phy_flags);
6047 /* set bmac loopback */
6048 bnx2x_bmac_enable(params, vars, 1);
6049
6050 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6051 params->port*4, 0);
6052
6053 } else if (params->loopback_mode == LOOPBACK_EMAC) {
6054
6055 vars->link_up = 1;
6056 vars->line_speed = SPEED_1000;
6057 vars->duplex = DUPLEX_FULL;
6058 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6059 vars->mac_type = MAC_TYPE_EMAC;
6060
6061 vars->phy_flags = PHY_XGXS_FLAG;
6062
6063 bnx2x_phy_deassert(params, vars->phy_flags);
6064 /* set bmac loopback */
6065 bnx2x_emac_enable(params, vars, 1);
6066 bnx2x_emac_program(params, vars->line_speed,
6067 vars->duplex);
6068 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6069 params->port*4, 0);
6070
6071 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
6072 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6073
6074 vars->link_up = 1;
6075 vars->line_speed = SPEED_10000;
6076 vars->duplex = DUPLEX_FULL;
6077 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6078
6079 vars->phy_flags = PHY_XGXS_FLAG;
6080
6081 val = REG_RD(bp,
6082 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6083 params->port*0x18);
6084 params->phy_addr = (u8)val;
6085
6086 bnx2x_phy_deassert(params, vars->phy_flags);
6087 bnx2x_link_initialize(params, vars);
6088
6089 vars->mac_type = MAC_TYPE_BMAC;
6090
6091 bnx2x_bmac_enable(params, vars, 0);
6092
6093 if (params->loopback_mode == LOOPBACK_XGXS_10) {
6094 /* set 10G XGXS loopback */
6095 bnx2x_set_xgxs_loopback(params, vars, 1);
6096 } else {
6097 /* set external phy loopback */
6098 bnx2x_ext_phy_loopback(params);
6099 }
6100 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6101 params->port*4, 0);
6102
6103 bnx2x_set_led(params, LED_MODE_OPER, vars->line_speed);
6104 } else
6105 /* No loopback */
6106 {
6107 bnx2x_phy_deassert(params, vars->phy_flags);
6108 switch (params->switch_cfg) {
6109 case SWITCH_CFG_1G:
6110 vars->phy_flags |= PHY_SERDES_FLAG;
6111 if ((params->ext_phy_config &
6112 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
6113 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
6114 vars->phy_flags |= PHY_SGMII_FLAG;
6115 }
6116
6117 val = REG_RD(bp,
6118 NIG_REG_SERDES0_CTRL_PHY_ADDR+
6119 params->port*0x10);
6120
6121 params->phy_addr = (u8)val;
6122
6123 break;
6124 case SWITCH_CFG_10G:
6125 vars->phy_flags |= PHY_XGXS_FLAG;
6126 val = REG_RD(bp,
6127 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6128 params->port*0x18);
6129 params->phy_addr = (u8)val;
6130
6131 break;
6132 default:
6133 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6134 return -EINVAL;
6135 }
6136 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
6137
6138 bnx2x_link_initialize(params, vars);
6139 msleep(30);
6140 bnx2x_link_int_enable(params);
6141 }
6142 return 0;
6143 }
6144
6145 static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
6146 {
6147 DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
6148
6149 /* Set serial boot control for external load */
6150 bnx2x_cl45_write(bp, port,
6151 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
6152 MDIO_PMA_DEVAD,
6153 MDIO_PMA_REG_GEN_CTRL, 0x0001);
6154 }
6155
6156 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6157 u8 reset_ext_phy)
6158 {
6159 struct bnx2x *bp = params->bp;
6160 u32 ext_phy_config = params->ext_phy_config;
6161 u8 port = params->port;
6162 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6163 u32 val = REG_RD(bp, params->shmem_base +
6164 offsetof(struct shmem_region, dev_info.
6165 port_feature_config[params->port].
6166 config));
6167 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
6168 /* disable attentions */
6169 vars->link_status = 0;
6170 bnx2x_update_mng(params, vars->link_status);
6171 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6172 (NIG_MASK_XGXS0_LINK_STATUS |
6173 NIG_MASK_XGXS0_LINK10G |
6174 NIG_MASK_SERDES0_LINK_STATUS |
6175 NIG_MASK_MI_INT));
6176
6177 /* activate nig drain */
6178 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6179
6180 /* disable nig egress interface */
6181 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6182 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6183
6184 /* Stop BigMac rx */
6185 bnx2x_bmac_rx_disable(bp, port);
6186
6187 /* disable emac */
6188 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6189
6190 msleep(10);
6191 /* The PHY reset is controled by GPIO 1
6192 * Hold it as vars low
6193 */
6194 /* clear link led */
6195 bnx2x_set_led(params, LED_MODE_OFF, 0);
6196 if (reset_ext_phy) {
6197 switch (ext_phy_type) {
6198 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6199 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6200 break;
6201
6202 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6203 {
6204
6205 /* Disable Transmitter */
6206 u8 ext_phy_addr =
6207 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
6208 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
6209 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
6210 bnx2x_sfp_set_transmitter(bp, port,
6211 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6212 ext_phy_addr, 0);
6213 break;
6214 }
6215 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6216 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
6217 "low power mode\n",
6218 port);
6219 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6220 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6221 port);
6222 break;
6223 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6224 {
6225 u8 ext_phy_addr =
6226 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
6227 /* Set soft reset */
6228 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6229 break;
6230 }
6231 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6232 {
6233 u8 ext_phy_addr =
6234 XGXS_EXT_PHY_ADDR(params->ext_phy_config);
6235 bnx2x_cl45_write(bp, port,
6236 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6237 ext_phy_addr,
6238 MDIO_AN_DEVAD,
6239 MDIO_AN_REG_CTRL, 0x0000);
6240 bnx2x_cl45_write(bp, port,
6241 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6242 ext_phy_addr,
6243 MDIO_PMA_DEVAD,
6244 MDIO_PMA_REG_CTRL, 1);
6245 break;
6246 }
6247 default:
6248 /* HW reset */
6249 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6250 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6251 port);
6252 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6253 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6254 port);
6255 DP(NETIF_MSG_LINK, "reset external PHY\n");
6256 }
6257 }
6258 /* reset the SerDes/XGXS */
6259 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6260 (0x1ff << (port*16)));
6261
6262 /* reset BigMac */
6263 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6264 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6265
6266 /* disable nig ingress interface */
6267 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
6268 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
6269 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6270 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6271 vars->link_up = 0;
6272 return 0;
6273 }
6274
6275 static u8 bnx2x_update_link_down(struct link_params *params,
6276 struct link_vars *vars)
6277 {
6278 struct bnx2x *bp = params->bp;
6279 u8 port = params->port;
6280
6281 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6282 bnx2x_set_led(params, LED_MODE_OFF, 0);
6283
6284 /* indicate no mac active */
6285 vars->mac_type = MAC_TYPE_NONE;
6286
6287 /* update shared memory */
6288 vars->link_status = 0;
6289 vars->line_speed = 0;
6290 bnx2x_update_mng(params, vars->link_status);
6291
6292 /* activate nig drain */
6293 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6294
6295 /* disable emac */
6296 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6297
6298 msleep(10);
6299
6300 /* reset BigMac */
6301 bnx2x_bmac_rx_disable(bp, params->port);
6302 REG_WR(bp, GRCBASE_MISC +
6303 MISC_REGISTERS_RESET_REG_2_CLEAR,
6304 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6305 return 0;
6306 }
6307
6308 static u8 bnx2x_update_link_up(struct link_params *params,
6309 struct link_vars *vars,
6310 u8 link_10g, u32 gp_status)
6311 {
6312 struct bnx2x *bp = params->bp;
6313 u8 port = params->port;
6314 u8 rc = 0;
6315
6316 vars->link_status |= LINK_STATUS_LINK_UP;
6317 if (link_10g) {
6318 bnx2x_bmac_enable(params, vars, 0);
6319 bnx2x_set_led(params, LED_MODE_OPER, SPEED_10000);
6320 } else {
6321 rc = bnx2x_emac_program(params, vars->line_speed,
6322 vars->duplex);
6323
6324 bnx2x_emac_enable(params, vars, 0);
6325
6326 /* AN complete? */
6327 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
6328 if (!(vars->phy_flags &
6329 PHY_SGMII_FLAG))
6330 bnx2x_set_gmii_tx_driver(params);
6331 }
6332 }
6333
6334 /* PBF - link up */
6335 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6336 vars->line_speed);
6337
6338 /* disable drain */
6339 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6340
6341 /* update shared memory */
6342 bnx2x_update_mng(params, vars->link_status);
6343 msleep(20);
6344 return rc;
6345 }
6346 /* This function should called upon link interrupt */
6347 /* In case vars->link_up, driver needs to
6348 1. Update the pbf
6349 2. Disable drain
6350 3. Update the shared memory
6351 4. Indicate link up
6352 5. Set LEDs
6353 Otherwise,
6354 1. Update shared memory
6355 2. Reset BigMac
6356 3. Report link down
6357 4. Unset LEDs
6358 */
6359 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6360 {
6361 struct bnx2x *bp = params->bp;
6362 u8 port = params->port;
6363 u16 gp_status;
6364 u8 link_10g;
6365 u8 ext_phy_link_up, rc = 0;
6366 u32 ext_phy_type;
6367 u8 is_mi_int = 0;
6368
6369 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6370 port, (vars->phy_flags & PHY_XGXS_FLAG),
6371 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6372
6373 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6374 port*0x18) > 0);
6375 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6376 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6377 is_mi_int,
6378 REG_RD(bp,
6379 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6380
6381 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6382 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6383 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6384
6385 /* disable emac */
6386 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6387
6388 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
6389
6390 /* Check external link change only for non-direct */
6391 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars, is_mi_int);
6392
6393 /* Read gp_status */
6394 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
6395 MDIO_REG_BANK_GP_STATUS,
6396 MDIO_GP_STATUS_TOP_AN_STATUS1,
6397 &gp_status);
6398
6399 rc = bnx2x_link_settings_status(params, vars, gp_status,
6400 ext_phy_link_up);
6401 if (rc != 0)
6402 return rc;
6403
6404 /* anything 10 and over uses the bmac */
6405 link_10g = ((vars->line_speed == SPEED_10000) ||
6406 (vars->line_speed == SPEED_12000) ||
6407 (vars->line_speed == SPEED_12500) ||
6408 (vars->line_speed == SPEED_13000) ||
6409 (vars->line_speed == SPEED_15000) ||
6410 (vars->line_speed == SPEED_16000));
6411
6412 bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
6413
6414 /* In case external phy link is up, and internal link is down
6415 ( not initialized yet probably after link initialization, it needs
6416 to be initialized.
6417 Note that after link down-up as result of cable plug,
6418 the xgxs link would probably become up again without the need to
6419 initialize it*/
6420
6421 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6422 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
6423 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706) &&
6424 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
6425 (ext_phy_link_up && !vars->phy_link_up))
6426 bnx2x_init_internal_phy(params, vars, 0);
6427
6428 /* link is up only if both local phy and external phy are up */
6429 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
6430
6431 if (vars->link_up)
6432 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
6433 else
6434 rc = bnx2x_update_link_down(params, vars);
6435
6436 return rc;
6437 }
6438
6439 static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6440 {
6441 u8 ext_phy_addr[PORT_MAX];
6442 u16 val;
6443 s8 port;
6444
6445 /* PART1 - Reset both phys */
6446 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6447 /* Extract the ext phy address for the port */
6448 u32 ext_phy_config = REG_RD(bp, shmem_base +
6449 offsetof(struct shmem_region,
6450 dev_info.port_hw_config[port].external_phy_config));
6451
6452 /* disable attentions */
6453 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6454 (NIG_MASK_XGXS0_LINK_STATUS |
6455 NIG_MASK_XGXS0_LINK10G |
6456 NIG_MASK_SERDES0_LINK_STATUS |
6457 NIG_MASK_MI_INT));
6458
6459 ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
6460
6461 /* Need to take the phy out of low power mode in order
6462 to write to access its registers */
6463 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6464 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6465
6466 /* Reset the phy */
6467 bnx2x_cl45_write(bp, port,
6468 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6469 ext_phy_addr[port],
6470 MDIO_PMA_DEVAD,
6471 MDIO_PMA_REG_CTRL,
6472 1<<15);
6473 }
6474
6475 /* Add delay of 150ms after reset */
6476 msleep(150);
6477
6478 /* PART2 - Download firmware to both phys */
6479 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6480 u16 fw_ver1;
6481
6482 bnx2x_bcm8073_external_rom_boot(bp, port,
6483 ext_phy_addr[port], shmem_base);
6484
6485 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6486 ext_phy_addr[port],
6487 MDIO_PMA_DEVAD,
6488 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6489 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6490 DP(NETIF_MSG_LINK,
6491 "bnx2x_8073_common_init_phy port %x:"
6492 "Download failed. fw version = 0x%x\n",
6493 port, fw_ver1);
6494 return -EINVAL;
6495 }
6496
6497 /* Only set bit 10 = 1 (Tx power down) */
6498 bnx2x_cl45_read(bp, port,
6499 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6500 ext_phy_addr[port],
6501 MDIO_PMA_DEVAD,
6502 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6503
6504 /* Phase1 of TX_POWER_DOWN reset */
6505 bnx2x_cl45_write(bp, port,
6506 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6507 ext_phy_addr[port],
6508 MDIO_PMA_DEVAD,
6509 MDIO_PMA_REG_TX_POWER_DOWN,
6510 (val | 1<<10));
6511 }
6512
6513 /* Toggle Transmitter: Power down and then up with 600ms
6514 delay between */
6515 msleep(600);
6516
6517 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6518 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6519 /* Phase2 of POWER_DOWN_RESET */
6520 /* Release bit 10 (Release Tx power down) */
6521 bnx2x_cl45_read(bp, port,
6522 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6523 ext_phy_addr[port],
6524 MDIO_PMA_DEVAD,
6525 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6526
6527 bnx2x_cl45_write(bp, port,
6528 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6529 ext_phy_addr[port],
6530 MDIO_PMA_DEVAD,
6531 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6532 msleep(15);
6533
6534 /* Read modify write the SPI-ROM version select register */
6535 bnx2x_cl45_read(bp, port,
6536 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6537 ext_phy_addr[port],
6538 MDIO_PMA_DEVAD,
6539 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
6540 bnx2x_cl45_write(bp, port,
6541 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6542 ext_phy_addr[port],
6543 MDIO_PMA_DEVAD,
6544 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6545
6546 /* set GPIO2 back to LOW */
6547 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6548 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6549 }
6550 return 0;
6551
6552 }
6553
6554 static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6555 {
6556 u8 ext_phy_addr[PORT_MAX];
6557 s8 port, first_port, i;
6558 u32 swap_val, swap_override;
6559 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6560 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6561 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6562
6563 bnx2x_ext_phy_hw_reset(bp, 1 ^ (swap_val && swap_override));
6564 msleep(5);
6565
6566 if (swap_val && swap_override)
6567 first_port = PORT_0;
6568 else
6569 first_port = PORT_1;
6570
6571 /* PART1 - Reset both phys */
6572 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
6573 /* Extract the ext phy address for the port */
6574 u32 ext_phy_config = REG_RD(bp, shmem_base +
6575 offsetof(struct shmem_region,
6576 dev_info.port_hw_config[port].external_phy_config));
6577
6578 /* disable attentions */
6579 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6580 (NIG_MASK_XGXS0_LINK_STATUS |
6581 NIG_MASK_XGXS0_LINK10G |
6582 NIG_MASK_SERDES0_LINK_STATUS |
6583 NIG_MASK_MI_INT));
6584
6585 ext_phy_addr[port] = XGXS_EXT_PHY_ADDR(ext_phy_config);
6586
6587 /* Reset the phy */
6588 bnx2x_cl45_write(bp, port,
6589 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6590 ext_phy_addr[port],
6591 MDIO_PMA_DEVAD,
6592 MDIO_PMA_REG_CTRL,
6593 1<<15);
6594 }
6595
6596 /* Add delay of 150ms after reset */
6597 msleep(150);
6598
6599 /* PART2 - Download firmware to both phys */
6600 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
6601 u16 fw_ver1;
6602
6603 bnx2x_bcm8727_external_rom_boot(bp, port,
6604 ext_phy_addr[port], shmem_base);
6605
6606 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6607 ext_phy_addr[port],
6608 MDIO_PMA_DEVAD,
6609 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6610 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6611 DP(NETIF_MSG_LINK,
6612 "bnx2x_8727_common_init_phy port %x:"
6613 "Download failed. fw version = 0x%x\n",
6614 port, fw_ver1);
6615 return -EINVAL;
6616 }
6617 }
6618
6619 return 0;
6620 }
6621
6622
6623 static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6624 {
6625 u8 ext_phy_addr;
6626 u32 val;
6627 s8 port;
6628
6629 /* Use port1 because of the static port-swap */
6630 /* Enable the module detection interrupt */
6631 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
6632 val |= ((1<<MISC_REGISTERS_GPIO_3)|
6633 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
6634 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
6635
6636 bnx2x_ext_phy_hw_reset(bp, 1);
6637 msleep(5);
6638 for (port = 0; port < PORT_MAX; port++) {
6639 /* Extract the ext phy address for the port */
6640 u32 ext_phy_config = REG_RD(bp, shmem_base +
6641 offsetof(struct shmem_region,
6642 dev_info.port_hw_config[port].external_phy_config));
6643
6644 ext_phy_addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
6645 DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
6646 ext_phy_addr);
6647
6648 bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
6649
6650 /* Set fault module detected LED on */
6651 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6652 MISC_REGISTERS_GPIO_HIGH,
6653 port);
6654 }
6655
6656 return 0;
6657 }
6658
6659
6660 static u8 bnx2x_84823_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6661 {
6662 /* HW reset */
6663 bnx2x_ext_phy_hw_reset(bp, 1);
6664 return 0;
6665 }
6666 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6667 {
6668 u8 rc = 0;
6669 u32 ext_phy_type;
6670
6671 DP(NETIF_MSG_LINK, "Begin common phy init\n");
6672
6673 /* Read the ext_phy_type for arbitrary port(0) */
6674 ext_phy_type = XGXS_EXT_PHY_TYPE(
6675 REG_RD(bp, shmem_base +
6676 offsetof(struct shmem_region,
6677 dev_info.port_hw_config[0].external_phy_config)));
6678
6679 switch (ext_phy_type) {
6680 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6681 {
6682 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
6683 break;
6684 }
6685
6686 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6687 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6688 rc = bnx2x_8727_common_init_phy(bp, shmem_base);
6689 break;
6690
6691 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6692 /* GPIO1 affects both ports, so there's need to pull
6693 it for single port alone */
6694 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6695 break;
6696 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6697 rc = bnx2x_84823_common_init_phy(bp, shmem_base);
6698 break;
6699 default:
6700 DP(NETIF_MSG_LINK,
6701 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6702 ext_phy_type);
6703 break;
6704 }
6705
6706 return rc;
6707 }
6708
6709 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
6710 {
6711 u16 val, cnt;
6712
6713 bnx2x_cl45_read(bp, port,
6714 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6715 phy_addr,
6716 MDIO_PMA_DEVAD,
6717 MDIO_PMA_REG_7101_RESET, &val);
6718
6719 for (cnt = 0; cnt < 10; cnt++) {
6720 msleep(50);
6721 /* Writes a self-clearing reset */
6722 bnx2x_cl45_write(bp, port,
6723 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6724 phy_addr,
6725 MDIO_PMA_DEVAD,
6726 MDIO_PMA_REG_7101_RESET,
6727 (val | (1<<15)));
6728 /* Wait for clear */
6729 bnx2x_cl45_read(bp, port,
6730 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6731 phy_addr,
6732 MDIO_PMA_DEVAD,
6733 MDIO_PMA_REG_7101_RESET, &val);
6734
6735 if ((val & (1<<15)) == 0)
6736 break;
6737 }
6738 }
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