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[mirror_ubuntu-zesty-kernel.git] / drivers / net / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
41 #include <net/ip.h>
42 #include <net/ipv6.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
51 #include <linux/io.h>
52 #include <linux/stringify.h>
53
54 #include "bnx2x.h"
55 #include "bnx2x_init.h"
56 #include "bnx2x_init_ops.h"
57 #include "bnx2x_cmn.h"
58 #include "bnx2x_dcb.h"
59 #include "bnx2x_sp.h"
60
61 #include <linux/firmware.h>
62 #include "bnx2x_fw_file_hdr.h"
63 /* FW files */
64 #define FW_FILE_VERSION \
65 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
66 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
67 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
68 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
69 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
70 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
71 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
72
73 /* Time in jiffies before concluding the transmitter is hung */
74 #define TX_TIMEOUT (5*HZ)
75
76 static char version[] __devinitdata =
77 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
78 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
79
80 MODULE_AUTHOR("Eliezer Tamir");
81 MODULE_DESCRIPTION("Broadcom NetXtreme II "
82 "BCM57710/57711/57711E/"
83 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
84 "57840/57840_MF Driver");
85 MODULE_LICENSE("GPL");
86 MODULE_VERSION(DRV_MODULE_VERSION);
87 MODULE_FIRMWARE(FW_FILE_NAME_E1);
88 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
89 MODULE_FIRMWARE(FW_FILE_NAME_E2);
90
91 static int multi_mode = 1;
92 module_param(multi_mode, int, 0);
93 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
94 "(0 Disable; 1 Enable (default))");
95
96 int num_queues;
97 module_param(num_queues, int, 0);
98 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
99 " (default is as a number of CPUs)");
100
101 static int disable_tpa;
102 module_param(disable_tpa, int, 0);
103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
104
105 #define INT_MODE_INTx 1
106 #define INT_MODE_MSI 2
107 static int int_mode;
108 module_param(int_mode, int, 0);
109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
110 "(1 INT#x; 2 MSI)");
111
112 static int dropless_fc;
113 module_param(dropless_fc, int, 0);
114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
115
116 static int poll;
117 module_param(poll, int, 0);
118 MODULE_PARM_DESC(poll, " Use polling (for debug)");
119
120 static int mrrs = -1;
121 module_param(mrrs, int, 0);
122 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123
124 static int debug;
125 module_param(debug, int, 0);
126 MODULE_PARM_DESC(debug, " Default debug msglevel");
127
128
129
130 struct workqueue_struct *bnx2x_wq;
131
132 enum bnx2x_board_type {
133 BCM57710 = 0,
134 BCM57711,
135 BCM57711E,
136 BCM57712,
137 BCM57712_MF,
138 BCM57800,
139 BCM57800_MF,
140 BCM57810,
141 BCM57810_MF,
142 BCM57840,
143 BCM57840_MF
144 };
145
146 /* indexed by board_type, above */
147 static struct {
148 char *name;
149 } board_info[] __devinitdata = {
150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
161 "Ethernet Multi Function"}
162 };
163
164 #ifndef PCI_DEVICE_ID_NX2_57710
165 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
166 #endif
167 #ifndef PCI_DEVICE_ID_NX2_57711
168 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
169 #endif
170 #ifndef PCI_DEVICE_ID_NX2_57711E
171 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
172 #endif
173 #ifndef PCI_DEVICE_ID_NX2_57712
174 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
175 #endif
176 #ifndef PCI_DEVICE_ID_NX2_57712_MF
177 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
178 #endif
179 #ifndef PCI_DEVICE_ID_NX2_57800
180 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
181 #endif
182 #ifndef PCI_DEVICE_ID_NX2_57800_MF
183 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
184 #endif
185 #ifndef PCI_DEVICE_ID_NX2_57810
186 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
187 #endif
188 #ifndef PCI_DEVICE_ID_NX2_57810_MF
189 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
190 #endif
191 #ifndef PCI_DEVICE_ID_NX2_57840
192 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57840_MF
195 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
196 #endif
197 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
209 { 0 }
210 };
211
212 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
213
214 /****************************************************************************
215 * General service functions
216 ****************************************************************************/
217
218 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
219 u32 addr, dma_addr_t mapping)
220 {
221 REG_WR(bp, addr, U64_LO(mapping));
222 REG_WR(bp, addr + 4, U64_HI(mapping));
223 }
224
225 static inline void storm_memset_spq_addr(struct bnx2x *bp,
226 dma_addr_t mapping, u16 abs_fid)
227 {
228 u32 addr = XSEM_REG_FAST_MEMORY +
229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
230
231 __storm_memset_dma_mapping(bp, addr, mapping);
232 }
233
234 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
235 u16 pf_id)
236 {
237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
238 pf_id);
239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
240 pf_id);
241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
245 }
246
247 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
248 u8 enable)
249 {
250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
251 enable);
252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
253 enable);
254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258 }
259
260 static inline void storm_memset_eq_data(struct bnx2x *bp,
261 struct event_ring_data *eq_data,
262 u16 pfid)
263 {
264 size_t size = sizeof(struct event_ring_data);
265
266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
269 }
270
271 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
272 u16 pfid)
273 {
274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
275 REG_WR16(bp, addr, eq_prod);
276 }
277
278 /* used only at init
279 * locking is done by mcp
280 */
281 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
282 {
283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
286 PCICFG_VENDOR_ID_OFFSET);
287 }
288
289 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
290 {
291 u32 val;
292
293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
296 PCICFG_VENDOR_ID_OFFSET);
297
298 return val;
299 }
300
301 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
302 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
303 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
304 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
305 #define DMAE_DP_DST_NONE "dst_addr [none]"
306
307 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
308 int msglvl)
309 {
310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
311
312 switch (dmae->opcode & DMAE_COMMAND_DST) {
313 case DMAE_CMD_DST_PCI:
314 if (src_type == DMAE_CMD_SRC_PCI)
315 DP(msglvl, "DMAE: opcode 0x%08x\n"
316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
317 "comp_addr [%x:%08x], comp_val 0x%08x\n",
318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
320 dmae->comp_addr_hi, dmae->comp_addr_lo,
321 dmae->comp_val);
322 else
323 DP(msglvl, "DMAE: opcode 0x%08x\n"
324 "src [%08x], len [%d*4], dst [%x:%08x]\n"
325 "comp_addr [%x:%08x], comp_val 0x%08x\n",
326 dmae->opcode, dmae->src_addr_lo >> 2,
327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
328 dmae->comp_addr_hi, dmae->comp_addr_lo,
329 dmae->comp_val);
330 break;
331 case DMAE_CMD_DST_GRC:
332 if (src_type == DMAE_CMD_SRC_PCI)
333 DP(msglvl, "DMAE: opcode 0x%08x\n"
334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
335 "comp_addr [%x:%08x], comp_val 0x%08x\n",
336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
337 dmae->len, dmae->dst_addr_lo >> 2,
338 dmae->comp_addr_hi, dmae->comp_addr_lo,
339 dmae->comp_val);
340 else
341 DP(msglvl, "DMAE: opcode 0x%08x\n"
342 "src [%08x], len [%d*4], dst [%08x]\n"
343 "comp_addr [%x:%08x], comp_val 0x%08x\n",
344 dmae->opcode, dmae->src_addr_lo >> 2,
345 dmae->len, dmae->dst_addr_lo >> 2,
346 dmae->comp_addr_hi, dmae->comp_addr_lo,
347 dmae->comp_val);
348 break;
349 default:
350 if (src_type == DMAE_CMD_SRC_PCI)
351 DP(msglvl, "DMAE: opcode 0x%08x\n"
352 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
353 "dst_addr [none]\n"
354 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
355 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
356 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
357 dmae->comp_val);
358 else
359 DP(msglvl, "DMAE: opcode 0x%08x\n"
360 DP_LEVEL "src_addr [%08x] len [%d * 4] "
361 "dst_addr [none]\n"
362 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
363 dmae->opcode, dmae->src_addr_lo >> 2,
364 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
365 dmae->comp_val);
366 break;
367 }
368
369 }
370
371 /* copy command into DMAE command memory and set DMAE command go */
372 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
373 {
374 u32 cmd_offset;
375 int i;
376
377 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
378 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
379 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
380
381 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
382 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
383 }
384 REG_WR(bp, dmae_reg_go_c[idx], 1);
385 }
386
387 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
388 {
389 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
390 DMAE_CMD_C_ENABLE);
391 }
392
393 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
394 {
395 return opcode & ~DMAE_CMD_SRC_RESET;
396 }
397
398 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
399 bool with_comp, u8 comp_type)
400 {
401 u32 opcode = 0;
402
403 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
404 (dst_type << DMAE_COMMAND_DST_SHIFT));
405
406 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
407
408 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
409 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
410 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
411 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
412
413 #ifdef __BIG_ENDIAN
414 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
415 #else
416 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
417 #endif
418 if (with_comp)
419 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
420 return opcode;
421 }
422
423 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
424 struct dmae_command *dmae,
425 u8 src_type, u8 dst_type)
426 {
427 memset(dmae, 0, sizeof(struct dmae_command));
428
429 /* set the opcode */
430 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
431 true, DMAE_COMP_PCI);
432
433 /* fill in the completion parameters */
434 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
435 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_val = DMAE_COMP_VAL;
437 }
438
439 /* issue a dmae command over the init-channel and wailt for completion */
440 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
441 struct dmae_command *dmae)
442 {
443 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
444 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
445 int rc = 0;
446
447 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
448 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
449 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
450
451 /*
452 * Lock the dmae channel. Disable BHs to prevent a dead-lock
453 * as long as this code is called both from syscall context and
454 * from ndo_set_rx_mode() flow that may be called from BH.
455 */
456 spin_lock_bh(&bp->dmae_lock);
457
458 /* reset completion */
459 *wb_comp = 0;
460
461 /* post the command on the channel used for initializations */
462 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
463
464 /* wait for completion */
465 udelay(5);
466 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
467 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
468
469 if (!cnt) {
470 BNX2X_ERR("DMAE timeout!\n");
471 rc = DMAE_TIMEOUT;
472 goto unlock;
473 }
474 cnt--;
475 udelay(50);
476 }
477 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
478 BNX2X_ERR("DMAE PCI error!\n");
479 rc = DMAE_PCI_ERROR;
480 }
481
482 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
483 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
484 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
485
486 unlock:
487 spin_unlock_bh(&bp->dmae_lock);
488 return rc;
489 }
490
491 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
492 u32 len32)
493 {
494 struct dmae_command dmae;
495
496 if (!bp->dmae_ready) {
497 u32 *data = bnx2x_sp(bp, wb_data[0]);
498
499 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
500 " using indirect\n", dst_addr, len32);
501 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
502 return;
503 }
504
505 /* set opcode and fixed command fields */
506 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
507
508 /* fill in addresses and len */
509 dmae.src_addr_lo = U64_LO(dma_addr);
510 dmae.src_addr_hi = U64_HI(dma_addr);
511 dmae.dst_addr_lo = dst_addr >> 2;
512 dmae.dst_addr_hi = 0;
513 dmae.len = len32;
514
515 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
516
517 /* issue the command and wait for completion */
518 bnx2x_issue_dmae_with_comp(bp, &dmae);
519 }
520
521 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
522 {
523 struct dmae_command dmae;
524
525 if (!bp->dmae_ready) {
526 u32 *data = bnx2x_sp(bp, wb_data[0]);
527 int i;
528
529 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
530 " using indirect\n", src_addr, len32);
531 for (i = 0; i < len32; i++)
532 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
533 return;
534 }
535
536 /* set opcode and fixed command fields */
537 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
538
539 /* fill in addresses and len */
540 dmae.src_addr_lo = src_addr >> 2;
541 dmae.src_addr_hi = 0;
542 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
543 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
544 dmae.len = len32;
545
546 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
547
548 /* issue the command and wait for completion */
549 bnx2x_issue_dmae_with_comp(bp, &dmae);
550 }
551
552 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
553 u32 addr, u32 len)
554 {
555 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
556 int offset = 0;
557
558 while (len > dmae_wr_max) {
559 bnx2x_write_dmae(bp, phys_addr + offset,
560 addr + offset, dmae_wr_max);
561 offset += dmae_wr_max * 4;
562 len -= dmae_wr_max;
563 }
564
565 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
566 }
567
568 /* used only for slowpath so not inlined */
569 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
570 {
571 u32 wb_write[2];
572
573 wb_write[0] = val_hi;
574 wb_write[1] = val_lo;
575 REG_WR_DMAE(bp, reg, wb_write, 2);
576 }
577
578 #ifdef USE_WB_RD
579 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
580 {
581 u32 wb_data[2];
582
583 REG_RD_DMAE(bp, reg, wb_data, 2);
584
585 return HILO_U64(wb_data[0], wb_data[1]);
586 }
587 #endif
588
589 static int bnx2x_mc_assert(struct bnx2x *bp)
590 {
591 char last_idx;
592 int i, rc = 0;
593 u32 row0, row1, row2, row3;
594
595 /* XSTORM */
596 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
597 XSTORM_ASSERT_LIST_INDEX_OFFSET);
598 if (last_idx)
599 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
600
601 /* print the asserts */
602 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
603
604 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
605 XSTORM_ASSERT_LIST_OFFSET(i));
606 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
608 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
610 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
611 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
612
613 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
614 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
615 " 0x%08x 0x%08x 0x%08x\n",
616 i, row3, row2, row1, row0);
617 rc++;
618 } else {
619 break;
620 }
621 }
622
623 /* TSTORM */
624 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
625 TSTORM_ASSERT_LIST_INDEX_OFFSET);
626 if (last_idx)
627 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
628
629 /* print the asserts */
630 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
631
632 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
633 TSTORM_ASSERT_LIST_OFFSET(i));
634 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
636 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
638 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
640
641 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
642 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
643 " 0x%08x 0x%08x 0x%08x\n",
644 i, row3, row2, row1, row0);
645 rc++;
646 } else {
647 break;
648 }
649 }
650
651 /* CSTORM */
652 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
653 CSTORM_ASSERT_LIST_INDEX_OFFSET);
654 if (last_idx)
655 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
656
657 /* print the asserts */
658 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
659
660 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
661 CSTORM_ASSERT_LIST_OFFSET(i));
662 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
664 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
666 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
667 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
668
669 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
670 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
671 " 0x%08x 0x%08x 0x%08x\n",
672 i, row3, row2, row1, row0);
673 rc++;
674 } else {
675 break;
676 }
677 }
678
679 /* USTORM */
680 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
681 USTORM_ASSERT_LIST_INDEX_OFFSET);
682 if (last_idx)
683 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
684
685 /* print the asserts */
686 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
687
688 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
689 USTORM_ASSERT_LIST_OFFSET(i));
690 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
691 USTORM_ASSERT_LIST_OFFSET(i) + 4);
692 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i) + 8);
694 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 12);
696
697 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
698 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
699 " 0x%08x 0x%08x 0x%08x\n",
700 i, row3, row2, row1, row0);
701 rc++;
702 } else {
703 break;
704 }
705 }
706
707 return rc;
708 }
709
710 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
711 {
712 u32 addr, val;
713 u32 mark, offset;
714 __be32 data[9];
715 int word;
716 u32 trace_shmem_base;
717 if (BP_NOMCP(bp)) {
718 BNX2X_ERR("NO MCP - can not dump\n");
719 return;
720 }
721 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
722 (bp->common.bc_ver & 0xff0000) >> 16,
723 (bp->common.bc_ver & 0xff00) >> 8,
724 (bp->common.bc_ver & 0xff));
725
726 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
727 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
728 printk("%s" "MCP PC at 0x%x\n", lvl, val);
729
730 if (BP_PATH(bp) == 0)
731 trace_shmem_base = bp->common.shmem_base;
732 else
733 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
734 addr = trace_shmem_base - 0x0800 + 4;
735 mark = REG_RD(bp, addr);
736 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
737 + ((mark + 0x3) & ~0x3) - 0x08000000;
738 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
739
740 printk("%s", lvl);
741 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
742 for (word = 0; word < 8; word++)
743 data[word] = htonl(REG_RD(bp, offset + 4*word));
744 data[8] = 0x0;
745 pr_cont("%s", (char *)data);
746 }
747 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
748 for (word = 0; word < 8; word++)
749 data[word] = htonl(REG_RD(bp, offset + 4*word));
750 data[8] = 0x0;
751 pr_cont("%s", (char *)data);
752 }
753 printk("%s" "end of fw dump\n", lvl);
754 }
755
756 static inline void bnx2x_fw_dump(struct bnx2x *bp)
757 {
758 bnx2x_fw_dump_lvl(bp, KERN_ERR);
759 }
760
761 void bnx2x_panic_dump(struct bnx2x *bp)
762 {
763 int i;
764 u16 j;
765 struct hc_sp_status_block_data sp_sb_data;
766 int func = BP_FUNC(bp);
767 #ifdef BNX2X_STOP_ON_ERROR
768 u16 start = 0, end = 0;
769 #endif
770
771 bp->stats_state = STATS_STATE_DISABLED;
772 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
773
774 BNX2X_ERR("begin crash dump -----------------\n");
775
776 /* Indices */
777 /* Common */
778 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
779 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
780 bp->def_idx, bp->def_att_idx, bp->attn_state,
781 bp->spq_prod_idx, bp->stats_counter);
782 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
783 bp->def_status_blk->atten_status_block.attn_bits,
784 bp->def_status_blk->atten_status_block.attn_bits_ack,
785 bp->def_status_blk->atten_status_block.status_block_id,
786 bp->def_status_blk->atten_status_block.attn_bits_index);
787 BNX2X_ERR(" def (");
788 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
789 pr_cont("0x%x%s",
790 bp->def_status_blk->sp_sb.index_values[i],
791 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
792
793 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
794 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
795 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
796 i*sizeof(u32));
797
798 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
799 "pf_id(0x%x) vnic_id(0x%x) "
800 "vf_id(0x%x) vf_valid (0x%x) "
801 "state(0x%x)\n",
802 sp_sb_data.igu_sb_id,
803 sp_sb_data.igu_seg_id,
804 sp_sb_data.p_func.pf_id,
805 sp_sb_data.p_func.vnic_id,
806 sp_sb_data.p_func.vf_id,
807 sp_sb_data.p_func.vf_valid,
808 sp_sb_data.state);
809
810
811 for_each_eth_queue(bp, i) {
812 struct bnx2x_fastpath *fp = &bp->fp[i];
813 int loop;
814 struct hc_status_block_data_e2 sb_data_e2;
815 struct hc_status_block_data_e1x sb_data_e1x;
816 struct hc_status_block_sm *hc_sm_p =
817 CHIP_IS_E1x(bp) ?
818 sb_data_e1x.common.state_machine :
819 sb_data_e2.common.state_machine;
820 struct hc_index_data *hc_index_p =
821 CHIP_IS_E1x(bp) ?
822 sb_data_e1x.index_data :
823 sb_data_e2.index_data;
824 int data_size;
825 u32 *sb_data_p;
826
827 /* Rx */
828 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
829 " rx_comp_prod(0x%x)"
830 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
831 i, fp->rx_bd_prod, fp->rx_bd_cons,
832 fp->rx_comp_prod,
833 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
834 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
835 " fp_hc_idx(0x%x)\n",
836 fp->rx_sge_prod, fp->last_max_sge,
837 le16_to_cpu(fp->fp_hc_idx));
838
839 /* Tx */
840 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
841 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
842 " *tx_cons_sb(0x%x)\n",
843 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
844 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
845
846 loop = CHIP_IS_E1x(bp) ?
847 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
848
849 /* host sb data */
850
851 #ifdef BCM_CNIC
852 if (IS_FCOE_FP(fp))
853 continue;
854 #endif
855 BNX2X_ERR(" run indexes (");
856 for (j = 0; j < HC_SB_MAX_SM; j++)
857 pr_cont("0x%x%s",
858 fp->sb_running_index[j],
859 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
860
861 BNX2X_ERR(" indexes (");
862 for (j = 0; j < loop; j++)
863 pr_cont("0x%x%s",
864 fp->sb_index_values[j],
865 (j == loop - 1) ? ")" : " ");
866 /* fw sb data */
867 data_size = CHIP_IS_E1x(bp) ?
868 sizeof(struct hc_status_block_data_e1x) :
869 sizeof(struct hc_status_block_data_e2);
870 data_size /= sizeof(u32);
871 sb_data_p = CHIP_IS_E1x(bp) ?
872 (u32 *)&sb_data_e1x :
873 (u32 *)&sb_data_e2;
874 /* copy sb data in here */
875 for (j = 0; j < data_size; j++)
876 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
877 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
878 j * sizeof(u32));
879
880 if (!CHIP_IS_E1x(bp)) {
881 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
882 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
883 "state(0x%x)\n",
884 sb_data_e2.common.p_func.pf_id,
885 sb_data_e2.common.p_func.vf_id,
886 sb_data_e2.common.p_func.vf_valid,
887 sb_data_e2.common.p_func.vnic_id,
888 sb_data_e2.common.same_igu_sb_1b,
889 sb_data_e2.common.state);
890 } else {
891 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
892 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
893 "state(0x%x)\n",
894 sb_data_e1x.common.p_func.pf_id,
895 sb_data_e1x.common.p_func.vf_id,
896 sb_data_e1x.common.p_func.vf_valid,
897 sb_data_e1x.common.p_func.vnic_id,
898 sb_data_e1x.common.same_igu_sb_1b,
899 sb_data_e1x.common.state);
900 }
901
902 /* SB_SMs data */
903 for (j = 0; j < HC_SB_MAX_SM; j++) {
904 pr_cont("SM[%d] __flags (0x%x) "
905 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
906 "time_to_expire (0x%x) "
907 "timer_value(0x%x)\n", j,
908 hc_sm_p[j].__flags,
909 hc_sm_p[j].igu_sb_id,
910 hc_sm_p[j].igu_seg_id,
911 hc_sm_p[j].time_to_expire,
912 hc_sm_p[j].timer_value);
913 }
914
915 /* Indecies data */
916 for (j = 0; j < loop; j++) {
917 pr_cont("INDEX[%d] flags (0x%x) "
918 "timeout (0x%x)\n", j,
919 hc_index_p[j].flags,
920 hc_index_p[j].timeout);
921 }
922 }
923
924 #ifdef BNX2X_STOP_ON_ERROR
925 /* Rings */
926 /* Rx */
927 for_each_rx_queue(bp, i) {
928 struct bnx2x_fastpath *fp = &bp->fp[i];
929
930 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
931 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
932 for (j = start; j != end; j = RX_BD(j + 1)) {
933 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
934 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
935
936 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
937 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
938 }
939
940 start = RX_SGE(fp->rx_sge_prod);
941 end = RX_SGE(fp->last_max_sge);
942 for (j = start; j != end; j = RX_SGE(j + 1)) {
943 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
944 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
945
946 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
947 i, j, rx_sge[1], rx_sge[0], sw_page->page);
948 }
949
950 start = RCQ_BD(fp->rx_comp_cons - 10);
951 end = RCQ_BD(fp->rx_comp_cons + 503);
952 for (j = start; j != end; j = RCQ_BD(j + 1)) {
953 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
954
955 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
956 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
957 }
958 }
959
960 /* Tx */
961 for_each_tx_queue(bp, i) {
962 struct bnx2x_fastpath *fp = &bp->fp[i];
963
964 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
965 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
966 for (j = start; j != end; j = TX_BD(j + 1)) {
967 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
968
969 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
970 i, j, sw_bd->skb, sw_bd->first_bd);
971 }
972
973 start = TX_BD(fp->tx_bd_cons - 10);
974 end = TX_BD(fp->tx_bd_cons + 254);
975 for (j = start; j != end; j = TX_BD(j + 1)) {
976 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
977
978 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
979 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
980 }
981 }
982 #endif
983 bnx2x_fw_dump(bp);
984 bnx2x_mc_assert(bp);
985 BNX2X_ERR("end crash dump -----------------\n");
986 }
987
988 /*
989 * FLR Support for E2
990 *
991 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
992 * initialization.
993 */
994 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
995 #define FLR_WAIT_INTERAVAL 50 /* usec */
996 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
997
998 struct pbf_pN_buf_regs {
999 int pN;
1000 u32 init_crd;
1001 u32 crd;
1002 u32 crd_freed;
1003 };
1004
1005 struct pbf_pN_cmd_regs {
1006 int pN;
1007 u32 lines_occup;
1008 u32 lines_freed;
1009 };
1010
1011 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1012 struct pbf_pN_buf_regs *regs,
1013 u32 poll_count)
1014 {
1015 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1016 u32 cur_cnt = poll_count;
1017
1018 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1019 crd = crd_start = REG_RD(bp, regs->crd);
1020 init_crd = REG_RD(bp, regs->init_crd);
1021
1022 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1023 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1024 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1025
1026 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1027 (init_crd - crd_start))) {
1028 if (cur_cnt--) {
1029 udelay(FLR_WAIT_INTERAVAL);
1030 crd = REG_RD(bp, regs->crd);
1031 crd_freed = REG_RD(bp, regs->crd_freed);
1032 } else {
1033 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1034 regs->pN);
1035 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1036 regs->pN, crd);
1037 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1038 regs->pN, crd_freed);
1039 break;
1040 }
1041 }
1042 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1043 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1044 }
1045
1046 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1047 struct pbf_pN_cmd_regs *regs,
1048 u32 poll_count)
1049 {
1050 u32 occup, to_free, freed, freed_start;
1051 u32 cur_cnt = poll_count;
1052
1053 occup = to_free = REG_RD(bp, regs->lines_occup);
1054 freed = freed_start = REG_RD(bp, regs->lines_freed);
1055
1056 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1057 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1058
1059 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1060 if (cur_cnt--) {
1061 udelay(FLR_WAIT_INTERAVAL);
1062 occup = REG_RD(bp, regs->lines_occup);
1063 freed = REG_RD(bp, regs->lines_freed);
1064 } else {
1065 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1066 regs->pN);
1067 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1068 regs->pN, occup);
1069 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1070 regs->pN, freed);
1071 break;
1072 }
1073 }
1074 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1075 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1076 }
1077
1078 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1079 u32 expected, u32 poll_count)
1080 {
1081 u32 cur_cnt = poll_count;
1082 u32 val;
1083
1084 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1085 udelay(FLR_WAIT_INTERAVAL);
1086
1087 return val;
1088 }
1089
1090 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1091 char *msg, u32 poll_cnt)
1092 {
1093 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1094 if (val != 0) {
1095 BNX2X_ERR("%s usage count=%d\n", msg, val);
1096 return 1;
1097 }
1098 return 0;
1099 }
1100
1101 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1102 {
1103 /* adjust polling timeout */
1104 if (CHIP_REV_IS_EMUL(bp))
1105 return FLR_POLL_CNT * 2000;
1106
1107 if (CHIP_REV_IS_FPGA(bp))
1108 return FLR_POLL_CNT * 120;
1109
1110 return FLR_POLL_CNT;
1111 }
1112
1113 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1114 {
1115 struct pbf_pN_cmd_regs cmd_regs[] = {
1116 {0, (CHIP_IS_E3B0(bp)) ?
1117 PBF_REG_TQ_OCCUPANCY_Q0 :
1118 PBF_REG_P0_TQ_OCCUPANCY,
1119 (CHIP_IS_E3B0(bp)) ?
1120 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1121 PBF_REG_P0_TQ_LINES_FREED_CNT},
1122 {1, (CHIP_IS_E3B0(bp)) ?
1123 PBF_REG_TQ_OCCUPANCY_Q1 :
1124 PBF_REG_P1_TQ_OCCUPANCY,
1125 (CHIP_IS_E3B0(bp)) ?
1126 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1127 PBF_REG_P1_TQ_LINES_FREED_CNT},
1128 {4, (CHIP_IS_E3B0(bp)) ?
1129 PBF_REG_TQ_OCCUPANCY_LB_Q :
1130 PBF_REG_P4_TQ_OCCUPANCY,
1131 (CHIP_IS_E3B0(bp)) ?
1132 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1133 PBF_REG_P4_TQ_LINES_FREED_CNT}
1134 };
1135
1136 struct pbf_pN_buf_regs buf_regs[] = {
1137 {0, (CHIP_IS_E3B0(bp)) ?
1138 PBF_REG_INIT_CRD_Q0 :
1139 PBF_REG_P0_INIT_CRD ,
1140 (CHIP_IS_E3B0(bp)) ?
1141 PBF_REG_CREDIT_Q0 :
1142 PBF_REG_P0_CREDIT,
1143 (CHIP_IS_E3B0(bp)) ?
1144 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1145 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1146 {1, (CHIP_IS_E3B0(bp)) ?
1147 PBF_REG_INIT_CRD_Q1 :
1148 PBF_REG_P1_INIT_CRD,
1149 (CHIP_IS_E3B0(bp)) ?
1150 PBF_REG_CREDIT_Q1 :
1151 PBF_REG_P1_CREDIT,
1152 (CHIP_IS_E3B0(bp)) ?
1153 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1154 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1155 {4, (CHIP_IS_E3B0(bp)) ?
1156 PBF_REG_INIT_CRD_LB_Q :
1157 PBF_REG_P4_INIT_CRD,
1158 (CHIP_IS_E3B0(bp)) ?
1159 PBF_REG_CREDIT_LB_Q :
1160 PBF_REG_P4_CREDIT,
1161 (CHIP_IS_E3B0(bp)) ?
1162 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1163 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1164 };
1165
1166 int i;
1167
1168 /* Verify the command queues are flushed P0, P1, P4 */
1169 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1170 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1171
1172
1173 /* Verify the transmission buffers are flushed P0, P1, P4 */
1174 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1175 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1176 }
1177
1178 #define OP_GEN_PARAM(param) \
1179 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1180
1181 #define OP_GEN_TYPE(type) \
1182 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1183
1184 #define OP_GEN_AGG_VECT(index) \
1185 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1186
1187
1188 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1189 u32 poll_cnt)
1190 {
1191 struct sdm_op_gen op_gen = {0};
1192
1193 u32 comp_addr = BAR_CSTRORM_INTMEM +
1194 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1195 int ret = 0;
1196
1197 if (REG_RD(bp, comp_addr)) {
1198 BNX2X_ERR("Cleanup complete is not 0\n");
1199 return 1;
1200 }
1201
1202 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1203 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1204 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1205 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1206
1207 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1208 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1209
1210 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1211 BNX2X_ERR("FW final cleanup did not succeed\n");
1212 ret = 1;
1213 }
1214 /* Zero completion for nxt FLR */
1215 REG_WR(bp, comp_addr, 0);
1216
1217 return ret;
1218 }
1219
1220 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1221 {
1222 int pos;
1223 u16 status;
1224
1225 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1226 if (!pos)
1227 return false;
1228
1229 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1230 return status & PCI_EXP_DEVSTA_TRPND;
1231 }
1232
1233 /* PF FLR specific routines
1234 */
1235 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1236 {
1237
1238 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1239 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1240 CFC_REG_NUM_LCIDS_INSIDE_PF,
1241 "CFC PF usage counter timed out",
1242 poll_cnt))
1243 return 1;
1244
1245
1246 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1247 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1248 DORQ_REG_PF_USAGE_CNT,
1249 "DQ PF usage counter timed out",
1250 poll_cnt))
1251 return 1;
1252
1253 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1256 "QM PF usage counter timed out",
1257 poll_cnt))
1258 return 1;
1259
1260 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1261 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1262 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1263 "Timers VNIC usage counter timed out",
1264 poll_cnt))
1265 return 1;
1266 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1267 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1268 "Timers NUM_SCANS usage counter timed out",
1269 poll_cnt))
1270 return 1;
1271
1272 /* Wait DMAE PF usage counter to zero */
1273 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1274 dmae_reg_go_c[INIT_DMAE_C(bp)],
1275 "DMAE dommand register timed out",
1276 poll_cnt))
1277 return 1;
1278
1279 return 0;
1280 }
1281
1282 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1283 {
1284 u32 val;
1285
1286 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1287 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1288
1289 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1290 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1291
1292 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1293 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1294
1295 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1296 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1297
1298 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1299 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1300
1301 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1302 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1303
1304 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1305 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1306
1307 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1308 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1309 val);
1310 }
1311
1312 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1313 {
1314 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1315
1316 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1317
1318 /* Re-enable PF target read access */
1319 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1320
1321 /* Poll HW usage counters */
1322 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1323 return -EBUSY;
1324
1325 /* Zero the igu 'trailing edge' and 'leading edge' */
1326
1327 /* Send the FW cleanup command */
1328 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1329 return -EBUSY;
1330
1331 /* ATC cleanup */
1332
1333 /* Verify TX hw is flushed */
1334 bnx2x_tx_hw_flushed(bp, poll_cnt);
1335
1336 /* Wait 100ms (not adjusted according to platform) */
1337 msleep(100);
1338
1339 /* Verify no pending pci transactions */
1340 if (bnx2x_is_pcie_pending(bp->pdev))
1341 BNX2X_ERR("PCIE Transactions still pending\n");
1342
1343 /* Debug */
1344 bnx2x_hw_enable_status(bp);
1345
1346 /*
1347 * Master enable - Due to WB DMAE writes performed before this
1348 * register is re-initialized as part of the regular function init
1349 */
1350 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1351
1352 return 0;
1353 }
1354
1355 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1356 {
1357 int port = BP_PORT(bp);
1358 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1359 u32 val = REG_RD(bp, addr);
1360 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1361 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1362
1363 if (msix) {
1364 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1365 HC_CONFIG_0_REG_INT_LINE_EN_0);
1366 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1367 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1368 } else if (msi) {
1369 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1370 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1371 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1372 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1373 } else {
1374 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1375 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1376 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1377 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1378
1379 if (!CHIP_IS_E1(bp)) {
1380 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1381 val, port, addr);
1382
1383 REG_WR(bp, addr, val);
1384
1385 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1386 }
1387 }
1388
1389 if (CHIP_IS_E1(bp))
1390 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1391
1392 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1393 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1394
1395 REG_WR(bp, addr, val);
1396 /*
1397 * Ensure that HC_CONFIG is written before leading/trailing edge config
1398 */
1399 mmiowb();
1400 barrier();
1401
1402 if (!CHIP_IS_E1(bp)) {
1403 /* init leading/trailing edge */
1404 if (IS_MF(bp)) {
1405 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1406 if (bp->port.pmf)
1407 /* enable nig and gpio3 attention */
1408 val |= 0x1100;
1409 } else
1410 val = 0xffff;
1411
1412 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1413 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1414 }
1415
1416 /* Make sure that interrupts are indeed enabled from here on */
1417 mmiowb();
1418 }
1419
1420 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1421 {
1422 u32 val;
1423 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1424 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1425
1426 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1427
1428 if (msix) {
1429 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1430 IGU_PF_CONF_SINGLE_ISR_EN);
1431 val |= (IGU_PF_CONF_FUNC_EN |
1432 IGU_PF_CONF_MSI_MSIX_EN |
1433 IGU_PF_CONF_ATTN_BIT_EN);
1434 } else if (msi) {
1435 val &= ~IGU_PF_CONF_INT_LINE_EN;
1436 val |= (IGU_PF_CONF_FUNC_EN |
1437 IGU_PF_CONF_MSI_MSIX_EN |
1438 IGU_PF_CONF_ATTN_BIT_EN |
1439 IGU_PF_CONF_SINGLE_ISR_EN);
1440 } else {
1441 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1442 val |= (IGU_PF_CONF_FUNC_EN |
1443 IGU_PF_CONF_INT_LINE_EN |
1444 IGU_PF_CONF_ATTN_BIT_EN |
1445 IGU_PF_CONF_SINGLE_ISR_EN);
1446 }
1447
1448 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1449 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1450
1451 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1452
1453 barrier();
1454
1455 /* init leading/trailing edge */
1456 if (IS_MF(bp)) {
1457 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1458 if (bp->port.pmf)
1459 /* enable nig and gpio3 attention */
1460 val |= 0x1100;
1461 } else
1462 val = 0xffff;
1463
1464 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1465 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1466
1467 /* Make sure that interrupts are indeed enabled from here on */
1468 mmiowb();
1469 }
1470
1471 void bnx2x_int_enable(struct bnx2x *bp)
1472 {
1473 if (bp->common.int_block == INT_BLOCK_HC)
1474 bnx2x_hc_int_enable(bp);
1475 else
1476 bnx2x_igu_int_enable(bp);
1477 }
1478
1479 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1480 {
1481 int port = BP_PORT(bp);
1482 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1483 u32 val = REG_RD(bp, addr);
1484
1485 /*
1486 * in E1 we must use only PCI configuration space to disable
1487 * MSI/MSIX capablility
1488 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1489 */
1490 if (CHIP_IS_E1(bp)) {
1491 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1492 * Use mask register to prevent from HC sending interrupts
1493 * after we exit the function
1494 */
1495 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1496
1497 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1498 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1499 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1500 } else
1501 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1502 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1503 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1504 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1505
1506 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1507 val, port, addr);
1508
1509 /* flush all outstanding writes */
1510 mmiowb();
1511
1512 REG_WR(bp, addr, val);
1513 if (REG_RD(bp, addr) != val)
1514 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1515 }
1516
1517 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1518 {
1519 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1520
1521 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1522 IGU_PF_CONF_INT_LINE_EN |
1523 IGU_PF_CONF_ATTN_BIT_EN);
1524
1525 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1526
1527 /* flush all outstanding writes */
1528 mmiowb();
1529
1530 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1531 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1532 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1533 }
1534
1535 static void bnx2x_int_disable(struct bnx2x *bp)
1536 {
1537 if (bp->common.int_block == INT_BLOCK_HC)
1538 bnx2x_hc_int_disable(bp);
1539 else
1540 bnx2x_igu_int_disable(bp);
1541 }
1542
1543 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1544 {
1545 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1546 int i, offset;
1547
1548 if (disable_hw)
1549 /* prevent the HW from sending interrupts */
1550 bnx2x_int_disable(bp);
1551
1552 /* make sure all ISRs are done */
1553 if (msix) {
1554 synchronize_irq(bp->msix_table[0].vector);
1555 offset = 1;
1556 #ifdef BCM_CNIC
1557 offset++;
1558 #endif
1559 for_each_eth_queue(bp, i)
1560 synchronize_irq(bp->msix_table[offset++].vector);
1561 } else
1562 synchronize_irq(bp->pdev->irq);
1563
1564 /* make sure sp_task is not running */
1565 cancel_delayed_work(&bp->sp_task);
1566 flush_workqueue(bnx2x_wq);
1567 }
1568
1569 /* fast path */
1570
1571 /*
1572 * General service functions
1573 */
1574
1575 /* Return true if succeeded to acquire the lock */
1576 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1577 {
1578 u32 lock_status;
1579 u32 resource_bit = (1 << resource);
1580 int func = BP_FUNC(bp);
1581 u32 hw_lock_control_reg;
1582
1583 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1584
1585 /* Validating that the resource is within range */
1586 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1587 DP(NETIF_MSG_HW,
1588 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1589 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1590 return false;
1591 }
1592
1593 if (func <= 5)
1594 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1595 else
1596 hw_lock_control_reg =
1597 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1598
1599 /* Try to acquire the lock */
1600 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1601 lock_status = REG_RD(bp, hw_lock_control_reg);
1602 if (lock_status & resource_bit)
1603 return true;
1604
1605 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1606 return false;
1607 }
1608
1609 /**
1610 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1611 *
1612 * @bp: driver handle
1613 *
1614 * Returns the recovery leader resource id according to the engine this function
1615 * belongs to. Currently only only 2 engines is supported.
1616 */
1617 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1618 {
1619 if (BP_PATH(bp))
1620 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1621 else
1622 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1623 }
1624
1625 /**
1626 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1627 *
1628 * @bp: driver handle
1629 *
1630 * Tries to aquire a leader lock for cuurent engine.
1631 */
1632 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1633 {
1634 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1635 }
1636
1637 #ifdef BCM_CNIC
1638 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1639 #endif
1640
1641 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1642 {
1643 struct bnx2x *bp = fp->bp;
1644 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1645 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1646 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1647 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1648
1649 DP(BNX2X_MSG_SP,
1650 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1651 fp->index, cid, command, bp->state,
1652 rr_cqe->ramrod_cqe.ramrod_type);
1653
1654 switch (command) {
1655 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1656 DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid);
1657 drv_cmd = BNX2X_Q_CMD_UPDATE;
1658 break;
1659 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1660 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1661 drv_cmd = BNX2X_Q_CMD_SETUP;
1662 break;
1663
1664 case (RAMROD_CMD_ID_ETH_HALT):
1665 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1666 drv_cmd = BNX2X_Q_CMD_HALT;
1667 break;
1668
1669 case (RAMROD_CMD_ID_ETH_TERMINATE):
1670 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1671 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1672 break;
1673
1674 case (RAMROD_CMD_ID_ETH_EMPTY):
1675 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid);
1676 drv_cmd = BNX2X_Q_CMD_EMPTY;
1677 break;
1678
1679 default:
1680 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1681 command, fp->index);
1682 return;
1683 }
1684
1685 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1686 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1687 /* q_obj->complete_cmd() failure means that this was
1688 * an unexpected completion.
1689 *
1690 * In this case we don't want to increase the bp->spq_left
1691 * because apparently we haven't sent this command the first
1692 * place.
1693 */
1694 #ifdef BNX2X_STOP_ON_ERROR
1695 bnx2x_panic();
1696 #else
1697 return;
1698 #endif
1699
1700 smp_mb__before_atomic_inc();
1701 atomic_inc(&bp->cq_spq_left);
1702 /* push the change in bp->spq_left and towards the memory */
1703 smp_mb__after_atomic_inc();
1704
1705 return;
1706 }
1707
1708 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1709 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1710 {
1711 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1712
1713 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1714 start);
1715 }
1716
1717 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1718 {
1719 struct bnx2x *bp = netdev_priv(dev_instance);
1720 u16 status = bnx2x_ack_int(bp);
1721 u16 mask;
1722 int i;
1723
1724 /* Return here if interrupt is shared and it's not for us */
1725 if (unlikely(status == 0)) {
1726 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1727 return IRQ_NONE;
1728 }
1729 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1730
1731 #ifdef BNX2X_STOP_ON_ERROR
1732 if (unlikely(bp->panic))
1733 return IRQ_HANDLED;
1734 #endif
1735
1736 for_each_eth_queue(bp, i) {
1737 struct bnx2x_fastpath *fp = &bp->fp[i];
1738
1739 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1740 if (status & mask) {
1741 /* Handle Rx or Tx according to SB id */
1742 prefetch(fp->rx_cons_sb);
1743 prefetch(fp->tx_cons_sb);
1744 prefetch(&fp->sb_running_index[SM_RX_ID]);
1745 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1746 status &= ~mask;
1747 }
1748 }
1749
1750 #ifdef BCM_CNIC
1751 mask = 0x2;
1752 if (status & (mask | 0x1)) {
1753 struct cnic_ops *c_ops = NULL;
1754
1755 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1756 rcu_read_lock();
1757 c_ops = rcu_dereference(bp->cnic_ops);
1758 if (c_ops)
1759 c_ops->cnic_handler(bp->cnic_data, NULL);
1760 rcu_read_unlock();
1761 }
1762
1763 status &= ~mask;
1764 }
1765 #endif
1766
1767 if (unlikely(status & 0x1)) {
1768 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1769
1770 status &= ~0x1;
1771 if (!status)
1772 return IRQ_HANDLED;
1773 }
1774
1775 if (unlikely(status))
1776 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1777 status);
1778
1779 return IRQ_HANDLED;
1780 }
1781
1782 /* Link */
1783
1784 /*
1785 * General service functions
1786 */
1787
1788 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1789 {
1790 u32 lock_status;
1791 u32 resource_bit = (1 << resource);
1792 int func = BP_FUNC(bp);
1793 u32 hw_lock_control_reg;
1794 int cnt;
1795
1796 /* Validating that the resource is within range */
1797 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1798 DP(NETIF_MSG_HW,
1799 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1800 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1801 return -EINVAL;
1802 }
1803
1804 if (func <= 5) {
1805 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1806 } else {
1807 hw_lock_control_reg =
1808 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1809 }
1810
1811 /* Validating that the resource is not already taken */
1812 lock_status = REG_RD(bp, hw_lock_control_reg);
1813 if (lock_status & resource_bit) {
1814 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1815 lock_status, resource_bit);
1816 return -EEXIST;
1817 }
1818
1819 /* Try for 5 second every 5ms */
1820 for (cnt = 0; cnt < 1000; cnt++) {
1821 /* Try to acquire the lock */
1822 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1823 lock_status = REG_RD(bp, hw_lock_control_reg);
1824 if (lock_status & resource_bit)
1825 return 0;
1826
1827 msleep(5);
1828 }
1829 DP(NETIF_MSG_HW, "Timeout\n");
1830 return -EAGAIN;
1831 }
1832
1833 int bnx2x_release_leader_lock(struct bnx2x *bp)
1834 {
1835 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1836 }
1837
1838 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1839 {
1840 u32 lock_status;
1841 u32 resource_bit = (1 << resource);
1842 int func = BP_FUNC(bp);
1843 u32 hw_lock_control_reg;
1844
1845 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1846
1847 /* Validating that the resource is within range */
1848 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1849 DP(NETIF_MSG_HW,
1850 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1851 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1852 return -EINVAL;
1853 }
1854
1855 if (func <= 5) {
1856 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1857 } else {
1858 hw_lock_control_reg =
1859 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1860 }
1861
1862 /* Validating that the resource is currently taken */
1863 lock_status = REG_RD(bp, hw_lock_control_reg);
1864 if (!(lock_status & resource_bit)) {
1865 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1866 lock_status, resource_bit);
1867 return -EFAULT;
1868 }
1869
1870 REG_WR(bp, hw_lock_control_reg, resource_bit);
1871 return 0;
1872 }
1873
1874
1875 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1876 {
1877 /* The GPIO should be swapped if swap register is set and active */
1878 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1879 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1880 int gpio_shift = gpio_num +
1881 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1882 u32 gpio_mask = (1 << gpio_shift);
1883 u32 gpio_reg;
1884 int value;
1885
1886 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1887 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1888 return -EINVAL;
1889 }
1890
1891 /* read GPIO value */
1892 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1893
1894 /* get the requested pin value */
1895 if ((gpio_reg & gpio_mask) == gpio_mask)
1896 value = 1;
1897 else
1898 value = 0;
1899
1900 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1901
1902 return value;
1903 }
1904
1905 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1906 {
1907 /* The GPIO should be swapped if swap register is set and active */
1908 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1909 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1910 int gpio_shift = gpio_num +
1911 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1912 u32 gpio_mask = (1 << gpio_shift);
1913 u32 gpio_reg;
1914
1915 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1916 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1917 return -EINVAL;
1918 }
1919
1920 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1921 /* read GPIO and mask except the float bits */
1922 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1923
1924 switch (mode) {
1925 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1926 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1927 gpio_num, gpio_shift);
1928 /* clear FLOAT and set CLR */
1929 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1930 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1931 break;
1932
1933 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1934 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1935 gpio_num, gpio_shift);
1936 /* clear FLOAT and set SET */
1937 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1938 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1939 break;
1940
1941 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1942 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1943 gpio_num, gpio_shift);
1944 /* set FLOAT */
1945 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1946 break;
1947
1948 default:
1949 break;
1950 }
1951
1952 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1953 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1954
1955 return 0;
1956 }
1957
1958 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1959 {
1960 /* The GPIO should be swapped if swap register is set and active */
1961 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1962 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1963 int gpio_shift = gpio_num +
1964 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1965 u32 gpio_mask = (1 << gpio_shift);
1966 u32 gpio_reg;
1967
1968 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1969 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1970 return -EINVAL;
1971 }
1972
1973 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1974 /* read GPIO int */
1975 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1976
1977 switch (mode) {
1978 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1979 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1980 "output low\n", gpio_num, gpio_shift);
1981 /* clear SET and set CLR */
1982 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1983 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1984 break;
1985
1986 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1987 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1988 "output high\n", gpio_num, gpio_shift);
1989 /* clear CLR and set SET */
1990 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1991 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1992 break;
1993
1994 default:
1995 break;
1996 }
1997
1998 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1999 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2000
2001 return 0;
2002 }
2003
2004 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2005 {
2006 u32 spio_mask = (1 << spio_num);
2007 u32 spio_reg;
2008
2009 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2010 (spio_num > MISC_REGISTERS_SPIO_7)) {
2011 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2012 return -EINVAL;
2013 }
2014
2015 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2016 /* read SPIO and mask except the float bits */
2017 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2018
2019 switch (mode) {
2020 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2021 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2022 /* clear FLOAT and set CLR */
2023 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2024 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2025 break;
2026
2027 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2028 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2029 /* clear FLOAT and set SET */
2030 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2031 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2032 break;
2033
2034 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2035 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2036 /* set FLOAT */
2037 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2038 break;
2039
2040 default:
2041 break;
2042 }
2043
2044 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2045 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2046
2047 return 0;
2048 }
2049
2050 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2051 {
2052 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2053 switch (bp->link_vars.ieee_fc &
2054 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2055 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2056 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2057 ADVERTISED_Pause);
2058 break;
2059
2060 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2061 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2062 ADVERTISED_Pause);
2063 break;
2064
2065 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2066 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2067 break;
2068
2069 default:
2070 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2071 ADVERTISED_Pause);
2072 break;
2073 }
2074 }
2075
2076 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2077 {
2078 if (!BP_NOMCP(bp)) {
2079 u8 rc;
2080 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2081 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2082 /* Initialize link parameters structure variables */
2083 /* It is recommended to turn off RX FC for jumbo frames
2084 for better performance */
2085 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
2086 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2087 else
2088 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2089
2090 bnx2x_acquire_phy_lock(bp);
2091
2092 if (load_mode == LOAD_DIAG) {
2093 bp->link_params.loopback_mode = LOOPBACK_XGXS;
2094 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
2095 }
2096
2097 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2098
2099 bnx2x_release_phy_lock(bp);
2100
2101 bnx2x_calc_fc_adv(bp);
2102
2103 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2104 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2105 bnx2x_link_report(bp);
2106 }
2107 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2108 return rc;
2109 }
2110 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2111 return -EINVAL;
2112 }
2113
2114 void bnx2x_link_set(struct bnx2x *bp)
2115 {
2116 if (!BP_NOMCP(bp)) {
2117 bnx2x_acquire_phy_lock(bp);
2118 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2119 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2120 bnx2x_release_phy_lock(bp);
2121
2122 bnx2x_calc_fc_adv(bp);
2123 } else
2124 BNX2X_ERR("Bootcode is missing - can not set link\n");
2125 }
2126
2127 static void bnx2x__link_reset(struct bnx2x *bp)
2128 {
2129 if (!BP_NOMCP(bp)) {
2130 bnx2x_acquire_phy_lock(bp);
2131 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2132 bnx2x_release_phy_lock(bp);
2133 } else
2134 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2135 }
2136
2137 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2138 {
2139 u8 rc = 0;
2140
2141 if (!BP_NOMCP(bp)) {
2142 bnx2x_acquire_phy_lock(bp);
2143 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2144 is_serdes);
2145 bnx2x_release_phy_lock(bp);
2146 } else
2147 BNX2X_ERR("Bootcode is missing - can not test link\n");
2148
2149 return rc;
2150 }
2151
2152 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2153 {
2154 u32 r_param = bp->link_vars.line_speed / 8;
2155 u32 fair_periodic_timeout_usec;
2156 u32 t_fair;
2157
2158 memset(&(bp->cmng.rs_vars), 0,
2159 sizeof(struct rate_shaping_vars_per_port));
2160 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2161
2162 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2163 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2164
2165 /* this is the threshold below which no timer arming will occur
2166 1.25 coefficient is for the threshold to be a little bigger
2167 than the real time, to compensate for timer in-accuracy */
2168 bp->cmng.rs_vars.rs_threshold =
2169 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2170
2171 /* resolution of fairness timer */
2172 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2173 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2174 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2175
2176 /* this is the threshold below which we won't arm the timer anymore */
2177 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2178
2179 /* we multiply by 1e3/8 to get bytes/msec.
2180 We don't want the credits to pass a credit
2181 of the t_fair*FAIR_MEM (algorithm resolution) */
2182 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2183 /* since each tick is 4 usec */
2184 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2185 }
2186
2187 /* Calculates the sum of vn_min_rates.
2188 It's needed for further normalizing of the min_rates.
2189 Returns:
2190 sum of vn_min_rates.
2191 or
2192 0 - if all the min_rates are 0.
2193 In the later case fainess algorithm should be deactivated.
2194 If not all min_rates are zero then those that are zeroes will be set to 1.
2195 */
2196 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2197 {
2198 int all_zero = 1;
2199 int vn;
2200
2201 bp->vn_weight_sum = 0;
2202 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2203 u32 vn_cfg = bp->mf_config[vn];
2204 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2205 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2206
2207 /* Skip hidden vns */
2208 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2209 continue;
2210
2211 /* If min rate is zero - set it to 1 */
2212 if (!vn_min_rate)
2213 vn_min_rate = DEF_MIN_RATE;
2214 else
2215 all_zero = 0;
2216
2217 bp->vn_weight_sum += vn_min_rate;
2218 }
2219
2220 /* if ETS or all min rates are zeros - disable fairness */
2221 if (BNX2X_IS_ETS_ENABLED(bp)) {
2222 bp->cmng.flags.cmng_enables &=
2223 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2224 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2225 } else if (all_zero) {
2226 bp->cmng.flags.cmng_enables &=
2227 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2228 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2229 " fairness will be disabled\n");
2230 } else
2231 bp->cmng.flags.cmng_enables |=
2232 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2233 }
2234
2235 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2236 {
2237 struct rate_shaping_vars_per_vn m_rs_vn;
2238 struct fairness_vars_per_vn m_fair_vn;
2239 u32 vn_cfg = bp->mf_config[vn];
2240 int func = 2*vn + BP_PORT(bp);
2241 u16 vn_min_rate, vn_max_rate;
2242 int i;
2243
2244 /* If function is hidden - set min and max to zeroes */
2245 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2246 vn_min_rate = 0;
2247 vn_max_rate = 0;
2248
2249 } else {
2250 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2251
2252 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2253 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2254 /* If fairness is enabled (not all min rates are zeroes) and
2255 if current min rate is zero - set it to 1.
2256 This is a requirement of the algorithm. */
2257 if (bp->vn_weight_sum && (vn_min_rate == 0))
2258 vn_min_rate = DEF_MIN_RATE;
2259
2260 if (IS_MF_SI(bp))
2261 /* maxCfg in percents of linkspeed */
2262 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2263 else
2264 /* maxCfg is absolute in 100Mb units */
2265 vn_max_rate = maxCfg * 100;
2266 }
2267
2268 DP(NETIF_MSG_IFUP,
2269 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2270 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2271
2272 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2273 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2274
2275 /* global vn counter - maximal Mbps for this vn */
2276 m_rs_vn.vn_counter.rate = vn_max_rate;
2277
2278 /* quota - number of bytes transmitted in this period */
2279 m_rs_vn.vn_counter.quota =
2280 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2281
2282 if (bp->vn_weight_sum) {
2283 /* credit for each period of the fairness algorithm:
2284 number of bytes in T_FAIR (the vn share the port rate).
2285 vn_weight_sum should not be larger than 10000, thus
2286 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2287 than zero */
2288 m_fair_vn.vn_credit_delta =
2289 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2290 (8 * bp->vn_weight_sum))),
2291 (bp->cmng.fair_vars.fair_threshold +
2292 MIN_ABOVE_THRESH));
2293 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2294 m_fair_vn.vn_credit_delta);
2295 }
2296
2297 /* Store it to internal memory */
2298 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2299 REG_WR(bp, BAR_XSTRORM_INTMEM +
2300 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2301 ((u32 *)(&m_rs_vn))[i]);
2302
2303 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2304 REG_WR(bp, BAR_XSTRORM_INTMEM +
2305 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2306 ((u32 *)(&m_fair_vn))[i]);
2307 }
2308
2309 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2310 {
2311 if (CHIP_REV_IS_SLOW(bp))
2312 return CMNG_FNS_NONE;
2313 if (IS_MF(bp))
2314 return CMNG_FNS_MINMAX;
2315
2316 return CMNG_FNS_NONE;
2317 }
2318
2319 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2320 {
2321 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2322
2323 if (BP_NOMCP(bp))
2324 return; /* what should be the default bvalue in this case */
2325
2326 /* For 2 port configuration the absolute function number formula
2327 * is:
2328 * abs_func = 2 * vn + BP_PORT + BP_PATH
2329 *
2330 * and there are 4 functions per port
2331 *
2332 * For 4 port configuration it is
2333 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2334 *
2335 * and there are 2 functions per port
2336 */
2337 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2338 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2339
2340 if (func >= E1H_FUNC_MAX)
2341 break;
2342
2343 bp->mf_config[vn] =
2344 MF_CFG_RD(bp, func_mf_config[func].config);
2345 }
2346 }
2347
2348 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2349 {
2350
2351 if (cmng_type == CMNG_FNS_MINMAX) {
2352 int vn;
2353
2354 /* clear cmng_enables */
2355 bp->cmng.flags.cmng_enables = 0;
2356
2357 /* read mf conf from shmem */
2358 if (read_cfg)
2359 bnx2x_read_mf_cfg(bp);
2360
2361 /* Init rate shaping and fairness contexts */
2362 bnx2x_init_port_minmax(bp);
2363
2364 /* vn_weight_sum and enable fairness if not 0 */
2365 bnx2x_calc_vn_weight_sum(bp);
2366
2367 /* calculate and set min-max rate for each vn */
2368 if (bp->port.pmf)
2369 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2370 bnx2x_init_vn_minmax(bp, vn);
2371
2372 /* always enable rate shaping and fairness */
2373 bp->cmng.flags.cmng_enables |=
2374 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2375 if (!bp->vn_weight_sum)
2376 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2377 " fairness will be disabled\n");
2378 return;
2379 }
2380
2381 /* rate shaping and fairness are disabled */
2382 DP(NETIF_MSG_IFUP,
2383 "rate shaping and fairness are disabled\n");
2384 }
2385
2386 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2387 {
2388 int port = BP_PORT(bp);
2389 int func;
2390 int vn;
2391
2392 /* Set the attention towards other drivers on the same port */
2393 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2394 if (vn == BP_E1HVN(bp))
2395 continue;
2396
2397 func = ((vn << 1) | port);
2398 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2399 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2400 }
2401 }
2402
2403 /* This function is called upon link interrupt */
2404 static void bnx2x_link_attn(struct bnx2x *bp)
2405 {
2406 /* Make sure that we are synced with the current statistics */
2407 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2408
2409 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2410
2411 if (bp->link_vars.link_up) {
2412
2413 /* dropless flow control */
2414 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2415 int port = BP_PORT(bp);
2416 u32 pause_enabled = 0;
2417
2418 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2419 pause_enabled = 1;
2420
2421 REG_WR(bp, BAR_USTRORM_INTMEM +
2422 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2423 pause_enabled);
2424 }
2425
2426 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2427 struct host_port_stats *pstats;
2428
2429 pstats = bnx2x_sp(bp, port_stats);
2430 /* reset old mac stats */
2431 memset(&(pstats->mac_stx[0]), 0,
2432 sizeof(struct mac_stx));
2433 }
2434 if (bp->state == BNX2X_STATE_OPEN)
2435 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2436 }
2437
2438 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2439 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2440
2441 if (cmng_fns != CMNG_FNS_NONE) {
2442 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2443 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2444 } else
2445 /* rate shaping and fairness are disabled */
2446 DP(NETIF_MSG_IFUP,
2447 "single function mode without fairness\n");
2448 }
2449
2450 __bnx2x_link_report(bp);
2451
2452 if (IS_MF(bp))
2453 bnx2x_link_sync_notify(bp);
2454 }
2455
2456 void bnx2x__link_status_update(struct bnx2x *bp)
2457 {
2458 if (bp->state != BNX2X_STATE_OPEN)
2459 return;
2460
2461 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2462
2463 if (bp->link_vars.link_up)
2464 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2465 else
2466 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2467
2468 /* indicate link status */
2469 bnx2x_link_report(bp);
2470 }
2471
2472 static void bnx2x_pmf_update(struct bnx2x *bp)
2473 {
2474 int port = BP_PORT(bp);
2475 u32 val;
2476
2477 bp->port.pmf = 1;
2478 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2479
2480 bnx2x_dcbx_pmf_update(bp);
2481
2482 /* enable nig attention */
2483 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2484 if (bp->common.int_block == INT_BLOCK_HC) {
2485 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2486 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2487 } else if (!CHIP_IS_E1x(bp)) {
2488 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2489 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2490 }
2491
2492 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2493 }
2494
2495 /* end of Link */
2496
2497 /* slow path */
2498
2499 /*
2500 * General service functions
2501 */
2502
2503 /* send the MCP a request, block until there is a reply */
2504 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2505 {
2506 int mb_idx = BP_FW_MB_IDX(bp);
2507 u32 seq;
2508 u32 rc = 0;
2509 u32 cnt = 1;
2510 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2511
2512 mutex_lock(&bp->fw_mb_mutex);
2513 seq = ++bp->fw_seq;
2514 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2515 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2516
2517 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2518 (command | seq), param);
2519
2520 do {
2521 /* let the FW do it's magic ... */
2522 msleep(delay);
2523
2524 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2525
2526 /* Give the FW up to 5 second (500*10ms) */
2527 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2528
2529 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2530 cnt*delay, rc, seq);
2531
2532 /* is this a reply to our command? */
2533 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2534 rc &= FW_MSG_CODE_MASK;
2535 else {
2536 /* FW BUG! */
2537 BNX2X_ERR("FW failed to respond!\n");
2538 bnx2x_fw_dump(bp);
2539 rc = 0;
2540 }
2541 mutex_unlock(&bp->fw_mb_mutex);
2542
2543 return rc;
2544 }
2545
2546 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2547 {
2548 #ifdef BCM_CNIC
2549 /* Statistics are not supported for CNIC Clients at the moment */
2550 if (IS_FCOE_FP(fp))
2551 return false;
2552 #endif
2553 return true;
2554 }
2555
2556 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2557 {
2558 if (CHIP_IS_E1x(bp)) {
2559 struct tstorm_eth_function_common_config tcfg = {0};
2560
2561 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2562 }
2563
2564 /* Enable the function in the FW */
2565 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2566 storm_memset_func_en(bp, p->func_id, 1);
2567
2568 /* spq */
2569 if (p->func_flgs & FUNC_FLG_SPQ) {
2570 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2571 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2572 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2573 }
2574 }
2575
2576 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2577 struct bnx2x_fastpath *fp,
2578 bool leading)
2579 {
2580 unsigned long flags = 0;
2581
2582 /* PF driver will always initialize the Queue to an ACTIVE state */
2583 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2584
2585 /* calculate other queue flags */
2586 if (IS_MF_SD(bp))
2587 __set_bit(BNX2X_Q_FLG_OV, &flags);
2588
2589 if (IS_FCOE_FP(fp))
2590 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2591
2592 if (!fp->disable_tpa)
2593 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2594
2595 if (stat_counter_valid(bp, fp)) {
2596 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2597 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2598 }
2599
2600 if (leading) {
2601 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2602 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2603 }
2604
2605 /* Always set HW VLAN stripping */
2606 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2607
2608 return flags;
2609 }
2610
2611 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2612 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init)
2613 {
2614 gen_init->stat_id = bnx2x_stats_id(fp);
2615 gen_init->spcl_id = fp->cl_id;
2616
2617 /* Always use mini-jumbo MTU for FCoE L2 ring */
2618 if (IS_FCOE_FP(fp))
2619 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2620 else
2621 gen_init->mtu = bp->dev->mtu;
2622 }
2623
2624 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2625 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2626 struct bnx2x_rxq_setup_params *rxq_init)
2627 {
2628 u8 max_sge = 0;
2629 u16 sge_sz = 0;
2630 u16 tpa_agg_size = 0;
2631
2632 if (!fp->disable_tpa) {
2633 pause->sge_th_hi = 250;
2634 pause->sge_th_lo = 150;
2635 tpa_agg_size = min_t(u32,
2636 (min_t(u32, 8, MAX_SKB_FRAGS) *
2637 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2638 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2639 SGE_PAGE_SHIFT;
2640 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2641 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2642 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2643 0xffff);
2644 }
2645
2646 /* pause - not for e1 */
2647 if (!CHIP_IS_E1(bp)) {
2648 pause->bd_th_hi = 350;
2649 pause->bd_th_lo = 250;
2650 pause->rcq_th_hi = 350;
2651 pause->rcq_th_lo = 250;
2652
2653 pause->pri_map = 1;
2654 }
2655
2656 /* rxq setup */
2657 rxq_init->dscr_map = fp->rx_desc_mapping;
2658 rxq_init->sge_map = fp->rx_sge_mapping;
2659 rxq_init->rcq_map = fp->rx_comp_mapping;
2660 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2661
2662 /* This should be a maximum number of data bytes that may be
2663 * placed on the BD (not including paddings).
2664 */
2665 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2666 IP_HEADER_ALIGNMENT_PADDING;
2667
2668 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2669 rxq_init->tpa_agg_sz = tpa_agg_size;
2670 rxq_init->sge_buf_sz = sge_sz;
2671 rxq_init->max_sges_pkt = max_sge;
2672 rxq_init->rss_engine_id = BP_FUNC(bp);
2673
2674 /* Maximum number or simultaneous TPA aggregation for this Queue.
2675 *
2676 * For PF Clients it should be the maximum avaliable number.
2677 * VF driver(s) may want to define it to a smaller value.
2678 */
2679 rxq_init->max_tpa_queues =
2680 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2681 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2682
2683 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2684 rxq_init->fw_sb_id = fp->fw_sb_id;
2685
2686 if (IS_FCOE_FP(fp))
2687 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2688 else
2689 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2690 }
2691
2692 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2693 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init)
2694 {
2695 txq_init->dscr_map = fp->tx_desc_mapping;
2696 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2697 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2698 txq_init->fw_sb_id = fp->fw_sb_id;
2699
2700 /*
2701 * set the tss leading client id for TX classfication ==
2702 * leading RSS client id
2703 */
2704 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2705
2706 if (IS_FCOE_FP(fp)) {
2707 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2708 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2709 }
2710 }
2711
2712 static void bnx2x_pf_init(struct bnx2x *bp)
2713 {
2714 struct bnx2x_func_init_params func_init = {0};
2715 struct event_ring_data eq_data = { {0} };
2716 u16 flags;
2717
2718 if (!CHIP_IS_E1x(bp)) {
2719 /* reset IGU PF statistics: MSIX + ATTN */
2720 /* PF */
2721 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2722 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2723 (CHIP_MODE_IS_4_PORT(bp) ?
2724 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2725 /* ATTN */
2726 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2727 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2728 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2729 (CHIP_MODE_IS_4_PORT(bp) ?
2730 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2731 }
2732
2733 /* function setup flags */
2734 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2735
2736 /* This flag is relevant for E1x only.
2737 * E2 doesn't have a TPA configuration in a function level.
2738 */
2739 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2740
2741 func_init.func_flgs = flags;
2742 func_init.pf_id = BP_FUNC(bp);
2743 func_init.func_id = BP_FUNC(bp);
2744 func_init.spq_map = bp->spq_mapping;
2745 func_init.spq_prod = bp->spq_prod_idx;
2746
2747 bnx2x_func_init(bp, &func_init);
2748
2749 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2750
2751 /*
2752 * Congestion management values depend on the link rate
2753 * There is no active link so initial link rate is set to 10 Gbps.
2754 * When the link comes up The congestion management values are
2755 * re-calculated according to the actual link rate.
2756 */
2757 bp->link_vars.line_speed = SPEED_10000;
2758 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2759
2760 /* Only the PMF sets the HW */
2761 if (bp->port.pmf)
2762 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2763
2764 /* init Event Queue */
2765 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2766 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2767 eq_data.producer = bp->eq_prod;
2768 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2769 eq_data.sb_id = DEF_SB_ID;
2770 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2771 }
2772
2773
2774 static void bnx2x_e1h_disable(struct bnx2x *bp)
2775 {
2776 int port = BP_PORT(bp);
2777
2778 bnx2x_tx_disable(bp);
2779
2780 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2781 }
2782
2783 static void bnx2x_e1h_enable(struct bnx2x *bp)
2784 {
2785 int port = BP_PORT(bp);
2786
2787 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2788
2789 /* Tx queue should be only reenabled */
2790 netif_tx_wake_all_queues(bp->dev);
2791
2792 /*
2793 * Should not call netif_carrier_on since it will be called if the link
2794 * is up when checking for link state
2795 */
2796 }
2797
2798 /* called due to MCP event (on pmf):
2799 * reread new bandwidth configuration
2800 * configure FW
2801 * notify others function about the change
2802 */
2803 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2804 {
2805 if (bp->link_vars.link_up) {
2806 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2807 bnx2x_link_sync_notify(bp);
2808 }
2809 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2810 }
2811
2812 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2813 {
2814 bnx2x_config_mf_bw(bp);
2815 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2816 }
2817
2818 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2819 {
2820 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2821
2822 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2823
2824 /*
2825 * This is the only place besides the function initialization
2826 * where the bp->flags can change so it is done without any
2827 * locks
2828 */
2829 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2830 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2831 bp->flags |= MF_FUNC_DIS;
2832
2833 bnx2x_e1h_disable(bp);
2834 } else {
2835 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2836 bp->flags &= ~MF_FUNC_DIS;
2837
2838 bnx2x_e1h_enable(bp);
2839 }
2840 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2841 }
2842 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2843 bnx2x_config_mf_bw(bp);
2844 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2845 }
2846
2847 /* Report results to MCP */
2848 if (dcc_event)
2849 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2850 else
2851 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2852 }
2853
2854 /* must be called under the spq lock */
2855 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2856 {
2857 struct eth_spe *next_spe = bp->spq_prod_bd;
2858
2859 if (bp->spq_prod_bd == bp->spq_last_bd) {
2860 bp->spq_prod_bd = bp->spq;
2861 bp->spq_prod_idx = 0;
2862 DP(NETIF_MSG_TIMER, "end of spq\n");
2863 } else {
2864 bp->spq_prod_bd++;
2865 bp->spq_prod_idx++;
2866 }
2867 return next_spe;
2868 }
2869
2870 /* must be called under the spq lock */
2871 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2872 {
2873 int func = BP_FUNC(bp);
2874
2875 /* Make sure that BD data is updated before writing the producer */
2876 wmb();
2877
2878 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2879 bp->spq_prod_idx);
2880 mmiowb();
2881 }
2882
2883 /**
2884 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
2885 *
2886 * @cmd: command to check
2887 * @cmd_type: command type
2888 */
2889 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
2890 {
2891 if ((cmd_type == NONE_CONNECTION_TYPE) ||
2892 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2893 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2894 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2895 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2896 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
2897 return true;
2898 else
2899 return false;
2900
2901 }
2902
2903
2904 /**
2905 * bnx2x_sp_post - place a single command on an SP ring
2906 *
2907 * @bp: driver handle
2908 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
2909 * @cid: SW CID the command is related to
2910 * @data_hi: command private data address (high 32 bits)
2911 * @data_lo: command private data address (low 32 bits)
2912 * @cmd_type: command type (e.g. NONE, ETH)
2913 *
2914 * SP data is handled as if it's always an address pair, thus data fields are
2915 * not swapped to little endian in upper functions. Instead this function swaps
2916 * data as if it's two u32 fields.
2917 */
2918 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2919 u32 data_hi, u32 data_lo, int cmd_type)
2920 {
2921 struct eth_spe *spe;
2922 u16 type;
2923 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
2924
2925 #ifdef BNX2X_STOP_ON_ERROR
2926 if (unlikely(bp->panic))
2927 return -EIO;
2928 #endif
2929
2930 spin_lock_bh(&bp->spq_lock);
2931
2932 if (common) {
2933 if (!atomic_read(&bp->eq_spq_left)) {
2934 BNX2X_ERR("BUG! EQ ring full!\n");
2935 spin_unlock_bh(&bp->spq_lock);
2936 bnx2x_panic();
2937 return -EBUSY;
2938 }
2939 } else if (!atomic_read(&bp->cq_spq_left)) {
2940 BNX2X_ERR("BUG! SPQ ring full!\n");
2941 spin_unlock_bh(&bp->spq_lock);
2942 bnx2x_panic();
2943 return -EBUSY;
2944 }
2945
2946 spe = bnx2x_sp_get_next(bp);
2947
2948 /* CID needs port number to be encoded int it */
2949 spe->hdr.conn_and_cmd_data =
2950 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2951 HW_CID(bp, cid));
2952
2953 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
2954
2955 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2956 SPE_HDR_FUNCTION_ID);
2957
2958 spe->hdr.type = cpu_to_le16(type);
2959
2960 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2961 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2962
2963 /* stats ramrod has it's own slot on the spq */
2964 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
2965 /*
2966 * It's ok if the actual decrement is issued towards the memory
2967 * somewhere between the spin_lock and spin_unlock. Thus no
2968 * more explict memory barrier is needed.
2969 */
2970 if (common)
2971 atomic_dec(&bp->eq_spq_left);
2972 else
2973 atomic_dec(&bp->cq_spq_left);
2974 }
2975
2976
2977 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2978 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2979 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
2980 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2981 (u32)(U64_LO(bp->spq_mapping) +
2982 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2983 HW_CID(bp, cid), data_hi, data_lo, type,
2984 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
2985
2986 bnx2x_sp_prod_update(bp);
2987 spin_unlock_bh(&bp->spq_lock);
2988 return 0;
2989 }
2990
2991 /* acquire split MCP access lock register */
2992 static int bnx2x_acquire_alr(struct bnx2x *bp)
2993 {
2994 u32 j, val;
2995 int rc = 0;
2996
2997 might_sleep();
2998 for (j = 0; j < 1000; j++) {
2999 val = (1UL << 31);
3000 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3001 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3002 if (val & (1L << 31))
3003 break;
3004
3005 msleep(5);
3006 }
3007 if (!(val & (1L << 31))) {
3008 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3009 rc = -EBUSY;
3010 }
3011
3012 return rc;
3013 }
3014
3015 /* release split MCP access lock register */
3016 static void bnx2x_release_alr(struct bnx2x *bp)
3017 {
3018 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3019 }
3020
3021 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3022 #define BNX2X_DEF_SB_IDX 0x0002
3023
3024 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3025 {
3026 struct host_sp_status_block *def_sb = bp->def_status_blk;
3027 u16 rc = 0;
3028
3029 barrier(); /* status block is written to by the chip */
3030 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3031 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3032 rc |= BNX2X_DEF_SB_ATT_IDX;
3033 }
3034
3035 if (bp->def_idx != def_sb->sp_sb.running_index) {
3036 bp->def_idx = def_sb->sp_sb.running_index;
3037 rc |= BNX2X_DEF_SB_IDX;
3038 }
3039
3040 /* Do not reorder: indecies reading should complete before handling */
3041 barrier();
3042 return rc;
3043 }
3044
3045 /*
3046 * slow path service functions
3047 */
3048
3049 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3050 {
3051 int port = BP_PORT(bp);
3052 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3053 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3054 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3055 NIG_REG_MASK_INTERRUPT_PORT0;
3056 u32 aeu_mask;
3057 u32 nig_mask = 0;
3058 u32 reg_addr;
3059
3060 if (bp->attn_state & asserted)
3061 BNX2X_ERR("IGU ERROR\n");
3062
3063 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3064 aeu_mask = REG_RD(bp, aeu_addr);
3065
3066 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3067 aeu_mask, asserted);
3068 aeu_mask &= ~(asserted & 0x3ff);
3069 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3070
3071 REG_WR(bp, aeu_addr, aeu_mask);
3072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3073
3074 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3075 bp->attn_state |= asserted;
3076 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3077
3078 if (asserted & ATTN_HARD_WIRED_MASK) {
3079 if (asserted & ATTN_NIG_FOR_FUNC) {
3080
3081 bnx2x_acquire_phy_lock(bp);
3082
3083 /* save nig interrupt mask */
3084 nig_mask = REG_RD(bp, nig_int_mask_addr);
3085
3086 /* If nig_mask is not set, no need to call the update
3087 * function.
3088 */
3089 if (nig_mask) {
3090 REG_WR(bp, nig_int_mask_addr, 0);
3091
3092 bnx2x_link_attn(bp);
3093 }
3094
3095 /* handle unicore attn? */
3096 }
3097 if (asserted & ATTN_SW_TIMER_4_FUNC)
3098 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3099
3100 if (asserted & GPIO_2_FUNC)
3101 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3102
3103 if (asserted & GPIO_3_FUNC)
3104 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3105
3106 if (asserted & GPIO_4_FUNC)
3107 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3108
3109 if (port == 0) {
3110 if (asserted & ATTN_GENERAL_ATTN_1) {
3111 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3112 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3113 }
3114 if (asserted & ATTN_GENERAL_ATTN_2) {
3115 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3116 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3117 }
3118 if (asserted & ATTN_GENERAL_ATTN_3) {
3119 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3120 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3121 }
3122 } else {
3123 if (asserted & ATTN_GENERAL_ATTN_4) {
3124 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3125 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3126 }
3127 if (asserted & ATTN_GENERAL_ATTN_5) {
3128 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3129 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3130 }
3131 if (asserted & ATTN_GENERAL_ATTN_6) {
3132 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3133 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3134 }
3135 }
3136
3137 } /* if hardwired */
3138
3139 if (bp->common.int_block == INT_BLOCK_HC)
3140 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3141 COMMAND_REG_ATTN_BITS_SET);
3142 else
3143 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3144
3145 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3146 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3147 REG_WR(bp, reg_addr, asserted);
3148
3149 /* now set back the mask */
3150 if (asserted & ATTN_NIG_FOR_FUNC) {
3151 REG_WR(bp, nig_int_mask_addr, nig_mask);
3152 bnx2x_release_phy_lock(bp);
3153 }
3154 }
3155
3156 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3157 {
3158 int port = BP_PORT(bp);
3159 u32 ext_phy_config;
3160 /* mark the failure */
3161 ext_phy_config =
3162 SHMEM_RD(bp,
3163 dev_info.port_hw_config[port].external_phy_config);
3164
3165 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3166 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3167 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3168 ext_phy_config);
3169
3170 /* log the failure */
3171 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3172 " the driver to shutdown the card to prevent permanent"
3173 " damage. Please contact OEM Support for assistance\n");
3174 }
3175
3176 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3177 {
3178 int port = BP_PORT(bp);
3179 int reg_offset;
3180 u32 val;
3181
3182 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3183 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3184
3185 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3186
3187 val = REG_RD(bp, reg_offset);
3188 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3189 REG_WR(bp, reg_offset, val);
3190
3191 BNX2X_ERR("SPIO5 hw attention\n");
3192
3193 /* Fan failure attention */
3194 bnx2x_hw_reset_phy(&bp->link_params);
3195 bnx2x_fan_failure(bp);
3196 }
3197
3198 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3199 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3200 bnx2x_acquire_phy_lock(bp);
3201 bnx2x_handle_module_detect_int(&bp->link_params);
3202 bnx2x_release_phy_lock(bp);
3203 }
3204
3205 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3206
3207 val = REG_RD(bp, reg_offset);
3208 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3209 REG_WR(bp, reg_offset, val);
3210
3211 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3212 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3213 bnx2x_panic();
3214 }
3215 }
3216
3217 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3218 {
3219 u32 val;
3220
3221 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3222
3223 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3224 BNX2X_ERR("DB hw attention 0x%x\n", val);
3225 /* DORQ discard attention */
3226 if (val & 0x2)
3227 BNX2X_ERR("FATAL error from DORQ\n");
3228 }
3229
3230 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3231
3232 int port = BP_PORT(bp);
3233 int reg_offset;
3234
3235 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3236 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3237
3238 val = REG_RD(bp, reg_offset);
3239 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3240 REG_WR(bp, reg_offset, val);
3241
3242 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3243 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3244 bnx2x_panic();
3245 }
3246 }
3247
3248 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3249 {
3250 u32 val;
3251
3252 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3253
3254 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3255 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3256 /* CFC error attention */
3257 if (val & 0x2)
3258 BNX2X_ERR("FATAL error from CFC\n");
3259 }
3260
3261 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3262 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3263 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3264 /* RQ_USDMDP_FIFO_OVERFLOW */
3265 if (val & 0x18000)
3266 BNX2X_ERR("FATAL error from PXP\n");
3267
3268 if (!CHIP_IS_E1x(bp)) {
3269 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3270 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3271 }
3272 }
3273
3274 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3275
3276 int port = BP_PORT(bp);
3277 int reg_offset;
3278
3279 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3280 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3281
3282 val = REG_RD(bp, reg_offset);
3283 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3284 REG_WR(bp, reg_offset, val);
3285
3286 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3287 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3288 bnx2x_panic();
3289 }
3290 }
3291
3292 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3293 {
3294 u32 val;
3295
3296 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3297
3298 if (attn & BNX2X_PMF_LINK_ASSERT) {
3299 int func = BP_FUNC(bp);
3300
3301 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3302 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3303 func_mf_config[BP_ABS_FUNC(bp)].config);
3304 val = SHMEM_RD(bp,
3305 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3306 if (val & DRV_STATUS_DCC_EVENT_MASK)
3307 bnx2x_dcc_event(bp,
3308 (val & DRV_STATUS_DCC_EVENT_MASK));
3309
3310 if (val & DRV_STATUS_SET_MF_BW)
3311 bnx2x_set_mf_bw(bp);
3312
3313 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3314 bnx2x_pmf_update(bp);
3315
3316 /* Always call it here: bnx2x_link_report() will
3317 * prevent the link indication duplication.
3318 */
3319 bnx2x__link_status_update(bp);
3320
3321 if (bp->port.pmf &&
3322 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3323 bp->dcbx_enabled > 0)
3324 /* start dcbx state machine */
3325 bnx2x_dcbx_set_params(bp,
3326 BNX2X_DCBX_STATE_NEG_RECEIVED);
3327 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3328
3329 BNX2X_ERR("MC assert!\n");
3330 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3331 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3332 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3333 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3334 bnx2x_panic();
3335
3336 } else if (attn & BNX2X_MCP_ASSERT) {
3337
3338 BNX2X_ERR("MCP assert!\n");
3339 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3340 bnx2x_fw_dump(bp);
3341
3342 } else
3343 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3344 }
3345
3346 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3347 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3348 if (attn & BNX2X_GRC_TIMEOUT) {
3349 val = CHIP_IS_E1(bp) ? 0 :
3350 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3351 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3352 }
3353 if (attn & BNX2X_GRC_RSV) {
3354 val = CHIP_IS_E1(bp) ? 0 :
3355 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3356 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3357 }
3358 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3359 }
3360 }
3361
3362 /*
3363 * Bits map:
3364 * 0-7 - Engine0 load counter.
3365 * 8-15 - Engine1 load counter.
3366 * 16 - Engine0 RESET_IN_PROGRESS bit.
3367 * 17 - Engine1 RESET_IN_PROGRESS bit.
3368 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3369 * on the engine
3370 * 19 - Engine1 ONE_IS_LOADED.
3371 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3372 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3373 * just the one belonging to its engine).
3374 *
3375 */
3376 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3377
3378 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3379 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3380 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3381 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3382 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3383 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3384 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3385
3386 /*
3387 * Set the GLOBAL_RESET bit.
3388 *
3389 * Should be run under rtnl lock
3390 */
3391 void bnx2x_set_reset_global(struct bnx2x *bp)
3392 {
3393 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3394
3395 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3396 barrier();
3397 mmiowb();
3398 }
3399
3400 /*
3401 * Clear the GLOBAL_RESET bit.
3402 *
3403 * Should be run under rtnl lock
3404 */
3405 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3406 {
3407 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3408
3409 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3410 barrier();
3411 mmiowb();
3412 }
3413
3414 /*
3415 * Checks the GLOBAL_RESET bit.
3416 *
3417 * should be run under rtnl lock
3418 */
3419 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3420 {
3421 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3422
3423 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3424 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3425 }
3426
3427 /*
3428 * Clear RESET_IN_PROGRESS bit for the current engine.
3429 *
3430 * Should be run under rtnl lock
3431 */
3432 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3433 {
3434 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3435 u32 bit = BP_PATH(bp) ?
3436 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3437
3438 /* Clear the bit */
3439 val &= ~bit;
3440 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3441 barrier();
3442 mmiowb();
3443 }
3444
3445 /*
3446 * Set RESET_IN_PROGRESS for the current engine.
3447 *
3448 * should be run under rtnl lock
3449 */
3450 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3451 {
3452 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3453 u32 bit = BP_PATH(bp) ?
3454 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3455
3456 /* Set the bit */
3457 val |= bit;
3458 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3459 barrier();
3460 mmiowb();
3461 }
3462
3463 /*
3464 * Checks the RESET_IN_PROGRESS bit for the given engine.
3465 * should be run under rtnl lock
3466 */
3467 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3468 {
3469 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3470 u32 bit = engine ?
3471 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3472
3473 /* return false if bit is set */
3474 return (val & bit) ? false : true;
3475 }
3476
3477 /*
3478 * Increment the load counter for the current engine.
3479 *
3480 * should be run under rtnl lock
3481 */
3482 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3483 {
3484 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3485 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3486 BNX2X_PATH0_LOAD_CNT_MASK;
3487 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3488 BNX2X_PATH0_LOAD_CNT_SHIFT;
3489
3490 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3491
3492 /* get the current counter value */
3493 val1 = (val & mask) >> shift;
3494
3495 /* increment... */
3496 val1++;
3497
3498 /* clear the old value */
3499 val &= ~mask;
3500
3501 /* set the new one */
3502 val |= ((val1 << shift) & mask);
3503
3504 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3505 barrier();
3506 mmiowb();
3507 }
3508
3509 /**
3510 * bnx2x_dec_load_cnt - decrement the load counter
3511 *
3512 * @bp: driver handle
3513 *
3514 * Should be run under rtnl lock.
3515 * Decrements the load counter for the current engine. Returns
3516 * the new counter value.
3517 */
3518 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3519 {
3520 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3521 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3522 BNX2X_PATH0_LOAD_CNT_MASK;
3523 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3524 BNX2X_PATH0_LOAD_CNT_SHIFT;
3525
3526 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3527
3528 /* get the current counter value */
3529 val1 = (val & mask) >> shift;
3530
3531 /* decrement... */
3532 val1--;
3533
3534 /* clear the old value */
3535 val &= ~mask;
3536
3537 /* set the new one */
3538 val |= ((val1 << shift) & mask);
3539
3540 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3541 barrier();
3542 mmiowb();
3543
3544 return val1;
3545 }
3546
3547 /*
3548 * Read the load counter for the current engine.
3549 *
3550 * should be run under rtnl lock
3551 */
3552 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3553 {
3554 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3555 BNX2X_PATH0_LOAD_CNT_MASK);
3556 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3557 BNX2X_PATH0_LOAD_CNT_SHIFT);
3558 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3559
3560 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3561
3562 val = (val & mask) >> shift;
3563
3564 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3565
3566 return val;
3567 }
3568
3569 /*
3570 * Reset the load counter for the current engine.
3571 *
3572 * should be run under rtnl lock
3573 */
3574 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3575 {
3576 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3577 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3578 BNX2X_PATH0_LOAD_CNT_MASK);
3579
3580 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3581 }
3582
3583 static inline void _print_next_block(int idx, const char *blk)
3584 {
3585 if (idx)
3586 pr_cont(", ");
3587 pr_cont("%s", blk);
3588 }
3589
3590 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3591 bool print)
3592 {
3593 int i = 0;
3594 u32 cur_bit = 0;
3595 for (i = 0; sig; i++) {
3596 cur_bit = ((u32)0x1 << i);
3597 if (sig & cur_bit) {
3598 switch (cur_bit) {
3599 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3600 if (print)
3601 _print_next_block(par_num++, "BRB");
3602 break;
3603 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3604 if (print)
3605 _print_next_block(par_num++, "PARSER");
3606 break;
3607 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3608 if (print)
3609 _print_next_block(par_num++, "TSDM");
3610 break;
3611 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3612 if (print)
3613 _print_next_block(par_num++,
3614 "SEARCHER");
3615 break;
3616 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3617 if (print)
3618 _print_next_block(par_num++, "TCM");
3619 break;
3620 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3621 if (print)
3622 _print_next_block(par_num++, "TSEMI");
3623 break;
3624 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3625 if (print)
3626 _print_next_block(par_num++, "XPB");
3627 break;
3628 }
3629
3630 /* Clear the bit */
3631 sig &= ~cur_bit;
3632 }
3633 }
3634
3635 return par_num;
3636 }
3637
3638 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3639 bool *global, bool print)
3640 {
3641 int i = 0;
3642 u32 cur_bit = 0;
3643 for (i = 0; sig; i++) {
3644 cur_bit = ((u32)0x1 << i);
3645 if (sig & cur_bit) {
3646 switch (cur_bit) {
3647 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3648 if (print)
3649 _print_next_block(par_num++, "PBF");
3650 break;
3651 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3652 if (print)
3653 _print_next_block(par_num++, "QM");
3654 break;
3655 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3656 if (print)
3657 _print_next_block(par_num++, "TM");
3658 break;
3659 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3660 if (print)
3661 _print_next_block(par_num++, "XSDM");
3662 break;
3663 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3664 if (print)
3665 _print_next_block(par_num++, "XCM");
3666 break;
3667 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3668 if (print)
3669 _print_next_block(par_num++, "XSEMI");
3670 break;
3671 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3672 if (print)
3673 _print_next_block(par_num++,
3674 "DOORBELLQ");
3675 break;
3676 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3677 if (print)
3678 _print_next_block(par_num++, "NIG");
3679 break;
3680 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3681 if (print)
3682 _print_next_block(par_num++,
3683 "VAUX PCI CORE");
3684 *global = true;
3685 break;
3686 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3687 if (print)
3688 _print_next_block(par_num++, "DEBUG");
3689 break;
3690 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3691 if (print)
3692 _print_next_block(par_num++, "USDM");
3693 break;
3694 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3695 if (print)
3696 _print_next_block(par_num++, "USEMI");
3697 break;
3698 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3699 if (print)
3700 _print_next_block(par_num++, "UPB");
3701 break;
3702 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3703 if (print)
3704 _print_next_block(par_num++, "CSDM");
3705 break;
3706 }
3707
3708 /* Clear the bit */
3709 sig &= ~cur_bit;
3710 }
3711 }
3712
3713 return par_num;
3714 }
3715
3716 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3717 bool print)
3718 {
3719 int i = 0;
3720 u32 cur_bit = 0;
3721 for (i = 0; sig; i++) {
3722 cur_bit = ((u32)0x1 << i);
3723 if (sig & cur_bit) {
3724 switch (cur_bit) {
3725 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3726 if (print)
3727 _print_next_block(par_num++, "CSEMI");
3728 break;
3729 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3730 if (print)
3731 _print_next_block(par_num++, "PXP");
3732 break;
3733 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3734 if (print)
3735 _print_next_block(par_num++,
3736 "PXPPCICLOCKCLIENT");
3737 break;
3738 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3739 if (print)
3740 _print_next_block(par_num++, "CFC");
3741 break;
3742 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3743 if (print)
3744 _print_next_block(par_num++, "CDU");
3745 break;
3746 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3747 if (print)
3748 _print_next_block(par_num++, "DMAE");
3749 break;
3750 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3751 if (print)
3752 _print_next_block(par_num++, "IGU");
3753 break;
3754 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3755 if (print)
3756 _print_next_block(par_num++, "MISC");
3757 break;
3758 }
3759
3760 /* Clear the bit */
3761 sig &= ~cur_bit;
3762 }
3763 }
3764
3765 return par_num;
3766 }
3767
3768 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3769 bool *global, bool print)
3770 {
3771 int i = 0;
3772 u32 cur_bit = 0;
3773 for (i = 0; sig; i++) {
3774 cur_bit = ((u32)0x1 << i);
3775 if (sig & cur_bit) {
3776 switch (cur_bit) {
3777 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3778 if (print)
3779 _print_next_block(par_num++, "MCP ROM");
3780 *global = true;
3781 break;
3782 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3783 if (print)
3784 _print_next_block(par_num++,
3785 "MCP UMP RX");
3786 *global = true;
3787 break;
3788 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3789 if (print)
3790 _print_next_block(par_num++,
3791 "MCP UMP TX");
3792 *global = true;
3793 break;
3794 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3795 if (print)
3796 _print_next_block(par_num++,
3797 "MCP SCPAD");
3798 *global = true;
3799 break;
3800 }
3801
3802 /* Clear the bit */
3803 sig &= ~cur_bit;
3804 }
3805 }
3806
3807 return par_num;
3808 }
3809
3810 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3811 u32 sig0, u32 sig1, u32 sig2, u32 sig3)
3812 {
3813 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3814 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3815 int par_num = 0;
3816 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3817 "[0]:0x%08x [1]:0x%08x "
3818 "[2]:0x%08x [3]:0x%08x\n",
3819 sig0 & HW_PRTY_ASSERT_SET_0,
3820 sig1 & HW_PRTY_ASSERT_SET_1,
3821 sig2 & HW_PRTY_ASSERT_SET_2,
3822 sig3 & HW_PRTY_ASSERT_SET_3);
3823 if (print)
3824 netdev_err(bp->dev,
3825 "Parity errors detected in blocks: ");
3826 par_num = bnx2x_check_blocks_with_parity0(
3827 sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
3828 par_num = bnx2x_check_blocks_with_parity1(
3829 sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
3830 par_num = bnx2x_check_blocks_with_parity2(
3831 sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
3832 par_num = bnx2x_check_blocks_with_parity3(
3833 sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
3834 if (print)
3835 pr_cont("\n");
3836 return true;
3837 } else
3838 return false;
3839 }
3840
3841 /**
3842 * bnx2x_chk_parity_attn - checks for parity attentions.
3843 *
3844 * @bp: driver handle
3845 * @global: true if there was a global attention
3846 * @print: show parity attention in syslog
3847 */
3848 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
3849 {
3850 struct attn_route attn;
3851 int port = BP_PORT(bp);
3852
3853 attn.sig[0] = REG_RD(bp,
3854 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3855 port*4);
3856 attn.sig[1] = REG_RD(bp,
3857 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3858 port*4);
3859 attn.sig[2] = REG_RD(bp,
3860 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3861 port*4);
3862 attn.sig[3] = REG_RD(bp,
3863 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3864 port*4);
3865
3866 return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
3867 attn.sig[2], attn.sig[3]);
3868 }
3869
3870
3871 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3872 {
3873 u32 val;
3874 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3875
3876 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3877 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3878 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3879 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3880 "ADDRESS_ERROR\n");
3881 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3882 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3883 "INCORRECT_RCV_BEHAVIOR\n");
3884 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3885 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3886 "WAS_ERROR_ATTN\n");
3887 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3888 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3889 "VF_LENGTH_VIOLATION_ATTN\n");
3890 if (val &
3891 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3892 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3893 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3894 if (val &
3895 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3896 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3897 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3898 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3899 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3900 "TCPL_ERROR_ATTN\n");
3901 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3902 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3903 "TCPL_IN_TWO_RCBS_ATTN\n");
3904 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3905 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3906 "CSSNOOP_FIFO_OVERFLOW\n");
3907 }
3908 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3909 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3910 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3911 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3912 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3913 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3914 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3915 "_ATC_TCPL_TO_NOT_PEND\n");
3916 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3917 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3918 "ATC_GPA_MULTIPLE_HITS\n");
3919 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3920 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3921 "ATC_RCPL_TO_EMPTY_CNT\n");
3922 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3923 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3924 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3925 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3926 "ATC_IREQ_LESS_THAN_STU\n");
3927 }
3928
3929 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3930 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3931 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3932 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3933 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3934 }
3935
3936 }
3937
3938 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3939 {
3940 struct attn_route attn, *group_mask;
3941 int port = BP_PORT(bp);
3942 int index;
3943 u32 reg_addr;
3944 u32 val;
3945 u32 aeu_mask;
3946 bool global = false;
3947
3948 /* need to take HW lock because MCP or other port might also
3949 try to handle this event */
3950 bnx2x_acquire_alr(bp);
3951
3952 if (bnx2x_chk_parity_attn(bp, &global, true)) {
3953 #ifndef BNX2X_STOP_ON_ERROR
3954 bp->recovery_state = BNX2X_RECOVERY_INIT;
3955 schedule_delayed_work(&bp->reset_task, 0);
3956 /* Disable HW interrupts */
3957 bnx2x_int_disable(bp);
3958 /* In case of parity errors don't handle attentions so that
3959 * other function would "see" parity errors.
3960 */
3961 #else
3962 bnx2x_panic();
3963 #endif
3964 bnx2x_release_alr(bp);
3965 return;
3966 }
3967
3968 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3969 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3970 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3971 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3972 if (!CHIP_IS_E1x(bp))
3973 attn.sig[4] =
3974 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3975 else
3976 attn.sig[4] = 0;
3977
3978 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3979 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
3980
3981 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3982 if (deasserted & (1 << index)) {
3983 group_mask = &bp->attn_group[index];
3984
3985 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3986 "%08x %08x %08x\n",
3987 index,
3988 group_mask->sig[0], group_mask->sig[1],
3989 group_mask->sig[2], group_mask->sig[3],
3990 group_mask->sig[4]);
3991
3992 bnx2x_attn_int_deasserted4(bp,
3993 attn.sig[4] & group_mask->sig[4]);
3994 bnx2x_attn_int_deasserted3(bp,
3995 attn.sig[3] & group_mask->sig[3]);
3996 bnx2x_attn_int_deasserted1(bp,
3997 attn.sig[1] & group_mask->sig[1]);
3998 bnx2x_attn_int_deasserted2(bp,
3999 attn.sig[2] & group_mask->sig[2]);
4000 bnx2x_attn_int_deasserted0(bp,
4001 attn.sig[0] & group_mask->sig[0]);
4002 }
4003 }
4004
4005 bnx2x_release_alr(bp);
4006
4007 if (bp->common.int_block == INT_BLOCK_HC)
4008 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4009 COMMAND_REG_ATTN_BITS_CLR);
4010 else
4011 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4012
4013 val = ~deasserted;
4014 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4015 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4016 REG_WR(bp, reg_addr, val);
4017
4018 if (~bp->attn_state & deasserted)
4019 BNX2X_ERR("IGU ERROR\n");
4020
4021 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4022 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4023
4024 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4025 aeu_mask = REG_RD(bp, reg_addr);
4026
4027 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4028 aeu_mask, deasserted);
4029 aeu_mask |= (deasserted & 0x3ff);
4030 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4031
4032 REG_WR(bp, reg_addr, aeu_mask);
4033 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4034
4035 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4036 bp->attn_state &= ~deasserted;
4037 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4038 }
4039
4040 static void bnx2x_attn_int(struct bnx2x *bp)
4041 {
4042 /* read local copy of bits */
4043 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4044 attn_bits);
4045 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4046 attn_bits_ack);
4047 u32 attn_state = bp->attn_state;
4048
4049 /* look for changed bits */
4050 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4051 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4052
4053 DP(NETIF_MSG_HW,
4054 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4055 attn_bits, attn_ack, asserted, deasserted);
4056
4057 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4058 BNX2X_ERR("BAD attention state\n");
4059
4060 /* handle bits that were raised */
4061 if (asserted)
4062 bnx2x_attn_int_asserted(bp, asserted);
4063
4064 if (deasserted)
4065 bnx2x_attn_int_deasserted(bp, deasserted);
4066 }
4067
4068 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4069 u16 index, u8 op, u8 update)
4070 {
4071 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4072
4073 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4074 igu_addr);
4075 }
4076
4077 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4078 {
4079 /* No memory barriers */
4080 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4081 mmiowb(); /* keep prod updates ordered */
4082 }
4083
4084 #ifdef BCM_CNIC
4085 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4086 union event_ring_elem *elem)
4087 {
4088 u8 err = elem->message.error;
4089
4090 if (!bp->cnic_eth_dev.starting_cid ||
4091 (cid < bp->cnic_eth_dev.starting_cid &&
4092 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4093 return 1;
4094
4095 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4096
4097 if (unlikely(err)) {
4098
4099 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4100 cid);
4101 bnx2x_panic_dump(bp);
4102 }
4103 bnx2x_cnic_cfc_comp(bp, cid, err);
4104 return 0;
4105 }
4106 #endif
4107
4108 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4109 {
4110 struct bnx2x_mcast_ramrod_params rparam;
4111 int rc;
4112
4113 memset(&rparam, 0, sizeof(rparam));
4114
4115 rparam.mcast_obj = &bp->mcast_obj;
4116
4117 netif_addr_lock_bh(bp->dev);
4118
4119 /* Clear pending state for the last command */
4120 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4121
4122 /* If there are pending mcast commands - send them */
4123 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4124 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4125 if (rc < 0)
4126 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4127 rc);
4128 }
4129
4130 netif_addr_unlock_bh(bp->dev);
4131 }
4132
4133 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4134 union event_ring_elem *elem)
4135 {
4136 unsigned long ramrod_flags = 0;
4137 int rc = 0;
4138 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4139 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4140
4141 /* Always push next commands out, don't wait here */
4142 __set_bit(RAMROD_CONT, &ramrod_flags);
4143
4144 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4145 case BNX2X_FILTER_MAC_PENDING:
4146 #ifdef BCM_CNIC
4147 if (cid == BNX2X_ISCSI_ETH_CID)
4148 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4149 else
4150 #endif
4151 vlan_mac_obj = &bp->fp[cid].mac_obj;
4152
4153 break;
4154 vlan_mac_obj = &bp->fp[cid].mac_obj;
4155
4156 case BNX2X_FILTER_MCAST_PENDING:
4157 /* This is only relevant for 57710 where multicast MACs are
4158 * configured as unicast MACs using the same ramrod.
4159 */
4160 bnx2x_handle_mcast_eqe(bp);
4161 return;
4162 default:
4163 BNX2X_ERR("Unsupported classification command: %d\n",
4164 elem->message.data.eth_event.echo);
4165 return;
4166 }
4167
4168 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4169
4170 if (rc < 0)
4171 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4172 else if (rc > 0)
4173 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4174
4175 }
4176
4177 #ifdef BCM_CNIC
4178 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4179 #endif
4180
4181 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4182 {
4183 netif_addr_lock_bh(bp->dev);
4184
4185 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4186
4187 /* Send rx_mode command again if was requested */
4188 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4189 bnx2x_set_storm_rx_mode(bp);
4190 #ifdef BCM_CNIC
4191 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4192 &bp->sp_state))
4193 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4194 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4195 &bp->sp_state))
4196 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4197 #endif
4198
4199 netif_addr_unlock_bh(bp->dev);
4200 }
4201
4202 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4203 struct bnx2x *bp, u32 cid)
4204 {
4205 #ifdef BCM_CNIC
4206 if (cid == BNX2X_FCOE_ETH_CID)
4207 return &bnx2x_fcoe(bp, q_obj);
4208 else
4209 #endif
4210 return &bnx2x_fp(bp, cid, q_obj);
4211 }
4212
4213 static void bnx2x_eq_int(struct bnx2x *bp)
4214 {
4215 u16 hw_cons, sw_cons, sw_prod;
4216 union event_ring_elem *elem;
4217 u32 cid;
4218 u8 opcode;
4219 int spqe_cnt = 0;
4220 struct bnx2x_queue_sp_obj *q_obj;
4221 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4222 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4223
4224 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4225
4226 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4227 * when we get the the next-page we nned to adjust so the loop
4228 * condition below will be met. The next element is the size of a
4229 * regular element and hence incrementing by 1
4230 */
4231 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4232 hw_cons++;
4233
4234 /* This function may never run in parallel with itself for a
4235 * specific bp, thus there is no need in "paired" read memory
4236 * barrier here.
4237 */
4238 sw_cons = bp->eq_cons;
4239 sw_prod = bp->eq_prod;
4240
4241 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
4242 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4243
4244 for (; sw_cons != hw_cons;
4245 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4246
4247
4248 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4249
4250 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4251 opcode = elem->message.opcode;
4252
4253
4254 /* handle eq element */
4255 switch (opcode) {
4256 case EVENT_RING_OPCODE_STAT_QUERY:
4257 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4258 bp->stats_comp++);
4259 /* nothing to do with stats comp */
4260 continue;
4261
4262 case EVENT_RING_OPCODE_CFC_DEL:
4263 /* handle according to cid range */
4264 /*
4265 * we may want to verify here that the bp state is
4266 * HALTING
4267 */
4268 DP(NETIF_MSG_IFDOWN,
4269 "got delete ramrod for MULTI[%d]\n", cid);
4270 #ifdef BCM_CNIC
4271 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4272 goto next_spqe;
4273 #endif
4274 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4275
4276 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4277 break;
4278
4279
4280
4281 goto next_spqe;
4282
4283 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4284 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
4285 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4286 goto next_spqe;
4287
4288 case EVENT_RING_OPCODE_START_TRAFFIC:
4289 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
4290 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4291 goto next_spqe;
4292 case EVENT_RING_OPCODE_FUNCTION_START:
4293 DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n");
4294 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4295 break;
4296
4297 goto next_spqe;
4298
4299 case EVENT_RING_OPCODE_FUNCTION_STOP:
4300 DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n");
4301 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4302 break;
4303
4304 goto next_spqe;
4305 }
4306
4307 switch (opcode | bp->state) {
4308 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4309 BNX2X_STATE_OPEN):
4310 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4311 BNX2X_STATE_OPENING_WAIT4_PORT):
4312 cid = elem->message.data.eth_event.echo &
4313 BNX2X_SWCID_MASK;
4314 DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n",
4315 cid);
4316 rss_raw->clear_pending(rss_raw);
4317 break;
4318
4319 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4320 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4321 case (EVENT_RING_OPCODE_SET_MAC |
4322 BNX2X_STATE_CLOSING_WAIT4_HALT):
4323 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4324 BNX2X_STATE_OPEN):
4325 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4326 BNX2X_STATE_DIAG):
4327 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4328 BNX2X_STATE_CLOSING_WAIT4_HALT):
4329 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
4330 bnx2x_handle_classification_eqe(bp, elem);
4331 break;
4332
4333 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4334 BNX2X_STATE_OPEN):
4335 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4336 BNX2X_STATE_DIAG):
4337 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4338 BNX2X_STATE_CLOSING_WAIT4_HALT):
4339 DP(NETIF_MSG_IFUP, "got mcast ramrod\n");
4340 bnx2x_handle_mcast_eqe(bp);
4341 break;
4342
4343 case (EVENT_RING_OPCODE_FILTERS_RULES |
4344 BNX2X_STATE_OPEN):
4345 case (EVENT_RING_OPCODE_FILTERS_RULES |
4346 BNX2X_STATE_DIAG):
4347 case (EVENT_RING_OPCODE_FILTERS_RULES |
4348 BNX2X_STATE_CLOSING_WAIT4_HALT):
4349 DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n");
4350 bnx2x_handle_rx_mode_eqe(bp);
4351 break;
4352 default:
4353 /* unknown event log error and continue */
4354 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4355 elem->message.opcode, bp->state);
4356 }
4357 next_spqe:
4358 spqe_cnt++;
4359 } /* for */
4360
4361 smp_mb__before_atomic_inc();
4362 atomic_add(spqe_cnt, &bp->eq_spq_left);
4363
4364 bp->eq_cons = sw_cons;
4365 bp->eq_prod = sw_prod;
4366 /* Make sure that above mem writes were issued towards the memory */
4367 smp_wmb();
4368
4369 /* update producer */
4370 bnx2x_update_eq_prod(bp, bp->eq_prod);
4371 }
4372
4373 static void bnx2x_sp_task(struct work_struct *work)
4374 {
4375 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4376 u16 status;
4377
4378 status = bnx2x_update_dsb_idx(bp);
4379 /* if (status == 0) */
4380 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4381
4382 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4383
4384 /* HW attentions */
4385 if (status & BNX2X_DEF_SB_ATT_IDX) {
4386 bnx2x_attn_int(bp);
4387 status &= ~BNX2X_DEF_SB_ATT_IDX;
4388 }
4389
4390 /* SP events: STAT_QUERY and others */
4391 if (status & BNX2X_DEF_SB_IDX) {
4392 #ifdef BCM_CNIC
4393 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4394
4395 if ((!NO_FCOE(bp)) &&
4396 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
4397 napi_schedule(&bnx2x_fcoe(bp, napi));
4398 #endif
4399 /* Handle EQ completions */
4400 bnx2x_eq_int(bp);
4401
4402 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4403 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4404
4405 status &= ~BNX2X_DEF_SB_IDX;
4406 }
4407
4408 if (unlikely(status))
4409 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4410 status);
4411
4412 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4413 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4414 }
4415
4416 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4417 {
4418 struct net_device *dev = dev_instance;
4419 struct bnx2x *bp = netdev_priv(dev);
4420
4421 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4422 IGU_INT_DISABLE, 0);
4423
4424 #ifdef BNX2X_STOP_ON_ERROR
4425 if (unlikely(bp->panic))
4426 return IRQ_HANDLED;
4427 #endif
4428
4429 #ifdef BCM_CNIC
4430 {
4431 struct cnic_ops *c_ops;
4432
4433 rcu_read_lock();
4434 c_ops = rcu_dereference(bp->cnic_ops);
4435 if (c_ops)
4436 c_ops->cnic_handler(bp->cnic_data, NULL);
4437 rcu_read_unlock();
4438 }
4439 #endif
4440 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4441
4442 return IRQ_HANDLED;
4443 }
4444
4445 /* end of slow path */
4446
4447
4448 void bnx2x_drv_pulse(struct bnx2x *bp)
4449 {
4450 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4451 bp->fw_drv_pulse_wr_seq);
4452 }
4453
4454
4455 static void bnx2x_timer(unsigned long data)
4456 {
4457 struct bnx2x *bp = (struct bnx2x *) data;
4458
4459 if (!netif_running(bp->dev))
4460 return;
4461
4462 if (poll) {
4463 struct bnx2x_fastpath *fp = &bp->fp[0];
4464
4465 bnx2x_tx_int(fp);
4466 bnx2x_rx_int(fp, 1000);
4467 }
4468
4469 if (!BP_NOMCP(bp)) {
4470 int mb_idx = BP_FW_MB_IDX(bp);
4471 u32 drv_pulse;
4472 u32 mcp_pulse;
4473
4474 ++bp->fw_drv_pulse_wr_seq;
4475 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4476 /* TBD - add SYSTEM_TIME */
4477 drv_pulse = bp->fw_drv_pulse_wr_seq;
4478 bnx2x_drv_pulse(bp);
4479
4480 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4481 MCP_PULSE_SEQ_MASK);
4482 /* The delta between driver pulse and mcp response
4483 * should be 1 (before mcp response) or 0 (after mcp response)
4484 */
4485 if ((drv_pulse != mcp_pulse) &&
4486 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4487 /* someone lost a heartbeat... */
4488 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4489 drv_pulse, mcp_pulse);
4490 }
4491 }
4492
4493 if (bp->state == BNX2X_STATE_OPEN)
4494 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4495
4496 mod_timer(&bp->timer, jiffies + bp->current_interval);
4497 }
4498
4499 /* end of Statistics */
4500
4501 /* nic init */
4502
4503 /*
4504 * nic init service functions
4505 */
4506
4507 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4508 {
4509 u32 i;
4510 if (!(len%4) && !(addr%4))
4511 for (i = 0; i < len; i += 4)
4512 REG_WR(bp, addr + i, fill);
4513 else
4514 for (i = 0; i < len; i++)
4515 REG_WR8(bp, addr + i, fill);
4516
4517 }
4518
4519 /* helper: writes FP SP data to FW - data_size in dwords */
4520 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4521 int fw_sb_id,
4522 u32 *sb_data_p,
4523 u32 data_size)
4524 {
4525 int index;
4526 for (index = 0; index < data_size; index++)
4527 REG_WR(bp, BAR_CSTRORM_INTMEM +
4528 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4529 sizeof(u32)*index,
4530 *(sb_data_p + index));
4531 }
4532
4533 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4534 {
4535 u32 *sb_data_p;
4536 u32 data_size = 0;
4537 struct hc_status_block_data_e2 sb_data_e2;
4538 struct hc_status_block_data_e1x sb_data_e1x;
4539
4540 /* disable the function first */
4541 if (!CHIP_IS_E1x(bp)) {
4542 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4543 sb_data_e2.common.state = SB_DISABLED;
4544 sb_data_e2.common.p_func.vf_valid = false;
4545 sb_data_p = (u32 *)&sb_data_e2;
4546 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4547 } else {
4548 memset(&sb_data_e1x, 0,
4549 sizeof(struct hc_status_block_data_e1x));
4550 sb_data_e1x.common.state = SB_DISABLED;
4551 sb_data_e1x.common.p_func.vf_valid = false;
4552 sb_data_p = (u32 *)&sb_data_e1x;
4553 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4554 }
4555 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4556
4557 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4558 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4559 CSTORM_STATUS_BLOCK_SIZE);
4560 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4561 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4562 CSTORM_SYNC_BLOCK_SIZE);
4563 }
4564
4565 /* helper: writes SP SB data to FW */
4566 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4567 struct hc_sp_status_block_data *sp_sb_data)
4568 {
4569 int func = BP_FUNC(bp);
4570 int i;
4571 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4572 REG_WR(bp, BAR_CSTRORM_INTMEM +
4573 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4574 i*sizeof(u32),
4575 *((u32 *)sp_sb_data + i));
4576 }
4577
4578 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4579 {
4580 int func = BP_FUNC(bp);
4581 struct hc_sp_status_block_data sp_sb_data;
4582 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4583
4584 sp_sb_data.state = SB_DISABLED;
4585 sp_sb_data.p_func.vf_valid = false;
4586
4587 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4588
4589 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4590 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4591 CSTORM_SP_STATUS_BLOCK_SIZE);
4592 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4593 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4594 CSTORM_SP_SYNC_BLOCK_SIZE);
4595
4596 }
4597
4598
4599 static inline
4600 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4601 int igu_sb_id, int igu_seg_id)
4602 {
4603 hc_sm->igu_sb_id = igu_sb_id;
4604 hc_sm->igu_seg_id = igu_seg_id;
4605 hc_sm->timer_value = 0xFF;
4606 hc_sm->time_to_expire = 0xFFFFFFFF;
4607 }
4608
4609 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4610 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4611 {
4612 int igu_seg_id;
4613
4614 struct hc_status_block_data_e2 sb_data_e2;
4615 struct hc_status_block_data_e1x sb_data_e1x;
4616 struct hc_status_block_sm *hc_sm_p;
4617 int data_size;
4618 u32 *sb_data_p;
4619
4620 if (CHIP_INT_MODE_IS_BC(bp))
4621 igu_seg_id = HC_SEG_ACCESS_NORM;
4622 else
4623 igu_seg_id = IGU_SEG_ACCESS_NORM;
4624
4625 bnx2x_zero_fp_sb(bp, fw_sb_id);
4626
4627 if (!CHIP_IS_E1x(bp)) {
4628 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4629 sb_data_e2.common.state = SB_ENABLED;
4630 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4631 sb_data_e2.common.p_func.vf_id = vfid;
4632 sb_data_e2.common.p_func.vf_valid = vf_valid;
4633 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4634 sb_data_e2.common.same_igu_sb_1b = true;
4635 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4636 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4637 hc_sm_p = sb_data_e2.common.state_machine;
4638 sb_data_p = (u32 *)&sb_data_e2;
4639 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4640 } else {
4641 memset(&sb_data_e1x, 0,
4642 sizeof(struct hc_status_block_data_e1x));
4643 sb_data_e1x.common.state = SB_ENABLED;
4644 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4645 sb_data_e1x.common.p_func.vf_id = 0xff;
4646 sb_data_e1x.common.p_func.vf_valid = false;
4647 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4648 sb_data_e1x.common.same_igu_sb_1b = true;
4649 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4650 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4651 hc_sm_p = sb_data_e1x.common.state_machine;
4652 sb_data_p = (u32 *)&sb_data_e1x;
4653 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4654 }
4655
4656 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4657 igu_sb_id, igu_seg_id);
4658 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4659 igu_sb_id, igu_seg_id);
4660
4661 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4662
4663 /* write indecies to HW */
4664 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4665 }
4666
4667 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4668 u16 tx_usec, u16 rx_usec)
4669 {
4670 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4671 false, rx_usec);
4672 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4673 false, tx_usec);
4674 }
4675
4676 static void bnx2x_init_def_sb(struct bnx2x *bp)
4677 {
4678 struct host_sp_status_block *def_sb = bp->def_status_blk;
4679 dma_addr_t mapping = bp->def_status_blk_mapping;
4680 int igu_sp_sb_index;
4681 int igu_seg_id;
4682 int port = BP_PORT(bp);
4683 int func = BP_FUNC(bp);
4684 int reg_offset;
4685 u64 section;
4686 int index;
4687 struct hc_sp_status_block_data sp_sb_data;
4688 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4689
4690 if (CHIP_INT_MODE_IS_BC(bp)) {
4691 igu_sp_sb_index = DEF_SB_IGU_ID;
4692 igu_seg_id = HC_SEG_ACCESS_DEF;
4693 } else {
4694 igu_sp_sb_index = bp->igu_dsb_id;
4695 igu_seg_id = IGU_SEG_ACCESS_DEF;
4696 }
4697
4698 /* ATTN */
4699 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4700 atten_status_block);
4701 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4702
4703 bp->attn_state = 0;
4704
4705 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4706 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4707 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4708 int sindex;
4709 /* take care of sig[0]..sig[4] */
4710 for (sindex = 0; sindex < 4; sindex++)
4711 bp->attn_group[index].sig[sindex] =
4712 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4713
4714 if (!CHIP_IS_E1x(bp))
4715 /*
4716 * enable5 is separate from the rest of the registers,
4717 * and therefore the address skip is 4
4718 * and not 16 between the different groups
4719 */
4720 bp->attn_group[index].sig[4] = REG_RD(bp,
4721 reg_offset + 0x10 + 0x4*index);
4722 else
4723 bp->attn_group[index].sig[4] = 0;
4724 }
4725
4726 if (bp->common.int_block == INT_BLOCK_HC) {
4727 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4728 HC_REG_ATTN_MSG0_ADDR_L);
4729
4730 REG_WR(bp, reg_offset, U64_LO(section));
4731 REG_WR(bp, reg_offset + 4, U64_HI(section));
4732 } else if (!CHIP_IS_E1x(bp)) {
4733 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4734 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4735 }
4736
4737 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4738 sp_sb);
4739
4740 bnx2x_zero_sp_sb(bp);
4741
4742 sp_sb_data.state = SB_ENABLED;
4743 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4744 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4745 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4746 sp_sb_data.igu_seg_id = igu_seg_id;
4747 sp_sb_data.p_func.pf_id = func;
4748 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4749 sp_sb_data.p_func.vf_id = 0xff;
4750
4751 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4752
4753 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4754 }
4755
4756 void bnx2x_update_coalesce(struct bnx2x *bp)
4757 {
4758 int i;
4759
4760 for_each_eth_queue(bp, i)
4761 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4762 bp->tx_ticks, bp->rx_ticks);
4763 }
4764
4765 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4766 {
4767 spin_lock_init(&bp->spq_lock);
4768 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4769
4770 bp->spq_prod_idx = 0;
4771 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4772 bp->spq_prod_bd = bp->spq;
4773 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4774 }
4775
4776 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4777 {
4778 int i;
4779 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4780 union event_ring_elem *elem =
4781 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4782
4783 elem->next_page.addr.hi =
4784 cpu_to_le32(U64_HI(bp->eq_mapping +
4785 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4786 elem->next_page.addr.lo =
4787 cpu_to_le32(U64_LO(bp->eq_mapping +
4788 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4789 }
4790 bp->eq_cons = 0;
4791 bp->eq_prod = NUM_EQ_DESC;
4792 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4793 /* we want a warning message before it gets rought... */
4794 atomic_set(&bp->eq_spq_left,
4795 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
4796 }
4797
4798
4799 /* called with netif_addr_lock_bh() */
4800 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
4801 unsigned long rx_mode_flags,
4802 unsigned long rx_accept_flags,
4803 unsigned long tx_accept_flags,
4804 unsigned long ramrod_flags)
4805 {
4806 struct bnx2x_rx_mode_ramrod_params ramrod_param;
4807 int rc;
4808
4809 memset(&ramrod_param, 0, sizeof(ramrod_param));
4810
4811 /* Prepare ramrod parameters */
4812 ramrod_param.cid = 0;
4813 ramrod_param.cl_id = cl_id;
4814 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
4815 ramrod_param.func_id = BP_FUNC(bp);
4816
4817 ramrod_param.pstate = &bp->sp_state;
4818 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
4819
4820 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
4821 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
4822
4823 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4824
4825 ramrod_param.ramrod_flags = ramrod_flags;
4826 ramrod_param.rx_mode_flags = rx_mode_flags;
4827
4828 ramrod_param.rx_accept_flags = rx_accept_flags;
4829 ramrod_param.tx_accept_flags = tx_accept_flags;
4830
4831 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
4832 if (rc < 0) {
4833 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
4834 return;
4835 }
4836 }
4837
4838 /* called with netif_addr_lock_bh() */
4839 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4840 {
4841 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
4842 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
4843
4844 #ifdef BCM_CNIC
4845 if (!NO_FCOE(bp))
4846
4847 /* Configure rx_mode of FCoE Queue */
4848 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
4849 #endif
4850
4851 switch (bp->rx_mode) {
4852 case BNX2X_RX_MODE_NONE:
4853 /*
4854 * 'drop all' supersedes any accept flags that may have been
4855 * passed to the function.
4856 */
4857 break;
4858 case BNX2X_RX_MODE_NORMAL:
4859 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4860 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
4861 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4862
4863 /* internal switching mode */
4864 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4865 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
4866 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4867
4868 break;
4869 case BNX2X_RX_MODE_ALLMULTI:
4870 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4871 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
4872 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4873
4874 /* internal switching mode */
4875 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4876 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
4877 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4878
4879 break;
4880 case BNX2X_RX_MODE_PROMISC:
4881 /* According to deffinition of SI mode, iface in promisc mode
4882 * should receive matched and unmatched (in resolution of port)
4883 * unicast packets.
4884 */
4885 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
4886 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4887 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
4888 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4889
4890 /* internal switching mode */
4891 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
4892 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4893
4894 if (IS_MF_SI(bp))
4895 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
4896 else
4897 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4898
4899 break;
4900 default:
4901 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
4902 return;
4903 }
4904
4905 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
4906 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
4907 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
4908 }
4909
4910 __set_bit(RAMROD_RX, &ramrod_flags);
4911 __set_bit(RAMROD_TX, &ramrod_flags);
4912
4913 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
4914 tx_accept_flags, ramrod_flags);
4915 }
4916
4917 static void bnx2x_init_internal_common(struct bnx2x *bp)
4918 {
4919 int i;
4920
4921 if (IS_MF_SI(bp))
4922 /*
4923 * In switch independent mode, the TSTORM needs to accept
4924 * packets that failed classification, since approximate match
4925 * mac addresses aren't written to NIG LLH
4926 */
4927 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4928 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4929 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
4930 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4931 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
4932
4933 /* Zero this manually as its initialization is
4934 currently missing in the initTool */
4935 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4936 REG_WR(bp, BAR_USTRORM_INTMEM +
4937 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4938 if (!CHIP_IS_E1x(bp)) {
4939 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4940 CHIP_INT_MODE_IS_BC(bp) ?
4941 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4942 }
4943 }
4944
4945 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4946 {
4947 switch (load_code) {
4948 case FW_MSG_CODE_DRV_LOAD_COMMON:
4949 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4950 bnx2x_init_internal_common(bp);
4951 /* no break */
4952
4953 case FW_MSG_CODE_DRV_LOAD_PORT:
4954 /* nothing to do */
4955 /* no break */
4956
4957 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4958 /* internal memory per function is
4959 initialized inside bnx2x_pf_init */
4960 break;
4961
4962 default:
4963 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4964 break;
4965 }
4966 }
4967
4968 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
4969 {
4970 return fp->bp->igu_base_sb + fp->index + CNIC_CONTEXT_USE;
4971 }
4972
4973 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
4974 {
4975 return fp->bp->base_fw_ndsb + fp->index + CNIC_CONTEXT_USE;
4976 }
4977
4978 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
4979 {
4980 if (CHIP_IS_E1x(fp->bp))
4981 return BP_L_ID(fp->bp) + fp->index;
4982 else /* We want Client ID to be the same as IGU SB ID for 57712 */
4983 return bnx2x_fp_igu_sb_id(fp);
4984 }
4985
4986 static void bnx2x_init_fp(struct bnx2x *bp, int fp_idx)
4987 {
4988 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4989 unsigned long q_type = 0;
4990
4991 fp->cid = fp_idx;
4992 fp->cl_id = bnx2x_fp_cl_id(fp);
4993 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
4994 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
4995 /* qZone id equals to FW (per path) client id */
4996 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4997
4998 /* init shortcut */
4999 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5000 /* Setup SB indicies */
5001 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5002 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
5003
5004 /* Configure Queue State object */
5005 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5006 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5007 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, fp->cid, BP_FUNC(bp),
5008 bnx2x_sp(bp, q_rdata), bnx2x_sp_mapping(bp, q_rdata),
5009 q_type);
5010
5011 /**
5012 * Configure classification DBs: Always enable Tx switching
5013 */
5014 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5015
5016 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5017 "cl_id %d fw_sb %d igu_sb %d\n",
5018 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5019 fp->igu_sb_id);
5020 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5021 fp->fw_sb_id, fp->igu_sb_id);
5022
5023 bnx2x_update_fpsb_idx(fp);
5024 }
5025
5026 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5027 {
5028 int i;
5029
5030 for_each_eth_queue(bp, i)
5031 bnx2x_init_fp(bp, i);
5032 #ifdef BCM_CNIC
5033 if (!NO_FCOE(bp))
5034 bnx2x_init_fcoe_fp(bp);
5035
5036 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5037 BNX2X_VF_ID_INVALID, false,
5038 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5039
5040 #endif
5041
5042 /* Initialize MOD_ABS interrupts */
5043 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5044 bp->common.shmem_base, bp->common.shmem2_base,
5045 BP_PORT(bp));
5046 /* ensure status block indices were read */
5047 rmb();
5048
5049 bnx2x_init_def_sb(bp);
5050 bnx2x_update_dsb_idx(bp);
5051 bnx2x_init_rx_rings(bp);
5052 bnx2x_init_tx_rings(bp);
5053 bnx2x_init_sp_ring(bp);
5054 bnx2x_init_eq_ring(bp);
5055 bnx2x_init_internal(bp, load_code);
5056 bnx2x_pf_init(bp);
5057 bnx2x_stats_init(bp);
5058
5059 /* flush all before enabling interrupts */
5060 mb();
5061 mmiowb();
5062
5063 bnx2x_int_enable(bp);
5064
5065 /* Check for SPIO5 */
5066 bnx2x_attn_int_deasserted0(bp,
5067 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5068 AEU_INPUTS_ATTN_BITS_SPIO5);
5069 }
5070
5071 /* end of nic init */
5072
5073 /*
5074 * gzip service functions
5075 */
5076
5077 static int bnx2x_gunzip_init(struct bnx2x *bp)
5078 {
5079 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5080 &bp->gunzip_mapping, GFP_KERNEL);
5081 if (bp->gunzip_buf == NULL)
5082 goto gunzip_nomem1;
5083
5084 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5085 if (bp->strm == NULL)
5086 goto gunzip_nomem2;
5087
5088 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
5089 GFP_KERNEL);
5090 if (bp->strm->workspace == NULL)
5091 goto gunzip_nomem3;
5092
5093 return 0;
5094
5095 gunzip_nomem3:
5096 kfree(bp->strm);
5097 bp->strm = NULL;
5098
5099 gunzip_nomem2:
5100 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5101 bp->gunzip_mapping);
5102 bp->gunzip_buf = NULL;
5103
5104 gunzip_nomem1:
5105 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5106 " un-compression\n");
5107 return -ENOMEM;
5108 }
5109
5110 static void bnx2x_gunzip_end(struct bnx2x *bp)
5111 {
5112 if (bp->strm) {
5113 kfree(bp->strm->workspace);
5114 kfree(bp->strm);
5115 bp->strm = NULL;
5116 }
5117
5118 if (bp->gunzip_buf) {
5119 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5120 bp->gunzip_mapping);
5121 bp->gunzip_buf = NULL;
5122 }
5123 }
5124
5125 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5126 {
5127 int n, rc;
5128
5129 /* check gzip header */
5130 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5131 BNX2X_ERR("Bad gzip header\n");
5132 return -EINVAL;
5133 }
5134
5135 n = 10;
5136
5137 #define FNAME 0x8
5138
5139 if (zbuf[3] & FNAME)
5140 while ((zbuf[n++] != 0) && (n < len));
5141
5142 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5143 bp->strm->avail_in = len - n;
5144 bp->strm->next_out = bp->gunzip_buf;
5145 bp->strm->avail_out = FW_BUF_SIZE;
5146
5147 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5148 if (rc != Z_OK)
5149 return rc;
5150
5151 rc = zlib_inflate(bp->strm, Z_FINISH);
5152 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5153 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5154 bp->strm->msg);
5155
5156 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5157 if (bp->gunzip_outlen & 0x3)
5158 netdev_err(bp->dev, "Firmware decompression error:"
5159 " gunzip_outlen (%d) not aligned\n",
5160 bp->gunzip_outlen);
5161 bp->gunzip_outlen >>= 2;
5162
5163 zlib_inflateEnd(bp->strm);
5164
5165 if (rc == Z_STREAM_END)
5166 return 0;
5167
5168 return rc;
5169 }
5170
5171 /* nic load/unload */
5172
5173 /*
5174 * General service functions
5175 */
5176
5177 /* send a NIG loopback debug packet */
5178 static void bnx2x_lb_pckt(struct bnx2x *bp)
5179 {
5180 u32 wb_write[3];
5181
5182 /* Ethernet source and destination addresses */
5183 wb_write[0] = 0x55555555;
5184 wb_write[1] = 0x55555555;
5185 wb_write[2] = 0x20; /* SOP */
5186 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5187
5188 /* NON-IP protocol */
5189 wb_write[0] = 0x09000000;
5190 wb_write[1] = 0x55555555;
5191 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5192 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5193 }
5194
5195 /* some of the internal memories
5196 * are not directly readable from the driver
5197 * to test them we send debug packets
5198 */
5199 static int bnx2x_int_mem_test(struct bnx2x *bp)
5200 {
5201 int factor;
5202 int count, i;
5203 u32 val = 0;
5204
5205 if (CHIP_REV_IS_FPGA(bp))
5206 factor = 120;
5207 else if (CHIP_REV_IS_EMUL(bp))
5208 factor = 200;
5209 else
5210 factor = 1;
5211
5212 /* Disable inputs of parser neighbor blocks */
5213 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5214 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5215 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5216 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5217
5218 /* Write 0 to parser credits for CFC search request */
5219 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5220
5221 /* send Ethernet packet */
5222 bnx2x_lb_pckt(bp);
5223
5224 /* TODO do i reset NIG statistic? */
5225 /* Wait until NIG register shows 1 packet of size 0x10 */
5226 count = 1000 * factor;
5227 while (count) {
5228
5229 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5230 val = *bnx2x_sp(bp, wb_data[0]);
5231 if (val == 0x10)
5232 break;
5233
5234 msleep(10);
5235 count--;
5236 }
5237 if (val != 0x10) {
5238 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5239 return -1;
5240 }
5241
5242 /* Wait until PRS register shows 1 packet */
5243 count = 1000 * factor;
5244 while (count) {
5245 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5246 if (val == 1)
5247 break;
5248
5249 msleep(10);
5250 count--;
5251 }
5252 if (val != 0x1) {
5253 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5254 return -2;
5255 }
5256
5257 /* Reset and init BRB, PRS */
5258 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5259 msleep(50);
5260 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5261 msleep(50);
5262 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5263 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5264
5265 DP(NETIF_MSG_HW, "part2\n");
5266
5267 /* Disable inputs of parser neighbor blocks */
5268 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5269 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5270 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5271 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5272
5273 /* Write 0 to parser credits for CFC search request */
5274 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5275
5276 /* send 10 Ethernet packets */
5277 for (i = 0; i < 10; i++)
5278 bnx2x_lb_pckt(bp);
5279
5280 /* Wait until NIG register shows 10 + 1
5281 packets of size 11*0x10 = 0xb0 */
5282 count = 1000 * factor;
5283 while (count) {
5284
5285 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5286 val = *bnx2x_sp(bp, wb_data[0]);
5287 if (val == 0xb0)
5288 break;
5289
5290 msleep(10);
5291 count--;
5292 }
5293 if (val != 0xb0) {
5294 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5295 return -3;
5296 }
5297
5298 /* Wait until PRS register shows 2 packets */
5299 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5300 if (val != 2)
5301 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5302
5303 /* Write 1 to parser credits for CFC search request */
5304 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5305
5306 /* Wait until PRS register shows 3 packets */
5307 msleep(10 * factor);
5308 /* Wait until NIG register shows 1 packet of size 0x10 */
5309 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5310 if (val != 3)
5311 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5312
5313 /* clear NIG EOP FIFO */
5314 for (i = 0; i < 11; i++)
5315 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5316 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5317 if (val != 1) {
5318 BNX2X_ERR("clear of NIG failed\n");
5319 return -4;
5320 }
5321
5322 /* Reset and init BRB, PRS, NIG */
5323 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5324 msleep(50);
5325 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5326 msleep(50);
5327 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5328 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5329 #ifndef BCM_CNIC
5330 /* set NIC mode */
5331 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5332 #endif
5333
5334 /* Enable inputs of parser neighbor blocks */
5335 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5336 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5337 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5338 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5339
5340 DP(NETIF_MSG_HW, "done\n");
5341
5342 return 0; /* OK */
5343 }
5344
5345 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5346 {
5347 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5348 if (!CHIP_IS_E1x(bp))
5349 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5350 else
5351 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5352 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5353 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5354 /*
5355 * mask read length error interrupts in brb for parser
5356 * (parsing unit and 'checksum and crc' unit)
5357 * these errors are legal (PU reads fixed length and CAC can cause
5358 * read length error on truncated packets)
5359 */
5360 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5361 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5362 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5363 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5364 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5365 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5366 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5367 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5368 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5369 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5370 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5371 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5372 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5373 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5374 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5375 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5376 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5377 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5378 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5379
5380 if (CHIP_REV_IS_FPGA(bp))
5381 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5382 else if (!CHIP_IS_E1x(bp))
5383 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5384 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5385 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5386 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5387 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5388 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5389 else
5390 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5391 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5392 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5393 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5394 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5395
5396 if (!CHIP_IS_E1x(bp))
5397 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5398 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5399
5400 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5401 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5402 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5403 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5404 }
5405
5406 static void bnx2x_reset_common(struct bnx2x *bp)
5407 {
5408 u32 val = 0x1400;
5409
5410 /* reset_common */
5411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5412 0xd3ffff7f);
5413
5414 if (CHIP_IS_E3(bp)) {
5415 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5416 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5417 }
5418
5419 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5420 }
5421
5422 static void bnx2x_setup_dmae(struct bnx2x *bp)
5423 {
5424 bp->dmae_ready = 0;
5425 spin_lock_init(&bp->dmae_lock);
5426 }
5427
5428 static void bnx2x_init_pxp(struct bnx2x *bp)
5429 {
5430 u16 devctl;
5431 int r_order, w_order;
5432
5433 pci_read_config_word(bp->pdev,
5434 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
5435 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5436 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5437 if (bp->mrrs == -1)
5438 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5439 else {
5440 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5441 r_order = bp->mrrs;
5442 }
5443
5444 bnx2x_init_pxp_arb(bp, r_order, w_order);
5445 }
5446
5447 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5448 {
5449 int is_required;
5450 u32 val;
5451 int port;
5452
5453 if (BP_NOMCP(bp))
5454 return;
5455
5456 is_required = 0;
5457 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5458 SHARED_HW_CFG_FAN_FAILURE_MASK;
5459
5460 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5461 is_required = 1;
5462
5463 /*
5464 * The fan failure mechanism is usually related to the PHY type since
5465 * the power consumption of the board is affected by the PHY. Currently,
5466 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5467 */
5468 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5469 for (port = PORT_0; port < PORT_MAX; port++) {
5470 is_required |=
5471 bnx2x_fan_failure_det_req(
5472 bp,
5473 bp->common.shmem_base,
5474 bp->common.shmem2_base,
5475 port);
5476 }
5477
5478 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5479
5480 if (is_required == 0)
5481 return;
5482
5483 /* Fan failure is indicated by SPIO 5 */
5484 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5485 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5486
5487 /* set to active low mode */
5488 val = REG_RD(bp, MISC_REG_SPIO_INT);
5489 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5490 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5491 REG_WR(bp, MISC_REG_SPIO_INT, val);
5492
5493 /* enable interrupt to signal the IGU */
5494 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5495 val |= (1 << MISC_REGISTERS_SPIO_5);
5496 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5497 }
5498
5499 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5500 {
5501 u32 offset = 0;
5502
5503 if (CHIP_IS_E1(bp))
5504 return;
5505 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5506 return;
5507
5508 switch (BP_ABS_FUNC(bp)) {
5509 case 0:
5510 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5511 break;
5512 case 1:
5513 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5514 break;
5515 case 2:
5516 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5517 break;
5518 case 3:
5519 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5520 break;
5521 case 4:
5522 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5523 break;
5524 case 5:
5525 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5526 break;
5527 case 6:
5528 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5529 break;
5530 case 7:
5531 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5532 break;
5533 default:
5534 return;
5535 }
5536
5537 REG_WR(bp, offset, pretend_func_num);
5538 REG_RD(bp, offset);
5539 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5540 }
5541
5542 void bnx2x_pf_disable(struct bnx2x *bp)
5543 {
5544 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5545 val &= ~IGU_PF_CONF_FUNC_EN;
5546
5547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5548 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5549 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5550 }
5551
5552 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5553 {
5554 u32 shmem_base[2], shmem2_base[2];
5555 shmem_base[0] = bp->common.shmem_base;
5556 shmem2_base[0] = bp->common.shmem2_base;
5557 if (!CHIP_IS_E1x(bp)) {
5558 shmem_base[1] =
5559 SHMEM2_RD(bp, other_shmem_base_addr);
5560 shmem2_base[1] =
5561 SHMEM2_RD(bp, other_shmem2_base_addr);
5562 }
5563 bnx2x_acquire_phy_lock(bp);
5564 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5565 bp->common.chip_id);
5566 bnx2x_release_phy_lock(bp);
5567 }
5568
5569 /**
5570 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5571 *
5572 * @bp: driver handle
5573 */
5574 static int bnx2x_init_hw_common(struct bnx2x *bp)
5575 {
5576 u32 val;
5577
5578 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5579
5580 bnx2x_reset_common(bp);
5581 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5582
5583 val = 0xfffc;
5584 if (CHIP_IS_E3(bp)) {
5585 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5586 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5587 }
5588 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5589
5590 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5591
5592 if (!CHIP_IS_E1x(bp)) {
5593 u8 abs_func_id;
5594
5595 /**
5596 * 4-port mode or 2-port mode we need to turn of master-enable
5597 * for everyone, after that, turn it back on for self.
5598 * so, we disregard multi-function or not, and always disable
5599 * for all functions on the given path, this means 0,2,4,6 for
5600 * path 0 and 1,3,5,7 for path 1
5601 */
5602 for (abs_func_id = BP_PATH(bp);
5603 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5604 if (abs_func_id == BP_ABS_FUNC(bp)) {
5605 REG_WR(bp,
5606 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5607 1);
5608 continue;
5609 }
5610
5611 bnx2x_pretend_func(bp, abs_func_id);
5612 /* clear pf enable */
5613 bnx2x_pf_disable(bp);
5614 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5615 }
5616 }
5617
5618 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5619 if (CHIP_IS_E1(bp)) {
5620 /* enable HW interrupt from PXP on USDM overflow
5621 bit 16 on INT_MASK_0 */
5622 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5623 }
5624
5625 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5626 bnx2x_init_pxp(bp);
5627
5628 #ifdef __BIG_ENDIAN
5629 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5630 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5631 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5632 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5633 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5634 /* make sure this value is 0 */
5635 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5636
5637 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5638 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5639 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5640 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5641 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5642 #endif
5643
5644 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5645
5646 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5647 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5648
5649 /* let the HW do it's magic ... */
5650 msleep(100);
5651 /* finish PXP init */
5652 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5653 if (val != 1) {
5654 BNX2X_ERR("PXP2 CFG failed\n");
5655 return -EBUSY;
5656 }
5657 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5658 if (val != 1) {
5659 BNX2X_ERR("PXP2 RD_INIT failed\n");
5660 return -EBUSY;
5661 }
5662
5663 /* Timers bug workaround E2 only. We need to set the entire ILT to
5664 * have entries with value "0" and valid bit on.
5665 * This needs to be done by the first PF that is loaded in a path
5666 * (i.e. common phase)
5667 */
5668 if (!CHIP_IS_E1x(bp)) {
5669 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5670 * (i.e. vnic3) to start even if it is marked as "scan-off".
5671 * This occurs when a different function (func2,3) is being marked
5672 * as "scan-off". Real-life scenario for example: if a driver is being
5673 * load-unloaded while func6,7 are down. This will cause the timer to access
5674 * the ilt, translate to a logical address and send a request to read/write.
5675 * Since the ilt for the function that is down is not valid, this will cause
5676 * a translation error which is unrecoverable.
5677 * The Workaround is intended to make sure that when this happens nothing fatal
5678 * will occur. The workaround:
5679 * 1. First PF driver which loads on a path will:
5680 * a. After taking the chip out of reset, by using pretend,
5681 * it will write "0" to the following registers of
5682 * the other vnics.
5683 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5684 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5685 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5686 * And for itself it will write '1' to
5687 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5688 * dmae-operations (writing to pram for example.)
5689 * note: can be done for only function 6,7 but cleaner this
5690 * way.
5691 * b. Write zero+valid to the entire ILT.
5692 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5693 * VNIC3 (of that port). The range allocated will be the
5694 * entire ILT. This is needed to prevent ILT range error.
5695 * 2. Any PF driver load flow:
5696 * a. ILT update with the physical addresses of the allocated
5697 * logical pages.
5698 * b. Wait 20msec. - note that this timeout is needed to make
5699 * sure there are no requests in one of the PXP internal
5700 * queues with "old" ILT addresses.
5701 * c. PF enable in the PGLC.
5702 * d. Clear the was_error of the PF in the PGLC. (could have
5703 * occured while driver was down)
5704 * e. PF enable in the CFC (WEAK + STRONG)
5705 * f. Timers scan enable
5706 * 3. PF driver unload flow:
5707 * a. Clear the Timers scan_en.
5708 * b. Polling for scan_on=0 for that PF.
5709 * c. Clear the PF enable bit in the PXP.
5710 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5711 * e. Write zero+valid to all ILT entries (The valid bit must
5712 * stay set)
5713 * f. If this is VNIC 3 of a port then also init
5714 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5715 * to the last enrty in the ILT.
5716 *
5717 * Notes:
5718 * Currently the PF error in the PGLC is non recoverable.
5719 * In the future the there will be a recovery routine for this error.
5720 * Currently attention is masked.
5721 * Having an MCP lock on the load/unload process does not guarantee that
5722 * there is no Timer disable during Func6/7 enable. This is because the
5723 * Timers scan is currently being cleared by the MCP on FLR.
5724 * Step 2.d can be done only for PF6/7 and the driver can also check if
5725 * there is error before clearing it. But the flow above is simpler and
5726 * more general.
5727 * All ILT entries are written by zero+valid and not just PF6/7
5728 * ILT entries since in the future the ILT entries allocation for
5729 * PF-s might be dynamic.
5730 */
5731 struct ilt_client_info ilt_cli;
5732 struct bnx2x_ilt ilt;
5733 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5734 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5735
5736 /* initialize dummy TM client */
5737 ilt_cli.start = 0;
5738 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5739 ilt_cli.client_num = ILT_CLIENT_TM;
5740
5741 /* Step 1: set zeroes to all ilt page entries with valid bit on
5742 * Step 2: set the timers first/last ilt entry to point
5743 * to the entire range to prevent ILT range error for 3rd/4th
5744 * vnic (this code assumes existance of the vnic)
5745 *
5746 * both steps performed by call to bnx2x_ilt_client_init_op()
5747 * with dummy TM client
5748 *
5749 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5750 * and his brother are split registers
5751 */
5752 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5753 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5754 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5755
5756 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5757 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5758 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5759 }
5760
5761
5762 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5763 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5764
5765 if (!CHIP_IS_E1x(bp)) {
5766 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5767 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5768 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
5769
5770 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
5771
5772 /* let the HW do it's magic ... */
5773 do {
5774 msleep(200);
5775 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5776 } while (factor-- && (val != 1));
5777
5778 if (val != 1) {
5779 BNX2X_ERR("ATC_INIT failed\n");
5780 return -EBUSY;
5781 }
5782 }
5783
5784 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
5785
5786 /* clean the DMAE memory */
5787 bp->dmae_ready = 1;
5788 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
5789
5790 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
5791
5792 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
5793
5794 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
5795
5796 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
5797
5798 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5799 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5800 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5801 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5802
5803 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
5804
5805
5806 /* QM queues pointers table */
5807 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5808
5809 /* soft reset pulse */
5810 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5811 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5812
5813 #ifdef BCM_CNIC
5814 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
5815 #endif
5816
5817 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
5818 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5819 if (!CHIP_REV_IS_SLOW(bp))
5820 /* enable hw interrupt from doorbell Q */
5821 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5822
5823 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5824
5825 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5826 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5827
5828 if (!CHIP_IS_E1(bp))
5829 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
5830
5831 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
5832 /* Bit-map indicating which L2 hdrs may appear
5833 * after the basic Ethernet header
5834 */
5835 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
5836 bp->path_has_ovlan ? 7 : 6);
5837
5838 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
5839 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
5840 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
5841 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
5842
5843 if (!CHIP_IS_E1x(bp)) {
5844 /* reset VFC memories */
5845 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
5846 VFC_MEMORIES_RST_REG_CAM_RST |
5847 VFC_MEMORIES_RST_REG_RAM_RST);
5848 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
5849 VFC_MEMORIES_RST_REG_CAM_RST |
5850 VFC_MEMORIES_RST_REG_RAM_RST);
5851
5852 msleep(20);
5853 }
5854
5855 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
5856 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
5857 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
5858 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
5859
5860 /* sync semi rtc */
5861 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5862 0x80000000);
5863 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5864 0x80000000);
5865
5866 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
5867 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
5868 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
5869
5870 if (!CHIP_IS_E1x(bp))
5871 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
5872 bp->path_has_ovlan ? 7 : 6);
5873
5874 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5875
5876 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
5877
5878 #ifdef BCM_CNIC
5879 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5880 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5881 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5882 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5883 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5884 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5885 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5886 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5887 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5888 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5889 #endif
5890 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5891
5892 if (sizeof(union cdu_context) != 1024)
5893 /* we currently assume that a context is 1024 bytes */
5894 dev_alert(&bp->pdev->dev, "please adjust the size "
5895 "of cdu_context(%ld)\n",
5896 (long)sizeof(union cdu_context));
5897
5898 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
5899 val = (4 << 24) + (0 << 12) + 1024;
5900 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5901
5902 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
5903 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5904 /* enable context validation interrupt from CFC */
5905 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5906
5907 /* set the thresholds to prevent CFC/CDU race */
5908 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5909
5910 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
5911
5912 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
5913 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5914
5915 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
5916 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
5917
5918 /* Reset PCIE errors for debug */
5919 REG_WR(bp, 0x2814, 0xffffffff);
5920 REG_WR(bp, 0x3820, 0xffffffff);
5921
5922 if (!CHIP_IS_E1x(bp)) {
5923 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5924 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5925 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5926 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5927 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5928 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5929 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5930 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5931 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5932 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5933 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5934 }
5935
5936 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
5937 if (!CHIP_IS_E1(bp)) {
5938 /* in E3 this done in per-port section */
5939 if (!CHIP_IS_E3(bp))
5940 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5941 }
5942 if (CHIP_IS_E1H(bp))
5943 /* not applicable for E2 (and above ...) */
5944 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5945
5946 if (CHIP_REV_IS_SLOW(bp))
5947 msleep(200);
5948
5949 /* finish CFC init */
5950 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5951 if (val != 1) {
5952 BNX2X_ERR("CFC LL_INIT failed\n");
5953 return -EBUSY;
5954 }
5955 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5956 if (val != 1) {
5957 BNX2X_ERR("CFC AC_INIT failed\n");
5958 return -EBUSY;
5959 }
5960 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5961 if (val != 1) {
5962 BNX2X_ERR("CFC CAM_INIT failed\n");
5963 return -EBUSY;
5964 }
5965 REG_WR(bp, CFC_REG_DEBUG0, 0);
5966
5967 if (CHIP_IS_E1(bp)) {
5968 /* read NIG statistic
5969 to see if this is our first up since powerup */
5970 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5971 val = *bnx2x_sp(bp, wb_data[0]);
5972
5973 /* do internal memory self test */
5974 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5975 BNX2X_ERR("internal mem self test failed\n");
5976 return -EBUSY;
5977 }
5978 }
5979
5980 bnx2x_setup_fan_failure_detection(bp);
5981
5982 /* clear PXP2 attentions */
5983 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5984
5985 bnx2x_enable_blocks_attention(bp);
5986 bnx2x_enable_blocks_parity(bp);
5987
5988 if (!BP_NOMCP(bp)) {
5989 if (CHIP_IS_E1x(bp))
5990 bnx2x__common_init_phy(bp);
5991 } else
5992 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5993
5994 return 0;
5995 }
5996
5997 /**
5998 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
5999 *
6000 * @bp: driver handle
6001 */
6002 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6003 {
6004 int rc = bnx2x_init_hw_common(bp);
6005
6006 if (rc)
6007 return rc;
6008
6009 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6010 if (!BP_NOMCP(bp))
6011 bnx2x__common_init_phy(bp);
6012
6013 return 0;
6014 }
6015
6016 static int bnx2x_init_hw_port(struct bnx2x *bp)
6017 {
6018 int port = BP_PORT(bp);
6019 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6020 u32 low, high;
6021 u32 val;
6022
6023 bnx2x__link_reset(bp);
6024
6025 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6026
6027 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6028
6029 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6030 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6031 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6032
6033 /* Timers bug workaround: disables the pf_master bit in pglue at
6034 * common phase, we need to enable it here before any dmae access are
6035 * attempted. Therefore we manually added the enable-master to the
6036 * port phase (it also happens in the function phase)
6037 */
6038 if (!CHIP_IS_E1x(bp))
6039 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6040
6041 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6042 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6043 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6044 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6045
6046 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6047 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6048 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6049 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6050
6051 /* QM cid (connection) count */
6052 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6053
6054 #ifdef BCM_CNIC
6055 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6056 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6057 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6058 #endif
6059
6060 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6061
6062 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6063 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6064
6065 if (IS_MF(bp))
6066 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6067 else if (bp->dev->mtu > 4096) {
6068 if (bp->flags & ONE_PORT_FLAG)
6069 low = 160;
6070 else {
6071 val = bp->dev->mtu;
6072 /* (24*1024 + val*4)/256 */
6073 low = 96 + (val/64) +
6074 ((val % 64) ? 1 : 0);
6075 }
6076 } else
6077 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6078 high = low + 56; /* 14*1024/256 */
6079 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6080 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6081 }
6082
6083 if (CHIP_MODE_IS_4_PORT(bp))
6084 REG_WR(bp, (BP_PORT(bp) ?
6085 BRB1_REG_MAC_GUARANTIED_1 :
6086 BRB1_REG_MAC_GUARANTIED_0), 40);
6087
6088
6089 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6090 if (CHIP_IS_E3B0(bp))
6091 /* Ovlan exists only if we are in multi-function +
6092 * switch-dependent mode, in switch-independent there
6093 * is no ovlan headers
6094 */
6095 REG_WR(bp, BP_PORT(bp) ?
6096 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6097 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6098 (bp->path_has_ovlan ? 7 : 6));
6099
6100 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6101 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6102 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6103 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6104
6105 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6106 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6107 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6108 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6109
6110 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6111 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6112
6113 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6114
6115 if (CHIP_IS_E1x(bp)) {
6116 /* configure PBF to work without PAUSE mtu 9000 */
6117 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6118
6119 /* update threshold */
6120 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6121 /* update init credit */
6122 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6123
6124 /* probe changes */
6125 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6126 udelay(50);
6127 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6128 }
6129
6130 #ifdef BCM_CNIC
6131 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6132 #endif
6133 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6134 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6135
6136 if (CHIP_IS_E1(bp)) {
6137 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6138 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6139 }
6140 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6141
6142 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6143
6144 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6145 /* init aeu_mask_attn_func_0/1:
6146 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6147 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6148 * bits 4-7 are used for "per vn group attention" */
6149 val = IS_MF(bp) ? 0xF7 : 0x7;
6150 /* Enable DCBX attention for all but E1 */
6151 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6152 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6153
6154 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6155
6156 if (!CHIP_IS_E1x(bp)) {
6157 /* Bit-map indicating which L2 hdrs may appear after the
6158 * basic Ethernet header
6159 */
6160 REG_WR(bp, BP_PORT(bp) ?
6161 NIG_REG_P1_HDRS_AFTER_BASIC :
6162 NIG_REG_P0_HDRS_AFTER_BASIC,
6163 IS_MF_SD(bp) ? 7 : 6);
6164
6165 if (CHIP_IS_E3(bp))
6166 REG_WR(bp, BP_PORT(bp) ?
6167 NIG_REG_LLH1_MF_MODE :
6168 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6169 }
6170 if (!CHIP_IS_E3(bp))
6171 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6172
6173 if (!CHIP_IS_E1(bp)) {
6174 /* 0x2 disable mf_ov, 0x1 enable */
6175 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6176 (IS_MF_SD(bp) ? 0x1 : 0x2));
6177
6178 if (!CHIP_IS_E1x(bp)) {
6179 val = 0;
6180 switch (bp->mf_mode) {
6181 case MULTI_FUNCTION_SD:
6182 val = 1;
6183 break;
6184 case MULTI_FUNCTION_SI:
6185 val = 2;
6186 break;
6187 }
6188
6189 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6190 NIG_REG_LLH0_CLS_TYPE), val);
6191 }
6192 {
6193 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6194 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6195 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6196 }
6197 }
6198
6199
6200 /* If SPIO5 is set to generate interrupts, enable it for this port */
6201 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6202 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6203 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6204 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6205 val = REG_RD(bp, reg_addr);
6206 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6207 REG_WR(bp, reg_addr, val);
6208 }
6209
6210 return 0;
6211 }
6212
6213 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6214 {
6215 int reg;
6216
6217 if (CHIP_IS_E1(bp))
6218 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6219 else
6220 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6221
6222 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6223 }
6224
6225 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6226 {
6227 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6228 }
6229
6230 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6231 {
6232 u32 i, base = FUNC_ILT_BASE(func);
6233 for (i = base; i < base + ILT_PER_FUNC; i++)
6234 bnx2x_ilt_wr(bp, i, 0);
6235 }
6236
6237 static int bnx2x_init_hw_func(struct bnx2x *bp)
6238 {
6239 int port = BP_PORT(bp);
6240 int func = BP_FUNC(bp);
6241 int init_phase = PHASE_PF0 + func;
6242 struct bnx2x_ilt *ilt = BP_ILT(bp);
6243 u16 cdu_ilt_start;
6244 u32 addr, val;
6245 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6246 int i, main_mem_width;
6247
6248 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6249
6250 /* FLR cleanup - hmmm */
6251 if (!CHIP_IS_E1x(bp))
6252 bnx2x_pf_flr_clnup(bp);
6253
6254 /* set MSI reconfigure capability */
6255 if (bp->common.int_block == INT_BLOCK_HC) {
6256 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6257 val = REG_RD(bp, addr);
6258 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6259 REG_WR(bp, addr, val);
6260 }
6261
6262 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6263 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6264
6265 ilt = BP_ILT(bp);
6266 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6267
6268 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6269 ilt->lines[cdu_ilt_start + i].page =
6270 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6271 ilt->lines[cdu_ilt_start + i].page_mapping =
6272 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6273 /* cdu ilt pages are allocated manually so there's no need to
6274 set the size */
6275 }
6276 bnx2x_ilt_init_op(bp, INITOP_SET);
6277
6278 #ifdef BCM_CNIC
6279 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6280
6281 /* T1 hash bits value determines the T1 number of entries */
6282 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6283 #endif
6284
6285 #ifndef BCM_CNIC
6286 /* set NIC mode */
6287 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6288 #endif /* BCM_CNIC */
6289
6290 if (!CHIP_IS_E1x(bp)) {
6291 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6292
6293 /* Turn on a single ISR mode in IGU if driver is going to use
6294 * INT#x or MSI
6295 */
6296 if (!(bp->flags & USING_MSIX_FLAG))
6297 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6298 /*
6299 * Timers workaround bug: function init part.
6300 * Need to wait 20msec after initializing ILT,
6301 * needed to make sure there are no requests in
6302 * one of the PXP internal queues with "old" ILT addresses
6303 */
6304 msleep(20);
6305 /*
6306 * Master enable - Due to WB DMAE writes performed before this
6307 * register is re-initialized as part of the regular function
6308 * init
6309 */
6310 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6311 /* Enable the function in IGU */
6312 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6313 }
6314
6315 bp->dmae_ready = 1;
6316
6317 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6318
6319 if (!CHIP_IS_E1x(bp))
6320 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6321
6322 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6323 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6324 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6325 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6326 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6327 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6328 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6329 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6330 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6331 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6332 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6333 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6334 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6335
6336 if (!CHIP_IS_E1x(bp))
6337 REG_WR(bp, QM_REG_PF_EN, 1);
6338
6339 if (!CHIP_IS_E1x(bp)) {
6340 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6341 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6342 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6343 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6344 }
6345 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6346
6347 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6348 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6349 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6350 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6351 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6352 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6353 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6354 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6355 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6356 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6357 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6358 if (!CHIP_IS_E1x(bp))
6359 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6360
6361 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6362
6363 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6364
6365 if (!CHIP_IS_E1x(bp))
6366 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6367
6368 if (IS_MF(bp)) {
6369 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6370 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6371 }
6372
6373 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6374
6375 /* HC init per function */
6376 if (bp->common.int_block == INT_BLOCK_HC) {
6377 if (CHIP_IS_E1H(bp)) {
6378 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6379
6380 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6381 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6382 }
6383 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6384
6385 } else {
6386 int num_segs, sb_idx, prod_offset;
6387
6388 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6389
6390 if (!CHIP_IS_E1x(bp)) {
6391 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6392 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6393 }
6394
6395 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6396
6397 if (!CHIP_IS_E1x(bp)) {
6398 int dsb_idx = 0;
6399 /**
6400 * Producer memory:
6401 * E2 mode: address 0-135 match to the mapping memory;
6402 * 136 - PF0 default prod; 137 - PF1 default prod;
6403 * 138 - PF2 default prod; 139 - PF3 default prod;
6404 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6405 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6406 * 144-147 reserved.
6407 *
6408 * E1.5 mode - In backward compatible mode;
6409 * for non default SB; each even line in the memory
6410 * holds the U producer and each odd line hold
6411 * the C producer. The first 128 producers are for
6412 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6413 * producers are for the DSB for each PF.
6414 * Each PF has five segments: (the order inside each
6415 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6416 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6417 * 144-147 attn prods;
6418 */
6419 /* non-default-status-blocks */
6420 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6421 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6422 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6423 prod_offset = (bp->igu_base_sb + sb_idx) *
6424 num_segs;
6425
6426 for (i = 0; i < num_segs; i++) {
6427 addr = IGU_REG_PROD_CONS_MEMORY +
6428 (prod_offset + i) * 4;
6429 REG_WR(bp, addr, 0);
6430 }
6431 /* send consumer update with value 0 */
6432 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6433 USTORM_ID, 0, IGU_INT_NOP, 1);
6434 bnx2x_igu_clear_sb(bp,
6435 bp->igu_base_sb + sb_idx);
6436 }
6437
6438 /* default-status-blocks */
6439 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6440 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6441
6442 if (CHIP_MODE_IS_4_PORT(bp))
6443 dsb_idx = BP_FUNC(bp);
6444 else
6445 dsb_idx = BP_E1HVN(bp);
6446
6447 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6448 IGU_BC_BASE_DSB_PROD + dsb_idx :
6449 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6450
6451 for (i = 0; i < (num_segs * E1HVN_MAX);
6452 i += E1HVN_MAX) {
6453 addr = IGU_REG_PROD_CONS_MEMORY +
6454 (prod_offset + i)*4;
6455 REG_WR(bp, addr, 0);
6456 }
6457 /* send consumer update with 0 */
6458 if (CHIP_INT_MODE_IS_BC(bp)) {
6459 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6460 USTORM_ID, 0, IGU_INT_NOP, 1);
6461 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6462 CSTORM_ID, 0, IGU_INT_NOP, 1);
6463 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6464 XSTORM_ID, 0, IGU_INT_NOP, 1);
6465 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6466 TSTORM_ID, 0, IGU_INT_NOP, 1);
6467 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6468 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6469 } else {
6470 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6471 USTORM_ID, 0, IGU_INT_NOP, 1);
6472 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6473 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6474 }
6475 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6476
6477 /* !!! these should become driver const once
6478 rf-tool supports split-68 const */
6479 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6480 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6481 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6482 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6483 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6484 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6485 }
6486 }
6487
6488 /* Reset PCIE errors for debug */
6489 REG_WR(bp, 0x2114, 0xffffffff);
6490 REG_WR(bp, 0x2120, 0xffffffff);
6491
6492 if (CHIP_IS_E1x(bp)) {
6493 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6494 main_mem_base = HC_REG_MAIN_MEMORY +
6495 BP_PORT(bp) * (main_mem_size * 4);
6496 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6497 main_mem_width = 8;
6498
6499 val = REG_RD(bp, main_mem_prty_clr);
6500 if (val)
6501 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6502 "block during "
6503 "function init (0x%x)!\n", val);
6504
6505 /* Clear "false" parity errors in MSI-X table */
6506 for (i = main_mem_base;
6507 i < main_mem_base + main_mem_size * 4;
6508 i += main_mem_width) {
6509 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6510 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6511 i, main_mem_width / 4);
6512 }
6513 /* Clear HC parity attention */
6514 REG_RD(bp, main_mem_prty_clr);
6515 }
6516
6517 #ifdef BNX2X_STOP_ON_ERROR
6518 /* Enable STORMs SP logging */
6519 REG_WR8(bp, BAR_USTRORM_INTMEM +
6520 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6521 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6522 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6523 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6524 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6525 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6526 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6527 #endif
6528
6529 bnx2x_phy_probe(&bp->link_params);
6530
6531 return 0;
6532 }
6533
6534
6535 void bnx2x_free_mem(struct bnx2x *bp)
6536 {
6537 /* fastpath */
6538 bnx2x_free_fp_mem(bp);
6539 /* end of fastpath */
6540
6541 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6542 sizeof(struct host_sp_status_block));
6543
6544 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6545 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6546
6547 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6548 sizeof(struct bnx2x_slowpath));
6549
6550 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6551 bp->context.size);
6552
6553 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6554
6555 BNX2X_FREE(bp->ilt->lines);
6556
6557 #ifdef BCM_CNIC
6558 if (!CHIP_IS_E1x(bp))
6559 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6560 sizeof(struct host_hc_status_block_e2));
6561 else
6562 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6563 sizeof(struct host_hc_status_block_e1x));
6564
6565 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6566 #endif
6567
6568 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6569
6570 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6571 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6572 }
6573
6574 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6575 {
6576 int num_groups;
6577
6578 /* number of eth_queues */
6579 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6580
6581 /* Total number of FW statistics requests =
6582 * 1 for port stats + 1 for PF stats + num_eth_queues */
6583 bp->fw_stats_num = 2 + num_queue_stats;
6584
6585
6586 /* Request is built from stats_query_header and an array of
6587 * stats_query_cmd_group each of which contains
6588 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6589 * configured in the stats_query_header.
6590 */
6591 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6592 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6593
6594 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6595 num_groups * sizeof(struct stats_query_cmd_group);
6596
6597 /* Data for statistics requests + stats_conter
6598 *
6599 * stats_counter holds per-STORM counters that are incremented
6600 * when STORM has finished with the current request.
6601 */
6602 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6603 sizeof(struct per_pf_stats) +
6604 sizeof(struct per_queue_stats) * num_queue_stats +
6605 sizeof(struct stats_counter);
6606
6607 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6608 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6609
6610 /* Set shortcuts */
6611 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6612 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6613
6614 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6615 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6616
6617 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6618 bp->fw_stats_req_sz;
6619 return 0;
6620
6621 alloc_mem_err:
6622 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6623 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6624 return -ENOMEM;
6625 }
6626
6627
6628 int bnx2x_alloc_mem(struct bnx2x *bp)
6629 {
6630 #ifdef BCM_CNIC
6631 if (!CHIP_IS_E1x(bp))
6632 /* size = the status block + ramrod buffers */
6633 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6634 sizeof(struct host_hc_status_block_e2));
6635 else
6636 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6637 sizeof(struct host_hc_status_block_e1x));
6638
6639 /* allocate searcher T2 table */
6640 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6641 #endif
6642
6643
6644 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6645 sizeof(struct host_sp_status_block));
6646
6647 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6648 sizeof(struct bnx2x_slowpath));
6649
6650 /* Allocated memory for FW statistics */
6651 if (bnx2x_alloc_fw_stats_mem(bp))
6652 goto alloc_mem_err;
6653
6654 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
6655
6656 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6657 bp->context.size);
6658
6659 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6660
6661 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6662 goto alloc_mem_err;
6663
6664 /* Slow path ring */
6665 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6666
6667 /* EQ */
6668 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6669 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6670
6671
6672 /* fastpath */
6673 /* need to be done at the end, since it's self adjusting to amount
6674 * of memory available for RSS queues
6675 */
6676 if (bnx2x_alloc_fp_mem(bp))
6677 goto alloc_mem_err;
6678 return 0;
6679
6680 alloc_mem_err:
6681 bnx2x_free_mem(bp);
6682 return -ENOMEM;
6683 }
6684
6685 /*
6686 * Init service functions
6687 */
6688
6689 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6690 struct bnx2x_vlan_mac_obj *obj, bool set,
6691 int mac_type, unsigned long *ramrod_flags)
6692 {
6693 int rc;
6694 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6695
6696 memset(&ramrod_param, 0, sizeof(ramrod_param));
6697
6698 /* Fill general parameters */
6699 ramrod_param.vlan_mac_obj = obj;
6700 ramrod_param.ramrod_flags = *ramrod_flags;
6701
6702 /* Fill a user request section if needed */
6703 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6704 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6705
6706 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6707
6708 /* Set the command: ADD or DEL */
6709 if (set)
6710 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6711 else
6712 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6713 }
6714
6715 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6716 if (rc < 0)
6717 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6718 return rc;
6719 }
6720
6721 int bnx2x_del_all_macs(struct bnx2x *bp,
6722 struct bnx2x_vlan_mac_obj *mac_obj,
6723 int mac_type, bool wait_for_comp)
6724 {
6725 int rc;
6726 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
6727
6728 /* Wait for completion of requested */
6729 if (wait_for_comp)
6730 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6731
6732 /* Set the mac type of addresses we want to clear */
6733 __set_bit(mac_type, &vlan_mac_flags);
6734
6735 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6736 if (rc < 0)
6737 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
6738
6739 return rc;
6740 }
6741
6742 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
6743 {
6744 unsigned long ramrod_flags = 0;
6745
6746 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
6747
6748 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6749 /* Eth MAC is set on RSS leading client (fp[0]) */
6750 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6751 BNX2X_ETH_MAC, &ramrod_flags);
6752 }
6753
6754 int bnx2x_setup_leading(struct bnx2x *bp)
6755 {
6756 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
6757 }
6758
6759 /**
6760 * bnx2x_set_int_mode - configure interrupt mode
6761 *
6762 * @bp: driver handle
6763 *
6764 * In case of MSI-X it will also try to enable MSI-X.
6765 */
6766 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6767 {
6768 switch (int_mode) {
6769 case INT_MODE_MSI:
6770 bnx2x_enable_msi(bp);
6771 /* falling through... */
6772 case INT_MODE_INTx:
6773 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6774 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6775 break;
6776 default:
6777 /* Set number of queues according to bp->multi_mode value */
6778 bnx2x_set_num_queues(bp);
6779
6780 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6781 bp->num_queues);
6782
6783 /* if we can't use MSI-X we only need one fp,
6784 * so try to enable MSI-X with the requested number of fp's
6785 * and fallback to MSI or legacy INTx with one fp
6786 */
6787 if (bnx2x_enable_msix(bp)) {
6788 /* failed to enable MSI-X */
6789 if (bp->multi_mode)
6790 DP(NETIF_MSG_IFUP,
6791 "Multi requested but failed to "
6792 "enable MSI-X (%d), "
6793 "set number of queues to %d\n",
6794 bp->num_queues,
6795 1 + NONE_ETH_CONTEXT_USE);
6796 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6797
6798 /* Try to enable MSI */
6799 if (!(bp->flags & DISABLE_MSI_FLAG))
6800 bnx2x_enable_msi(bp);
6801 }
6802 break;
6803 }
6804 }
6805
6806 /* must be called prioir to any HW initializations */
6807 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6808 {
6809 return L2_ILT_LINES(bp);
6810 }
6811
6812 void bnx2x_ilt_set_info(struct bnx2x *bp)
6813 {
6814 struct ilt_client_info *ilt_client;
6815 struct bnx2x_ilt *ilt = BP_ILT(bp);
6816 u16 line = 0;
6817
6818 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6819 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6820
6821 /* CDU */
6822 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6823 ilt_client->client_num = ILT_CLIENT_CDU;
6824 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6825 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6826 ilt_client->start = line;
6827 line += bnx2x_cid_ilt_lines(bp);
6828 #ifdef BCM_CNIC
6829 line += CNIC_ILT_LINES;
6830 #endif
6831 ilt_client->end = line - 1;
6832
6833 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6834 "flags 0x%x, hw psz %d\n",
6835 ilt_client->start,
6836 ilt_client->end,
6837 ilt_client->page_size,
6838 ilt_client->flags,
6839 ilog2(ilt_client->page_size >> 12));
6840
6841 /* QM */
6842 if (QM_INIT(bp->qm_cid_count)) {
6843 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6844 ilt_client->client_num = ILT_CLIENT_QM;
6845 ilt_client->page_size = QM_ILT_PAGE_SZ;
6846 ilt_client->flags = 0;
6847 ilt_client->start = line;
6848
6849 /* 4 bytes for each cid */
6850 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6851 QM_ILT_PAGE_SZ);
6852
6853 ilt_client->end = line - 1;
6854
6855 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6856 "flags 0x%x, hw psz %d\n",
6857 ilt_client->start,
6858 ilt_client->end,
6859 ilt_client->page_size,
6860 ilt_client->flags,
6861 ilog2(ilt_client->page_size >> 12));
6862
6863 }
6864 /* SRC */
6865 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6866 #ifdef BCM_CNIC
6867 ilt_client->client_num = ILT_CLIENT_SRC;
6868 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6869 ilt_client->flags = 0;
6870 ilt_client->start = line;
6871 line += SRC_ILT_LINES;
6872 ilt_client->end = line - 1;
6873
6874 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6875 "flags 0x%x, hw psz %d\n",
6876 ilt_client->start,
6877 ilt_client->end,
6878 ilt_client->page_size,
6879 ilt_client->flags,
6880 ilog2(ilt_client->page_size >> 12));
6881
6882 #else
6883 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6884 #endif
6885
6886 /* TM */
6887 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6888 #ifdef BCM_CNIC
6889 ilt_client->client_num = ILT_CLIENT_TM;
6890 ilt_client->page_size = TM_ILT_PAGE_SZ;
6891 ilt_client->flags = 0;
6892 ilt_client->start = line;
6893 line += TM_ILT_LINES;
6894 ilt_client->end = line - 1;
6895
6896 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6897 "flags 0x%x, hw psz %d\n",
6898 ilt_client->start,
6899 ilt_client->end,
6900 ilt_client->page_size,
6901 ilt_client->flags,
6902 ilog2(ilt_client->page_size >> 12));
6903
6904 #else
6905 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6906 #endif
6907 BUG_ON(line > ILT_MAX_LINES);
6908 }
6909
6910 /**
6911 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
6912 *
6913 * @bp: driver handle
6914 * @fp: pointer to fastpath
6915 * @init_params: pointer to parameters structure
6916 *
6917 * parameters configured:
6918 * - HC configuration
6919 * - Queue's CDU context
6920 */
6921 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
6922 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
6923 {
6924 /* FCoE Queue uses Default SB, thus has no HC capabilities */
6925 if (!IS_FCOE_FP(fp)) {
6926 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
6927 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
6928
6929 /* If HC is supporterd, enable host coalescing in the transition
6930 * to INIT state.
6931 */
6932 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
6933 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
6934
6935 /* HC rate */
6936 init_params->rx.hc_rate = bp->rx_ticks ?
6937 (1000000 / bp->rx_ticks) : 0;
6938 init_params->tx.hc_rate = bp->tx_ticks ?
6939 (1000000 / bp->tx_ticks) : 0;
6940
6941 /* FW SB ID */
6942 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
6943 fp->fw_sb_id;
6944
6945 /*
6946 * CQ index among the SB indices: FCoE clients uses the default
6947 * SB, therefore it's different.
6948 */
6949 init_params->rx.sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
6950 init_params->tx.sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
6951 }
6952
6953 init_params->cxt = &bp->context.vcxt[fp->cid].eth;
6954 }
6955
6956 /**
6957 * bnx2x_setup_queue - setup queue
6958 *
6959 * @bp: driver handle
6960 * @fp: pointer to fastpath
6961 * @leading: is leading
6962 *
6963 * This function performs 2 steps in a Queue state machine
6964 * actually: 1) RESET->INIT 2) INIT->SETUP
6965 */
6966
6967 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6968 bool leading)
6969 {
6970 struct bnx2x_queue_state_params q_params = {0};
6971 struct bnx2x_queue_setup_params *setup_params =
6972 &q_params.params.setup;
6973 int rc;
6974
6975 /* reset IGU state skip FCoE L2 queue */
6976 if (!IS_FCOE_FP(fp))
6977 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6978 IGU_INT_ENABLE, 0);
6979
6980 q_params.q_obj = &fp->q_obj;
6981 /* We want to wait for completion in this context */
6982 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6983
6984 /* Prepare the INIT parameters */
6985 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
6986
6987 /* Set the command */
6988 q_params.cmd = BNX2X_Q_CMD_INIT;
6989
6990 /* Change the state to INIT */
6991 rc = bnx2x_queue_state_change(bp, &q_params);
6992 if (rc) {
6993 BNX2X_ERR("Queue INIT failed\n");
6994 return rc;
6995 }
6996
6997 /* Now move the Queue to the SETUP state... */
6998 memset(setup_params, 0, sizeof(*setup_params));
6999
7000 /* Set QUEUE flags */
7001 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7002
7003 /* Set general SETUP parameters */
7004 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params);
7005
7006 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause,
7007 &setup_params->rxq_params);
7008
7009 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params);
7010
7011 /* Set the command */
7012 q_params.cmd = BNX2X_Q_CMD_SETUP;
7013
7014 /* Change the state to SETUP */
7015 rc = bnx2x_queue_state_change(bp, &q_params);
7016 if (rc)
7017 BNX2X_ERR("Queue SETUP failed\n");
7018
7019 return rc;
7020 }
7021
7022 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7023 {
7024 struct bnx2x_fastpath *fp = &bp->fp[index];
7025 struct bnx2x_queue_state_params q_params = {0};
7026 int rc;
7027
7028 q_params.q_obj = &fp->q_obj;
7029 /* We want to wait for completion in this context */
7030 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7031
7032 /* halt the connection */
7033 q_params.cmd = BNX2X_Q_CMD_HALT;
7034 rc = bnx2x_queue_state_change(bp, &q_params);
7035 if (rc)
7036 return rc;
7037
7038 /* terminate the connection */
7039 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7040 rc = bnx2x_queue_state_change(bp, &q_params);
7041 if (rc)
7042 return rc;
7043
7044 /* delete cfc entry */
7045 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7046 return bnx2x_queue_state_change(bp, &q_params);
7047 }
7048
7049
7050 static void bnx2x_reset_func(struct bnx2x *bp)
7051 {
7052 int port = BP_PORT(bp);
7053 int func = BP_FUNC(bp);
7054 int i;
7055
7056 /* Disable the function in the FW */
7057 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7058 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7059 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7060 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7061
7062 /* FP SBs */
7063 for_each_eth_queue(bp, i) {
7064 struct bnx2x_fastpath *fp = &bp->fp[i];
7065 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7066 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7067 SB_DISABLED);
7068 }
7069
7070 #ifdef BCM_CNIC
7071 /* CNIC SB */
7072 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7073 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7074 SB_DISABLED);
7075 #endif
7076 /* SP SB */
7077 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7078 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7079 SB_DISABLED);
7080
7081 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7082 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7083 0);
7084
7085 /* Configure IGU */
7086 if (bp->common.int_block == INT_BLOCK_HC) {
7087 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7088 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7089 } else {
7090 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7091 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7092 }
7093
7094 #ifdef BCM_CNIC
7095 /* Disable Timer scan */
7096 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7097 /*
7098 * Wait for at least 10ms and up to 2 second for the timers scan to
7099 * complete
7100 */
7101 for (i = 0; i < 200; i++) {
7102 msleep(10);
7103 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7104 break;
7105 }
7106 #endif
7107 /* Clear ILT */
7108 bnx2x_clear_func_ilt(bp, func);
7109
7110 /* Timers workaround bug for E2: if this is vnic-3,
7111 * we need to set the entire ilt range for this timers.
7112 */
7113 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7114 struct ilt_client_info ilt_cli;
7115 /* use dummy TM client */
7116 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7117 ilt_cli.start = 0;
7118 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7119 ilt_cli.client_num = ILT_CLIENT_TM;
7120
7121 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7122 }
7123
7124 /* this assumes that reset_port() called before reset_func()*/
7125 if (!CHIP_IS_E1x(bp))
7126 bnx2x_pf_disable(bp);
7127
7128 bp->dmae_ready = 0;
7129 }
7130
7131 static void bnx2x_reset_port(struct bnx2x *bp)
7132 {
7133 int port = BP_PORT(bp);
7134 u32 val;
7135
7136 /* Reset physical Link */
7137 bnx2x__link_reset(bp);
7138
7139 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7140
7141 /* Do not rcv packets to BRB */
7142 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7143 /* Do not direct rcv packets that are not for MCP to the BRB */
7144 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7145 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7146
7147 /* Configure AEU */
7148 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7149
7150 msleep(100);
7151 /* Check for BRB port occupancy */
7152 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7153 if (val)
7154 DP(NETIF_MSG_IFDOWN,
7155 "BRB1 is not empty %d blocks are occupied\n", val);
7156
7157 /* TODO: Close Doorbell port? */
7158 }
7159
7160 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7161 {
7162 struct bnx2x_func_state_params func_params = {0};
7163
7164 /* Prepare parameters for function state transitions */
7165 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7166
7167 func_params.f_obj = &bp->func_obj;
7168 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7169
7170 func_params.params.hw_init.load_phase = load_code;
7171
7172 return bnx2x_func_state_change(bp, &func_params);
7173 }
7174
7175 static inline int bnx2x_func_stop(struct bnx2x *bp)
7176 {
7177 struct bnx2x_func_state_params func_params = {0};
7178 int rc;
7179
7180 /* Prepare parameters for function state transitions */
7181 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7182 func_params.f_obj = &bp->func_obj;
7183 func_params.cmd = BNX2X_F_CMD_STOP;
7184
7185 /*
7186 * Try to stop the function the 'good way'. If fails (in case
7187 * of a parity error during bnx2x_chip_cleanup()) and we are
7188 * not in a debug mode, perform a state transaction in order to
7189 * enable further HW_RESET transaction.
7190 */
7191 rc = bnx2x_func_state_change(bp, &func_params);
7192 if (rc) {
7193 #ifdef BNX2X_STOP_ON_ERROR
7194 return rc;
7195 #else
7196 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7197 "transaction\n");
7198 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7199 return bnx2x_func_state_change(bp, &func_params);
7200 #endif
7201 }
7202
7203 return 0;
7204 }
7205
7206 /**
7207 * bnx2x_send_unload_req - request unload mode from the MCP.
7208 *
7209 * @bp: driver handle
7210 * @unload_mode: requested function's unload mode
7211 *
7212 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7213 */
7214 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7215 {
7216 u32 reset_code = 0;
7217 int port = BP_PORT(bp);
7218
7219 /* Select the UNLOAD request mode */
7220 if (unload_mode == UNLOAD_NORMAL)
7221 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7222
7223 else if (bp->flags & NO_WOL_FLAG)
7224 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7225
7226 else if (bp->wol) {
7227 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7228 u8 *mac_addr = bp->dev->dev_addr;
7229 u32 val;
7230 /* The mac address is written to entries 1-4 to
7231 preserve entry 0 which is used by the PMF */
7232 u8 entry = (BP_E1HVN(bp) + 1)*8;
7233
7234 val = (mac_addr[0] << 8) | mac_addr[1];
7235 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7236
7237 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7238 (mac_addr[4] << 8) | mac_addr[5];
7239 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7240
7241 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7242
7243 } else
7244 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7245
7246 /* Send the request to the MCP */
7247 if (!BP_NOMCP(bp))
7248 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7249 else {
7250 int path = BP_PATH(bp);
7251
7252 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7253 "%d, %d, %d\n",
7254 path, load_count[path][0], load_count[path][1],
7255 load_count[path][2]);
7256 load_count[path][0]--;
7257 load_count[path][1 + port]--;
7258 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7259 "%d, %d, %d\n",
7260 path, load_count[path][0], load_count[path][1],
7261 load_count[path][2]);
7262 if (load_count[path][0] == 0)
7263 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7264 else if (load_count[path][1 + port] == 0)
7265 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7266 else
7267 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7268 }
7269
7270 return reset_code;
7271 }
7272
7273 /**
7274 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7275 *
7276 * @bp: driver handle
7277 */
7278 void bnx2x_send_unload_done(struct bnx2x *bp)
7279 {
7280 /* Report UNLOAD_DONE to MCP */
7281 if (!BP_NOMCP(bp))
7282 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7283 }
7284
7285 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7286 {
7287 int port = BP_PORT(bp);
7288 int i, rc;
7289 struct bnx2x_mcast_ramrod_params rparam = {0};
7290 u32 reset_code;
7291
7292 /* Wait until tx fastpath tasks complete */
7293 for_each_tx_queue(bp, i) {
7294 struct bnx2x_fastpath *fp = &bp->fp[i];
7295
7296 rc = bnx2x_clean_tx_queue(bp, fp);
7297 #ifdef BNX2X_STOP_ON_ERROR
7298 if (rc)
7299 return;
7300 #endif
7301 }
7302
7303 /* Give HW time to discard old tx messages */
7304 usleep_range(1000, 1000);
7305
7306 /* Clean all ETH MACs */
7307 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7308 if (rc < 0)
7309 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7310
7311 /* Clean up UC list */
7312 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7313 true);
7314 if (rc < 0)
7315 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7316 "%d\n", rc);
7317
7318 /* Disable LLH */
7319 if (!CHIP_IS_E1(bp))
7320 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7321
7322 /* Set "drop all" (stop Rx).
7323 * We need to take a netif_addr_lock() here in order to prevent
7324 * a race between the completion code and this code.
7325 */
7326 netif_addr_lock_bh(bp->dev);
7327 /* Schedule the rx_mode command */
7328 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7329 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7330 else
7331 bnx2x_set_storm_rx_mode(bp);
7332
7333 /* Cleanup multicast configuration */
7334 rparam.mcast_obj = &bp->mcast_obj;
7335 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7336 if (rc < 0)
7337 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7338
7339 netif_addr_unlock_bh(bp->dev);
7340
7341
7342 /* Close multi and leading connections
7343 * Completions for ramrods are collected in a synchronous way
7344 */
7345 for_each_queue(bp, i)
7346 if (bnx2x_stop_queue(bp, i))
7347 #ifdef BNX2X_STOP_ON_ERROR
7348 return;
7349 #else
7350 goto unload_error;
7351 #endif
7352 /* If SP settings didn't get completed so far - something
7353 * very wrong has happen.
7354 */
7355 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7356 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7357
7358 #ifndef BNX2X_STOP_ON_ERROR
7359 unload_error:
7360 #endif
7361 rc = bnx2x_func_stop(bp);
7362 if (rc) {
7363 BNX2X_ERR("Function stop failed!\n");
7364 #ifdef BNX2X_STOP_ON_ERROR
7365 return;
7366 #endif
7367 }
7368
7369 /*
7370 * Send the UNLOAD_REQUEST to the MCP. This will return if
7371 * this function should perform FUNC, PORT or COMMON HW
7372 * reset.
7373 */
7374 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7375
7376 /* Disable HW interrupts, NAPI */
7377 bnx2x_netif_stop(bp, 1);
7378
7379 /* Release IRQs */
7380 bnx2x_free_irq(bp);
7381
7382 /* Reset the chip */
7383 rc = bnx2x_reset_hw(bp, reset_code);
7384 if (rc)
7385 BNX2X_ERR("HW_RESET failed\n");
7386
7387
7388 /* Report UNLOAD_DONE to MCP */
7389 bnx2x_send_unload_done(bp);
7390 }
7391
7392 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7393 {
7394 u32 val;
7395
7396 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7397
7398 if (CHIP_IS_E1(bp)) {
7399 int port = BP_PORT(bp);
7400 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7401 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7402
7403 val = REG_RD(bp, addr);
7404 val &= ~(0x300);
7405 REG_WR(bp, addr, val);
7406 } else {
7407 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7408 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7409 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7410 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7411 }
7412 }
7413
7414 /* Close gates #2, #3 and #4: */
7415 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7416 {
7417 u32 val;
7418
7419 /* Gates #2 and #4a are closed/opened for "not E1" only */
7420 if (!CHIP_IS_E1(bp)) {
7421 /* #4 */
7422 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7423 /* #2 */
7424 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7425 }
7426
7427 /* #3 */
7428 if (CHIP_IS_E1x(bp)) {
7429 /* Prevent interrupts from HC on both ports */
7430 val = REG_RD(bp, HC_REG_CONFIG_1);
7431 REG_WR(bp, HC_REG_CONFIG_1,
7432 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7433 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7434
7435 val = REG_RD(bp, HC_REG_CONFIG_0);
7436 REG_WR(bp, HC_REG_CONFIG_0,
7437 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7438 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7439 } else {
7440 /* Prevent incomming interrupts in IGU */
7441 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7442
7443 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7444 (!close) ?
7445 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7446 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7447 }
7448
7449 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7450 close ? "closing" : "opening");
7451 mmiowb();
7452 }
7453
7454 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7455
7456 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7457 {
7458 /* Do some magic... */
7459 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7460 *magic_val = val & SHARED_MF_CLP_MAGIC;
7461 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7462 }
7463
7464 /**
7465 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7466 *
7467 * @bp: driver handle
7468 * @magic_val: old value of the `magic' bit.
7469 */
7470 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7471 {
7472 /* Restore the `magic' bit value... */
7473 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7474 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7475 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7476 }
7477
7478 /**
7479 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7480 *
7481 * @bp: driver handle
7482 * @magic_val: old value of 'magic' bit.
7483 *
7484 * Takes care of CLP configurations.
7485 */
7486 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7487 {
7488 u32 shmem;
7489 u32 validity_offset;
7490
7491 DP(NETIF_MSG_HW, "Starting\n");
7492
7493 /* Set `magic' bit in order to save MF config */
7494 if (!CHIP_IS_E1(bp))
7495 bnx2x_clp_reset_prep(bp, magic_val);
7496
7497 /* Get shmem offset */
7498 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7499 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7500
7501 /* Clear validity map flags */
7502 if (shmem > 0)
7503 REG_WR(bp, shmem + validity_offset, 0);
7504 }
7505
7506 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7507 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7508
7509 /**
7510 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7511 *
7512 * @bp: driver handle
7513 */
7514 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7515 {
7516 /* special handling for emulation and FPGA,
7517 wait 10 times longer */
7518 if (CHIP_REV_IS_SLOW(bp))
7519 msleep(MCP_ONE_TIMEOUT*10);
7520 else
7521 msleep(MCP_ONE_TIMEOUT);
7522 }
7523
7524 /*
7525 * initializes bp->common.shmem_base and waits for validity signature to appear
7526 */
7527 static int bnx2x_init_shmem(struct bnx2x *bp)
7528 {
7529 int cnt = 0;
7530 u32 val = 0;
7531
7532 do {
7533 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7534 if (bp->common.shmem_base) {
7535 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7536 if (val & SHR_MEM_VALIDITY_MB)
7537 return 0;
7538 }
7539
7540 bnx2x_mcp_wait_one(bp);
7541
7542 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7543
7544 BNX2X_ERR("BAD MCP validity signature\n");
7545
7546 return -ENODEV;
7547 }
7548
7549 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7550 {
7551 int rc = bnx2x_init_shmem(bp);
7552
7553 /* Restore the `magic' bit value */
7554 if (!CHIP_IS_E1(bp))
7555 bnx2x_clp_reset_done(bp, magic_val);
7556
7557 return rc;
7558 }
7559
7560 static void bnx2x_pxp_prep(struct bnx2x *bp)
7561 {
7562 if (!CHIP_IS_E1(bp)) {
7563 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7564 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7565 mmiowb();
7566 }
7567 }
7568
7569 /*
7570 * Reset the whole chip except for:
7571 * - PCIE core
7572 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7573 * one reset bit)
7574 * - IGU
7575 * - MISC (including AEU)
7576 * - GRC
7577 * - RBCN, RBCP
7578 */
7579 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
7580 {
7581 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7582 u32 global_bits2;
7583
7584 /*
7585 * Bits that have to be set in reset_mask2 if we want to reset 'global'
7586 * (per chip) blocks.
7587 */
7588 global_bits2 =
7589 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
7590 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
7591
7592 not_reset_mask1 =
7593 MISC_REGISTERS_RESET_REG_1_RST_HC |
7594 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7595 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7596
7597 not_reset_mask2 =
7598 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
7599 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7600 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7601 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7602 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7603 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7604 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7605 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7606
7607 reset_mask1 = 0xffffffff;
7608
7609 if (CHIP_IS_E1(bp))
7610 reset_mask2 = 0xffff;
7611 else
7612 reset_mask2 = 0x1ffff;
7613
7614 if (CHIP_IS_E3(bp)) {
7615 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7616 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7617 }
7618
7619 /* Don't reset global blocks unless we need to */
7620 if (!global)
7621 reset_mask2 &= ~global_bits2;
7622
7623 /*
7624 * In case of attention in the QM, we need to reset PXP
7625 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
7626 * because otherwise QM reset would release 'close the gates' shortly
7627 * before resetting the PXP, then the PSWRQ would send a write
7628 * request to PGLUE. Then when PXP is reset, PGLUE would try to
7629 * read the payload data from PSWWR, but PSWWR would not
7630 * respond. The write queue in PGLUE would stuck, dmae commands
7631 * would not return. Therefore it's important to reset the second
7632 * reset register (containing the
7633 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
7634 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
7635 * bit).
7636 */
7637 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7638 reset_mask2 & (~not_reset_mask2));
7639
7640 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7641 reset_mask1 & (~not_reset_mask1));
7642
7643 barrier();
7644 mmiowb();
7645
7646 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7647 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7648 mmiowb();
7649 }
7650
7651 /**
7652 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
7653 * It should get cleared in no more than 1s.
7654 *
7655 * @bp: driver handle
7656 *
7657 * It should get cleared in no more than 1s. Returns 0 if
7658 * pending writes bit gets cleared.
7659 */
7660 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
7661 {
7662 u32 cnt = 1000;
7663 u32 pend_bits = 0;
7664
7665 do {
7666 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
7667
7668 if (pend_bits == 0)
7669 break;
7670
7671 usleep_range(1000, 1000);
7672 } while (cnt-- > 0);
7673
7674 if (cnt <= 0) {
7675 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
7676 pend_bits);
7677 return -EBUSY;
7678 }
7679
7680 return 0;
7681 }
7682
7683 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
7684 {
7685 int cnt = 1000;
7686 u32 val = 0;
7687 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7688
7689
7690 /* Empty the Tetris buffer, wait for 1s */
7691 do {
7692 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7693 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7694 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7695 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7696 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7697 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7698 ((port_is_idle_0 & 0x1) == 0x1) &&
7699 ((port_is_idle_1 & 0x1) == 0x1) &&
7700 (pgl_exp_rom2 == 0xffffffff))
7701 break;
7702 usleep_range(1000, 1000);
7703 } while (cnt-- > 0);
7704
7705 if (cnt <= 0) {
7706 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7707 " are still"
7708 " outstanding read requests after 1s!\n");
7709 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7710 " port_is_idle_0=0x%08x,"
7711 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7712 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7713 pgl_exp_rom2);
7714 return -EAGAIN;
7715 }
7716
7717 barrier();
7718
7719 /* Close gates #2, #3 and #4 */
7720 bnx2x_set_234_gates(bp, true);
7721
7722 /* Poll for IGU VQs for 57712 and newer chips */
7723 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
7724 return -EAGAIN;
7725
7726
7727 /* TBD: Indicate that "process kill" is in progress to MCP */
7728
7729 /* Clear "unprepared" bit */
7730 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7731 barrier();
7732
7733 /* Make sure all is written to the chip before the reset */
7734 mmiowb();
7735
7736 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7737 * PSWHST, GRC and PSWRD Tetris buffer.
7738 */
7739 usleep_range(1000, 1000);
7740
7741 /* Prepare to chip reset: */
7742 /* MCP */
7743 if (global)
7744 bnx2x_reset_mcp_prep(bp, &val);
7745
7746 /* PXP */
7747 bnx2x_pxp_prep(bp);
7748 barrier();
7749
7750 /* reset the chip */
7751 bnx2x_process_kill_chip_reset(bp, global);
7752 barrier();
7753
7754 /* Recover after reset: */
7755 /* MCP */
7756 if (global && bnx2x_reset_mcp_comp(bp, val))
7757 return -EAGAIN;
7758
7759 /* TBD: Add resetting the NO_MCP mode DB here */
7760
7761 /* PXP */
7762 bnx2x_pxp_prep(bp);
7763
7764 /* Open the gates #2, #3 and #4 */
7765 bnx2x_set_234_gates(bp, false);
7766
7767 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7768 * reset state, re-enable attentions. */
7769
7770 return 0;
7771 }
7772
7773 int bnx2x_leader_reset(struct bnx2x *bp)
7774 {
7775 int rc = 0;
7776 bool global = bnx2x_reset_is_global(bp);
7777
7778 /* Try to recover after the failure */
7779 if (bnx2x_process_kill(bp, global)) {
7780 netdev_err(bp->dev, "Something bad had happen on engine %d! "
7781 "Aii!\n", BP_PATH(bp));
7782 rc = -EAGAIN;
7783 goto exit_leader_reset;
7784 }
7785
7786 /*
7787 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
7788 * state.
7789 */
7790 bnx2x_set_reset_done(bp);
7791 if (global)
7792 bnx2x_clear_reset_global(bp);
7793
7794 exit_leader_reset:
7795 bp->is_leader = 0;
7796 bnx2x_release_leader_lock(bp);
7797 smp_mb();
7798 return rc;
7799 }
7800
7801 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
7802 {
7803 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
7804
7805 /* Disconnect this device */
7806 netif_device_detach(bp->dev);
7807
7808 /*
7809 * Block ifup for all function on this engine until "process kill"
7810 * or power cycle.
7811 */
7812 bnx2x_set_reset_in_progress(bp);
7813
7814 /* Shut down the power */
7815 bnx2x_set_power_state(bp, PCI_D3hot);
7816
7817 bp->recovery_state = BNX2X_RECOVERY_FAILED;
7818
7819 smp_mb();
7820 }
7821
7822 /*
7823 * Assumption: runs under rtnl lock. This together with the fact
7824 * that it's called only from bnx2x_reset_task() ensure that it
7825 * will never be called when netif_running(bp->dev) is false.
7826 */
7827 static void bnx2x_parity_recover(struct bnx2x *bp)
7828 {
7829 bool global = false;
7830
7831 DP(NETIF_MSG_HW, "Handling parity\n");
7832 while (1) {
7833 switch (bp->recovery_state) {
7834 case BNX2X_RECOVERY_INIT:
7835 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7836 bnx2x_chk_parity_attn(bp, &global, false);
7837
7838 /* Try to get a LEADER_LOCK HW lock */
7839 if (bnx2x_trylock_leader_lock(bp)) {
7840 bnx2x_set_reset_in_progress(bp);
7841 /*
7842 * Check if there is a global attention and if
7843 * there was a global attention, set the global
7844 * reset bit.
7845 */
7846
7847 if (global)
7848 bnx2x_set_reset_global(bp);
7849
7850 bp->is_leader = 1;
7851 }
7852
7853 /* Stop the driver */
7854 /* If interface has been removed - break */
7855 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7856 return;
7857
7858 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7859
7860 /*
7861 * Reset MCP command sequence number and MCP mail box
7862 * sequence as we are going to reset the MCP.
7863 */
7864 if (global) {
7865 bp->fw_seq = 0;
7866 bp->fw_drv_pulse_wr_seq = 0;
7867 }
7868
7869 /* Ensure "is_leader", MCP command sequence and
7870 * "recovery_state" update values are seen on other
7871 * CPUs.
7872 */
7873 smp_mb();
7874 break;
7875
7876 case BNX2X_RECOVERY_WAIT:
7877 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7878 if (bp->is_leader) {
7879 int other_engine = BP_PATH(bp) ? 0 : 1;
7880 u32 other_load_counter =
7881 bnx2x_get_load_cnt(bp, other_engine);
7882 u32 load_counter =
7883 bnx2x_get_load_cnt(bp, BP_PATH(bp));
7884 global = bnx2x_reset_is_global(bp);
7885
7886 /*
7887 * In case of a parity in a global block, let
7888 * the first leader that performs a
7889 * leader_reset() reset the global blocks in
7890 * order to clear global attentions. Otherwise
7891 * the the gates will remain closed for that
7892 * engine.
7893 */
7894 if (load_counter ||
7895 (global && other_load_counter)) {
7896 /* Wait until all other functions get
7897 * down.
7898 */
7899 schedule_delayed_work(&bp->reset_task,
7900 HZ/10);
7901 return;
7902 } else {
7903 /* If all other functions got down -
7904 * try to bring the chip back to
7905 * normal. In any case it's an exit
7906 * point for a leader.
7907 */
7908 if (bnx2x_leader_reset(bp)) {
7909 bnx2x_recovery_failed(bp);
7910 return;
7911 }
7912
7913 /* If we are here, means that the
7914 * leader has succeeded and doesn't
7915 * want to be a leader any more. Try
7916 * to continue as a none-leader.
7917 */
7918 break;
7919 }
7920 } else { /* non-leader */
7921 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
7922 /* Try to get a LEADER_LOCK HW lock as
7923 * long as a former leader may have
7924 * been unloaded by the user or
7925 * released a leadership by another
7926 * reason.
7927 */
7928 if (bnx2x_trylock_leader_lock(bp)) {
7929 /* I'm a leader now! Restart a
7930 * switch case.
7931 */
7932 bp->is_leader = 1;
7933 break;
7934 }
7935
7936 schedule_delayed_work(&bp->reset_task,
7937 HZ/10);
7938 return;
7939
7940 } else {
7941 /*
7942 * If there was a global attention, wait
7943 * for it to be cleared.
7944 */
7945 if (bnx2x_reset_is_global(bp)) {
7946 schedule_delayed_work(
7947 &bp->reset_task, HZ/10);
7948 return;
7949 }
7950
7951 if (bnx2x_nic_load(bp, LOAD_NORMAL))
7952 bnx2x_recovery_failed(bp);
7953 else {
7954 bp->recovery_state =
7955 BNX2X_RECOVERY_DONE;
7956 smp_mb();
7957 }
7958
7959 return;
7960 }
7961 }
7962 default:
7963 return;
7964 }
7965 }
7966 }
7967
7968 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7969 * scheduled on a general queue in order to prevent a dead lock.
7970 */
7971 static void bnx2x_reset_task(struct work_struct *work)
7972 {
7973 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
7974
7975 #ifdef BNX2X_STOP_ON_ERROR
7976 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7977 " so reset not done to allow debug dump,\n"
7978 KERN_ERR " you will need to reboot when done\n");
7979 return;
7980 #endif
7981
7982 rtnl_lock();
7983
7984 if (!netif_running(bp->dev))
7985 goto reset_task_exit;
7986
7987 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7988 bnx2x_parity_recover(bp);
7989 else {
7990 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7991 bnx2x_nic_load(bp, LOAD_NORMAL);
7992 }
7993
7994 reset_task_exit:
7995 rtnl_unlock();
7996 }
7997
7998 /* end of nic load/unload */
7999
8000 /*
8001 * Init service functions
8002 */
8003
8004 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8005 {
8006 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8007 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8008 return base + (BP_ABS_FUNC(bp)) * stride;
8009 }
8010
8011 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8012 {
8013 u32 reg = bnx2x_get_pretend_reg(bp);
8014
8015 /* Flush all outstanding writes */
8016 mmiowb();
8017
8018 /* Pretend to be function 0 */
8019 REG_WR(bp, reg, 0);
8020 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8021
8022 /* From now we are in the "like-E1" mode */
8023 bnx2x_int_disable(bp);
8024
8025 /* Flush all outstanding writes */
8026 mmiowb();
8027
8028 /* Restore the original function */
8029 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8030 REG_RD(bp, reg);
8031 }
8032
8033 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8034 {
8035 if (CHIP_IS_E1(bp))
8036 bnx2x_int_disable(bp);
8037 else
8038 bnx2x_undi_int_disable_e1h(bp);
8039 }
8040
8041 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8042 {
8043 u32 val;
8044
8045 /* Check if there is any driver already loaded */
8046 val = REG_RD(bp, MISC_REG_UNPREPARED);
8047 if (val == 0x1) {
8048 /* Check if it is the UNDI driver
8049 * UNDI driver initializes CID offset for normal bell to 0x7
8050 */
8051 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8052 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8053 if (val == 0x7) {
8054 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8055 /* save our pf_num */
8056 int orig_pf_num = bp->pf_num;
8057 int port;
8058 u32 swap_en, swap_val, value;
8059
8060 /* clear the UNDI indication */
8061 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8062
8063 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8064
8065 /* try unload UNDI on port 0 */
8066 bp->pf_num = 0;
8067 bp->fw_seq =
8068 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8069 DRV_MSG_SEQ_NUMBER_MASK);
8070 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8071
8072 /* if UNDI is loaded on the other port */
8073 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8074
8075 /* send "DONE" for previous unload */
8076 bnx2x_fw_command(bp,
8077 DRV_MSG_CODE_UNLOAD_DONE, 0);
8078
8079 /* unload UNDI on port 1 */
8080 bp->pf_num = 1;
8081 bp->fw_seq =
8082 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8083 DRV_MSG_SEQ_NUMBER_MASK);
8084 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8085
8086 bnx2x_fw_command(bp, reset_code, 0);
8087 }
8088
8089 /* now it's safe to release the lock */
8090 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8091
8092 bnx2x_undi_int_disable(bp);
8093 port = BP_PORT(bp);
8094
8095 /* close input traffic and wait for it */
8096 /* Do not rcv packets to BRB */
8097 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8098 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8099 /* Do not direct rcv packets that are not for MCP to
8100 * the BRB */
8101 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8102 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8103 /* clear AEU */
8104 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8105 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8106 msleep(10);
8107
8108 /* save NIG port swap info */
8109 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8110 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8111 /* reset device */
8112 REG_WR(bp,
8113 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8114 0xd3ffffff);
8115
8116 value = 0x1400;
8117 if (CHIP_IS_E3(bp)) {
8118 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8119 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8120 }
8121
8122 REG_WR(bp,
8123 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8124 value);
8125
8126 /* take the NIG out of reset and restore swap values */
8127 REG_WR(bp,
8128 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8129 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8130 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8131 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8132
8133 /* send unload done to the MCP */
8134 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8135
8136 /* restore our func and fw_seq */
8137 bp->pf_num = orig_pf_num;
8138 bp->fw_seq =
8139 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8140 DRV_MSG_SEQ_NUMBER_MASK);
8141 } else
8142 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8143 }
8144 }
8145
8146 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8147 {
8148 u32 val, val2, val3, val4, id;
8149 u16 pmc;
8150
8151 /* Get the chip revision id and number. */
8152 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8153 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8154 id = ((val & 0xffff) << 16);
8155 val = REG_RD(bp, MISC_REG_CHIP_REV);
8156 id |= ((val & 0xf) << 12);
8157 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8158 id |= ((val & 0xff) << 4);
8159 val = REG_RD(bp, MISC_REG_BOND_ID);
8160 id |= (val & 0xf);
8161 bp->common.chip_id = id;
8162
8163 /* Set doorbell size */
8164 bp->db_size = (1 << BNX2X_DB_SHIFT);
8165
8166 if (!CHIP_IS_E1x(bp)) {
8167 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8168 if ((val & 1) == 0)
8169 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8170 else
8171 val = (val >> 1) & 1;
8172 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8173 "2_PORT_MODE");
8174 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8175 CHIP_2_PORT_MODE;
8176
8177 if (CHIP_MODE_IS_4_PORT(bp))
8178 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8179 else
8180 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8181 } else {
8182 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8183 bp->pfid = bp->pf_num; /* 0..7 */
8184 }
8185
8186 bp->link_params.chip_id = bp->common.chip_id;
8187 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8188
8189 val = (REG_RD(bp, 0x2874) & 0x55);
8190 if ((bp->common.chip_id & 0x1) ||
8191 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8192 bp->flags |= ONE_PORT_FLAG;
8193 BNX2X_DEV_INFO("single port device\n");
8194 }
8195
8196 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8197 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8198 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8199 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8200 bp->common.flash_size, bp->common.flash_size);
8201
8202 bnx2x_init_shmem(bp);
8203
8204
8205
8206 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8207 MISC_REG_GENERIC_CR_1 :
8208 MISC_REG_GENERIC_CR_0));
8209
8210 bp->link_params.shmem_base = bp->common.shmem_base;
8211 bp->link_params.shmem2_base = bp->common.shmem2_base;
8212 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8213 bp->common.shmem_base, bp->common.shmem2_base);
8214
8215 if (!bp->common.shmem_base) {
8216 BNX2X_DEV_INFO("MCP not active\n");
8217 bp->flags |= NO_MCP_FLAG;
8218 return;
8219 }
8220
8221 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8222 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8223
8224 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8225 SHARED_HW_CFG_LED_MODE_MASK) >>
8226 SHARED_HW_CFG_LED_MODE_SHIFT);
8227
8228 bp->link_params.feature_config_flags = 0;
8229 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8230 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8231 bp->link_params.feature_config_flags |=
8232 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8233 else
8234 bp->link_params.feature_config_flags &=
8235 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8236
8237 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8238 bp->common.bc_ver = val;
8239 BNX2X_DEV_INFO("bc_ver %X\n", val);
8240 if (val < BNX2X_BC_VER) {
8241 /* for now only warn
8242 * later we might need to enforce this */
8243 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8244 "please upgrade BC\n", BNX2X_BC_VER, val);
8245 }
8246 bp->link_params.feature_config_flags |=
8247 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8248 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8249
8250 bp->link_params.feature_config_flags |=
8251 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8252 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8253
8254 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8255 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8256
8257 BNX2X_DEV_INFO("%sWoL capable\n",
8258 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8259
8260 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8261 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8262 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8263 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8264
8265 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8266 val, val2, val3, val4);
8267 }
8268
8269 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8270 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8271
8272 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8273 {
8274 int pfid = BP_FUNC(bp);
8275 int vn = BP_E1HVN(bp);
8276 int igu_sb_id;
8277 u32 val;
8278 u8 fid;
8279
8280 bp->igu_base_sb = 0xff;
8281 bp->igu_sb_cnt = 0;
8282 if (CHIP_INT_MODE_IS_BC(bp)) {
8283 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8284 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8285
8286 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8287 FP_SB_MAX_E1x;
8288
8289 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8290 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8291
8292 return;
8293 }
8294
8295 /* IGU in normal mode - read CAM */
8296 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8297 igu_sb_id++) {
8298 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8299 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8300 continue;
8301 fid = IGU_FID(val);
8302 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8303 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8304 continue;
8305 if (IGU_VEC(val) == 0)
8306 /* default status block */
8307 bp->igu_dsb_id = igu_sb_id;
8308 else {
8309 if (bp->igu_base_sb == 0xff)
8310 bp->igu_base_sb = igu_sb_id;
8311 bp->igu_sb_cnt++;
8312 }
8313 }
8314 }
8315
8316 /* It's expected that number of CAM entries for this
8317 * functions is equal to the MSI-X table size (which was a
8318 * used during bp->l2_cid_count value calculation.
8319 * We want a harsh warning if these values are different!
8320 */
8321 WARN_ON(bp->igu_sb_cnt != NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8322
8323 if (bp->igu_sb_cnt == 0)
8324 BNX2X_ERR("CAM configuration error\n");
8325 }
8326
8327 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8328 u32 switch_cfg)
8329 {
8330 int cfg_size = 0, idx, port = BP_PORT(bp);
8331
8332 /* Aggregation of supported attributes of all external phys */
8333 bp->port.supported[0] = 0;
8334 bp->port.supported[1] = 0;
8335 switch (bp->link_params.num_phys) {
8336 case 1:
8337 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8338 cfg_size = 1;
8339 break;
8340 case 2:
8341 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8342 cfg_size = 1;
8343 break;
8344 case 3:
8345 if (bp->link_params.multi_phy_config &
8346 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8347 bp->port.supported[1] =
8348 bp->link_params.phy[EXT_PHY1].supported;
8349 bp->port.supported[0] =
8350 bp->link_params.phy[EXT_PHY2].supported;
8351 } else {
8352 bp->port.supported[0] =
8353 bp->link_params.phy[EXT_PHY1].supported;
8354 bp->port.supported[1] =
8355 bp->link_params.phy[EXT_PHY2].supported;
8356 }
8357 cfg_size = 2;
8358 break;
8359 }
8360
8361 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8362 BNX2X_ERR("NVRAM config error. BAD phy config."
8363 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8364 SHMEM_RD(bp,
8365 dev_info.port_hw_config[port].external_phy_config),
8366 SHMEM_RD(bp,
8367 dev_info.port_hw_config[port].external_phy_config2));
8368 return;
8369 }
8370
8371 if (CHIP_IS_E3(bp))
8372 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8373 else {
8374 switch (switch_cfg) {
8375 case SWITCH_CFG_1G:
8376 bp->port.phy_addr = REG_RD(
8377 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8378 break;
8379 case SWITCH_CFG_10G:
8380 bp->port.phy_addr = REG_RD(
8381 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8382 break;
8383 default:
8384 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8385 bp->port.link_config[0]);
8386 return;
8387 }
8388 }
8389 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8390 /* mask what we support according to speed_cap_mask per configuration */
8391 for (idx = 0; idx < cfg_size; idx++) {
8392 if (!(bp->link_params.speed_cap_mask[idx] &
8393 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8394 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8395
8396 if (!(bp->link_params.speed_cap_mask[idx] &
8397 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8398 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8399
8400 if (!(bp->link_params.speed_cap_mask[idx] &
8401 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8402 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8403
8404 if (!(bp->link_params.speed_cap_mask[idx] &
8405 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8406 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8407
8408 if (!(bp->link_params.speed_cap_mask[idx] &
8409 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8410 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8411 SUPPORTED_1000baseT_Full);
8412
8413 if (!(bp->link_params.speed_cap_mask[idx] &
8414 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8415 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8416
8417 if (!(bp->link_params.speed_cap_mask[idx] &
8418 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8419 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8420
8421 }
8422
8423 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8424 bp->port.supported[1]);
8425 }
8426
8427 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8428 {
8429 u32 link_config, idx, cfg_size = 0;
8430 bp->port.advertising[0] = 0;
8431 bp->port.advertising[1] = 0;
8432 switch (bp->link_params.num_phys) {
8433 case 1:
8434 case 2:
8435 cfg_size = 1;
8436 break;
8437 case 3:
8438 cfg_size = 2;
8439 break;
8440 }
8441 for (idx = 0; idx < cfg_size; idx++) {
8442 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8443 link_config = bp->port.link_config[idx];
8444 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8445 case PORT_FEATURE_LINK_SPEED_AUTO:
8446 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8447 bp->link_params.req_line_speed[idx] =
8448 SPEED_AUTO_NEG;
8449 bp->port.advertising[idx] |=
8450 bp->port.supported[idx];
8451 } else {
8452 /* force 10G, no AN */
8453 bp->link_params.req_line_speed[idx] =
8454 SPEED_10000;
8455 bp->port.advertising[idx] |=
8456 (ADVERTISED_10000baseT_Full |
8457 ADVERTISED_FIBRE);
8458 continue;
8459 }
8460 break;
8461
8462 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8463 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8464 bp->link_params.req_line_speed[idx] =
8465 SPEED_10;
8466 bp->port.advertising[idx] |=
8467 (ADVERTISED_10baseT_Full |
8468 ADVERTISED_TP);
8469 } else {
8470 BNX2X_ERR("NVRAM config error. "
8471 "Invalid link_config 0x%x"
8472 " speed_cap_mask 0x%x\n",
8473 link_config,
8474 bp->link_params.speed_cap_mask[idx]);
8475 return;
8476 }
8477 break;
8478
8479 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8480 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8481 bp->link_params.req_line_speed[idx] =
8482 SPEED_10;
8483 bp->link_params.req_duplex[idx] =
8484 DUPLEX_HALF;
8485 bp->port.advertising[idx] |=
8486 (ADVERTISED_10baseT_Half |
8487 ADVERTISED_TP);
8488 } else {
8489 BNX2X_ERR("NVRAM config error. "
8490 "Invalid link_config 0x%x"
8491 " speed_cap_mask 0x%x\n",
8492 link_config,
8493 bp->link_params.speed_cap_mask[idx]);
8494 return;
8495 }
8496 break;
8497
8498 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8499 if (bp->port.supported[idx] &
8500 SUPPORTED_100baseT_Full) {
8501 bp->link_params.req_line_speed[idx] =
8502 SPEED_100;
8503 bp->port.advertising[idx] |=
8504 (ADVERTISED_100baseT_Full |
8505 ADVERTISED_TP);
8506 } else {
8507 BNX2X_ERR("NVRAM config error. "
8508 "Invalid link_config 0x%x"
8509 " speed_cap_mask 0x%x\n",
8510 link_config,
8511 bp->link_params.speed_cap_mask[idx]);
8512 return;
8513 }
8514 break;
8515
8516 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8517 if (bp->port.supported[idx] &
8518 SUPPORTED_100baseT_Half) {
8519 bp->link_params.req_line_speed[idx] =
8520 SPEED_100;
8521 bp->link_params.req_duplex[idx] =
8522 DUPLEX_HALF;
8523 bp->port.advertising[idx] |=
8524 (ADVERTISED_100baseT_Half |
8525 ADVERTISED_TP);
8526 } else {
8527 BNX2X_ERR("NVRAM config error. "
8528 "Invalid link_config 0x%x"
8529 " speed_cap_mask 0x%x\n",
8530 link_config,
8531 bp->link_params.speed_cap_mask[idx]);
8532 return;
8533 }
8534 break;
8535
8536 case PORT_FEATURE_LINK_SPEED_1G:
8537 if (bp->port.supported[idx] &
8538 SUPPORTED_1000baseT_Full) {
8539 bp->link_params.req_line_speed[idx] =
8540 SPEED_1000;
8541 bp->port.advertising[idx] |=
8542 (ADVERTISED_1000baseT_Full |
8543 ADVERTISED_TP);
8544 } else {
8545 BNX2X_ERR("NVRAM config error. "
8546 "Invalid link_config 0x%x"
8547 " speed_cap_mask 0x%x\n",
8548 link_config,
8549 bp->link_params.speed_cap_mask[idx]);
8550 return;
8551 }
8552 break;
8553
8554 case PORT_FEATURE_LINK_SPEED_2_5G:
8555 if (bp->port.supported[idx] &
8556 SUPPORTED_2500baseX_Full) {
8557 bp->link_params.req_line_speed[idx] =
8558 SPEED_2500;
8559 bp->port.advertising[idx] |=
8560 (ADVERTISED_2500baseX_Full |
8561 ADVERTISED_TP);
8562 } else {
8563 BNX2X_ERR("NVRAM config error. "
8564 "Invalid link_config 0x%x"
8565 " speed_cap_mask 0x%x\n",
8566 link_config,
8567 bp->link_params.speed_cap_mask[idx]);
8568 return;
8569 }
8570 break;
8571
8572 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8573 if (bp->port.supported[idx] &
8574 SUPPORTED_10000baseT_Full) {
8575 bp->link_params.req_line_speed[idx] =
8576 SPEED_10000;
8577 bp->port.advertising[idx] |=
8578 (ADVERTISED_10000baseT_Full |
8579 ADVERTISED_FIBRE);
8580 } else {
8581 BNX2X_ERR("NVRAM config error. "
8582 "Invalid link_config 0x%x"
8583 " speed_cap_mask 0x%x\n",
8584 link_config,
8585 bp->link_params.speed_cap_mask[idx]);
8586 return;
8587 }
8588 break;
8589 case PORT_FEATURE_LINK_SPEED_20G:
8590 bp->link_params.req_line_speed[idx] = SPEED_20000;
8591
8592 break;
8593 default:
8594 BNX2X_ERR("NVRAM config error. "
8595 "BAD link speed link_config 0x%x\n",
8596 link_config);
8597 bp->link_params.req_line_speed[idx] =
8598 SPEED_AUTO_NEG;
8599 bp->port.advertising[idx] =
8600 bp->port.supported[idx];
8601 break;
8602 }
8603
8604 bp->link_params.req_flow_ctrl[idx] = (link_config &
8605 PORT_FEATURE_FLOW_CONTROL_MASK);
8606 if ((bp->link_params.req_flow_ctrl[idx] ==
8607 BNX2X_FLOW_CTRL_AUTO) &&
8608 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8609 bp->link_params.req_flow_ctrl[idx] =
8610 BNX2X_FLOW_CTRL_NONE;
8611 }
8612
8613 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8614 " 0x%x advertising 0x%x\n",
8615 bp->link_params.req_line_speed[idx],
8616 bp->link_params.req_duplex[idx],
8617 bp->link_params.req_flow_ctrl[idx],
8618 bp->port.advertising[idx]);
8619 }
8620 }
8621
8622 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8623 {
8624 mac_hi = cpu_to_be16(mac_hi);
8625 mac_lo = cpu_to_be32(mac_lo);
8626 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8627 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8628 }
8629
8630 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8631 {
8632 int port = BP_PORT(bp);
8633 u32 config;
8634 u32 ext_phy_type, ext_phy_config;
8635
8636 bp->link_params.bp = bp;
8637 bp->link_params.port = port;
8638
8639 bp->link_params.lane_config =
8640 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8641
8642 bp->link_params.speed_cap_mask[0] =
8643 SHMEM_RD(bp,
8644 dev_info.port_hw_config[port].speed_capability_mask);
8645 bp->link_params.speed_cap_mask[1] =
8646 SHMEM_RD(bp,
8647 dev_info.port_hw_config[port].speed_capability_mask2);
8648 bp->port.link_config[0] =
8649 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8650
8651 bp->port.link_config[1] =
8652 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8653
8654 bp->link_params.multi_phy_config =
8655 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8656 /* If the device is capable of WoL, set the default state according
8657 * to the HW
8658 */
8659 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8660 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8661 (config & PORT_FEATURE_WOL_ENABLED));
8662
8663 BNX2X_DEV_INFO("lane_config 0x%08x "
8664 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
8665 bp->link_params.lane_config,
8666 bp->link_params.speed_cap_mask[0],
8667 bp->port.link_config[0]);
8668
8669 bp->link_params.switch_cfg = (bp->port.link_config[0] &
8670 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8671 bnx2x_phy_probe(&bp->link_params);
8672 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8673
8674 bnx2x_link_settings_requested(bp);
8675
8676 /*
8677 * If connected directly, work with the internal PHY, otherwise, work
8678 * with the external PHY
8679 */
8680 ext_phy_config =
8681 SHMEM_RD(bp,
8682 dev_info.port_hw_config[port].external_phy_config);
8683 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8684 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8685 bp->mdio.prtad = bp->port.phy_addr;
8686
8687 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8688 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8689 bp->mdio.prtad =
8690 XGXS_EXT_PHY_ADDR(ext_phy_config);
8691
8692 /*
8693 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8694 * In MF mode, it is set to cover self test cases
8695 */
8696 if (IS_MF(bp))
8697 bp->port.need_hw_lock = 1;
8698 else
8699 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8700 bp->common.shmem_base,
8701 bp->common.shmem2_base);
8702 }
8703
8704 #ifdef BCM_CNIC
8705 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8706 {
8707 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8708 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8709 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8710 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8711
8712 /* Get the number of maximum allowed iSCSI and FCoE connections */
8713 bp->cnic_eth_dev.max_iscsi_conn =
8714 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8715 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8716
8717 bp->cnic_eth_dev.max_fcoe_conn =
8718 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8719 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8720
8721 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8722 bp->cnic_eth_dev.max_iscsi_conn,
8723 bp->cnic_eth_dev.max_fcoe_conn);
8724
8725 /* If mamimum allowed number of connections is zero -
8726 * disable the feature.
8727 */
8728 if (!bp->cnic_eth_dev.max_iscsi_conn)
8729 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8730
8731 if (!bp->cnic_eth_dev.max_fcoe_conn)
8732 bp->flags |= NO_FCOE_FLAG;
8733 }
8734 #endif
8735
8736 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8737 {
8738 u32 val, val2;
8739 int func = BP_ABS_FUNC(bp);
8740 int port = BP_PORT(bp);
8741 #ifdef BCM_CNIC
8742 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8743 u8 *fip_mac = bp->fip_mac;
8744 #endif
8745
8746 /* Zero primary MAC configuration */
8747 memset(bp->dev->dev_addr, 0, ETH_ALEN);
8748
8749 if (BP_NOMCP(bp)) {
8750 BNX2X_ERROR("warning: random MAC workaround active\n");
8751 random_ether_addr(bp->dev->dev_addr);
8752 } else if (IS_MF(bp)) {
8753 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8754 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8755 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8756 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8757 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8758
8759 #ifdef BCM_CNIC
8760 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8761 * FCoE MAC then the appropriate feature should be disabled.
8762 */
8763 if (IS_MF_SI(bp)) {
8764 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8765 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8766 val2 = MF_CFG_RD(bp, func_ext_config[func].
8767 iscsi_mac_addr_upper);
8768 val = MF_CFG_RD(bp, func_ext_config[func].
8769 iscsi_mac_addr_lower);
8770 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8771 BNX2X_DEV_INFO("Read iSCSI MAC: "
8772 BNX2X_MAC_FMT"\n",
8773 BNX2X_MAC_PRN_LIST(iscsi_mac));
8774 } else
8775 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8776
8777 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8778 val2 = MF_CFG_RD(bp, func_ext_config[func].
8779 fcoe_mac_addr_upper);
8780 val = MF_CFG_RD(bp, func_ext_config[func].
8781 fcoe_mac_addr_lower);
8782 bnx2x_set_mac_buf(fip_mac, val, val2);
8783 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
8784 BNX2X_MAC_FMT"\n",
8785 BNX2X_MAC_PRN_LIST(fip_mac));
8786
8787 } else
8788 bp->flags |= NO_FCOE_FLAG;
8789 }
8790 #endif
8791 } else {
8792 /* in SF read MACs from port configuration */
8793 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8794 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8795 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8796
8797 #ifdef BCM_CNIC
8798 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8799 iscsi_mac_upper);
8800 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8801 iscsi_mac_lower);
8802 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8803 #endif
8804 }
8805
8806 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8807 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8808
8809 #ifdef BCM_CNIC
8810 /* Set the FCoE MAC in modes other then MF_SI */
8811 if (!CHIP_IS_E1x(bp)) {
8812 if (IS_MF_SD(bp))
8813 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8814 else if (!IS_MF(bp))
8815 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
8816 }
8817
8818 /* Disable iSCSI if MAC configuration is
8819 * invalid.
8820 */
8821 if (!is_valid_ether_addr(iscsi_mac)) {
8822 bp->flags |= NO_ISCSI_FLAG;
8823 memset(iscsi_mac, 0, ETH_ALEN);
8824 }
8825
8826 /* Disable FCoE if MAC configuration is
8827 * invalid.
8828 */
8829 if (!is_valid_ether_addr(fip_mac)) {
8830 bp->flags |= NO_FCOE_FLAG;
8831 memset(bp->fip_mac, 0, ETH_ALEN);
8832 }
8833 #endif
8834
8835 if (!is_valid_ether_addr(bp->dev->dev_addr))
8836 dev_err(&bp->pdev->dev,
8837 "bad Ethernet MAC address configuration: "
8838 BNX2X_MAC_FMT", change it manually before bringing up "
8839 "the appropriate network interface\n",
8840 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
8841 }
8842
8843 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8844 {
8845 int /*abs*/func = BP_ABS_FUNC(bp);
8846 int vn;
8847 u32 val = 0;
8848 int rc = 0;
8849
8850 bnx2x_get_common_hwinfo(bp);
8851
8852 if (CHIP_IS_E1x(bp)) {
8853 bp->common.int_block = INT_BLOCK_HC;
8854
8855 bp->igu_dsb_id = DEF_SB_IGU_ID;
8856 bp->igu_base_sb = 0;
8857 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8858 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8859 } else {
8860 bp->common.int_block = INT_BLOCK_IGU;
8861 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8862
8863 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8864 int tout = 5000;
8865
8866 BNX2X_DEV_INFO("FORCING Normal Mode\n");
8867
8868 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8869 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
8870 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
8871
8872 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
8873 tout--;
8874 usleep_range(1000, 1000);
8875 }
8876
8877 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
8878 dev_err(&bp->pdev->dev,
8879 "FORCING Normal Mode failed!!!\n");
8880 return -EPERM;
8881 }
8882 }
8883
8884 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8885 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
8886 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8887 } else
8888 BNX2X_DEV_INFO("IGU Normal Mode\n");
8889
8890 bnx2x_get_igu_cam_info(bp);
8891
8892 }
8893
8894 /*
8895 * set base FW non-default (fast path) status block id, this value is
8896 * used to initialize the fw_sb_id saved on the fp/queue structure to
8897 * determine the id used by the FW.
8898 */
8899 if (CHIP_IS_E1x(bp))
8900 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
8901 else /*
8902 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
8903 * the same queue are indicated on the same IGU SB). So we prefer
8904 * FW and IGU SBs to be the same value.
8905 */
8906 bp->base_fw_ndsb = bp->igu_base_sb;
8907
8908 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
8909 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
8910 bp->igu_sb_cnt, bp->base_fw_ndsb);
8911
8912 /*
8913 * Initialize MF configuration
8914 */
8915
8916 bp->mf_ov = 0;
8917 bp->mf_mode = 0;
8918 vn = BP_E1HVN(bp);
8919
8920 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8921 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
8922 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8923 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8924
8925 if (SHMEM2_HAS(bp, mf_cfg_addr))
8926 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8927 else
8928 bp->common.mf_cfg_base = bp->common.shmem_base +
8929 offsetof(struct shmem_region, func_mb) +
8930 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8931 /*
8932 * get mf configuration:
8933 * 1. existence of MF configuration
8934 * 2. MAC address must be legal (check only upper bytes)
8935 * for Switch-Independent mode;
8936 * OVLAN must be legal for Switch-Dependent mode
8937 * 3. SF_MODE configures specific MF mode
8938 */
8939 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8940 /* get mf configuration */
8941 val = SHMEM_RD(bp,
8942 dev_info.shared_feature_config.config);
8943 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8944
8945 switch (val) {
8946 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8947 val = MF_CFG_RD(bp, func_mf_config[func].
8948 mac_upper);
8949 /* check for legal mac (upper bytes)*/
8950 if (val != 0xffff) {
8951 bp->mf_mode = MULTI_FUNCTION_SI;
8952 bp->mf_config[vn] = MF_CFG_RD(bp,
8953 func_mf_config[func].config);
8954 } else
8955 BNX2X_DEV_INFO("illegal MAC address "
8956 "for SI\n");
8957 break;
8958 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8959 /* get OV configuration */
8960 val = MF_CFG_RD(bp,
8961 func_mf_config[FUNC_0].e1hov_tag);
8962 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8963
8964 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8965 bp->mf_mode = MULTI_FUNCTION_SD;
8966 bp->mf_config[vn] = MF_CFG_RD(bp,
8967 func_mf_config[func].config);
8968 } else
8969 BNX2X_DEV_INFO("illegal OV for SD\n");
8970 break;
8971 default:
8972 /* Unknown configuration: reset mf_config */
8973 bp->mf_config[vn] = 0;
8974 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
8975 }
8976 }
8977
8978 BNX2X_DEV_INFO("%s function mode\n",
8979 IS_MF(bp) ? "multi" : "single");
8980
8981 switch (bp->mf_mode) {
8982 case MULTI_FUNCTION_SD:
8983 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8984 FUNC_MF_CFG_E1HOV_TAG_MASK;
8985 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8986 bp->mf_ov = val;
8987 bp->path_has_ovlan = true;
8988
8989 BNX2X_DEV_INFO("MF OV for func %d is %d "
8990 "(0x%04x)\n", func, bp->mf_ov,
8991 bp->mf_ov);
8992 } else {
8993 dev_err(&bp->pdev->dev,
8994 "No valid MF OV for func %d, "
8995 "aborting\n", func);
8996 return -EPERM;
8997 }
8998 break;
8999 case MULTI_FUNCTION_SI:
9000 BNX2X_DEV_INFO("func %d is in MF "
9001 "switch-independent mode\n", func);
9002 break;
9003 default:
9004 if (vn) {
9005 dev_err(&bp->pdev->dev,
9006 "VN %d is in a single function mode, "
9007 "aborting\n", vn);
9008 return -EPERM;
9009 }
9010 break;
9011 }
9012
9013 /* check if other port on the path needs ovlan:
9014 * Since MF configuration is shared between ports
9015 * Possible mixed modes are only
9016 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9017 */
9018 if (CHIP_MODE_IS_4_PORT(bp) &&
9019 !bp->path_has_ovlan &&
9020 !IS_MF(bp) &&
9021 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9022 u8 other_port = !BP_PORT(bp);
9023 u8 other_func = BP_PATH(bp) + 2*other_port;
9024 val = MF_CFG_RD(bp,
9025 func_mf_config[other_func].e1hov_tag);
9026 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9027 bp->path_has_ovlan = true;
9028 }
9029 }
9030
9031 /* adjust igu_sb_cnt to MF for E1x */
9032 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9033 bp->igu_sb_cnt /= E1HVN_MAX;
9034
9035 /* port info */
9036 bnx2x_get_port_hwinfo(bp);
9037
9038 if (!BP_NOMCP(bp)) {
9039 bp->fw_seq =
9040 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9041 DRV_MSG_SEQ_NUMBER_MASK);
9042 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9043 }
9044
9045 /* Get MAC addresses */
9046 bnx2x_get_mac_hwinfo(bp);
9047
9048 #ifdef BCM_CNIC
9049 bnx2x_get_cnic_info(bp);
9050 #endif
9051
9052 /* Get current FW pulse sequence */
9053 if (!BP_NOMCP(bp)) {
9054 int mb_idx = BP_FW_MB_IDX(bp);
9055
9056 bp->fw_drv_pulse_wr_seq =
9057 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9058 DRV_PULSE_SEQ_MASK);
9059 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9060 }
9061
9062 return rc;
9063 }
9064
9065 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9066 {
9067 int cnt, i, block_end, rodi;
9068 char vpd_data[BNX2X_VPD_LEN+1];
9069 char str_id_reg[VENDOR_ID_LEN+1];
9070 char str_id_cap[VENDOR_ID_LEN+1];
9071 u8 len;
9072
9073 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9074 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9075
9076 if (cnt < BNX2X_VPD_LEN)
9077 goto out_not_found;
9078
9079 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9080 PCI_VPD_LRDT_RO_DATA);
9081 if (i < 0)
9082 goto out_not_found;
9083
9084
9085 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9086 pci_vpd_lrdt_size(&vpd_data[i]);
9087
9088 i += PCI_VPD_LRDT_TAG_SIZE;
9089
9090 if (block_end > BNX2X_VPD_LEN)
9091 goto out_not_found;
9092
9093 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9094 PCI_VPD_RO_KEYWORD_MFR_ID);
9095 if (rodi < 0)
9096 goto out_not_found;
9097
9098 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9099
9100 if (len != VENDOR_ID_LEN)
9101 goto out_not_found;
9102
9103 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9104
9105 /* vendor specific info */
9106 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9107 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9108 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9109 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9110
9111 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9112 PCI_VPD_RO_KEYWORD_VENDOR0);
9113 if (rodi >= 0) {
9114 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9115
9116 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9117
9118 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9119 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9120 bp->fw_ver[len] = ' ';
9121 }
9122 }
9123 return;
9124 }
9125 out_not_found:
9126 return;
9127 }
9128
9129 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9130 {
9131 u32 flags = 0;
9132
9133 if (CHIP_REV_IS_FPGA(bp))
9134 SET_FLAGS(flags, MODE_FPGA);
9135 else if (CHIP_REV_IS_EMUL(bp))
9136 SET_FLAGS(flags, MODE_EMUL);
9137 else
9138 SET_FLAGS(flags, MODE_ASIC);
9139
9140 if (CHIP_MODE_IS_4_PORT(bp))
9141 SET_FLAGS(flags, MODE_PORT4);
9142 else
9143 SET_FLAGS(flags, MODE_PORT2);
9144
9145 if (CHIP_IS_E2(bp))
9146 SET_FLAGS(flags, MODE_E2);
9147 else if (CHIP_IS_E3(bp)) {
9148 SET_FLAGS(flags, MODE_E3);
9149 if (CHIP_REV(bp) == CHIP_REV_Ax)
9150 SET_FLAGS(flags, MODE_E3_A0);
9151 else {/*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9152 SET_FLAGS(flags, MODE_E3_B0);
9153 SET_FLAGS(flags, MODE_COS_BC);
9154 }
9155 }
9156
9157 if (IS_MF(bp)) {
9158 SET_FLAGS(flags, MODE_MF);
9159 switch (bp->mf_mode) {
9160 case MULTI_FUNCTION_SD:
9161 SET_FLAGS(flags, MODE_MF_SD);
9162 break;
9163 case MULTI_FUNCTION_SI:
9164 SET_FLAGS(flags, MODE_MF_SI);
9165 break;
9166 }
9167 } else
9168 SET_FLAGS(flags, MODE_SF);
9169
9170 #if defined(__LITTLE_ENDIAN)
9171 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9172 #else /*(__BIG_ENDIAN)*/
9173 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9174 #endif
9175 INIT_MODE_FLAGS(bp) = flags;
9176 }
9177
9178 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9179 {
9180 int func;
9181 int timer_interval;
9182 int rc;
9183
9184 mutex_init(&bp->port.phy_mutex);
9185 mutex_init(&bp->fw_mb_mutex);
9186 spin_lock_init(&bp->stats_lock);
9187 #ifdef BCM_CNIC
9188 mutex_init(&bp->cnic_mutex);
9189 #endif
9190
9191 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9192 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
9193
9194 rc = bnx2x_get_hwinfo(bp);
9195 if (rc)
9196 return rc;
9197
9198 bnx2x_set_modes_bitmap(bp);
9199
9200 rc = bnx2x_alloc_mem_bp(bp);
9201 if (rc)
9202 return rc;
9203
9204 bnx2x_read_fwinfo(bp);
9205
9206 func = BP_FUNC(bp);
9207
9208 /* need to reset chip if undi was active */
9209 if (!BP_NOMCP(bp))
9210 bnx2x_undi_unload(bp);
9211
9212 if (CHIP_REV_IS_FPGA(bp))
9213 dev_err(&bp->pdev->dev, "FPGA detected\n");
9214
9215 if (BP_NOMCP(bp) && (func == 0))
9216 dev_err(&bp->pdev->dev, "MCP disabled, "
9217 "must load devices in order!\n");
9218
9219 bp->multi_mode = multi_mode;
9220
9221 /* Set TPA flags */
9222 if (disable_tpa) {
9223 bp->flags &= ~TPA_ENABLE_FLAG;
9224 bp->dev->features &= ~NETIF_F_LRO;
9225 } else {
9226 bp->flags |= TPA_ENABLE_FLAG;
9227 bp->dev->features |= NETIF_F_LRO;
9228 }
9229 bp->disable_tpa = disable_tpa;
9230
9231 if (CHIP_IS_E1(bp))
9232 bp->dropless_fc = 0;
9233 else
9234 bp->dropless_fc = dropless_fc;
9235
9236 bp->mrrs = mrrs;
9237
9238 bp->tx_ring_size = MAX_TX_AVAIL;
9239
9240 /* make sure that the numbers are in the right granularity */
9241 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9242 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9243
9244 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9245 bp->current_interval = (poll ? poll : timer_interval);
9246
9247 init_timer(&bp->timer);
9248 bp->timer.expires = jiffies + bp->current_interval;
9249 bp->timer.data = (unsigned long) bp;
9250 bp->timer.function = bnx2x_timer;
9251
9252 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9253 bnx2x_dcbx_init_params(bp);
9254
9255 #ifdef BCM_CNIC
9256 if (CHIP_IS_E1x(bp))
9257 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9258 else
9259 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9260 #endif
9261
9262 return rc;
9263 }
9264
9265
9266 /****************************************************************************
9267 * General service functions
9268 ****************************************************************************/
9269
9270 /*
9271 * net_device service functions
9272 */
9273
9274 /* called with rtnl_lock */
9275 static int bnx2x_open(struct net_device *dev)
9276 {
9277 struct bnx2x *bp = netdev_priv(dev);
9278 bool global = false;
9279 int other_engine = BP_PATH(bp) ? 0 : 1;
9280 u32 other_load_counter, load_counter;
9281
9282 netif_carrier_off(dev);
9283
9284 bnx2x_set_power_state(bp, PCI_D0);
9285
9286 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9287 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9288
9289 /*
9290 * If parity had happen during the unload, then attentions
9291 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9292 * want the first function loaded on the current engine to
9293 * complete the recovery.
9294 */
9295 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9296 bnx2x_chk_parity_attn(bp, &global, true))
9297 do {
9298 /*
9299 * If there are attentions and they are in a global
9300 * blocks, set the GLOBAL_RESET bit regardless whether
9301 * it will be this function that will complete the
9302 * recovery or not.
9303 */
9304 if (global)
9305 bnx2x_set_reset_global(bp);
9306
9307 /*
9308 * Only the first function on the current engine should
9309 * try to recover in open. In case of attentions in
9310 * global blocks only the first in the chip should try
9311 * to recover.
9312 */
9313 if ((!load_counter &&
9314 (!global || !other_load_counter)) &&
9315 bnx2x_trylock_leader_lock(bp) &&
9316 !bnx2x_leader_reset(bp)) {
9317 netdev_info(bp->dev, "Recovered in open\n");
9318 break;
9319 }
9320
9321 /* recovery has failed... */
9322 bnx2x_set_power_state(bp, PCI_D3hot);
9323 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9324
9325 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9326 " completed yet. Try again later. If u still see this"
9327 " message after a few retries then power cycle is"
9328 " required.\n");
9329
9330 return -EAGAIN;
9331 } while (0);
9332
9333 bp->recovery_state = BNX2X_RECOVERY_DONE;
9334 return bnx2x_nic_load(bp, LOAD_OPEN);
9335 }
9336
9337 /* called with rtnl_lock */
9338 static int bnx2x_close(struct net_device *dev)
9339 {
9340 struct bnx2x *bp = netdev_priv(dev);
9341
9342 /* Unload the driver, release IRQs */
9343 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9344
9345 /* Power off */
9346 bnx2x_set_power_state(bp, PCI_D3hot);
9347
9348 return 0;
9349 }
9350
9351 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9352 struct bnx2x_mcast_ramrod_params *p)
9353 {
9354 int mc_count = netdev_mc_count(bp->dev);
9355 struct bnx2x_mcast_list_elem *mc_mac =
9356 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9357 struct netdev_hw_addr *ha;
9358
9359 if (!mc_mac)
9360 return -ENOMEM;
9361
9362 INIT_LIST_HEAD(&p->mcast_list);
9363
9364 netdev_for_each_mc_addr(ha, bp->dev) {
9365 mc_mac->mac = bnx2x_mc_addr(ha);
9366 list_add_tail(&mc_mac->link, &p->mcast_list);
9367 mc_mac++;
9368 }
9369
9370 p->mcast_list_len = mc_count;
9371
9372 return 0;
9373 }
9374
9375 static inline void bnx2x_free_mcast_macs_list(
9376 struct bnx2x_mcast_ramrod_params *p)
9377 {
9378 struct bnx2x_mcast_list_elem *mc_mac =
9379 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9380 link);
9381
9382 WARN_ON(!mc_mac);
9383 kfree(mc_mac);
9384 }
9385
9386 /**
9387 * bnx2x_set_uc_list - configure a new unicast MACs list.
9388 *
9389 * @bp: driver handle
9390 *
9391 * We will use zero (0) as a MAC type for these MACs.
9392 */
9393 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
9394 {
9395 int rc;
9396 struct net_device *dev = bp->dev;
9397 struct netdev_hw_addr *ha;
9398 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9399 unsigned long ramrod_flags = 0;
9400
9401 /* First schedule a cleanup up of old configuration */
9402 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9403 if (rc < 0) {
9404 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9405 return rc;
9406 }
9407
9408 netdev_for_each_uc_addr(ha, dev) {
9409 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9410 BNX2X_UC_LIST_MAC, &ramrod_flags);
9411 if (rc < 0) {
9412 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9413 rc);
9414 return rc;
9415 }
9416 }
9417
9418 /* Execute the pending commands */
9419 __set_bit(RAMROD_CONT, &ramrod_flags);
9420 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9421 BNX2X_UC_LIST_MAC, &ramrod_flags);
9422 }
9423
9424 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9425 {
9426 struct net_device *dev = bp->dev;
9427 struct bnx2x_mcast_ramrod_params rparam = {0};
9428 int rc = 0;
9429
9430 rparam.mcast_obj = &bp->mcast_obj;
9431
9432 /* first, clear all configured multicast MACs */
9433 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9434 if (rc < 0) {
9435 BNX2X_ERR("Failed to clear multicast "
9436 "configuration: %d\n", rc);
9437 return rc;
9438 }
9439
9440 /* then, configure a new MACs list */
9441 if (netdev_mc_count(dev)) {
9442 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
9443 if (rc) {
9444 BNX2X_ERR("Failed to create multicast MACs "
9445 "list: %d\n", rc);
9446 return rc;
9447 }
9448
9449 /* Now add the new MACs */
9450 rc = bnx2x_config_mcast(bp, &rparam,
9451 BNX2X_MCAST_CMD_ADD);
9452 if (rc < 0)
9453 BNX2X_ERR("Failed to set a new multicast "
9454 "configuration: %d\n", rc);
9455
9456 bnx2x_free_mcast_macs_list(&rparam);
9457 }
9458
9459 return rc;
9460 }
9461
9462
9463 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9464 void bnx2x_set_rx_mode(struct net_device *dev)
9465 {
9466 struct bnx2x *bp = netdev_priv(dev);
9467 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9468
9469 if (bp->state != BNX2X_STATE_OPEN) {
9470 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9471 return;
9472 }
9473
9474 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
9475
9476 if (dev->flags & IFF_PROMISC)
9477 rx_mode = BNX2X_RX_MODE_PROMISC;
9478 else if ((dev->flags & IFF_ALLMULTI) ||
9479 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
9480 CHIP_IS_E1(bp)))
9481 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9482 else {
9483 /* some multicasts */
9484 if (bnx2x_set_mc_list(bp) < 0)
9485 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9486
9487 if (bnx2x_set_uc_list(bp) < 0)
9488 rx_mode = BNX2X_RX_MODE_PROMISC;
9489 }
9490
9491 bp->rx_mode = rx_mode;
9492
9493 /* Schedule the rx_mode command */
9494 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
9495 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9496 return;
9497 }
9498
9499 bnx2x_set_storm_rx_mode(bp);
9500 }
9501
9502 /* called with rtnl_lock */
9503 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9504 int devad, u16 addr)
9505 {
9506 struct bnx2x *bp = netdev_priv(netdev);
9507 u16 value;
9508 int rc;
9509
9510 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9511 prtad, devad, addr);
9512
9513 /* The HW expects different devad if CL22 is used */
9514 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9515
9516 bnx2x_acquire_phy_lock(bp);
9517 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
9518 bnx2x_release_phy_lock(bp);
9519 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
9520
9521 if (!rc)
9522 rc = value;
9523 return rc;
9524 }
9525
9526 /* called with rtnl_lock */
9527 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9528 u16 addr, u16 value)
9529 {
9530 struct bnx2x *bp = netdev_priv(netdev);
9531 int rc;
9532
9533 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9534 " value 0x%x\n", prtad, devad, addr, value);
9535
9536 /* The HW expects different devad if CL22 is used */
9537 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9538
9539 bnx2x_acquire_phy_lock(bp);
9540 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
9541 bnx2x_release_phy_lock(bp);
9542 return rc;
9543 }
9544
9545 /* called with rtnl_lock */
9546 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9547 {
9548 struct bnx2x *bp = netdev_priv(dev);
9549 struct mii_ioctl_data *mdio = if_mii(ifr);
9550
9551 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9552 mdio->phy_id, mdio->reg_num, mdio->val_in);
9553
9554 if (!netif_running(dev))
9555 return -EAGAIN;
9556
9557 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
9558 }
9559
9560 #ifdef CONFIG_NET_POLL_CONTROLLER
9561 static void poll_bnx2x(struct net_device *dev)
9562 {
9563 struct bnx2x *bp = netdev_priv(dev);
9564
9565 disable_irq(bp->pdev->irq);
9566 bnx2x_interrupt(bp->pdev->irq, dev);
9567 enable_irq(bp->pdev->irq);
9568 }
9569 #endif
9570
9571 static const struct net_device_ops bnx2x_netdev_ops = {
9572 .ndo_open = bnx2x_open,
9573 .ndo_stop = bnx2x_close,
9574 .ndo_start_xmit = bnx2x_start_xmit,
9575 .ndo_select_queue = bnx2x_select_queue,
9576 .ndo_set_rx_mode = bnx2x_set_rx_mode,
9577 .ndo_set_mac_address = bnx2x_change_mac_addr,
9578 .ndo_validate_addr = eth_validate_addr,
9579 .ndo_do_ioctl = bnx2x_ioctl,
9580 .ndo_change_mtu = bnx2x_change_mtu,
9581 .ndo_fix_features = bnx2x_fix_features,
9582 .ndo_set_features = bnx2x_set_features,
9583 .ndo_tx_timeout = bnx2x_tx_timeout,
9584 #ifdef CONFIG_NET_POLL_CONTROLLER
9585 .ndo_poll_controller = poll_bnx2x,
9586 #endif
9587 };
9588
9589 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
9590 {
9591 struct device *dev = &bp->pdev->dev;
9592
9593 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
9594 bp->flags |= USING_DAC_FLAG;
9595 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
9596 dev_err(dev, "dma_set_coherent_mask failed, "
9597 "aborting\n");
9598 return -EIO;
9599 }
9600 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
9601 dev_err(dev, "System does not support DMA, aborting\n");
9602 return -EIO;
9603 }
9604
9605 return 0;
9606 }
9607
9608 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9609 struct net_device *dev,
9610 unsigned long board_type)
9611 {
9612 struct bnx2x *bp;
9613 int rc;
9614
9615 SET_NETDEV_DEV(dev, &pdev->dev);
9616 bp = netdev_priv(dev);
9617
9618 bp->dev = dev;
9619 bp->pdev = pdev;
9620 bp->flags = 0;
9621 bp->pf_num = PCI_FUNC(pdev->devfn);
9622
9623 rc = pci_enable_device(pdev);
9624 if (rc) {
9625 dev_err(&bp->pdev->dev,
9626 "Cannot enable PCI device, aborting\n");
9627 goto err_out;
9628 }
9629
9630 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9631 dev_err(&bp->pdev->dev,
9632 "Cannot find PCI device base address, aborting\n");
9633 rc = -ENODEV;
9634 goto err_out_disable;
9635 }
9636
9637 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9638 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9639 " base address, aborting\n");
9640 rc = -ENODEV;
9641 goto err_out_disable;
9642 }
9643
9644 if (atomic_read(&pdev->enable_cnt) == 1) {
9645 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9646 if (rc) {
9647 dev_err(&bp->pdev->dev,
9648 "Cannot obtain PCI resources, aborting\n");
9649 goto err_out_disable;
9650 }
9651
9652 pci_set_master(pdev);
9653 pci_save_state(pdev);
9654 }
9655
9656 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9657 if (bp->pm_cap == 0) {
9658 dev_err(&bp->pdev->dev,
9659 "Cannot find power management capability, aborting\n");
9660 rc = -EIO;
9661 goto err_out_release;
9662 }
9663
9664 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9665 if (bp->pcie_cap == 0) {
9666 dev_err(&bp->pdev->dev,
9667 "Cannot find PCI Express capability, aborting\n");
9668 rc = -EIO;
9669 goto err_out_release;
9670 }
9671
9672 rc = bnx2x_set_coherency_mask(bp);
9673 if (rc)
9674 goto err_out_release;
9675
9676 dev->mem_start = pci_resource_start(pdev, 0);
9677 dev->base_addr = dev->mem_start;
9678 dev->mem_end = pci_resource_end(pdev, 0);
9679
9680 dev->irq = pdev->irq;
9681
9682 bp->regview = pci_ioremap_bar(pdev, 0);
9683 if (!bp->regview) {
9684 dev_err(&bp->pdev->dev,
9685 "Cannot map register space, aborting\n");
9686 rc = -ENOMEM;
9687 goto err_out_release;
9688 }
9689
9690 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9691 min_t(u64, BNX2X_DB_SIZE(bp),
9692 pci_resource_len(pdev, 2)));
9693 if (!bp->doorbells) {
9694 dev_err(&bp->pdev->dev,
9695 "Cannot map doorbell space, aborting\n");
9696 rc = -ENOMEM;
9697 goto err_out_unmap;
9698 }
9699
9700 bnx2x_set_power_state(bp, PCI_D0);
9701
9702 /* clean indirect addresses */
9703 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9704 PCICFG_VENDOR_ID_OFFSET);
9705 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9706 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9707 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9708 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9709
9710 /**
9711 * Enable internal target-read (in case we are probed after PF FLR).
9712 * Must be done prior to any BAR read access
9713 */
9714 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
9715
9716 /* Reset the load counter */
9717 bnx2x_clear_load_cnt(bp);
9718
9719 dev->watchdog_timeo = TX_TIMEOUT;
9720
9721 dev->netdev_ops = &bnx2x_netdev_ops;
9722 bnx2x_set_ethtool_ops(dev);
9723
9724 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9725 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9726 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9727
9728 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9729 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9730
9731 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
9732 if (bp->flags & USING_DAC_FLAG)
9733 dev->features |= NETIF_F_HIGHDMA;
9734
9735 /* Add Loopback capability to the device */
9736 dev->hw_features |= NETIF_F_LOOPBACK;
9737
9738 #ifdef BCM_DCBNL
9739 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9740 #endif
9741
9742 /* get_port_hwinfo() will set prtad and mmds properly */
9743 bp->mdio.prtad = MDIO_PRTAD_NONE;
9744 bp->mdio.mmds = 0;
9745 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9746 bp->mdio.dev = dev;
9747 bp->mdio.mdio_read = bnx2x_mdio_read;
9748 bp->mdio.mdio_write = bnx2x_mdio_write;
9749
9750 return 0;
9751
9752 err_out_unmap:
9753 if (bp->regview) {
9754 iounmap(bp->regview);
9755 bp->regview = NULL;
9756 }
9757 if (bp->doorbells) {
9758 iounmap(bp->doorbells);
9759 bp->doorbells = NULL;
9760 }
9761
9762 err_out_release:
9763 if (atomic_read(&pdev->enable_cnt) == 1)
9764 pci_release_regions(pdev);
9765
9766 err_out_disable:
9767 pci_disable_device(pdev);
9768 pci_set_drvdata(pdev, NULL);
9769
9770 err_out:
9771 return rc;
9772 }
9773
9774 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9775 int *width, int *speed)
9776 {
9777 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9778
9779 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9780
9781 /* return value of 1=2.5GHz 2=5GHz */
9782 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9783 }
9784
9785 static int bnx2x_check_firmware(struct bnx2x *bp)
9786 {
9787 const struct firmware *firmware = bp->firmware;
9788 struct bnx2x_fw_file_hdr *fw_hdr;
9789 struct bnx2x_fw_file_section *sections;
9790 u32 offset, len, num_ops;
9791 u16 *ops_offsets;
9792 int i;
9793 const u8 *fw_ver;
9794
9795 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9796 return -EINVAL;
9797
9798 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9799 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9800
9801 /* Make sure none of the offsets and sizes make us read beyond
9802 * the end of the firmware data */
9803 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9804 offset = be32_to_cpu(sections[i].offset);
9805 len = be32_to_cpu(sections[i].len);
9806 if (offset + len > firmware->size) {
9807 dev_err(&bp->pdev->dev,
9808 "Section %d length is out of bounds\n", i);
9809 return -EINVAL;
9810 }
9811 }
9812
9813 /* Likewise for the init_ops offsets */
9814 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9815 ops_offsets = (u16 *)(firmware->data + offset);
9816 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9817
9818 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9819 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9820 dev_err(&bp->pdev->dev,
9821 "Section offset %d is out of bounds\n", i);
9822 return -EINVAL;
9823 }
9824 }
9825
9826 /* Check FW version */
9827 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9828 fw_ver = firmware->data + offset;
9829 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9830 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9831 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9832 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9833 dev_err(&bp->pdev->dev,
9834 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9835 fw_ver[0], fw_ver[1], fw_ver[2],
9836 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9837 BCM_5710_FW_MINOR_VERSION,
9838 BCM_5710_FW_REVISION_VERSION,
9839 BCM_5710_FW_ENGINEERING_VERSION);
9840 return -EINVAL;
9841 }
9842
9843 return 0;
9844 }
9845
9846 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9847 {
9848 const __be32 *source = (const __be32 *)_source;
9849 u32 *target = (u32 *)_target;
9850 u32 i;
9851
9852 for (i = 0; i < n/4; i++)
9853 target[i] = be32_to_cpu(source[i]);
9854 }
9855
9856 /*
9857 Ops array is stored in the following format:
9858 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9859 */
9860 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9861 {
9862 const __be32 *source = (const __be32 *)_source;
9863 struct raw_op *target = (struct raw_op *)_target;
9864 u32 i, j, tmp;
9865
9866 for (i = 0, j = 0; i < n/8; i++, j += 2) {
9867 tmp = be32_to_cpu(source[j]);
9868 target[i].op = (tmp >> 24) & 0xff;
9869 target[i].offset = tmp & 0xffffff;
9870 target[i].raw_data = be32_to_cpu(source[j + 1]);
9871 }
9872 }
9873
9874 /**
9875 * IRO array is stored in the following format:
9876 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9877 */
9878 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9879 {
9880 const __be32 *source = (const __be32 *)_source;
9881 struct iro *target = (struct iro *)_target;
9882 u32 i, j, tmp;
9883
9884 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9885 target[i].base = be32_to_cpu(source[j]);
9886 j++;
9887 tmp = be32_to_cpu(source[j]);
9888 target[i].m1 = (tmp >> 16) & 0xffff;
9889 target[i].m2 = tmp & 0xffff;
9890 j++;
9891 tmp = be32_to_cpu(source[j]);
9892 target[i].m3 = (tmp >> 16) & 0xffff;
9893 target[i].size = tmp & 0xffff;
9894 j++;
9895 }
9896 }
9897
9898 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9899 {
9900 const __be16 *source = (const __be16 *)_source;
9901 u16 *target = (u16 *)_target;
9902 u32 i;
9903
9904 for (i = 0; i < n/2; i++)
9905 target[i] = be16_to_cpu(source[i]);
9906 }
9907
9908 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9909 do { \
9910 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9911 bp->arr = kmalloc(len, GFP_KERNEL); \
9912 if (!bp->arr) { \
9913 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9914 goto lbl; \
9915 } \
9916 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9917 (u8 *)bp->arr, len); \
9918 } while (0)
9919
9920 int bnx2x_init_firmware(struct bnx2x *bp)
9921 {
9922 const char *fw_file_name;
9923 struct bnx2x_fw_file_hdr *fw_hdr;
9924 int rc;
9925
9926 if (CHIP_IS_E1(bp))
9927 fw_file_name = FW_FILE_NAME_E1;
9928 else if (CHIP_IS_E1H(bp))
9929 fw_file_name = FW_FILE_NAME_E1H;
9930 else if (!CHIP_IS_E1x(bp))
9931 fw_file_name = FW_FILE_NAME_E2;
9932 else {
9933 BNX2X_ERR("Unsupported chip revision\n");
9934 return -EINVAL;
9935 }
9936
9937 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9938
9939 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9940 if (rc) {
9941 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9942 goto request_firmware_exit;
9943 }
9944
9945 rc = bnx2x_check_firmware(bp);
9946 if (rc) {
9947 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9948 goto request_firmware_exit;
9949 }
9950
9951 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9952
9953 /* Initialize the pointers to the init arrays */
9954 /* Blob */
9955 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9956
9957 /* Opcodes */
9958 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9959
9960 /* Offsets */
9961 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9962 be16_to_cpu_n);
9963
9964 /* STORMs firmware */
9965 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9966 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9967 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9968 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9969 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9970 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9971 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9972 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9973 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9974 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9975 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9976 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9977 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9978 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9979 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9980 be32_to_cpu(fw_hdr->csem_pram_data.offset);
9981 /* IRO */
9982 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
9983
9984 return 0;
9985
9986 iro_alloc_err:
9987 kfree(bp->init_ops_offsets);
9988 init_offsets_alloc_err:
9989 kfree(bp->init_ops);
9990 init_ops_alloc_err:
9991 kfree(bp->init_data);
9992 request_firmware_exit:
9993 release_firmware(bp->firmware);
9994
9995 return rc;
9996 }
9997
9998 static void bnx2x_release_firmware(struct bnx2x *bp)
9999 {
10000 kfree(bp->init_ops_offsets);
10001 kfree(bp->init_ops);
10002 kfree(bp->init_data);
10003 release_firmware(bp->firmware);
10004 }
10005
10006
10007 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10008 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10009 .init_hw_cmn = bnx2x_init_hw_common,
10010 .init_hw_port = bnx2x_init_hw_port,
10011 .init_hw_func = bnx2x_init_hw_func,
10012
10013 .reset_hw_cmn = bnx2x_reset_common,
10014 .reset_hw_port = bnx2x_reset_port,
10015 .reset_hw_func = bnx2x_reset_func,
10016
10017 .gunzip_init = bnx2x_gunzip_init,
10018 .gunzip_end = bnx2x_gunzip_end,
10019
10020 .init_fw = bnx2x_init_firmware,
10021 .release_fw = bnx2x_release_firmware,
10022 };
10023
10024 void bnx2x__init_func_obj(struct bnx2x *bp)
10025 {
10026 /* Prepare DMAE related driver resources */
10027 bnx2x_setup_dmae(bp);
10028
10029 bnx2x_init_func_obj(bp, &bp->func_obj,
10030 bnx2x_sp(bp, func_rdata),
10031 bnx2x_sp_mapping(bp, func_rdata),
10032 &bnx2x_func_sp_drv);
10033 }
10034
10035 /* must be called after sriov-enable */
10036 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
10037 {
10038 int cid_count = L2_FP_COUNT(l2_cid_count);
10039
10040 #ifdef BCM_CNIC
10041 cid_count += CNIC_CID_MAX;
10042 #endif
10043 return roundup(cid_count, QM_CID_ROUND);
10044 }
10045
10046 /**
10047 * bnx2x_pci_msix_table_size - get the size of the MSI-X table.
10048 *
10049 * @dev: pci device
10050 *
10051 */
10052 static inline int bnx2x_pci_msix_table_size(struct pci_dev *pdev)
10053 {
10054 int pos;
10055 u16 control;
10056
10057 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10058 if (!pos)
10059 return 0;
10060
10061 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10062 return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
10063 }
10064
10065 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10066 const struct pci_device_id *ent)
10067 {
10068 struct net_device *dev = NULL;
10069 struct bnx2x *bp;
10070 int pcie_width, pcie_speed;
10071 int rc, cid_count;
10072
10073 switch (ent->driver_data) {
10074 case BCM57710:
10075 case BCM57711:
10076 case BCM57711E:
10077 case BCM57712:
10078 case BCM57712_MF:
10079 case BCM57800:
10080 case BCM57800_MF:
10081 case BCM57810:
10082 case BCM57810_MF:
10083 case BCM57840:
10084 case BCM57840_MF:
10085 /* The size requested for the MSI-X table corresponds to the
10086 * actual amount of avaliable IGU/HC status blocks. It includes
10087 * the default SB vector but we want cid_count to contain the
10088 * amount of only non-default SBs, that's what '-1' stands for.
10089 */
10090 cid_count = bnx2x_pci_msix_table_size(pdev) - 1;
10091
10092 /* do not allow initial cid_count grow above 16
10093 * since Special CIDs starts from this number
10094 * use old FP_SB_MAX_E1x define for this matter
10095 */
10096 cid_count = min_t(int, FP_SB_MAX_E1x, cid_count);
10097
10098 WARN_ON(!cid_count);
10099 break;
10100
10101 default:
10102 pr_err("Unknown board_type (%ld), aborting\n",
10103 ent->driver_data);
10104 return -ENODEV;
10105 }
10106
10107 cid_count += FCOE_CONTEXT_USE;
10108
10109 /* dev zeroed in init_etherdev */
10110 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
10111 if (!dev) {
10112 dev_err(&pdev->dev, "Cannot allocate net device\n");
10113 return -ENOMEM;
10114 }
10115
10116 /* We don't need a Tx queue for a CNIC and an OOO Rx-only ring,
10117 * so update a cid_count after a netdev allocation.
10118 */
10119 cid_count += CNIC_CONTEXT_USE;
10120
10121 bp = netdev_priv(dev);
10122 bp->msg_enable = debug;
10123
10124 pci_set_drvdata(pdev, dev);
10125
10126 bp->l2_cid_count = cid_count;
10127
10128 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10129 if (rc < 0) {
10130 free_netdev(dev);
10131 return rc;
10132 }
10133
10134 BNX2X_DEV_INFO("cid_count=%d\n", cid_count);
10135
10136 rc = bnx2x_init_bp(bp);
10137 if (rc)
10138 goto init_one_exit;
10139
10140 /* calc qm_cid_count */
10141 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
10142
10143 #ifdef BCM_CNIC
10144 /* disable FCOE L2 queue for E1x*/
10145 if (CHIP_IS_E1x(bp))
10146 bp->flags |= NO_FCOE_FLAG;
10147
10148 #endif
10149
10150 /* Configure interrupt mode: try to enable MSI-X/MSI if
10151 * needed, set bp->num_queues appropriately.
10152 */
10153 bnx2x_set_int_mode(bp);
10154
10155 /* Add all NAPI objects */
10156 bnx2x_add_all_napi(bp);
10157
10158 rc = register_netdev(dev);
10159 if (rc) {
10160 dev_err(&pdev->dev, "Cannot register net device\n");
10161 goto init_one_exit;
10162 }
10163
10164 #ifdef BCM_CNIC
10165 if (!NO_FCOE(bp)) {
10166 /* Add storage MAC address */
10167 rtnl_lock();
10168 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10169 rtnl_unlock();
10170 }
10171 #endif
10172
10173 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10174
10175 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10176 " IRQ %d, ", board_info[ent->driver_data].name,
10177 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10178 pcie_width,
10179 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10180 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10181 "5GHz (Gen2)" : "2.5GHz",
10182 dev->base_addr, bp->pdev->irq);
10183 pr_cont("node addr %pM\n", dev->dev_addr);
10184
10185 return 0;
10186
10187 init_one_exit:
10188 if (bp->regview)
10189 iounmap(bp->regview);
10190
10191 if (bp->doorbells)
10192 iounmap(bp->doorbells);
10193
10194 free_netdev(dev);
10195
10196 if (atomic_read(&pdev->enable_cnt) == 1)
10197 pci_release_regions(pdev);
10198
10199 pci_disable_device(pdev);
10200 pci_set_drvdata(pdev, NULL);
10201
10202 return rc;
10203 }
10204
10205 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10206 {
10207 struct net_device *dev = pci_get_drvdata(pdev);
10208 struct bnx2x *bp;
10209
10210 if (!dev) {
10211 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10212 return;
10213 }
10214 bp = netdev_priv(dev);
10215
10216 #ifdef BCM_CNIC
10217 /* Delete storage MAC address */
10218 if (!NO_FCOE(bp)) {
10219 rtnl_lock();
10220 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10221 rtnl_unlock();
10222 }
10223 #endif
10224
10225 #ifdef BCM_DCBNL
10226 /* Delete app tlvs from dcbnl */
10227 bnx2x_dcbnl_update_applist(bp, true);
10228 #endif
10229
10230 unregister_netdev(dev);
10231
10232 /* Delete all NAPI objects */
10233 bnx2x_del_all_napi(bp);
10234
10235 /* Power on: we can't let PCI layer write to us while we are in D3 */
10236 bnx2x_set_power_state(bp, PCI_D0);
10237
10238 /* Disable MSI/MSI-X */
10239 bnx2x_disable_msi(bp);
10240
10241 /* Power off */
10242 bnx2x_set_power_state(bp, PCI_D3hot);
10243
10244 /* Make sure RESET task is not scheduled before continuing */
10245 cancel_delayed_work_sync(&bp->reset_task);
10246
10247 if (bp->regview)
10248 iounmap(bp->regview);
10249
10250 if (bp->doorbells)
10251 iounmap(bp->doorbells);
10252
10253 bnx2x_free_mem_bp(bp);
10254
10255 free_netdev(dev);
10256
10257 if (atomic_read(&pdev->enable_cnt) == 1)
10258 pci_release_regions(pdev);
10259
10260 pci_disable_device(pdev);
10261 pci_set_drvdata(pdev, NULL);
10262 }
10263
10264 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10265 {
10266 int i;
10267
10268 bp->state = BNX2X_STATE_ERROR;
10269
10270 bp->rx_mode = BNX2X_RX_MODE_NONE;
10271
10272 #ifdef BCM_CNIC
10273 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10274 #endif
10275 /* Stop Tx */
10276 bnx2x_tx_disable(bp);
10277
10278 bnx2x_netif_stop(bp, 0);
10279
10280 del_timer_sync(&bp->timer);
10281
10282 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10283
10284 /* Release IRQs */
10285 bnx2x_free_irq(bp);
10286
10287 /* Free SKBs, SGEs, TPA pool and driver internals */
10288 bnx2x_free_skbs(bp);
10289
10290 for_each_rx_queue(bp, i)
10291 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10292
10293 bnx2x_free_mem(bp);
10294
10295 bp->state = BNX2X_STATE_CLOSED;
10296
10297 netif_carrier_off(bp->dev);
10298
10299 return 0;
10300 }
10301
10302 static void bnx2x_eeh_recover(struct bnx2x *bp)
10303 {
10304 u32 val;
10305
10306 mutex_init(&bp->port.phy_mutex);
10307
10308 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10309 bp->link_params.shmem_base = bp->common.shmem_base;
10310 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10311
10312 if (!bp->common.shmem_base ||
10313 (bp->common.shmem_base < 0xA0000) ||
10314 (bp->common.shmem_base >= 0xC0000)) {
10315 BNX2X_DEV_INFO("MCP not active\n");
10316 bp->flags |= NO_MCP_FLAG;
10317 return;
10318 }
10319
10320 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10321 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10322 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10323 BNX2X_ERR("BAD MCP validity signature\n");
10324
10325 if (!BP_NOMCP(bp)) {
10326 bp->fw_seq =
10327 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10328 DRV_MSG_SEQ_NUMBER_MASK);
10329 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10330 }
10331 }
10332
10333 /**
10334 * bnx2x_io_error_detected - called when PCI error is detected
10335 * @pdev: Pointer to PCI device
10336 * @state: The current pci connection state
10337 *
10338 * This function is called after a PCI bus error affecting
10339 * this device has been detected.
10340 */
10341 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10342 pci_channel_state_t state)
10343 {
10344 struct net_device *dev = pci_get_drvdata(pdev);
10345 struct bnx2x *bp = netdev_priv(dev);
10346
10347 rtnl_lock();
10348
10349 netif_device_detach(dev);
10350
10351 if (state == pci_channel_io_perm_failure) {
10352 rtnl_unlock();
10353 return PCI_ERS_RESULT_DISCONNECT;
10354 }
10355
10356 if (netif_running(dev))
10357 bnx2x_eeh_nic_unload(bp);
10358
10359 pci_disable_device(pdev);
10360
10361 rtnl_unlock();
10362
10363 /* Request a slot reset */
10364 return PCI_ERS_RESULT_NEED_RESET;
10365 }
10366
10367 /**
10368 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10369 * @pdev: Pointer to PCI device
10370 *
10371 * Restart the card from scratch, as if from a cold-boot.
10372 */
10373 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10374 {
10375 struct net_device *dev = pci_get_drvdata(pdev);
10376 struct bnx2x *bp = netdev_priv(dev);
10377
10378 rtnl_lock();
10379
10380 if (pci_enable_device(pdev)) {
10381 dev_err(&pdev->dev,
10382 "Cannot re-enable PCI device after reset\n");
10383 rtnl_unlock();
10384 return PCI_ERS_RESULT_DISCONNECT;
10385 }
10386
10387 pci_set_master(pdev);
10388 pci_restore_state(pdev);
10389
10390 if (netif_running(dev))
10391 bnx2x_set_power_state(bp, PCI_D0);
10392
10393 rtnl_unlock();
10394
10395 return PCI_ERS_RESULT_RECOVERED;
10396 }
10397
10398 /**
10399 * bnx2x_io_resume - called when traffic can start flowing again
10400 * @pdev: Pointer to PCI device
10401 *
10402 * This callback is called when the error recovery driver tells us that
10403 * its OK to resume normal operation.
10404 */
10405 static void bnx2x_io_resume(struct pci_dev *pdev)
10406 {
10407 struct net_device *dev = pci_get_drvdata(pdev);
10408 struct bnx2x *bp = netdev_priv(dev);
10409
10410 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10411 netdev_err(bp->dev, "Handling parity error recovery. "
10412 "Try again later\n");
10413 return;
10414 }
10415
10416 rtnl_lock();
10417
10418 bnx2x_eeh_recover(bp);
10419
10420 if (netif_running(dev))
10421 bnx2x_nic_load(bp, LOAD_NORMAL);
10422
10423 netif_device_attach(dev);
10424
10425 rtnl_unlock();
10426 }
10427
10428 static struct pci_error_handlers bnx2x_err_handler = {
10429 .error_detected = bnx2x_io_error_detected,
10430 .slot_reset = bnx2x_io_slot_reset,
10431 .resume = bnx2x_io_resume,
10432 };
10433
10434 static struct pci_driver bnx2x_pci_driver = {
10435 .name = DRV_MODULE_NAME,
10436 .id_table = bnx2x_pci_tbl,
10437 .probe = bnx2x_init_one,
10438 .remove = __devexit_p(bnx2x_remove_one),
10439 .suspend = bnx2x_suspend,
10440 .resume = bnx2x_resume,
10441 .err_handler = &bnx2x_err_handler,
10442 };
10443
10444 static int __init bnx2x_init(void)
10445 {
10446 int ret;
10447
10448 pr_info("%s", version);
10449
10450 bnx2x_wq = create_singlethread_workqueue("bnx2x");
10451 if (bnx2x_wq == NULL) {
10452 pr_err("Cannot create workqueue\n");
10453 return -ENOMEM;
10454 }
10455
10456 ret = pci_register_driver(&bnx2x_pci_driver);
10457 if (ret) {
10458 pr_err("Cannot register driver\n");
10459 destroy_workqueue(bnx2x_wq);
10460 }
10461 return ret;
10462 }
10463
10464 static void __exit bnx2x_cleanup(void)
10465 {
10466 pci_unregister_driver(&bnx2x_pci_driver);
10467
10468 destroy_workqueue(bnx2x_wq);
10469 }
10470
10471 module_init(bnx2x_init);
10472 module_exit(bnx2x_cleanup);
10473
10474 #ifdef BCM_CNIC
10475 /**
10476 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
10477 *
10478 * @bp: driver handle
10479 * @set: set or clear the CAM entry
10480 *
10481 * This function will wait until the ramdord completion returns.
10482 * Return 0 if success, -ENODEV if ramrod doesn't return.
10483 */
10484 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
10485 {
10486 unsigned long ramrod_flags = 0;
10487
10488 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
10489 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
10490 &bp->iscsi_l2_mac_obj, true,
10491 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
10492 }
10493
10494 /* count denotes the number of new completions we have seen */
10495 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
10496 {
10497 struct eth_spe *spe;
10498
10499 #ifdef BNX2X_STOP_ON_ERROR
10500 if (unlikely(bp->panic))
10501 return;
10502 #endif
10503
10504 spin_lock_bh(&bp->spq_lock);
10505 BUG_ON(bp->cnic_spq_pending < count);
10506 bp->cnic_spq_pending -= count;
10507
10508
10509 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
10510 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
10511 & SPE_HDR_CONN_TYPE) >>
10512 SPE_HDR_CONN_TYPE_SHIFT;
10513 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
10514 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
10515
10516 /* Set validation for iSCSI L2 client before sending SETUP
10517 * ramrod
10518 */
10519 if (type == ETH_CONNECTION_TYPE) {
10520 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
10521 bnx2x_set_ctx_validation(bp, &bp->context.
10522 vcxt[BNX2X_ISCSI_ETH_CID].eth,
10523 BNX2X_ISCSI_ETH_CID);
10524 }
10525
10526 /*
10527 * There may be not more than 8 L2, not more than 8 L5 SPEs
10528 * and in the air. We also check that number of outstanding
10529 * COMMON ramrods is not more than the EQ and SPQ can
10530 * accommodate.
10531 */
10532 if (type == ETH_CONNECTION_TYPE) {
10533 if (!atomic_read(&bp->cq_spq_left))
10534 break;
10535 else
10536 atomic_dec(&bp->cq_spq_left);
10537 } else if (type == NONE_CONNECTION_TYPE) {
10538 if (!atomic_read(&bp->eq_spq_left))
10539 break;
10540 else
10541 atomic_dec(&bp->eq_spq_left);
10542 } else if ((type == ISCSI_CONNECTION_TYPE) ||
10543 (type == FCOE_CONNECTION_TYPE)) {
10544 if (bp->cnic_spq_pending >=
10545 bp->cnic_eth_dev.max_kwqe_pending)
10546 break;
10547 else
10548 bp->cnic_spq_pending++;
10549 } else {
10550 BNX2X_ERR("Unknown SPE type: %d\n", type);
10551 bnx2x_panic();
10552 break;
10553 }
10554
10555 spe = bnx2x_sp_get_next(bp);
10556 *spe = *bp->cnic_kwq_cons;
10557
10558 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
10559 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
10560
10561 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
10562 bp->cnic_kwq_cons = bp->cnic_kwq;
10563 else
10564 bp->cnic_kwq_cons++;
10565 }
10566 bnx2x_sp_prod_update(bp);
10567 spin_unlock_bh(&bp->spq_lock);
10568 }
10569
10570 static int bnx2x_cnic_sp_queue(struct net_device *dev,
10571 struct kwqe_16 *kwqes[], u32 count)
10572 {
10573 struct bnx2x *bp = netdev_priv(dev);
10574 int i;
10575
10576 #ifdef BNX2X_STOP_ON_ERROR
10577 if (unlikely(bp->panic))
10578 return -EIO;
10579 #endif
10580
10581 spin_lock_bh(&bp->spq_lock);
10582
10583 for (i = 0; i < count; i++) {
10584 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10585
10586 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10587 break;
10588
10589 *bp->cnic_kwq_prod = *spe;
10590
10591 bp->cnic_kwq_pending++;
10592
10593 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10594 spe->hdr.conn_and_cmd_data, spe->hdr.type,
10595 spe->data.update_data_addr.hi,
10596 spe->data.update_data_addr.lo,
10597 bp->cnic_kwq_pending);
10598
10599 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10600 bp->cnic_kwq_prod = bp->cnic_kwq;
10601 else
10602 bp->cnic_kwq_prod++;
10603 }
10604
10605 spin_unlock_bh(&bp->spq_lock);
10606
10607 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10608 bnx2x_cnic_sp_post(bp, 0);
10609
10610 return i;
10611 }
10612
10613 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10614 {
10615 struct cnic_ops *c_ops;
10616 int rc = 0;
10617
10618 mutex_lock(&bp->cnic_mutex);
10619 c_ops = rcu_dereference_protected(bp->cnic_ops,
10620 lockdep_is_held(&bp->cnic_mutex));
10621 if (c_ops)
10622 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10623 mutex_unlock(&bp->cnic_mutex);
10624
10625 return rc;
10626 }
10627
10628 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10629 {
10630 struct cnic_ops *c_ops;
10631 int rc = 0;
10632
10633 rcu_read_lock();
10634 c_ops = rcu_dereference(bp->cnic_ops);
10635 if (c_ops)
10636 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10637 rcu_read_unlock();
10638
10639 return rc;
10640 }
10641
10642 /*
10643 * for commands that have no data
10644 */
10645 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
10646 {
10647 struct cnic_ctl_info ctl = {0};
10648
10649 ctl.cmd = cmd;
10650
10651 return bnx2x_cnic_ctl_send(bp, &ctl);
10652 }
10653
10654 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
10655 {
10656 struct cnic_ctl_info ctl = {0};
10657
10658 /* first we tell CNIC and only then we count this as a completion */
10659 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10660 ctl.data.comp.cid = cid;
10661 ctl.data.comp.error = err;
10662
10663 bnx2x_cnic_ctl_send_bh(bp, &ctl);
10664 bnx2x_cnic_sp_post(bp, 0);
10665 }
10666
10667
10668 /* Called with netif_addr_lock_bh() taken.
10669 * Sets an rx_mode config for an iSCSI ETH client.
10670 * Doesn't block.
10671 * Completion should be checked outside.
10672 */
10673 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
10674 {
10675 unsigned long accept_flags = 0, ramrod_flags = 0;
10676 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
10677 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
10678
10679 if (start) {
10680 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10681 * because it's the only way for UIO Queue to accept
10682 * multicasts (in non-promiscuous mode only one Queue per
10683 * function will receive multicast packets (leading in our
10684 * case).
10685 */
10686 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
10687 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
10688 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
10689 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
10690
10691 /* Clear STOP_PENDING bit if START is requested */
10692 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
10693
10694 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
10695 } else
10696 /* Clear START_PENDING bit if STOP is requested */
10697 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
10698
10699 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
10700 set_bit(sched_state, &bp->sp_state);
10701 else {
10702 __set_bit(RAMROD_RX, &ramrod_flags);
10703 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
10704 ramrod_flags);
10705 }
10706 }
10707
10708
10709 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10710 {
10711 struct bnx2x *bp = netdev_priv(dev);
10712 int rc = 0;
10713
10714 switch (ctl->cmd) {
10715 case DRV_CTL_CTXTBL_WR_CMD: {
10716 u32 index = ctl->data.io.offset;
10717 dma_addr_t addr = ctl->data.io.dma_addr;
10718
10719 bnx2x_ilt_wr(bp, index, addr);
10720 break;
10721 }
10722
10723 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10724 int count = ctl->data.credit.credit_count;
10725
10726 bnx2x_cnic_sp_post(bp, count);
10727 break;
10728 }
10729
10730 /* rtnl_lock is held. */
10731 case DRV_CTL_START_L2_CMD: {
10732 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10733 unsigned long sp_bits = 0;
10734
10735 /* Configure the iSCSI classification object */
10736 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
10737 cp->iscsi_l2_client_id,
10738 cp->iscsi_l2_cid, BP_FUNC(bp),
10739 bnx2x_sp(bp, mac_rdata),
10740 bnx2x_sp_mapping(bp, mac_rdata),
10741 BNX2X_FILTER_MAC_PENDING,
10742 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
10743 &bp->macs_pool);
10744
10745 /* Set iSCSI MAC address */
10746 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
10747 if (rc)
10748 break;
10749
10750 mmiowb();
10751 barrier();
10752
10753 /* Start accepting on iSCSI L2 ring */
10754
10755 netif_addr_lock_bh(dev);
10756 bnx2x_set_iscsi_eth_rx_mode(bp, true);
10757 netif_addr_unlock_bh(dev);
10758
10759 /* bits to wait on */
10760 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
10761 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
10762
10763 if (!bnx2x_wait_sp_comp(bp, sp_bits))
10764 BNX2X_ERR("rx_mode completion timed out!\n");
10765
10766 break;
10767 }
10768
10769 /* rtnl_lock is held. */
10770 case DRV_CTL_STOP_L2_CMD: {
10771 unsigned long sp_bits = 0;
10772
10773 /* Stop accepting on iSCSI L2 ring */
10774 netif_addr_lock_bh(dev);
10775 bnx2x_set_iscsi_eth_rx_mode(bp, false);
10776 netif_addr_unlock_bh(dev);
10777
10778 /* bits to wait on */
10779 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
10780 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
10781
10782 if (!bnx2x_wait_sp_comp(bp, sp_bits))
10783 BNX2X_ERR("rx_mode completion timed out!\n");
10784
10785 mmiowb();
10786 barrier();
10787
10788 /* Unset iSCSI L2 MAC */
10789 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
10790 BNX2X_ISCSI_ETH_MAC, true);
10791 break;
10792 }
10793 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10794 int count = ctl->data.credit.credit_count;
10795
10796 smp_mb__before_atomic_inc();
10797 atomic_add(count, &bp->cq_spq_left);
10798 smp_mb__after_atomic_inc();
10799 break;
10800 }
10801
10802 default:
10803 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10804 rc = -EINVAL;
10805 }
10806
10807 return rc;
10808 }
10809
10810 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
10811 {
10812 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10813
10814 if (bp->flags & USING_MSIX_FLAG) {
10815 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10816 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10817 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10818 } else {
10819 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10820 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10821 }
10822 if (!CHIP_IS_E1x(bp))
10823 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10824 else
10825 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10826
10827 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
10828 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
10829 cp->irq_arr[1].status_blk = bp->def_status_blk;
10830 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10831 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10832
10833 cp->num_irq = 2;
10834 }
10835
10836 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10837 void *data)
10838 {
10839 struct bnx2x *bp = netdev_priv(dev);
10840 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10841
10842 if (ops == NULL)
10843 return -EINVAL;
10844
10845 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10846 if (!bp->cnic_kwq)
10847 return -ENOMEM;
10848
10849 bp->cnic_kwq_cons = bp->cnic_kwq;
10850 bp->cnic_kwq_prod = bp->cnic_kwq;
10851 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10852
10853 bp->cnic_spq_pending = 0;
10854 bp->cnic_kwq_pending = 0;
10855
10856 bp->cnic_data = data;
10857
10858 cp->num_irq = 0;
10859 cp->drv_state |= CNIC_DRV_STATE_REGD;
10860 cp->iro_arr = bp->iro_arr;
10861
10862 bnx2x_setup_cnic_irq_info(bp);
10863
10864 rcu_assign_pointer(bp->cnic_ops, ops);
10865
10866 return 0;
10867 }
10868
10869 static int bnx2x_unregister_cnic(struct net_device *dev)
10870 {
10871 struct bnx2x *bp = netdev_priv(dev);
10872 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10873
10874 mutex_lock(&bp->cnic_mutex);
10875 cp->drv_state = 0;
10876 rcu_assign_pointer(bp->cnic_ops, NULL);
10877 mutex_unlock(&bp->cnic_mutex);
10878 synchronize_rcu();
10879 kfree(bp->cnic_kwq);
10880 bp->cnic_kwq = NULL;
10881
10882 return 0;
10883 }
10884
10885 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10886 {
10887 struct bnx2x *bp = netdev_priv(dev);
10888 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10889
10890 /* If both iSCSI and FCoE are disabled - return NULL in
10891 * order to indicate CNIC that it should not try to work
10892 * with this device.
10893 */
10894 if (NO_ISCSI(bp) && NO_FCOE(bp))
10895 return NULL;
10896
10897 cp->drv_owner = THIS_MODULE;
10898 cp->chip_id = CHIP_ID(bp);
10899 cp->pdev = bp->pdev;
10900 cp->io_base = bp->regview;
10901 cp->io_base2 = bp->doorbells;
10902 cp->max_kwqe_pending = 8;
10903 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10904 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10905 bnx2x_cid_ilt_lines(bp);
10906 cp->ctx_tbl_len = CNIC_ILT_LINES;
10907 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10908 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10909 cp->drv_ctl = bnx2x_drv_ctl;
10910 cp->drv_register_cnic = bnx2x_register_cnic;
10911 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10912 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10913 cp->iscsi_l2_client_id =
10914 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
10915 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10916
10917 if (NO_ISCSI_OOO(bp))
10918 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10919
10920 if (NO_ISCSI(bp))
10921 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10922
10923 if (NO_FCOE(bp))
10924 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10925
10926 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10927 "starting cid %d\n",
10928 cp->ctx_blk_size,
10929 cp->ctx_tbl_offset,
10930 cp->ctx_tbl_len,
10931 cp->starting_cid);
10932 return cp;
10933 }
10934 EXPORT_SYMBOL(bnx2x_cnic_probe);
10935
10936 #endif /* BCM_CNIC */
10937
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