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[mirror_ubuntu-bionic-kernel.git] / drivers / net / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
41 #include <net/ip.h>
42 #include <net/tcp.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/crc32c.h>
48 #include <linux/prefetch.h>
49 #include <linux/zlib.h>
50 #include <linux/io.h>
51 #include <linux/stringify.h>
52
53 #define BNX2X_MAIN
54 #include "bnx2x.h"
55 #include "bnx2x_init.h"
56 #include "bnx2x_init_ops.h"
57 #include "bnx2x_cmn.h"
58 #include "bnx2x_dcb.h"
59
60 #include <linux/firmware.h>
61 #include "bnx2x_fw_file_hdr.h"
62 /* FW files */
63 #define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
68 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
70 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
71
72 /* Time in jiffies before concluding the transmitter is hung */
73 #define TX_TIMEOUT (5*HZ)
74
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78
79 MODULE_AUTHOR("Eliezer Tamir");
80 MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
84 MODULE_FIRMWARE(FW_FILE_NAME_E1);
85 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
86 MODULE_FIRMWARE(FW_FILE_NAME_E2);
87
88 static int multi_mode = 1;
89 module_param(multi_mode, int, 0);
90 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
92
93 int num_queues;
94 module_param(num_queues, int, 0);
95 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
97
98 static int disable_tpa;
99 module_param(disable_tpa, int, 0);
100 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
101
102 static int int_mode;
103 module_param(int_mode, int, 0);
104 MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
105 "(1 INT#x; 2 MSI)");
106
107 static int dropless_fc;
108 module_param(dropless_fc, int, 0);
109 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
111 static int poll;
112 module_param(poll, int, 0);
113 MODULE_PARM_DESC(poll, " Use polling (for debug)");
114
115 static int mrrs = -1;
116 module_param(mrrs, int, 0);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
119 static int debug;
120 module_param(debug, int, 0);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
122
123 static struct workqueue_struct *bnx2x_wq;
124
125 #ifdef BCM_CNIC
126 static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
127 #endif
128
129 enum bnx2x_board_type {
130 BCM57710 = 0,
131 BCM57711 = 1,
132 BCM57711E = 2,
133 BCM57712 = 3,
134 BCM57712E = 4
135 };
136
137 /* indexed by board_type, above */
138 static struct {
139 char *name;
140 } board_info[] __devinitdata = {
141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
146 };
147
148 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
149 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
150 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
151 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
152 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
153 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
154 { 0 }
155 };
156
157 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
158
159 /****************************************************************************
160 * General service functions
161 ****************************************************************************/
162
163 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
164 u32 addr, dma_addr_t mapping)
165 {
166 REG_WR(bp, addr, U64_LO(mapping));
167 REG_WR(bp, addr + 4, U64_HI(mapping));
168 }
169
170 static inline void __storm_memset_fill(struct bnx2x *bp,
171 u32 addr, size_t size, u32 val)
172 {
173 int i;
174 for (i = 0; i < size/4; i++)
175 REG_WR(bp, addr + (i * 4), val);
176 }
177
178 static inline void storm_memset_ustats_zero(struct bnx2x *bp,
179 u8 port, u16 stat_id)
180 {
181 size_t size = sizeof(struct ustorm_per_client_stats);
182
183 u32 addr = BAR_USTRORM_INTMEM +
184 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
185
186 __storm_memset_fill(bp, addr, size, 0);
187 }
188
189 static inline void storm_memset_tstats_zero(struct bnx2x *bp,
190 u8 port, u16 stat_id)
191 {
192 size_t size = sizeof(struct tstorm_per_client_stats);
193
194 u32 addr = BAR_TSTRORM_INTMEM +
195 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
196
197 __storm_memset_fill(bp, addr, size, 0);
198 }
199
200 static inline void storm_memset_xstats_zero(struct bnx2x *bp,
201 u8 port, u16 stat_id)
202 {
203 size_t size = sizeof(struct xstorm_per_client_stats);
204
205 u32 addr = BAR_XSTRORM_INTMEM +
206 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
207
208 __storm_memset_fill(bp, addr, size, 0);
209 }
210
211
212 static inline void storm_memset_spq_addr(struct bnx2x *bp,
213 dma_addr_t mapping, u16 abs_fid)
214 {
215 u32 addr = XSEM_REG_FAST_MEMORY +
216 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
217
218 __storm_memset_dma_mapping(bp, addr, mapping);
219 }
220
221 static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
222 {
223 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
224 }
225
226 static inline void storm_memset_func_cfg(struct bnx2x *bp,
227 struct tstorm_eth_function_common_config *tcfg,
228 u16 abs_fid)
229 {
230 size_t size = sizeof(struct tstorm_eth_function_common_config);
231
232 u32 addr = BAR_TSTRORM_INTMEM +
233 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
234
235 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
236 }
237
238 static inline void storm_memset_xstats_flags(struct bnx2x *bp,
239 struct stats_indication_flags *flags,
240 u16 abs_fid)
241 {
242 size_t size = sizeof(struct stats_indication_flags);
243
244 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
245
246 __storm_memset_struct(bp, addr, size, (u32 *)flags);
247 }
248
249 static inline void storm_memset_tstats_flags(struct bnx2x *bp,
250 struct stats_indication_flags *flags,
251 u16 abs_fid)
252 {
253 size_t size = sizeof(struct stats_indication_flags);
254
255 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
256
257 __storm_memset_struct(bp, addr, size, (u32 *)flags);
258 }
259
260 static inline void storm_memset_ustats_flags(struct bnx2x *bp,
261 struct stats_indication_flags *flags,
262 u16 abs_fid)
263 {
264 size_t size = sizeof(struct stats_indication_flags);
265
266 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)flags);
269 }
270
271 static inline void storm_memset_cstats_flags(struct bnx2x *bp,
272 struct stats_indication_flags *flags,
273 u16 abs_fid)
274 {
275 size_t size = sizeof(struct stats_indication_flags);
276
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
278
279 __storm_memset_struct(bp, addr, size, (u32 *)flags);
280 }
281
282 static inline void storm_memset_xstats_addr(struct bnx2x *bp,
283 dma_addr_t mapping, u16 abs_fid)
284 {
285 u32 addr = BAR_XSTRORM_INTMEM +
286 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
287
288 __storm_memset_dma_mapping(bp, addr, mapping);
289 }
290
291 static inline void storm_memset_tstats_addr(struct bnx2x *bp,
292 dma_addr_t mapping, u16 abs_fid)
293 {
294 u32 addr = BAR_TSTRORM_INTMEM +
295 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
296
297 __storm_memset_dma_mapping(bp, addr, mapping);
298 }
299
300 static inline void storm_memset_ustats_addr(struct bnx2x *bp,
301 dma_addr_t mapping, u16 abs_fid)
302 {
303 u32 addr = BAR_USTRORM_INTMEM +
304 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
305
306 __storm_memset_dma_mapping(bp, addr, mapping);
307 }
308
309 static inline void storm_memset_cstats_addr(struct bnx2x *bp,
310 dma_addr_t mapping, u16 abs_fid)
311 {
312 u32 addr = BAR_CSTRORM_INTMEM +
313 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
314
315 __storm_memset_dma_mapping(bp, addr, mapping);
316 }
317
318 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
319 u16 pf_id)
320 {
321 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
322 pf_id);
323 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
324 pf_id);
325 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
326 pf_id);
327 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
328 pf_id);
329 }
330
331 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
332 u8 enable)
333 {
334 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
335 enable);
336 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
337 enable);
338 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
339 enable);
340 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
341 enable);
342 }
343
344 static inline void storm_memset_eq_data(struct bnx2x *bp,
345 struct event_ring_data *eq_data,
346 u16 pfid)
347 {
348 size_t size = sizeof(struct event_ring_data);
349
350 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
351
352 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
353 }
354
355 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
356 u16 pfid)
357 {
358 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
359 REG_WR16(bp, addr, eq_prod);
360 }
361
362 static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
363 u16 fw_sb_id, u8 sb_index,
364 u8 ticks)
365 {
366
367 int index_offset = CHIP_IS_E2(bp) ?
368 offsetof(struct hc_status_block_data_e2, index_data) :
369 offsetof(struct hc_status_block_data_e1x, index_data);
370 u32 addr = BAR_CSTRORM_INTMEM +
371 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
372 index_offset +
373 sizeof(struct hc_index_data)*sb_index +
374 offsetof(struct hc_index_data, timeout);
375 REG_WR8(bp, addr, ticks);
376 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
377 port, fw_sb_id, sb_index, ticks);
378 }
379 static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
380 u16 fw_sb_id, u8 sb_index,
381 u8 disable)
382 {
383 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
384 int index_offset = CHIP_IS_E2(bp) ?
385 offsetof(struct hc_status_block_data_e2, index_data) :
386 offsetof(struct hc_status_block_data_e1x, index_data);
387 u32 addr = BAR_CSTRORM_INTMEM +
388 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
389 index_offset +
390 sizeof(struct hc_index_data)*sb_index +
391 offsetof(struct hc_index_data, flags);
392 u16 flags = REG_RD16(bp, addr);
393 /* clear and set */
394 flags &= ~HC_INDEX_DATA_HC_ENABLED;
395 flags |= enable_flag;
396 REG_WR16(bp, addr, flags);
397 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
398 port, fw_sb_id, sb_index, disable);
399 }
400
401 /* used only at init
402 * locking is done by mcp
403 */
404 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
405 {
406 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
407 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
408 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
409 PCICFG_VENDOR_ID_OFFSET);
410 }
411
412 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
413 {
414 u32 val;
415
416 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
417 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
418 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
419 PCICFG_VENDOR_ID_OFFSET);
420
421 return val;
422 }
423
424 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
425 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
426 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
427 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
428 #define DMAE_DP_DST_NONE "dst_addr [none]"
429
430 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
431 int msglvl)
432 {
433 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
434
435 switch (dmae->opcode & DMAE_COMMAND_DST) {
436 case DMAE_CMD_DST_PCI:
437 if (src_type == DMAE_CMD_SRC_PCI)
438 DP(msglvl, "DMAE: opcode 0x%08x\n"
439 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
440 "comp_addr [%x:%08x], comp_val 0x%08x\n",
441 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
442 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
443 dmae->comp_addr_hi, dmae->comp_addr_lo,
444 dmae->comp_val);
445 else
446 DP(msglvl, "DMAE: opcode 0x%08x\n"
447 "src [%08x], len [%d*4], dst [%x:%08x]\n"
448 "comp_addr [%x:%08x], comp_val 0x%08x\n",
449 dmae->opcode, dmae->src_addr_lo >> 2,
450 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
451 dmae->comp_addr_hi, dmae->comp_addr_lo,
452 dmae->comp_val);
453 break;
454 case DMAE_CMD_DST_GRC:
455 if (src_type == DMAE_CMD_SRC_PCI)
456 DP(msglvl, "DMAE: opcode 0x%08x\n"
457 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
458 "comp_addr [%x:%08x], comp_val 0x%08x\n",
459 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
460 dmae->len, dmae->dst_addr_lo >> 2,
461 dmae->comp_addr_hi, dmae->comp_addr_lo,
462 dmae->comp_val);
463 else
464 DP(msglvl, "DMAE: opcode 0x%08x\n"
465 "src [%08x], len [%d*4], dst [%08x]\n"
466 "comp_addr [%x:%08x], comp_val 0x%08x\n",
467 dmae->opcode, dmae->src_addr_lo >> 2,
468 dmae->len, dmae->dst_addr_lo >> 2,
469 dmae->comp_addr_hi, dmae->comp_addr_lo,
470 dmae->comp_val);
471 break;
472 default:
473 if (src_type == DMAE_CMD_SRC_PCI)
474 DP(msglvl, "DMAE: opcode 0x%08x\n"
475 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
476 "dst_addr [none]\n"
477 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
478 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
479 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
480 dmae->comp_val);
481 else
482 DP(msglvl, "DMAE: opcode 0x%08x\n"
483 DP_LEVEL "src_addr [%08x] len [%d * 4] "
484 "dst_addr [none]\n"
485 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
486 dmae->opcode, dmae->src_addr_lo >> 2,
487 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
488 dmae->comp_val);
489 break;
490 }
491
492 }
493
494 const u32 dmae_reg_go_c[] = {
495 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
496 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
497 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
498 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
499 };
500
501 /* copy command into DMAE command memory and set DMAE command go */
502 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
503 {
504 u32 cmd_offset;
505 int i;
506
507 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
508 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
509 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
510
511 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
512 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
513 }
514 REG_WR(bp, dmae_reg_go_c[idx], 1);
515 }
516
517 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
518 {
519 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
520 DMAE_CMD_C_ENABLE);
521 }
522
523 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
524 {
525 return opcode & ~DMAE_CMD_SRC_RESET;
526 }
527
528 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
529 bool with_comp, u8 comp_type)
530 {
531 u32 opcode = 0;
532
533 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
534 (dst_type << DMAE_COMMAND_DST_SHIFT));
535
536 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
537
538 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
539 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
540 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
541 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
542
543 #ifdef __BIG_ENDIAN
544 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
545 #else
546 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
547 #endif
548 if (with_comp)
549 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
550 return opcode;
551 }
552
553 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
554 struct dmae_command *dmae,
555 u8 src_type, u8 dst_type)
556 {
557 memset(dmae, 0, sizeof(struct dmae_command));
558
559 /* set the opcode */
560 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
561 true, DMAE_COMP_PCI);
562
563 /* fill in the completion parameters */
564 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
565 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
566 dmae->comp_val = DMAE_COMP_VAL;
567 }
568
569 /* issue a dmae command over the init-channel and wailt for completion */
570 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
571 struct dmae_command *dmae)
572 {
573 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
574 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
575 int rc = 0;
576
577 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
578 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
579 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
580
581 /* lock the dmae channel */
582 spin_lock_bh(&bp->dmae_lock);
583
584 /* reset completion */
585 *wb_comp = 0;
586
587 /* post the command on the channel used for initializations */
588 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
589
590 /* wait for completion */
591 udelay(5);
592 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
593 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
594
595 if (!cnt) {
596 BNX2X_ERR("DMAE timeout!\n");
597 rc = DMAE_TIMEOUT;
598 goto unlock;
599 }
600 cnt--;
601 udelay(50);
602 }
603 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
604 BNX2X_ERR("DMAE PCI error!\n");
605 rc = DMAE_PCI_ERROR;
606 }
607
608 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
609 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
610 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
611
612 unlock:
613 spin_unlock_bh(&bp->dmae_lock);
614 return rc;
615 }
616
617 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
618 u32 len32)
619 {
620 struct dmae_command dmae;
621
622 if (!bp->dmae_ready) {
623 u32 *data = bnx2x_sp(bp, wb_data[0]);
624
625 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
626 " using indirect\n", dst_addr, len32);
627 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
628 return;
629 }
630
631 /* set opcode and fixed command fields */
632 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
633
634 /* fill in addresses and len */
635 dmae.src_addr_lo = U64_LO(dma_addr);
636 dmae.src_addr_hi = U64_HI(dma_addr);
637 dmae.dst_addr_lo = dst_addr >> 2;
638 dmae.dst_addr_hi = 0;
639 dmae.len = len32;
640
641 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
642
643 /* issue the command and wait for completion */
644 bnx2x_issue_dmae_with_comp(bp, &dmae);
645 }
646
647 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
648 {
649 struct dmae_command dmae;
650
651 if (!bp->dmae_ready) {
652 u32 *data = bnx2x_sp(bp, wb_data[0]);
653 int i;
654
655 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
656 " using indirect\n", src_addr, len32);
657 for (i = 0; i < len32; i++)
658 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
659 return;
660 }
661
662 /* set opcode and fixed command fields */
663 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
664
665 /* fill in addresses and len */
666 dmae.src_addr_lo = src_addr >> 2;
667 dmae.src_addr_hi = 0;
668 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
669 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
670 dmae.len = len32;
671
672 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
673
674 /* issue the command and wait for completion */
675 bnx2x_issue_dmae_with_comp(bp, &dmae);
676 }
677
678 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
679 u32 addr, u32 len)
680 {
681 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
682 int offset = 0;
683
684 while (len > dmae_wr_max) {
685 bnx2x_write_dmae(bp, phys_addr + offset,
686 addr + offset, dmae_wr_max);
687 offset += dmae_wr_max * 4;
688 len -= dmae_wr_max;
689 }
690
691 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
692 }
693
694 /* used only for slowpath so not inlined */
695 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
696 {
697 u32 wb_write[2];
698
699 wb_write[0] = val_hi;
700 wb_write[1] = val_lo;
701 REG_WR_DMAE(bp, reg, wb_write, 2);
702 }
703
704 #ifdef USE_WB_RD
705 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
706 {
707 u32 wb_data[2];
708
709 REG_RD_DMAE(bp, reg, wb_data, 2);
710
711 return HILO_U64(wb_data[0], wb_data[1]);
712 }
713 #endif
714
715 static int bnx2x_mc_assert(struct bnx2x *bp)
716 {
717 char last_idx;
718 int i, rc = 0;
719 u32 row0, row1, row2, row3;
720
721 /* XSTORM */
722 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
723 XSTORM_ASSERT_LIST_INDEX_OFFSET);
724 if (last_idx)
725 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
726
727 /* print the asserts */
728 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
729
730 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
731 XSTORM_ASSERT_LIST_OFFSET(i));
732 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
733 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
734 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
735 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
736 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
737 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
738
739 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
740 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
741 " 0x%08x 0x%08x 0x%08x\n",
742 i, row3, row2, row1, row0);
743 rc++;
744 } else {
745 break;
746 }
747 }
748
749 /* TSTORM */
750 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
751 TSTORM_ASSERT_LIST_INDEX_OFFSET);
752 if (last_idx)
753 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
754
755 /* print the asserts */
756 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
757
758 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
759 TSTORM_ASSERT_LIST_OFFSET(i));
760 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
761 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
762 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
763 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
764 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
765 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
766
767 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
768 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
769 " 0x%08x 0x%08x 0x%08x\n",
770 i, row3, row2, row1, row0);
771 rc++;
772 } else {
773 break;
774 }
775 }
776
777 /* CSTORM */
778 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
779 CSTORM_ASSERT_LIST_INDEX_OFFSET);
780 if (last_idx)
781 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
782
783 /* print the asserts */
784 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
785
786 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
787 CSTORM_ASSERT_LIST_OFFSET(i));
788 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
789 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
790 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
791 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
792 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
793 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
794
795 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
796 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
797 " 0x%08x 0x%08x 0x%08x\n",
798 i, row3, row2, row1, row0);
799 rc++;
800 } else {
801 break;
802 }
803 }
804
805 /* USTORM */
806 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
807 USTORM_ASSERT_LIST_INDEX_OFFSET);
808 if (last_idx)
809 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
810
811 /* print the asserts */
812 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
813
814 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
815 USTORM_ASSERT_LIST_OFFSET(i));
816 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
817 USTORM_ASSERT_LIST_OFFSET(i) + 4);
818 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
819 USTORM_ASSERT_LIST_OFFSET(i) + 8);
820 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
821 USTORM_ASSERT_LIST_OFFSET(i) + 12);
822
823 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
824 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
825 " 0x%08x 0x%08x 0x%08x\n",
826 i, row3, row2, row1, row0);
827 rc++;
828 } else {
829 break;
830 }
831 }
832
833 return rc;
834 }
835
836 static void bnx2x_fw_dump(struct bnx2x *bp)
837 {
838 u32 addr;
839 u32 mark, offset;
840 __be32 data[9];
841 int word;
842 u32 trace_shmem_base;
843 if (BP_NOMCP(bp)) {
844 BNX2X_ERR("NO MCP - can not dump\n");
845 return;
846 }
847
848 if (BP_PATH(bp) == 0)
849 trace_shmem_base = bp->common.shmem_base;
850 else
851 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
852 addr = trace_shmem_base - 0x0800 + 4;
853 mark = REG_RD(bp, addr);
854 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
855 + ((mark + 0x3) & ~0x3) - 0x08000000;
856 pr_err("begin fw dump (mark 0x%x)\n", mark);
857
858 pr_err("");
859 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
860 for (word = 0; word < 8; word++)
861 data[word] = htonl(REG_RD(bp, offset + 4*word));
862 data[8] = 0x0;
863 pr_cont("%s", (char *)data);
864 }
865 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
866 for (word = 0; word < 8; word++)
867 data[word] = htonl(REG_RD(bp, offset + 4*word));
868 data[8] = 0x0;
869 pr_cont("%s", (char *)data);
870 }
871 pr_err("end of fw dump\n");
872 }
873
874 void bnx2x_panic_dump(struct bnx2x *bp)
875 {
876 int i;
877 u16 j;
878 struct hc_sp_status_block_data sp_sb_data;
879 int func = BP_FUNC(bp);
880 #ifdef BNX2X_STOP_ON_ERROR
881 u16 start = 0, end = 0;
882 #endif
883
884 bp->stats_state = STATS_STATE_DISABLED;
885 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
886
887 BNX2X_ERR("begin crash dump -----------------\n");
888
889 /* Indices */
890 /* Common */
891 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
892 " spq_prod_idx(0x%x)\n",
893 bp->def_idx, bp->def_att_idx,
894 bp->attn_state, bp->spq_prod_idx);
895 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
896 bp->def_status_blk->atten_status_block.attn_bits,
897 bp->def_status_blk->atten_status_block.attn_bits_ack,
898 bp->def_status_blk->atten_status_block.status_block_id,
899 bp->def_status_blk->atten_status_block.attn_bits_index);
900 BNX2X_ERR(" def (");
901 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
902 pr_cont("0x%x%s",
903 bp->def_status_blk->sp_sb.index_values[i],
904 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
905
906 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
907 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
908 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
909 i*sizeof(u32));
910
911 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
912 "pf_id(0x%x) vnic_id(0x%x) "
913 "vf_id(0x%x) vf_valid (0x%x)\n",
914 sp_sb_data.igu_sb_id,
915 sp_sb_data.igu_seg_id,
916 sp_sb_data.p_func.pf_id,
917 sp_sb_data.p_func.vnic_id,
918 sp_sb_data.p_func.vf_id,
919 sp_sb_data.p_func.vf_valid);
920
921
922 for_each_eth_queue(bp, i) {
923 struct bnx2x_fastpath *fp = &bp->fp[i];
924 int loop;
925 struct hc_status_block_data_e2 sb_data_e2;
926 struct hc_status_block_data_e1x sb_data_e1x;
927 struct hc_status_block_sm *hc_sm_p =
928 CHIP_IS_E2(bp) ?
929 sb_data_e2.common.state_machine :
930 sb_data_e1x.common.state_machine;
931 struct hc_index_data *hc_index_p =
932 CHIP_IS_E2(bp) ?
933 sb_data_e2.index_data :
934 sb_data_e1x.index_data;
935 int data_size;
936 u32 *sb_data_p;
937
938 /* Rx */
939 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
940 " rx_comp_prod(0x%x)"
941 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
942 i, fp->rx_bd_prod, fp->rx_bd_cons,
943 fp->rx_comp_prod,
944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
946 " fp_hc_idx(0x%x)\n",
947 fp->rx_sge_prod, fp->last_max_sge,
948 le16_to_cpu(fp->fp_hc_idx));
949
950 /* Tx */
951 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
952 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
953 " *tx_cons_sb(0x%x)\n",
954 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
955 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
956
957 loop = CHIP_IS_E2(bp) ?
958 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
959
960 /* host sb data */
961
962 #ifdef BCM_CNIC
963 if (IS_FCOE_FP(fp))
964 continue;
965 #endif
966 BNX2X_ERR(" run indexes (");
967 for (j = 0; j < HC_SB_MAX_SM; j++)
968 pr_cont("0x%x%s",
969 fp->sb_running_index[j],
970 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
971
972 BNX2X_ERR(" indexes (");
973 for (j = 0; j < loop; j++)
974 pr_cont("0x%x%s",
975 fp->sb_index_values[j],
976 (j == loop - 1) ? ")" : " ");
977 /* fw sb data */
978 data_size = CHIP_IS_E2(bp) ?
979 sizeof(struct hc_status_block_data_e2) :
980 sizeof(struct hc_status_block_data_e1x);
981 data_size /= sizeof(u32);
982 sb_data_p = CHIP_IS_E2(bp) ?
983 (u32 *)&sb_data_e2 :
984 (u32 *)&sb_data_e1x;
985 /* copy sb data in here */
986 for (j = 0; j < data_size; j++)
987 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
988 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
989 j * sizeof(u32));
990
991 if (CHIP_IS_E2(bp)) {
992 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
993 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
994 sb_data_e2.common.p_func.pf_id,
995 sb_data_e2.common.p_func.vf_id,
996 sb_data_e2.common.p_func.vf_valid,
997 sb_data_e2.common.p_func.vnic_id,
998 sb_data_e2.common.same_igu_sb_1b);
999 } else {
1000 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1001 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1002 sb_data_e1x.common.p_func.pf_id,
1003 sb_data_e1x.common.p_func.vf_id,
1004 sb_data_e1x.common.p_func.vf_valid,
1005 sb_data_e1x.common.p_func.vnic_id,
1006 sb_data_e1x.common.same_igu_sb_1b);
1007 }
1008
1009 /* SB_SMs data */
1010 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011 pr_cont("SM[%d] __flags (0x%x) "
1012 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1013 "time_to_expire (0x%x) "
1014 "timer_value(0x%x)\n", j,
1015 hc_sm_p[j].__flags,
1016 hc_sm_p[j].igu_sb_id,
1017 hc_sm_p[j].igu_seg_id,
1018 hc_sm_p[j].time_to_expire,
1019 hc_sm_p[j].timer_value);
1020 }
1021
1022 /* Indecies data */
1023 for (j = 0; j < loop; j++) {
1024 pr_cont("INDEX[%d] flags (0x%x) "
1025 "timeout (0x%x)\n", j,
1026 hc_index_p[j].flags,
1027 hc_index_p[j].timeout);
1028 }
1029 }
1030
1031 #ifdef BNX2X_STOP_ON_ERROR
1032 /* Rings */
1033 /* Rx */
1034 for_each_rx_queue(bp, i) {
1035 struct bnx2x_fastpath *fp = &bp->fp[i];
1036
1037 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1038 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1039 for (j = start; j != end; j = RX_BD(j + 1)) {
1040 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1041 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1042
1043 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1044 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
1045 }
1046
1047 start = RX_SGE(fp->rx_sge_prod);
1048 end = RX_SGE(fp->last_max_sge);
1049 for (j = start; j != end; j = RX_SGE(j + 1)) {
1050 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1051 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1052
1053 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1054 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1055 }
1056
1057 start = RCQ_BD(fp->rx_comp_cons - 10);
1058 end = RCQ_BD(fp->rx_comp_cons + 503);
1059 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1060 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1061
1062 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1063 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1064 }
1065 }
1066
1067 /* Tx */
1068 for_each_tx_queue(bp, i) {
1069 struct bnx2x_fastpath *fp = &bp->fp[i];
1070
1071 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1072 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1073 for (j = start; j != end; j = TX_BD(j + 1)) {
1074 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1075
1076 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1077 i, j, sw_bd->skb, sw_bd->first_bd);
1078 }
1079
1080 start = TX_BD(fp->tx_bd_cons - 10);
1081 end = TX_BD(fp->tx_bd_cons + 254);
1082 for (j = start; j != end; j = TX_BD(j + 1)) {
1083 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1084
1085 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1086 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
1087 }
1088 }
1089 #endif
1090 bnx2x_fw_dump(bp);
1091 bnx2x_mc_assert(bp);
1092 BNX2X_ERR("end crash dump -----------------\n");
1093 }
1094
1095 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1096 {
1097 int port = BP_PORT(bp);
1098 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1099 u32 val = REG_RD(bp, addr);
1100 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1101 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1102
1103 if (msix) {
1104 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1105 HC_CONFIG_0_REG_INT_LINE_EN_0);
1106 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1107 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1108 } else if (msi) {
1109 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1110 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1111 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1112 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1113 } else {
1114 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1115 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1116 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1117 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1118
1119 if (!CHIP_IS_E1(bp)) {
1120 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1121 val, port, addr);
1122
1123 REG_WR(bp, addr, val);
1124
1125 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1126 }
1127 }
1128
1129 if (CHIP_IS_E1(bp))
1130 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1131
1132 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1133 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1134
1135 REG_WR(bp, addr, val);
1136 /*
1137 * Ensure that HC_CONFIG is written before leading/trailing edge config
1138 */
1139 mmiowb();
1140 barrier();
1141
1142 if (!CHIP_IS_E1(bp)) {
1143 /* init leading/trailing edge */
1144 if (IS_MF(bp)) {
1145 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1146 if (bp->port.pmf)
1147 /* enable nig and gpio3 attention */
1148 val |= 0x1100;
1149 } else
1150 val = 0xffff;
1151
1152 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1153 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1154 }
1155
1156 /* Make sure that interrupts are indeed enabled from here on */
1157 mmiowb();
1158 }
1159
1160 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1161 {
1162 u32 val;
1163 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1164 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1165
1166 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1167
1168 if (msix) {
1169 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1170 IGU_PF_CONF_SINGLE_ISR_EN);
1171 val |= (IGU_PF_CONF_FUNC_EN |
1172 IGU_PF_CONF_MSI_MSIX_EN |
1173 IGU_PF_CONF_ATTN_BIT_EN);
1174 } else if (msi) {
1175 val &= ~IGU_PF_CONF_INT_LINE_EN;
1176 val |= (IGU_PF_CONF_FUNC_EN |
1177 IGU_PF_CONF_MSI_MSIX_EN |
1178 IGU_PF_CONF_ATTN_BIT_EN |
1179 IGU_PF_CONF_SINGLE_ISR_EN);
1180 } else {
1181 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1182 val |= (IGU_PF_CONF_FUNC_EN |
1183 IGU_PF_CONF_INT_LINE_EN |
1184 IGU_PF_CONF_ATTN_BIT_EN |
1185 IGU_PF_CONF_SINGLE_ISR_EN);
1186 }
1187
1188 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1189 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1190
1191 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1192
1193 barrier();
1194
1195 /* init leading/trailing edge */
1196 if (IS_MF(bp)) {
1197 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1198 if (bp->port.pmf)
1199 /* enable nig and gpio3 attention */
1200 val |= 0x1100;
1201 } else
1202 val = 0xffff;
1203
1204 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1205 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1206
1207 /* Make sure that interrupts are indeed enabled from here on */
1208 mmiowb();
1209 }
1210
1211 void bnx2x_int_enable(struct bnx2x *bp)
1212 {
1213 if (bp->common.int_block == INT_BLOCK_HC)
1214 bnx2x_hc_int_enable(bp);
1215 else
1216 bnx2x_igu_int_enable(bp);
1217 }
1218
1219 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1220 {
1221 int port = BP_PORT(bp);
1222 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1223 u32 val = REG_RD(bp, addr);
1224
1225 /*
1226 * in E1 we must use only PCI configuration space to disable
1227 * MSI/MSIX capablility
1228 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1229 */
1230 if (CHIP_IS_E1(bp)) {
1231 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1232 * Use mask register to prevent from HC sending interrupts
1233 * after we exit the function
1234 */
1235 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1236
1237 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1238 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1239 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1240 } else
1241 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1242 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1243 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1244 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1245
1246 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1247 val, port, addr);
1248
1249 /* flush all outstanding writes */
1250 mmiowb();
1251
1252 REG_WR(bp, addr, val);
1253 if (REG_RD(bp, addr) != val)
1254 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1255 }
1256
1257 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1258 {
1259 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1260
1261 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1262 IGU_PF_CONF_INT_LINE_EN |
1263 IGU_PF_CONF_ATTN_BIT_EN);
1264
1265 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1266
1267 /* flush all outstanding writes */
1268 mmiowb();
1269
1270 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1271 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1272 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1273 }
1274
1275 static void bnx2x_int_disable(struct bnx2x *bp)
1276 {
1277 if (bp->common.int_block == INT_BLOCK_HC)
1278 bnx2x_hc_int_disable(bp);
1279 else
1280 bnx2x_igu_int_disable(bp);
1281 }
1282
1283 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1284 {
1285 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1286 int i, offset;
1287
1288 /* disable interrupt handling */
1289 atomic_inc(&bp->intr_sem);
1290 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1291
1292 if (disable_hw)
1293 /* prevent the HW from sending interrupts */
1294 bnx2x_int_disable(bp);
1295
1296 /* make sure all ISRs are done */
1297 if (msix) {
1298 synchronize_irq(bp->msix_table[0].vector);
1299 offset = 1;
1300 #ifdef BCM_CNIC
1301 offset++;
1302 #endif
1303 for_each_eth_queue(bp, i)
1304 synchronize_irq(bp->msix_table[i + offset].vector);
1305 } else
1306 synchronize_irq(bp->pdev->irq);
1307
1308 /* make sure sp_task is not running */
1309 cancel_delayed_work(&bp->sp_task);
1310 flush_workqueue(bnx2x_wq);
1311 }
1312
1313 /* fast path */
1314
1315 /*
1316 * General service functions
1317 */
1318
1319 /* Return true if succeeded to acquire the lock */
1320 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1321 {
1322 u32 lock_status;
1323 u32 resource_bit = (1 << resource);
1324 int func = BP_FUNC(bp);
1325 u32 hw_lock_control_reg;
1326
1327 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1328
1329 /* Validating that the resource is within range */
1330 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1331 DP(NETIF_MSG_HW,
1332 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1333 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1334 return false;
1335 }
1336
1337 if (func <= 5)
1338 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1339 else
1340 hw_lock_control_reg =
1341 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1342
1343 /* Try to acquire the lock */
1344 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1345 lock_status = REG_RD(bp, hw_lock_control_reg);
1346 if (lock_status & resource_bit)
1347 return true;
1348
1349 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1350 return false;
1351 }
1352
1353 #ifdef BCM_CNIC
1354 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1355 #endif
1356
1357 void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1358 union eth_rx_cqe *rr_cqe)
1359 {
1360 struct bnx2x *bp = fp->bp;
1361 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1362 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1363
1364 DP(BNX2X_MSG_SP,
1365 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1366 fp->index, cid, command, bp->state,
1367 rr_cqe->ramrod_cqe.ramrod_type);
1368
1369 switch (command | fp->state) {
1370 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1371 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1372 fp->state = BNX2X_FP_STATE_OPEN;
1373 break;
1374
1375 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1376 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1377 fp->state = BNX2X_FP_STATE_HALTED;
1378 break;
1379
1380 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1381 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1382 fp->state = BNX2X_FP_STATE_TERMINATED;
1383 break;
1384
1385 default:
1386 BNX2X_ERR("unexpected MC reply (%d) "
1387 "fp[%d] state is %x\n",
1388 command, fp->index, fp->state);
1389 break;
1390 }
1391
1392 smp_mb__before_atomic_inc();
1393 atomic_inc(&bp->cq_spq_left);
1394 /* push the change in fp->state and towards the memory */
1395 smp_wmb();
1396
1397 return;
1398 }
1399
1400 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1401 {
1402 struct bnx2x *bp = netdev_priv(dev_instance);
1403 u16 status = bnx2x_ack_int(bp);
1404 u16 mask;
1405 int i;
1406
1407 /* Return here if interrupt is shared and it's not for us */
1408 if (unlikely(status == 0)) {
1409 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1410 return IRQ_NONE;
1411 }
1412 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1413
1414 /* Return here if interrupt is disabled */
1415 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1416 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1417 return IRQ_HANDLED;
1418 }
1419
1420 #ifdef BNX2X_STOP_ON_ERROR
1421 if (unlikely(bp->panic))
1422 return IRQ_HANDLED;
1423 #endif
1424
1425 for_each_eth_queue(bp, i) {
1426 struct bnx2x_fastpath *fp = &bp->fp[i];
1427
1428 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1429 if (status & mask) {
1430 /* Handle Rx and Tx according to SB id */
1431 prefetch(fp->rx_cons_sb);
1432 prefetch(fp->tx_cons_sb);
1433 prefetch(&fp->sb_running_index[SM_RX_ID]);
1434 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1435 status &= ~mask;
1436 }
1437 }
1438
1439 #ifdef BCM_CNIC
1440 mask = 0x2;
1441 if (status & (mask | 0x1)) {
1442 struct cnic_ops *c_ops = NULL;
1443
1444 rcu_read_lock();
1445 c_ops = rcu_dereference(bp->cnic_ops);
1446 if (c_ops)
1447 c_ops->cnic_handler(bp->cnic_data, NULL);
1448 rcu_read_unlock();
1449
1450 status &= ~mask;
1451 }
1452 #endif
1453
1454 if (unlikely(status & 0x1)) {
1455 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1456
1457 status &= ~0x1;
1458 if (!status)
1459 return IRQ_HANDLED;
1460 }
1461
1462 if (unlikely(status))
1463 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1464 status);
1465
1466 return IRQ_HANDLED;
1467 }
1468
1469 /* end of fast path */
1470
1471
1472 /* Link */
1473
1474 /*
1475 * General service functions
1476 */
1477
1478 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1479 {
1480 u32 lock_status;
1481 u32 resource_bit = (1 << resource);
1482 int func = BP_FUNC(bp);
1483 u32 hw_lock_control_reg;
1484 int cnt;
1485
1486 /* Validating that the resource is within range */
1487 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1488 DP(NETIF_MSG_HW,
1489 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1490 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1491 return -EINVAL;
1492 }
1493
1494 if (func <= 5) {
1495 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1496 } else {
1497 hw_lock_control_reg =
1498 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1499 }
1500
1501 /* Validating that the resource is not already taken */
1502 lock_status = REG_RD(bp, hw_lock_control_reg);
1503 if (lock_status & resource_bit) {
1504 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1505 lock_status, resource_bit);
1506 return -EEXIST;
1507 }
1508
1509 /* Try for 5 second every 5ms */
1510 for (cnt = 0; cnt < 1000; cnt++) {
1511 /* Try to acquire the lock */
1512 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1513 lock_status = REG_RD(bp, hw_lock_control_reg);
1514 if (lock_status & resource_bit)
1515 return 0;
1516
1517 msleep(5);
1518 }
1519 DP(NETIF_MSG_HW, "Timeout\n");
1520 return -EAGAIN;
1521 }
1522
1523 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1524 {
1525 u32 lock_status;
1526 u32 resource_bit = (1 << resource);
1527 int func = BP_FUNC(bp);
1528 u32 hw_lock_control_reg;
1529
1530 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1531
1532 /* Validating that the resource is within range */
1533 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1534 DP(NETIF_MSG_HW,
1535 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1536 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1537 return -EINVAL;
1538 }
1539
1540 if (func <= 5) {
1541 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1542 } else {
1543 hw_lock_control_reg =
1544 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1545 }
1546
1547 /* Validating that the resource is currently taken */
1548 lock_status = REG_RD(bp, hw_lock_control_reg);
1549 if (!(lock_status & resource_bit)) {
1550 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1551 lock_status, resource_bit);
1552 return -EFAULT;
1553 }
1554
1555 REG_WR(bp, hw_lock_control_reg, resource_bit);
1556 return 0;
1557 }
1558
1559
1560 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1561 {
1562 /* The GPIO should be swapped if swap register is set and active */
1563 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1564 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1565 int gpio_shift = gpio_num +
1566 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1567 u32 gpio_mask = (1 << gpio_shift);
1568 u32 gpio_reg;
1569 int value;
1570
1571 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1572 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1573 return -EINVAL;
1574 }
1575
1576 /* read GPIO value */
1577 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1578
1579 /* get the requested pin value */
1580 if ((gpio_reg & gpio_mask) == gpio_mask)
1581 value = 1;
1582 else
1583 value = 0;
1584
1585 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1586
1587 return value;
1588 }
1589
1590 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1591 {
1592 /* The GPIO should be swapped if swap register is set and active */
1593 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1594 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1595 int gpio_shift = gpio_num +
1596 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1597 u32 gpio_mask = (1 << gpio_shift);
1598 u32 gpio_reg;
1599
1600 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1601 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1602 return -EINVAL;
1603 }
1604
1605 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1606 /* read GPIO and mask except the float bits */
1607 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1608
1609 switch (mode) {
1610 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1611 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1612 gpio_num, gpio_shift);
1613 /* clear FLOAT and set CLR */
1614 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1615 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1616 break;
1617
1618 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1619 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1620 gpio_num, gpio_shift);
1621 /* clear FLOAT and set SET */
1622 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1623 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1624 break;
1625
1626 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1627 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1628 gpio_num, gpio_shift);
1629 /* set FLOAT */
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1631 break;
1632
1633 default:
1634 break;
1635 }
1636
1637 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1638 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1639
1640 return 0;
1641 }
1642
1643 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1644 {
1645 /* The GPIO should be swapped if swap register is set and active */
1646 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1647 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1648 int gpio_shift = gpio_num +
1649 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1650 u32 gpio_mask = (1 << gpio_shift);
1651 u32 gpio_reg;
1652
1653 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1654 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1655 return -EINVAL;
1656 }
1657
1658 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1659 /* read GPIO int */
1660 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1661
1662 switch (mode) {
1663 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1664 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1665 "output low\n", gpio_num, gpio_shift);
1666 /* clear SET and set CLR */
1667 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1668 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1669 break;
1670
1671 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1672 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1673 "output high\n", gpio_num, gpio_shift);
1674 /* clear CLR and set SET */
1675 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1677 break;
1678
1679 default:
1680 break;
1681 }
1682
1683 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1684 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1685
1686 return 0;
1687 }
1688
1689 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1690 {
1691 u32 spio_mask = (1 << spio_num);
1692 u32 spio_reg;
1693
1694 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1695 (spio_num > MISC_REGISTERS_SPIO_7)) {
1696 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1697 return -EINVAL;
1698 }
1699
1700 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1701 /* read SPIO and mask except the float bits */
1702 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1703
1704 switch (mode) {
1705 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1706 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1707 /* clear FLOAT and set CLR */
1708 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1709 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1710 break;
1711
1712 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1714 /* clear FLOAT and set SET */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1717 break;
1718
1719 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1721 /* set FLOAT */
1722 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 break;
1724
1725 default:
1726 break;
1727 }
1728
1729 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1730 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1731
1732 return 0;
1733 }
1734
1735 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1736 {
1737 u32 sel_phy_idx = 0;
1738 if (bp->link_vars.link_up) {
1739 sel_phy_idx = EXT_PHY1;
1740 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1741 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1742 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1743 sel_phy_idx = EXT_PHY2;
1744 } else {
1745
1746 switch (bnx2x_phy_selection(&bp->link_params)) {
1747 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1748 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1749 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1750 sel_phy_idx = EXT_PHY1;
1751 break;
1752 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1753 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1754 sel_phy_idx = EXT_PHY2;
1755 break;
1756 }
1757 }
1758 /*
1759 * The selected actived PHY is always after swapping (in case PHY
1760 * swapping is enabled). So when swapping is enabled, we need to reverse
1761 * the configuration
1762 */
1763
1764 if (bp->link_params.multi_phy_config &
1765 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1766 if (sel_phy_idx == EXT_PHY1)
1767 sel_phy_idx = EXT_PHY2;
1768 else if (sel_phy_idx == EXT_PHY2)
1769 sel_phy_idx = EXT_PHY1;
1770 }
1771 return LINK_CONFIG_IDX(sel_phy_idx);
1772 }
1773
1774 void bnx2x_calc_fc_adv(struct bnx2x *bp)
1775 {
1776 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1777 switch (bp->link_vars.ieee_fc &
1778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1779 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1780 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1781 ADVERTISED_Pause);
1782 break;
1783
1784 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1785 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
1786 ADVERTISED_Pause);
1787 break;
1788
1789 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1790 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
1791 break;
1792
1793 default:
1794 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1795 ADVERTISED_Pause);
1796 break;
1797 }
1798 }
1799
1800 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1801 {
1802 if (!BP_NOMCP(bp)) {
1803 u8 rc;
1804 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1805 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1806 /* Initialize link parameters structure variables */
1807 /* It is recommended to turn off RX FC for jumbo frames
1808 for better performance */
1809 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
1810 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1811 else
1812 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1813
1814 bnx2x_acquire_phy_lock(bp);
1815
1816 if (load_mode == LOAD_DIAG) {
1817 bp->link_params.loopback_mode = LOOPBACK_XGXS;
1818 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1819 }
1820
1821 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1822
1823 bnx2x_release_phy_lock(bp);
1824
1825 bnx2x_calc_fc_adv(bp);
1826
1827 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1828 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1829 bnx2x_link_report(bp);
1830 }
1831 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
1832 return rc;
1833 }
1834 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
1835 return -EINVAL;
1836 }
1837
1838 void bnx2x_link_set(struct bnx2x *bp)
1839 {
1840 if (!BP_NOMCP(bp)) {
1841 bnx2x_acquire_phy_lock(bp);
1842 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1843 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1844 bnx2x_release_phy_lock(bp);
1845
1846 bnx2x_calc_fc_adv(bp);
1847 } else
1848 BNX2X_ERR("Bootcode is missing - can not set link\n");
1849 }
1850
1851 static void bnx2x__link_reset(struct bnx2x *bp)
1852 {
1853 if (!BP_NOMCP(bp)) {
1854 bnx2x_acquire_phy_lock(bp);
1855 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1856 bnx2x_release_phy_lock(bp);
1857 } else
1858 BNX2X_ERR("Bootcode is missing - can not reset link\n");
1859 }
1860
1861 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
1862 {
1863 u8 rc = 0;
1864
1865 if (!BP_NOMCP(bp)) {
1866 bnx2x_acquire_phy_lock(bp);
1867 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1868 is_serdes);
1869 bnx2x_release_phy_lock(bp);
1870 } else
1871 BNX2X_ERR("Bootcode is missing - can not test link\n");
1872
1873 return rc;
1874 }
1875
1876 static void bnx2x_init_port_minmax(struct bnx2x *bp)
1877 {
1878 u32 r_param = bp->link_vars.line_speed / 8;
1879 u32 fair_periodic_timeout_usec;
1880 u32 t_fair;
1881
1882 memset(&(bp->cmng.rs_vars), 0,
1883 sizeof(struct rate_shaping_vars_per_port));
1884 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
1885
1886 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1887 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
1888
1889 /* this is the threshold below which no timer arming will occur
1890 1.25 coefficient is for the threshold to be a little bigger
1891 than the real time, to compensate for timer in-accuracy */
1892 bp->cmng.rs_vars.rs_threshold =
1893 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1894
1895 /* resolution of fairness timer */
1896 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1897 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1898 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
1899
1900 /* this is the threshold below which we won't arm the timer anymore */
1901 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
1902
1903 /* we multiply by 1e3/8 to get bytes/msec.
1904 We don't want the credits to pass a credit
1905 of the t_fair*FAIR_MEM (algorithm resolution) */
1906 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1907 /* since each tick is 4 usec */
1908 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
1909 }
1910
1911 /* Calculates the sum of vn_min_rates.
1912 It's needed for further normalizing of the min_rates.
1913 Returns:
1914 sum of vn_min_rates.
1915 or
1916 0 - if all the min_rates are 0.
1917 In the later case fainess algorithm should be deactivated.
1918 If not all min_rates are zero then those that are zeroes will be set to 1.
1919 */
1920 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1921 {
1922 int all_zero = 1;
1923 int vn;
1924
1925 bp->vn_weight_sum = 0;
1926 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1927 u32 vn_cfg = bp->mf_config[vn];
1928 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1929 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1930
1931 /* Skip hidden vns */
1932 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1933 continue;
1934
1935 /* If min rate is zero - set it to 1 */
1936 if (!vn_min_rate)
1937 vn_min_rate = DEF_MIN_RATE;
1938 else
1939 all_zero = 0;
1940
1941 bp->vn_weight_sum += vn_min_rate;
1942 }
1943
1944 /* ... only if all min rates are zeros - disable fairness */
1945 if (all_zero) {
1946 bp->cmng.flags.cmng_enables &=
1947 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1948 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1949 " fairness will be disabled\n");
1950 } else
1951 bp->cmng.flags.cmng_enables |=
1952 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1953 }
1954
1955 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
1956 {
1957 struct rate_shaping_vars_per_vn m_rs_vn;
1958 struct fairness_vars_per_vn m_fair_vn;
1959 u32 vn_cfg = bp->mf_config[vn];
1960 int func = 2*vn + BP_PORT(bp);
1961 u16 vn_min_rate, vn_max_rate;
1962 int i;
1963
1964 /* If function is hidden - set min and max to zeroes */
1965 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1966 vn_min_rate = 0;
1967 vn_max_rate = 0;
1968
1969 } else {
1970 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
1971
1972 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1973 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1974 /* If fairness is enabled (not all min rates are zeroes) and
1975 if current min rate is zero - set it to 1.
1976 This is a requirement of the algorithm. */
1977 if (bp->vn_weight_sum && (vn_min_rate == 0))
1978 vn_min_rate = DEF_MIN_RATE;
1979
1980 if (IS_MF_SI(bp))
1981 /* maxCfg in percents of linkspeed */
1982 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
1983 else
1984 /* maxCfg is absolute in 100Mb units */
1985 vn_max_rate = maxCfg * 100;
1986 }
1987
1988 DP(NETIF_MSG_IFUP,
1989 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
1990 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
1991
1992 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1993 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1994
1995 /* global vn counter - maximal Mbps for this vn */
1996 m_rs_vn.vn_counter.rate = vn_max_rate;
1997
1998 /* quota - number of bytes transmitted in this period */
1999 m_rs_vn.vn_counter.quota =
2000 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2001
2002 if (bp->vn_weight_sum) {
2003 /* credit for each period of the fairness algorithm:
2004 number of bytes in T_FAIR (the vn share the port rate).
2005 vn_weight_sum should not be larger than 10000, thus
2006 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2007 than zero */
2008 m_fair_vn.vn_credit_delta =
2009 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2010 (8 * bp->vn_weight_sum))),
2011 (bp->cmng.fair_vars.fair_threshold +
2012 MIN_ABOVE_THRESH));
2013 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2014 m_fair_vn.vn_credit_delta);
2015 }
2016
2017 /* Store it to internal memory */
2018 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2019 REG_WR(bp, BAR_XSTRORM_INTMEM +
2020 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2021 ((u32 *)(&m_rs_vn))[i]);
2022
2023 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2024 REG_WR(bp, BAR_XSTRORM_INTMEM +
2025 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2026 ((u32 *)(&m_fair_vn))[i]);
2027 }
2028
2029 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2030 {
2031 if (CHIP_REV_IS_SLOW(bp))
2032 return CMNG_FNS_NONE;
2033 if (IS_MF(bp))
2034 return CMNG_FNS_MINMAX;
2035
2036 return CMNG_FNS_NONE;
2037 }
2038
2039 static void bnx2x_read_mf_cfg(struct bnx2x *bp)
2040 {
2041 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2042
2043 if (BP_NOMCP(bp))
2044 return; /* what should be the default bvalue in this case */
2045
2046 /* For 2 port configuration the absolute function number formula
2047 * is:
2048 * abs_func = 2 * vn + BP_PORT + BP_PATH
2049 *
2050 * and there are 4 functions per port
2051 *
2052 * For 4 port configuration it is
2053 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2054 *
2055 * and there are 2 functions per port
2056 */
2057 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2058 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2059
2060 if (func >= E1H_FUNC_MAX)
2061 break;
2062
2063 bp->mf_config[vn] =
2064 MF_CFG_RD(bp, func_mf_config[func].config);
2065 }
2066 }
2067
2068 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2069 {
2070
2071 if (cmng_type == CMNG_FNS_MINMAX) {
2072 int vn;
2073
2074 /* clear cmng_enables */
2075 bp->cmng.flags.cmng_enables = 0;
2076
2077 /* read mf conf from shmem */
2078 if (read_cfg)
2079 bnx2x_read_mf_cfg(bp);
2080
2081 /* Init rate shaping and fairness contexts */
2082 bnx2x_init_port_minmax(bp);
2083
2084 /* vn_weight_sum and enable fairness if not 0 */
2085 bnx2x_calc_vn_weight_sum(bp);
2086
2087 /* calculate and set min-max rate for each vn */
2088 if (bp->port.pmf)
2089 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2090 bnx2x_init_vn_minmax(bp, vn);
2091
2092 /* always enable rate shaping and fairness */
2093 bp->cmng.flags.cmng_enables |=
2094 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2095 if (!bp->vn_weight_sum)
2096 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2097 " fairness will be disabled\n");
2098 return;
2099 }
2100
2101 /* rate shaping and fairness are disabled */
2102 DP(NETIF_MSG_IFUP,
2103 "rate shaping and fairness are disabled\n");
2104 }
2105
2106 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2107 {
2108 int port = BP_PORT(bp);
2109 int func;
2110 int vn;
2111
2112 /* Set the attention towards other drivers on the same port */
2113 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2114 if (vn == BP_E1HVN(bp))
2115 continue;
2116
2117 func = ((vn << 1) | port);
2118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2119 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2120 }
2121 }
2122
2123 /* This function is called upon link interrupt */
2124 static void bnx2x_link_attn(struct bnx2x *bp)
2125 {
2126 u32 prev_link_status = bp->link_vars.link_status;
2127 /* Make sure that we are synced with the current statistics */
2128 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2129
2130 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2131
2132 if (bp->link_vars.link_up) {
2133
2134 /* dropless flow control */
2135 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2136 int port = BP_PORT(bp);
2137 u32 pause_enabled = 0;
2138
2139 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2140 pause_enabled = 1;
2141
2142 REG_WR(bp, BAR_USTRORM_INTMEM +
2143 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2144 pause_enabled);
2145 }
2146
2147 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2148 struct host_port_stats *pstats;
2149
2150 pstats = bnx2x_sp(bp, port_stats);
2151 /* reset old bmac stats */
2152 memset(&(pstats->mac_stx[0]), 0,
2153 sizeof(struct mac_stx));
2154 }
2155 if (bp->state == BNX2X_STATE_OPEN)
2156 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2157 }
2158
2159 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2160 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2161
2162 if (cmng_fns != CMNG_FNS_NONE) {
2163 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2164 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2165 } else
2166 /* rate shaping and fairness are disabled */
2167 DP(NETIF_MSG_IFUP,
2168 "single function mode without fairness\n");
2169 }
2170
2171 if (IS_MF(bp))
2172 bnx2x_link_sync_notify(bp);
2173
2174 /* indicate link status only if link status actually changed */
2175 if (prev_link_status != bp->link_vars.link_status)
2176 bnx2x_link_report(bp);
2177 }
2178
2179 void bnx2x__link_status_update(struct bnx2x *bp)
2180 {
2181 if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
2182 return;
2183
2184 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2185
2186 if (bp->link_vars.link_up)
2187 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2188 else
2189 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2190
2191 /* the link status update could be the result of a DCC event
2192 hence re-read the shmem mf configuration */
2193 bnx2x_read_mf_cfg(bp);
2194
2195 /* indicate link status */
2196 bnx2x_link_report(bp);
2197 }
2198
2199 static void bnx2x_pmf_update(struct bnx2x *bp)
2200 {
2201 int port = BP_PORT(bp);
2202 u32 val;
2203
2204 bp->port.pmf = 1;
2205 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2206
2207 /* enable nig attention */
2208 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2209 if (bp->common.int_block == INT_BLOCK_HC) {
2210 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2211 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2212 } else if (CHIP_IS_E2(bp)) {
2213 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2214 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2215 }
2216
2217 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2218 }
2219
2220 /* end of Link */
2221
2222 /* slow path */
2223
2224 /*
2225 * General service functions
2226 */
2227
2228 /* send the MCP a request, block until there is a reply */
2229 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2230 {
2231 int mb_idx = BP_FW_MB_IDX(bp);
2232 u32 seq = ++bp->fw_seq;
2233 u32 rc = 0;
2234 u32 cnt = 1;
2235 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2236
2237 mutex_lock(&bp->fw_mb_mutex);
2238 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2239 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2240
2241 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2242
2243 do {
2244 /* let the FW do it's magic ... */
2245 msleep(delay);
2246
2247 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2248
2249 /* Give the FW up to 5 second (500*10ms) */
2250 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2251
2252 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2253 cnt*delay, rc, seq);
2254
2255 /* is this a reply to our command? */
2256 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2257 rc &= FW_MSG_CODE_MASK;
2258 else {
2259 /* FW BUG! */
2260 BNX2X_ERR("FW failed to respond!\n");
2261 bnx2x_fw_dump(bp);
2262 rc = 0;
2263 }
2264 mutex_unlock(&bp->fw_mb_mutex);
2265
2266 return rc;
2267 }
2268
2269 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2270 {
2271 #ifdef BCM_CNIC
2272 if (IS_FCOE_FP(fp) && IS_MF(bp))
2273 return false;
2274 #endif
2275 return true;
2276 }
2277
2278 /* must be called under rtnl_lock */
2279 static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2280 {
2281 u32 mask = (1 << cl_id);
2282
2283 /* initial seeting is BNX2X_ACCEPT_NONE */
2284 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2285 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2286 u8 unmatched_unicast = 0;
2287
2288 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2289 unmatched_unicast = 1;
2290
2291 if (filters & BNX2X_PROMISCUOUS_MODE) {
2292 /* promiscious - accept all, drop none */
2293 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2294 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
2295 if (IS_MF_SI(bp)) {
2296 /*
2297 * SI mode defines to accept in promiscuos mode
2298 * only unmatched packets
2299 */
2300 unmatched_unicast = 1;
2301 accp_all_ucast = 0;
2302 }
2303 }
2304 if (filters & BNX2X_ACCEPT_UNICAST) {
2305 /* accept matched ucast */
2306 drop_all_ucast = 0;
2307 }
2308 if (filters & BNX2X_ACCEPT_MULTICAST)
2309 /* accept matched mcast */
2310 drop_all_mcast = 0;
2311
2312 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2313 /* accept all mcast */
2314 drop_all_ucast = 0;
2315 accp_all_ucast = 1;
2316 }
2317 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2318 /* accept all mcast */
2319 drop_all_mcast = 0;
2320 accp_all_mcast = 1;
2321 }
2322 if (filters & BNX2X_ACCEPT_BROADCAST) {
2323 /* accept (all) bcast */
2324 drop_all_bcast = 0;
2325 accp_all_bcast = 1;
2326 }
2327
2328 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2329 bp->mac_filters.ucast_drop_all | mask :
2330 bp->mac_filters.ucast_drop_all & ~mask;
2331
2332 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2333 bp->mac_filters.mcast_drop_all | mask :
2334 bp->mac_filters.mcast_drop_all & ~mask;
2335
2336 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2337 bp->mac_filters.bcast_drop_all | mask :
2338 bp->mac_filters.bcast_drop_all & ~mask;
2339
2340 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2341 bp->mac_filters.ucast_accept_all | mask :
2342 bp->mac_filters.ucast_accept_all & ~mask;
2343
2344 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2345 bp->mac_filters.mcast_accept_all | mask :
2346 bp->mac_filters.mcast_accept_all & ~mask;
2347
2348 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2349 bp->mac_filters.bcast_accept_all | mask :
2350 bp->mac_filters.bcast_accept_all & ~mask;
2351
2352 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2353 bp->mac_filters.unmatched_unicast | mask :
2354 bp->mac_filters.unmatched_unicast & ~mask;
2355 }
2356
2357 static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2358 {
2359 struct tstorm_eth_function_common_config tcfg = {0};
2360 u16 rss_flgs;
2361
2362 /* tpa */
2363 if (p->func_flgs & FUNC_FLG_TPA)
2364 tcfg.config_flags |=
2365 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2366
2367 /* set rss flags */
2368 rss_flgs = (p->rss->mode <<
2369 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2370
2371 if (p->rss->cap & RSS_IPV4_CAP)
2372 rss_flgs |= RSS_IPV4_CAP_MASK;
2373 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2374 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2375 if (p->rss->cap & RSS_IPV6_CAP)
2376 rss_flgs |= RSS_IPV6_CAP_MASK;
2377 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2378 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2379
2380 tcfg.config_flags |= rss_flgs;
2381 tcfg.rss_result_mask = p->rss->result_mask;
2382
2383 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2384
2385 /* Enable the function in the FW */
2386 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2387 storm_memset_func_en(bp, p->func_id, 1);
2388
2389 /* statistics */
2390 if (p->func_flgs & FUNC_FLG_STATS) {
2391 struct stats_indication_flags stats_flags = {0};
2392 stats_flags.collect_eth = 1;
2393
2394 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2395 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2396
2397 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2398 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2399
2400 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2401 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2402
2403 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2404 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2405 }
2406
2407 /* spq */
2408 if (p->func_flgs & FUNC_FLG_SPQ) {
2409 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2410 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2411 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2412 }
2413 }
2414
2415 static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2416 struct bnx2x_fastpath *fp)
2417 {
2418 u16 flags = 0;
2419
2420 /* calculate queue flags */
2421 flags |= QUEUE_FLG_CACHE_ALIGN;
2422 flags |= QUEUE_FLG_HC;
2423 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
2424
2425 flags |= QUEUE_FLG_VLAN;
2426 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
2427
2428 if (!fp->disable_tpa)
2429 flags |= QUEUE_FLG_TPA;
2430
2431 flags = stat_counter_valid(bp, fp) ?
2432 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
2433
2434 return flags;
2435 }
2436
2437 static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2438 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2439 struct bnx2x_rxq_init_params *rxq_init)
2440 {
2441 u16 max_sge = 0;
2442 u16 sge_sz = 0;
2443 u16 tpa_agg_size = 0;
2444
2445 /* calculate queue flags */
2446 u16 flags = bnx2x_get_cl_flags(bp, fp);
2447
2448 if (!fp->disable_tpa) {
2449 pause->sge_th_hi = 250;
2450 pause->sge_th_lo = 150;
2451 tpa_agg_size = min_t(u32,
2452 (min_t(u32, 8, MAX_SKB_FRAGS) *
2453 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2454 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2455 SGE_PAGE_SHIFT;
2456 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2457 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2458 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2459 0xffff);
2460 }
2461
2462 /* pause - not for e1 */
2463 if (!CHIP_IS_E1(bp)) {
2464 pause->bd_th_hi = 350;
2465 pause->bd_th_lo = 250;
2466 pause->rcq_th_hi = 350;
2467 pause->rcq_th_lo = 250;
2468 pause->sge_th_hi = 0;
2469 pause->sge_th_lo = 0;
2470 pause->pri_map = 1;
2471 }
2472
2473 /* rxq setup */
2474 rxq_init->flags = flags;
2475 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2476 rxq_init->dscr_map = fp->rx_desc_mapping;
2477 rxq_init->sge_map = fp->rx_sge_mapping;
2478 rxq_init->rcq_map = fp->rx_comp_mapping;
2479 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2480
2481 /* Always use mini-jumbo MTU for FCoE L2 ring */
2482 if (IS_FCOE_FP(fp))
2483 rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2484 else
2485 rxq_init->mtu = bp->dev->mtu;
2486
2487 rxq_init->buf_sz = fp->rx_buf_size;
2488 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2489 rxq_init->cl_id = fp->cl_id;
2490 rxq_init->spcl_id = fp->cl_id;
2491 rxq_init->stat_id = fp->cl_id;
2492 rxq_init->tpa_agg_sz = tpa_agg_size;
2493 rxq_init->sge_buf_sz = sge_sz;
2494 rxq_init->max_sges_pkt = max_sge;
2495 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2496 rxq_init->fw_sb_id = fp->fw_sb_id;
2497
2498 if (IS_FCOE_FP(fp))
2499 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2500 else
2501 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2502
2503 rxq_init->cid = HW_CID(bp, fp->cid);
2504
2505 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2506 }
2507
2508 static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2509 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2510 {
2511 u16 flags = bnx2x_get_cl_flags(bp, fp);
2512
2513 txq_init->flags = flags;
2514 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2515 txq_init->dscr_map = fp->tx_desc_mapping;
2516 txq_init->stat_id = fp->cl_id;
2517 txq_init->cid = HW_CID(bp, fp->cid);
2518 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2519 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2520 txq_init->fw_sb_id = fp->fw_sb_id;
2521
2522 if (IS_FCOE_FP(fp)) {
2523 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2524 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2525 }
2526
2527 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2528 }
2529
2530 static void bnx2x_pf_init(struct bnx2x *bp)
2531 {
2532 struct bnx2x_func_init_params func_init = {0};
2533 struct bnx2x_rss_params rss = {0};
2534 struct event_ring_data eq_data = { {0} };
2535 u16 flags;
2536
2537 /* pf specific setups */
2538 if (!CHIP_IS_E1(bp))
2539 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
2540
2541 if (CHIP_IS_E2(bp)) {
2542 /* reset IGU PF statistics: MSIX + ATTN */
2543 /* PF */
2544 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2545 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2546 (CHIP_MODE_IS_4_PORT(bp) ?
2547 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2548 /* ATTN */
2549 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2550 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2551 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2552 (CHIP_MODE_IS_4_PORT(bp) ?
2553 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2554 }
2555
2556 /* function setup flags */
2557 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2558
2559 if (CHIP_IS_E1x(bp))
2560 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2561 else
2562 flags |= FUNC_FLG_TPA;
2563
2564 /* function setup */
2565
2566 /**
2567 * Although RSS is meaningless when there is a single HW queue we
2568 * still need it enabled in order to have HW Rx hash generated.
2569 */
2570 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2571 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2572 rss.mode = bp->multi_mode;
2573 rss.result_mask = MULTI_MASK;
2574 func_init.rss = &rss;
2575
2576 func_init.func_flgs = flags;
2577 func_init.pf_id = BP_FUNC(bp);
2578 func_init.func_id = BP_FUNC(bp);
2579 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2580 func_init.spq_map = bp->spq_mapping;
2581 func_init.spq_prod = bp->spq_prod_idx;
2582
2583 bnx2x_func_init(bp, &func_init);
2584
2585 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2586
2587 /*
2588 Congestion management values depend on the link rate
2589 There is no active link so initial link rate is set to 10 Gbps.
2590 When the link comes up The congestion management values are
2591 re-calculated according to the actual link rate.
2592 */
2593 bp->link_vars.line_speed = SPEED_10000;
2594 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2595
2596 /* Only the PMF sets the HW */
2597 if (bp->port.pmf)
2598 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2599
2600 /* no rx until link is up */
2601 bp->rx_mode = BNX2X_RX_MODE_NONE;
2602 bnx2x_set_storm_rx_mode(bp);
2603
2604 /* init Event Queue */
2605 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2606 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2607 eq_data.producer = bp->eq_prod;
2608 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2609 eq_data.sb_id = DEF_SB_ID;
2610 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2611 }
2612
2613
2614 static void bnx2x_e1h_disable(struct bnx2x *bp)
2615 {
2616 int port = BP_PORT(bp);
2617
2618 netif_tx_disable(bp->dev);
2619
2620 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2621
2622 netif_carrier_off(bp->dev);
2623 }
2624
2625 static void bnx2x_e1h_enable(struct bnx2x *bp)
2626 {
2627 int port = BP_PORT(bp);
2628
2629 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2630
2631 /* Tx queue should be only reenabled */
2632 netif_tx_wake_all_queues(bp->dev);
2633
2634 /*
2635 * Should not call netif_carrier_on since it will be called if the link
2636 * is up when checking for link state
2637 */
2638 }
2639
2640 /* called due to MCP event (on pmf):
2641 * reread new bandwidth configuration
2642 * configure FW
2643 * notify others function about the change
2644 */
2645 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2646 {
2647 if (bp->link_vars.link_up) {
2648 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2649 bnx2x_link_sync_notify(bp);
2650 }
2651 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2652 }
2653
2654 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2655 {
2656 bnx2x_config_mf_bw(bp);
2657 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2658 }
2659
2660 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2661 {
2662 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2663
2664 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2665
2666 /*
2667 * This is the only place besides the function initialization
2668 * where the bp->flags can change so it is done without any
2669 * locks
2670 */
2671 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2672 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2673 bp->flags |= MF_FUNC_DIS;
2674
2675 bnx2x_e1h_disable(bp);
2676 } else {
2677 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2678 bp->flags &= ~MF_FUNC_DIS;
2679
2680 bnx2x_e1h_enable(bp);
2681 }
2682 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2683 }
2684 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2685 bnx2x_config_mf_bw(bp);
2686 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2687 }
2688
2689 /* Report results to MCP */
2690 if (dcc_event)
2691 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2692 else
2693 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2694 }
2695
2696 /* must be called under the spq lock */
2697 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2698 {
2699 struct eth_spe *next_spe = bp->spq_prod_bd;
2700
2701 if (bp->spq_prod_bd == bp->spq_last_bd) {
2702 bp->spq_prod_bd = bp->spq;
2703 bp->spq_prod_idx = 0;
2704 DP(NETIF_MSG_TIMER, "end of spq\n");
2705 } else {
2706 bp->spq_prod_bd++;
2707 bp->spq_prod_idx++;
2708 }
2709 return next_spe;
2710 }
2711
2712 /* must be called under the spq lock */
2713 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2714 {
2715 int func = BP_FUNC(bp);
2716
2717 /* Make sure that BD data is updated before writing the producer */
2718 wmb();
2719
2720 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2721 bp->spq_prod_idx);
2722 mmiowb();
2723 }
2724
2725 /* the slow path queue is odd since completions arrive on the fastpath ring */
2726 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2727 u32 data_hi, u32 data_lo, int common)
2728 {
2729 struct eth_spe *spe;
2730 u16 type;
2731
2732 #ifdef BNX2X_STOP_ON_ERROR
2733 if (unlikely(bp->panic))
2734 return -EIO;
2735 #endif
2736
2737 spin_lock_bh(&bp->spq_lock);
2738
2739 if (common) {
2740 if (!atomic_read(&bp->eq_spq_left)) {
2741 BNX2X_ERR("BUG! EQ ring full!\n");
2742 spin_unlock_bh(&bp->spq_lock);
2743 bnx2x_panic();
2744 return -EBUSY;
2745 }
2746 } else if (!atomic_read(&bp->cq_spq_left)) {
2747 BNX2X_ERR("BUG! SPQ ring full!\n");
2748 spin_unlock_bh(&bp->spq_lock);
2749 bnx2x_panic();
2750 return -EBUSY;
2751 }
2752
2753 spe = bnx2x_sp_get_next(bp);
2754
2755 /* CID needs port number to be encoded int it */
2756 spe->hdr.conn_and_cmd_data =
2757 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2758 HW_CID(bp, cid));
2759
2760 if (common)
2761 /* Common ramrods:
2762 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2763 * TRAFFIC_STOP, TRAFFIC_START
2764 */
2765 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2766 & SPE_HDR_CONN_TYPE;
2767 else
2768 /* ETH ramrods: SETUP, HALT */
2769 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2770 & SPE_HDR_CONN_TYPE;
2771
2772 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2773 SPE_HDR_FUNCTION_ID);
2774
2775 spe->hdr.type = cpu_to_le16(type);
2776
2777 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2778 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2779
2780 /* stats ramrod has it's own slot on the spq */
2781 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
2782 /* It's ok if the actual decrement is issued towards the memory
2783 * somewhere between the spin_lock and spin_unlock. Thus no
2784 * more explict memory barrier is needed.
2785 */
2786 if (common)
2787 atomic_dec(&bp->eq_spq_left);
2788 else
2789 atomic_dec(&bp->cq_spq_left);
2790 }
2791
2792
2793 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2794 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2795 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
2796 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2797 (u32)(U64_LO(bp->spq_mapping) +
2798 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2799 HW_CID(bp, cid), data_hi, data_lo, type,
2800 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
2801
2802 bnx2x_sp_prod_update(bp);
2803 spin_unlock_bh(&bp->spq_lock);
2804 return 0;
2805 }
2806
2807 /* acquire split MCP access lock register */
2808 static int bnx2x_acquire_alr(struct bnx2x *bp)
2809 {
2810 u32 j, val;
2811 int rc = 0;
2812
2813 might_sleep();
2814 for (j = 0; j < 1000; j++) {
2815 val = (1UL << 31);
2816 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2817 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2818 if (val & (1L << 31))
2819 break;
2820
2821 msleep(5);
2822 }
2823 if (!(val & (1L << 31))) {
2824 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2825 rc = -EBUSY;
2826 }
2827
2828 return rc;
2829 }
2830
2831 /* release split MCP access lock register */
2832 static void bnx2x_release_alr(struct bnx2x *bp)
2833 {
2834 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
2835 }
2836
2837 #define BNX2X_DEF_SB_ATT_IDX 0x0001
2838 #define BNX2X_DEF_SB_IDX 0x0002
2839
2840 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2841 {
2842 struct host_sp_status_block *def_sb = bp->def_status_blk;
2843 u16 rc = 0;
2844
2845 barrier(); /* status block is written to by the chip */
2846 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2847 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2848 rc |= BNX2X_DEF_SB_ATT_IDX;
2849 }
2850
2851 if (bp->def_idx != def_sb->sp_sb.running_index) {
2852 bp->def_idx = def_sb->sp_sb.running_index;
2853 rc |= BNX2X_DEF_SB_IDX;
2854 }
2855
2856 /* Do not reorder: indecies reading should complete before handling */
2857 barrier();
2858 return rc;
2859 }
2860
2861 /*
2862 * slow path service functions
2863 */
2864
2865 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2866 {
2867 int port = BP_PORT(bp);
2868 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2869 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2870 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2871 NIG_REG_MASK_INTERRUPT_PORT0;
2872 u32 aeu_mask;
2873 u32 nig_mask = 0;
2874 u32 reg_addr;
2875
2876 if (bp->attn_state & asserted)
2877 BNX2X_ERR("IGU ERROR\n");
2878
2879 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2880 aeu_mask = REG_RD(bp, aeu_addr);
2881
2882 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2883 aeu_mask, asserted);
2884 aeu_mask &= ~(asserted & 0x3ff);
2885 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2886
2887 REG_WR(bp, aeu_addr, aeu_mask);
2888 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2889
2890 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2891 bp->attn_state |= asserted;
2892 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2893
2894 if (asserted & ATTN_HARD_WIRED_MASK) {
2895 if (asserted & ATTN_NIG_FOR_FUNC) {
2896
2897 bnx2x_acquire_phy_lock(bp);
2898
2899 /* save nig interrupt mask */
2900 nig_mask = REG_RD(bp, nig_int_mask_addr);
2901 REG_WR(bp, nig_int_mask_addr, 0);
2902
2903 bnx2x_link_attn(bp);
2904
2905 /* handle unicore attn? */
2906 }
2907 if (asserted & ATTN_SW_TIMER_4_FUNC)
2908 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2909
2910 if (asserted & GPIO_2_FUNC)
2911 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2912
2913 if (asserted & GPIO_3_FUNC)
2914 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2915
2916 if (asserted & GPIO_4_FUNC)
2917 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2918
2919 if (port == 0) {
2920 if (asserted & ATTN_GENERAL_ATTN_1) {
2921 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2922 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2923 }
2924 if (asserted & ATTN_GENERAL_ATTN_2) {
2925 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2926 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2927 }
2928 if (asserted & ATTN_GENERAL_ATTN_3) {
2929 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2930 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2931 }
2932 } else {
2933 if (asserted & ATTN_GENERAL_ATTN_4) {
2934 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2935 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2936 }
2937 if (asserted & ATTN_GENERAL_ATTN_5) {
2938 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2939 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2940 }
2941 if (asserted & ATTN_GENERAL_ATTN_6) {
2942 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2943 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2944 }
2945 }
2946
2947 } /* if hardwired */
2948
2949 if (bp->common.int_block == INT_BLOCK_HC)
2950 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2951 COMMAND_REG_ATTN_BITS_SET);
2952 else
2953 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2954
2955 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2956 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2957 REG_WR(bp, reg_addr, asserted);
2958
2959 /* now set back the mask */
2960 if (asserted & ATTN_NIG_FOR_FUNC) {
2961 REG_WR(bp, nig_int_mask_addr, nig_mask);
2962 bnx2x_release_phy_lock(bp);
2963 }
2964 }
2965
2966 static inline void bnx2x_fan_failure(struct bnx2x *bp)
2967 {
2968 int port = BP_PORT(bp);
2969 u32 ext_phy_config;
2970 /* mark the failure */
2971 ext_phy_config =
2972 SHMEM_RD(bp,
2973 dev_info.port_hw_config[port].external_phy_config);
2974
2975 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2976 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2977 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2978 ext_phy_config);
2979
2980 /* log the failure */
2981 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2982 " the driver to shutdown the card to prevent permanent"
2983 " damage. Please contact OEM Support for assistance\n");
2984 }
2985
2986 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2987 {
2988 int port = BP_PORT(bp);
2989 int reg_offset;
2990 u32 val;
2991
2992 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2993 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2994
2995 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2996
2997 val = REG_RD(bp, reg_offset);
2998 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2999 REG_WR(bp, reg_offset, val);
3000
3001 BNX2X_ERR("SPIO5 hw attention\n");
3002
3003 /* Fan failure attention */
3004 bnx2x_hw_reset_phy(&bp->link_params);
3005 bnx2x_fan_failure(bp);
3006 }
3007
3008 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3009 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3010 bnx2x_acquire_phy_lock(bp);
3011 bnx2x_handle_module_detect_int(&bp->link_params);
3012 bnx2x_release_phy_lock(bp);
3013 }
3014
3015 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3016
3017 val = REG_RD(bp, reg_offset);
3018 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3019 REG_WR(bp, reg_offset, val);
3020
3021 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3022 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3023 bnx2x_panic();
3024 }
3025 }
3026
3027 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3028 {
3029 u32 val;
3030
3031 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3032
3033 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3034 BNX2X_ERR("DB hw attention 0x%x\n", val);
3035 /* DORQ discard attention */
3036 if (val & 0x2)
3037 BNX2X_ERR("FATAL error from DORQ\n");
3038 }
3039
3040 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3041
3042 int port = BP_PORT(bp);
3043 int reg_offset;
3044
3045 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3046 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3047
3048 val = REG_RD(bp, reg_offset);
3049 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3050 REG_WR(bp, reg_offset, val);
3051
3052 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3053 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3054 bnx2x_panic();
3055 }
3056 }
3057
3058 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3059 {
3060 u32 val;
3061
3062 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3063
3064 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3065 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3066 /* CFC error attention */
3067 if (val & 0x2)
3068 BNX2X_ERR("FATAL error from CFC\n");
3069 }
3070
3071 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3072
3073 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3074 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3075 /* RQ_USDMDP_FIFO_OVERFLOW */
3076 if (val & 0x18000)
3077 BNX2X_ERR("FATAL error from PXP\n");
3078 if (CHIP_IS_E2(bp)) {
3079 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3080 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3081 }
3082 }
3083
3084 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3085
3086 int port = BP_PORT(bp);
3087 int reg_offset;
3088
3089 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3090 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3091
3092 val = REG_RD(bp, reg_offset);
3093 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3094 REG_WR(bp, reg_offset, val);
3095
3096 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3097 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3098 bnx2x_panic();
3099 }
3100 }
3101
3102 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3103 {
3104 u32 val;
3105
3106 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3107
3108 if (attn & BNX2X_PMF_LINK_ASSERT) {
3109 int func = BP_FUNC(bp);
3110
3111 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3112 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3113 func_mf_config[BP_ABS_FUNC(bp)].config);
3114 val = SHMEM_RD(bp,
3115 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3116 if (val & DRV_STATUS_DCC_EVENT_MASK)
3117 bnx2x_dcc_event(bp,
3118 (val & DRV_STATUS_DCC_EVENT_MASK));
3119
3120 if (val & DRV_STATUS_SET_MF_BW)
3121 bnx2x_set_mf_bw(bp);
3122
3123 bnx2x__link_status_update(bp);
3124 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3125 bnx2x_pmf_update(bp);
3126
3127 if (bp->port.pmf &&
3128 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3129 bp->dcbx_enabled > 0)
3130 /* start dcbx state machine */
3131 bnx2x_dcbx_set_params(bp,
3132 BNX2X_DCBX_STATE_NEG_RECEIVED);
3133 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3134
3135 BNX2X_ERR("MC assert!\n");
3136 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3137 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3138 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3139 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3140 bnx2x_panic();
3141
3142 } else if (attn & BNX2X_MCP_ASSERT) {
3143
3144 BNX2X_ERR("MCP assert!\n");
3145 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3146 bnx2x_fw_dump(bp);
3147
3148 } else
3149 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3150 }
3151
3152 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3153 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3154 if (attn & BNX2X_GRC_TIMEOUT) {
3155 val = CHIP_IS_E1(bp) ? 0 :
3156 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3157 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3158 }
3159 if (attn & BNX2X_GRC_RSV) {
3160 val = CHIP_IS_E1(bp) ? 0 :
3161 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3162 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3163 }
3164 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3165 }
3166 }
3167
3168 #define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3169 #define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3170 #define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3171 #define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3172 #define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
3173
3174 /*
3175 * should be run under rtnl lock
3176 */
3177 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3178 {
3179 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3180 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3181 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3182 barrier();
3183 mmiowb();
3184 }
3185
3186 /*
3187 * should be run under rtnl lock
3188 */
3189 static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3190 {
3191 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3192 val |= (1 << 16);
3193 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3194 barrier();
3195 mmiowb();
3196 }
3197
3198 /*
3199 * should be run under rtnl lock
3200 */
3201 bool bnx2x_reset_is_done(struct bnx2x *bp)
3202 {
3203 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3204 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3205 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3206 }
3207
3208 /*
3209 * should be run under rtnl lock
3210 */
3211 inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
3212 {
3213 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3214
3215 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3216
3217 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3218 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3219 barrier();
3220 mmiowb();
3221 }
3222
3223 /*
3224 * should be run under rtnl lock
3225 */
3226 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3227 {
3228 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3229
3230 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3231
3232 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3233 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3234 barrier();
3235 mmiowb();
3236
3237 return val1;
3238 }
3239
3240 /*
3241 * should be run under rtnl lock
3242 */
3243 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3244 {
3245 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3246 }
3247
3248 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3249 {
3250 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3251 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3252 }
3253
3254 static inline void _print_next_block(int idx, const char *blk)
3255 {
3256 if (idx)
3257 pr_cont(", ");
3258 pr_cont("%s", blk);
3259 }
3260
3261 static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3262 {
3263 int i = 0;
3264 u32 cur_bit = 0;
3265 for (i = 0; sig; i++) {
3266 cur_bit = ((u32)0x1 << i);
3267 if (sig & cur_bit) {
3268 switch (cur_bit) {
3269 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3270 _print_next_block(par_num++, "BRB");
3271 break;
3272 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3273 _print_next_block(par_num++, "PARSER");
3274 break;
3275 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3276 _print_next_block(par_num++, "TSDM");
3277 break;
3278 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3279 _print_next_block(par_num++, "SEARCHER");
3280 break;
3281 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3282 _print_next_block(par_num++, "TSEMI");
3283 break;
3284 }
3285
3286 /* Clear the bit */
3287 sig &= ~cur_bit;
3288 }
3289 }
3290
3291 return par_num;
3292 }
3293
3294 static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3295 {
3296 int i = 0;
3297 u32 cur_bit = 0;
3298 for (i = 0; sig; i++) {
3299 cur_bit = ((u32)0x1 << i);
3300 if (sig & cur_bit) {
3301 switch (cur_bit) {
3302 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3303 _print_next_block(par_num++, "PBCLIENT");
3304 break;
3305 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3306 _print_next_block(par_num++, "QM");
3307 break;
3308 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3309 _print_next_block(par_num++, "XSDM");
3310 break;
3311 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3312 _print_next_block(par_num++, "XSEMI");
3313 break;
3314 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3315 _print_next_block(par_num++, "DOORBELLQ");
3316 break;
3317 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3318 _print_next_block(par_num++, "VAUX PCI CORE");
3319 break;
3320 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3321 _print_next_block(par_num++, "DEBUG");
3322 break;
3323 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3324 _print_next_block(par_num++, "USDM");
3325 break;
3326 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3327 _print_next_block(par_num++, "USEMI");
3328 break;
3329 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3330 _print_next_block(par_num++, "UPB");
3331 break;
3332 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3333 _print_next_block(par_num++, "CSDM");
3334 break;
3335 }
3336
3337 /* Clear the bit */
3338 sig &= ~cur_bit;
3339 }
3340 }
3341
3342 return par_num;
3343 }
3344
3345 static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3346 {
3347 int i = 0;
3348 u32 cur_bit = 0;
3349 for (i = 0; sig; i++) {
3350 cur_bit = ((u32)0x1 << i);
3351 if (sig & cur_bit) {
3352 switch (cur_bit) {
3353 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3354 _print_next_block(par_num++, "CSEMI");
3355 break;
3356 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3357 _print_next_block(par_num++, "PXP");
3358 break;
3359 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3360 _print_next_block(par_num++,
3361 "PXPPCICLOCKCLIENT");
3362 break;
3363 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3364 _print_next_block(par_num++, "CFC");
3365 break;
3366 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3367 _print_next_block(par_num++, "CDU");
3368 break;
3369 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3370 _print_next_block(par_num++, "IGU");
3371 break;
3372 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3373 _print_next_block(par_num++, "MISC");
3374 break;
3375 }
3376
3377 /* Clear the bit */
3378 sig &= ~cur_bit;
3379 }
3380 }
3381
3382 return par_num;
3383 }
3384
3385 static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3386 {
3387 int i = 0;
3388 u32 cur_bit = 0;
3389 for (i = 0; sig; i++) {
3390 cur_bit = ((u32)0x1 << i);
3391 if (sig & cur_bit) {
3392 switch (cur_bit) {
3393 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3394 _print_next_block(par_num++, "MCP ROM");
3395 break;
3396 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3397 _print_next_block(par_num++, "MCP UMP RX");
3398 break;
3399 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3400 _print_next_block(par_num++, "MCP UMP TX");
3401 break;
3402 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3403 _print_next_block(par_num++, "MCP SCPAD");
3404 break;
3405 }
3406
3407 /* Clear the bit */
3408 sig &= ~cur_bit;
3409 }
3410 }
3411
3412 return par_num;
3413 }
3414
3415 static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3416 u32 sig2, u32 sig3)
3417 {
3418 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3419 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3420 int par_num = 0;
3421 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3422 "[0]:0x%08x [1]:0x%08x "
3423 "[2]:0x%08x [3]:0x%08x\n",
3424 sig0 & HW_PRTY_ASSERT_SET_0,
3425 sig1 & HW_PRTY_ASSERT_SET_1,
3426 sig2 & HW_PRTY_ASSERT_SET_2,
3427 sig3 & HW_PRTY_ASSERT_SET_3);
3428 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3429 bp->dev->name);
3430 par_num = bnx2x_print_blocks_with_parity0(
3431 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3432 par_num = bnx2x_print_blocks_with_parity1(
3433 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3434 par_num = bnx2x_print_blocks_with_parity2(
3435 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3436 par_num = bnx2x_print_blocks_with_parity3(
3437 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3438 printk("\n");
3439 return true;
3440 } else
3441 return false;
3442 }
3443
3444 bool bnx2x_chk_parity_attn(struct bnx2x *bp)
3445 {
3446 struct attn_route attn;
3447 int port = BP_PORT(bp);
3448
3449 attn.sig[0] = REG_RD(bp,
3450 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3451 port*4);
3452 attn.sig[1] = REG_RD(bp,
3453 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3454 port*4);
3455 attn.sig[2] = REG_RD(bp,
3456 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3457 port*4);
3458 attn.sig[3] = REG_RD(bp,
3459 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3460 port*4);
3461
3462 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3463 attn.sig[3]);
3464 }
3465
3466
3467 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3468 {
3469 u32 val;
3470 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3471
3472 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3473 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3474 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3475 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3476 "ADDRESS_ERROR\n");
3477 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3478 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3479 "INCORRECT_RCV_BEHAVIOR\n");
3480 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3481 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3482 "WAS_ERROR_ATTN\n");
3483 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3484 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3485 "VF_LENGTH_VIOLATION_ATTN\n");
3486 if (val &
3487 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3488 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3489 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3490 if (val &
3491 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3492 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3493 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3494 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3495 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3496 "TCPL_ERROR_ATTN\n");
3497 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3498 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3499 "TCPL_IN_TWO_RCBS_ATTN\n");
3500 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3501 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3502 "CSSNOOP_FIFO_OVERFLOW\n");
3503 }
3504 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3505 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3506 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3507 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3508 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3509 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3510 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3511 "_ATC_TCPL_TO_NOT_PEND\n");
3512 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3513 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3514 "ATC_GPA_MULTIPLE_HITS\n");
3515 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3516 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3517 "ATC_RCPL_TO_EMPTY_CNT\n");
3518 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3519 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3520 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3521 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3522 "ATC_IREQ_LESS_THAN_STU\n");
3523 }
3524
3525 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3526 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3527 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3528 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3529 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3530 }
3531
3532 }
3533
3534 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3535 {
3536 struct attn_route attn, *group_mask;
3537 int port = BP_PORT(bp);
3538 int index;
3539 u32 reg_addr;
3540 u32 val;
3541 u32 aeu_mask;
3542
3543 /* need to take HW lock because MCP or other port might also
3544 try to handle this event */
3545 bnx2x_acquire_alr(bp);
3546
3547 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
3548 bp->recovery_state = BNX2X_RECOVERY_INIT;
3549 bnx2x_set_reset_in_progress(bp);
3550 schedule_delayed_work(&bp->reset_task, 0);
3551 /* Disable HW interrupts */
3552 bnx2x_int_disable(bp);
3553 bnx2x_release_alr(bp);
3554 /* In case of parity errors don't handle attentions so that
3555 * other function would "see" parity errors.
3556 */
3557 return;
3558 }
3559
3560 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3561 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3562 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3563 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3564 if (CHIP_IS_E2(bp))
3565 attn.sig[4] =
3566 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3567 else
3568 attn.sig[4] = 0;
3569
3570 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3571 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
3572
3573 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3574 if (deasserted & (1 << index)) {
3575 group_mask = &bp->attn_group[index];
3576
3577 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3578 "%08x %08x %08x\n",
3579 index,
3580 group_mask->sig[0], group_mask->sig[1],
3581 group_mask->sig[2], group_mask->sig[3],
3582 group_mask->sig[4]);
3583
3584 bnx2x_attn_int_deasserted4(bp,
3585 attn.sig[4] & group_mask->sig[4]);
3586 bnx2x_attn_int_deasserted3(bp,
3587 attn.sig[3] & group_mask->sig[3]);
3588 bnx2x_attn_int_deasserted1(bp,
3589 attn.sig[1] & group_mask->sig[1]);
3590 bnx2x_attn_int_deasserted2(bp,
3591 attn.sig[2] & group_mask->sig[2]);
3592 bnx2x_attn_int_deasserted0(bp,
3593 attn.sig[0] & group_mask->sig[0]);
3594 }
3595 }
3596
3597 bnx2x_release_alr(bp);
3598
3599 if (bp->common.int_block == INT_BLOCK_HC)
3600 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3601 COMMAND_REG_ATTN_BITS_CLR);
3602 else
3603 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
3604
3605 val = ~deasserted;
3606 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3607 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3608 REG_WR(bp, reg_addr, val);
3609
3610 if (~bp->attn_state & deasserted)
3611 BNX2X_ERR("IGU ERROR\n");
3612
3613 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3614 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3615
3616 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3617 aeu_mask = REG_RD(bp, reg_addr);
3618
3619 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3620 aeu_mask, deasserted);
3621 aeu_mask |= (deasserted & 0x3ff);
3622 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3623
3624 REG_WR(bp, reg_addr, aeu_mask);
3625 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3626
3627 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3628 bp->attn_state &= ~deasserted;
3629 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3630 }
3631
3632 static void bnx2x_attn_int(struct bnx2x *bp)
3633 {
3634 /* read local copy of bits */
3635 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3636 attn_bits);
3637 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3638 attn_bits_ack);
3639 u32 attn_state = bp->attn_state;
3640
3641 /* look for changed bits */
3642 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3643 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3644
3645 DP(NETIF_MSG_HW,
3646 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3647 attn_bits, attn_ack, asserted, deasserted);
3648
3649 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
3650 BNX2X_ERR("BAD attention state\n");
3651
3652 /* handle bits that were raised */
3653 if (asserted)
3654 bnx2x_attn_int_asserted(bp, asserted);
3655
3656 if (deasserted)
3657 bnx2x_attn_int_deasserted(bp, deasserted);
3658 }
3659
3660 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3661 {
3662 /* No memory barriers */
3663 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3664 mmiowb(); /* keep prod updates ordered */
3665 }
3666
3667 #ifdef BCM_CNIC
3668 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3669 union event_ring_elem *elem)
3670 {
3671 if (!bp->cnic_eth_dev.starting_cid ||
3672 cid < bp->cnic_eth_dev.starting_cid)
3673 return 1;
3674
3675 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3676
3677 if (unlikely(elem->message.data.cfc_del_event.error)) {
3678 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3679 cid);
3680 bnx2x_panic_dump(bp);
3681 }
3682 bnx2x_cnic_cfc_comp(bp, cid);
3683 return 0;
3684 }
3685 #endif
3686
3687 static void bnx2x_eq_int(struct bnx2x *bp)
3688 {
3689 u16 hw_cons, sw_cons, sw_prod;
3690 union event_ring_elem *elem;
3691 u32 cid;
3692 u8 opcode;
3693 int spqe_cnt = 0;
3694
3695 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3696
3697 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3698 * when we get the the next-page we nned to adjust so the loop
3699 * condition below will be met. The next element is the size of a
3700 * regular element and hence incrementing by 1
3701 */
3702 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3703 hw_cons++;
3704
3705 /* This function may never run in parallel with itself for a
3706 * specific bp, thus there is no need in "paired" read memory
3707 * barrier here.
3708 */
3709 sw_cons = bp->eq_cons;
3710 sw_prod = bp->eq_prod;
3711
3712 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
3713 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
3714
3715 for (; sw_cons != hw_cons;
3716 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3717
3718
3719 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3720
3721 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3722 opcode = elem->message.opcode;
3723
3724
3725 /* handle eq element */
3726 switch (opcode) {
3727 case EVENT_RING_OPCODE_STAT_QUERY:
3728 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3729 /* nothing to do with stats comp */
3730 continue;
3731
3732 case EVENT_RING_OPCODE_CFC_DEL:
3733 /* handle according to cid range */
3734 /*
3735 * we may want to verify here that the bp state is
3736 * HALTING
3737 */
3738 DP(NETIF_MSG_IFDOWN,
3739 "got delete ramrod for MULTI[%d]\n", cid);
3740 #ifdef BCM_CNIC
3741 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3742 goto next_spqe;
3743 if (cid == BNX2X_FCOE_ETH_CID)
3744 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3745 else
3746 #endif
3747 bnx2x_fp(bp, cid, state) =
3748 BNX2X_FP_STATE_CLOSED;
3749
3750 goto next_spqe;
3751
3752 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3753 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3754 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3755 goto next_spqe;
3756 case EVENT_RING_OPCODE_START_TRAFFIC:
3757 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3758 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3759 goto next_spqe;
3760 }
3761
3762 switch (opcode | bp->state) {
3763 case (EVENT_RING_OPCODE_FUNCTION_START |
3764 BNX2X_STATE_OPENING_WAIT4_PORT):
3765 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3766 bp->state = BNX2X_STATE_FUNC_STARTED;
3767 break;
3768
3769 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3770 BNX2X_STATE_CLOSING_WAIT4_HALT):
3771 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3772 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3773 break;
3774
3775 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3776 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3777 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3778 if (elem->message.data.set_mac_event.echo)
3779 bp->set_mac_pending = 0;
3780 break;
3781
3782 case (EVENT_RING_OPCODE_SET_MAC |
3783 BNX2X_STATE_CLOSING_WAIT4_HALT):
3784 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3785 if (elem->message.data.set_mac_event.echo)
3786 bp->set_mac_pending = 0;
3787 break;
3788 default:
3789 /* unknown event log error and continue */
3790 BNX2X_ERR("Unknown EQ event %d\n",
3791 elem->message.opcode);
3792 }
3793 next_spqe:
3794 spqe_cnt++;
3795 } /* for */
3796
3797 smp_mb__before_atomic_inc();
3798 atomic_add(spqe_cnt, &bp->eq_spq_left);
3799
3800 bp->eq_cons = sw_cons;
3801 bp->eq_prod = sw_prod;
3802 /* Make sure that above mem writes were issued towards the memory */
3803 smp_wmb();
3804
3805 /* update producer */
3806 bnx2x_update_eq_prod(bp, bp->eq_prod);
3807 }
3808
3809 static void bnx2x_sp_task(struct work_struct *work)
3810 {
3811 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
3812 u16 status;
3813
3814 /* Return here if interrupt is disabled */
3815 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3816 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3817 return;
3818 }
3819
3820 status = bnx2x_update_dsb_idx(bp);
3821 /* if (status == 0) */
3822 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
3823
3824 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
3825
3826 /* HW attentions */
3827 if (status & BNX2X_DEF_SB_ATT_IDX) {
3828 bnx2x_attn_int(bp);
3829 status &= ~BNX2X_DEF_SB_ATT_IDX;
3830 }
3831
3832 /* SP events: STAT_QUERY and others */
3833 if (status & BNX2X_DEF_SB_IDX) {
3834 #ifdef BCM_CNIC
3835 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
3836
3837 if ((!NO_FCOE(bp)) &&
3838 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3839 napi_schedule(&bnx2x_fcoe(bp, napi));
3840 #endif
3841 /* Handle EQ completions */
3842 bnx2x_eq_int(bp);
3843
3844 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3845 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3846
3847 status &= ~BNX2X_DEF_SB_IDX;
3848 }
3849
3850 if (unlikely(status))
3851 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3852 status);
3853
3854 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3855 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
3856 }
3857
3858 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3859 {
3860 struct net_device *dev = dev_instance;
3861 struct bnx2x *bp = netdev_priv(dev);
3862
3863 /* Return here if interrupt is disabled */
3864 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3865 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3866 return IRQ_HANDLED;
3867 }
3868
3869 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3870 IGU_INT_DISABLE, 0);
3871
3872 #ifdef BNX2X_STOP_ON_ERROR
3873 if (unlikely(bp->panic))
3874 return IRQ_HANDLED;
3875 #endif
3876
3877 #ifdef BCM_CNIC
3878 {
3879 struct cnic_ops *c_ops;
3880
3881 rcu_read_lock();
3882 c_ops = rcu_dereference(bp->cnic_ops);
3883 if (c_ops)
3884 c_ops->cnic_handler(bp->cnic_data, NULL);
3885 rcu_read_unlock();
3886 }
3887 #endif
3888 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
3889
3890 return IRQ_HANDLED;
3891 }
3892
3893 /* end of slow path */
3894
3895 static void bnx2x_timer(unsigned long data)
3896 {
3897 struct bnx2x *bp = (struct bnx2x *) data;
3898
3899 if (!netif_running(bp->dev))
3900 return;
3901
3902 if (atomic_read(&bp->intr_sem) != 0)
3903 goto timer_restart;
3904
3905 if (poll) {
3906 struct bnx2x_fastpath *fp = &bp->fp[0];
3907 int rc;
3908
3909 bnx2x_tx_int(fp);
3910 rc = bnx2x_rx_int(fp, 1000);
3911 }
3912
3913 if (!BP_NOMCP(bp)) {
3914 int mb_idx = BP_FW_MB_IDX(bp);
3915 u32 drv_pulse;
3916 u32 mcp_pulse;
3917
3918 ++bp->fw_drv_pulse_wr_seq;
3919 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3920 /* TBD - add SYSTEM_TIME */
3921 drv_pulse = bp->fw_drv_pulse_wr_seq;
3922 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
3923
3924 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
3925 MCP_PULSE_SEQ_MASK);
3926 /* The delta between driver pulse and mcp response
3927 * should be 1 (before mcp response) or 0 (after mcp response)
3928 */
3929 if ((drv_pulse != mcp_pulse) &&
3930 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3931 /* someone lost a heartbeat... */
3932 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3933 drv_pulse, mcp_pulse);
3934 }
3935 }
3936
3937 if (bp->state == BNX2X_STATE_OPEN)
3938 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3939
3940 timer_restart:
3941 mod_timer(&bp->timer, jiffies + bp->current_interval);
3942 }
3943
3944 /* end of Statistics */
3945
3946 /* nic init */
3947
3948 /*
3949 * nic init service functions
3950 */
3951
3952 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
3953 {
3954 u32 i;
3955 if (!(len%4) && !(addr%4))
3956 for (i = 0; i < len; i += 4)
3957 REG_WR(bp, addr + i, fill);
3958 else
3959 for (i = 0; i < len; i++)
3960 REG_WR8(bp, addr + i, fill);
3961
3962 }
3963
3964 /* helper: writes FP SP data to FW - data_size in dwords */
3965 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3966 int fw_sb_id,
3967 u32 *sb_data_p,
3968 u32 data_size)
3969 {
3970 int index;
3971 for (index = 0; index < data_size; index++)
3972 REG_WR(bp, BAR_CSTRORM_INTMEM +
3973 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3974 sizeof(u32)*index,
3975 *(sb_data_p + index));
3976 }
3977
3978 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3979 {
3980 u32 *sb_data_p;
3981 u32 data_size = 0;
3982 struct hc_status_block_data_e2 sb_data_e2;
3983 struct hc_status_block_data_e1x sb_data_e1x;
3984
3985 /* disable the function first */
3986 if (CHIP_IS_E2(bp)) {
3987 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3988 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3989 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3990 sb_data_e2.common.p_func.vf_valid = false;
3991 sb_data_p = (u32 *)&sb_data_e2;
3992 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3993 } else {
3994 memset(&sb_data_e1x, 0,
3995 sizeof(struct hc_status_block_data_e1x));
3996 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3997 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3998 sb_data_e1x.common.p_func.vf_valid = false;
3999 sb_data_p = (u32 *)&sb_data_e1x;
4000 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4001 }
4002 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4003
4004 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4005 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4006 CSTORM_STATUS_BLOCK_SIZE);
4007 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4008 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4009 CSTORM_SYNC_BLOCK_SIZE);
4010 }
4011
4012 /* helper: writes SP SB data to FW */
4013 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4014 struct hc_sp_status_block_data *sp_sb_data)
4015 {
4016 int func = BP_FUNC(bp);
4017 int i;
4018 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4019 REG_WR(bp, BAR_CSTRORM_INTMEM +
4020 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4021 i*sizeof(u32),
4022 *((u32 *)sp_sb_data + i));
4023 }
4024
4025 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4026 {
4027 int func = BP_FUNC(bp);
4028 struct hc_sp_status_block_data sp_sb_data;
4029 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4030
4031 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4032 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4033 sp_sb_data.p_func.vf_valid = false;
4034
4035 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4036
4037 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4038 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4039 CSTORM_SP_STATUS_BLOCK_SIZE);
4040 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4041 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4042 CSTORM_SP_SYNC_BLOCK_SIZE);
4043
4044 }
4045
4046
4047 static inline
4048 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4049 int igu_sb_id, int igu_seg_id)
4050 {
4051 hc_sm->igu_sb_id = igu_sb_id;
4052 hc_sm->igu_seg_id = igu_seg_id;
4053 hc_sm->timer_value = 0xFF;
4054 hc_sm->time_to_expire = 0xFFFFFFFF;
4055 }
4056
4057 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4058 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4059 {
4060 int igu_seg_id;
4061
4062 struct hc_status_block_data_e2 sb_data_e2;
4063 struct hc_status_block_data_e1x sb_data_e1x;
4064 struct hc_status_block_sm *hc_sm_p;
4065 struct hc_index_data *hc_index_p;
4066 int data_size;
4067 u32 *sb_data_p;
4068
4069 if (CHIP_INT_MODE_IS_BC(bp))
4070 igu_seg_id = HC_SEG_ACCESS_NORM;
4071 else
4072 igu_seg_id = IGU_SEG_ACCESS_NORM;
4073
4074 bnx2x_zero_fp_sb(bp, fw_sb_id);
4075
4076 if (CHIP_IS_E2(bp)) {
4077 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4078 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4079 sb_data_e2.common.p_func.vf_id = vfid;
4080 sb_data_e2.common.p_func.vf_valid = vf_valid;
4081 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4082 sb_data_e2.common.same_igu_sb_1b = true;
4083 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4084 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4085 hc_sm_p = sb_data_e2.common.state_machine;
4086 hc_index_p = sb_data_e2.index_data;
4087 sb_data_p = (u32 *)&sb_data_e2;
4088 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4089 } else {
4090 memset(&sb_data_e1x, 0,
4091 sizeof(struct hc_status_block_data_e1x));
4092 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4093 sb_data_e1x.common.p_func.vf_id = 0xff;
4094 sb_data_e1x.common.p_func.vf_valid = false;
4095 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4096 sb_data_e1x.common.same_igu_sb_1b = true;
4097 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4098 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4099 hc_sm_p = sb_data_e1x.common.state_machine;
4100 hc_index_p = sb_data_e1x.index_data;
4101 sb_data_p = (u32 *)&sb_data_e1x;
4102 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4103 }
4104
4105 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4106 igu_sb_id, igu_seg_id);
4107 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4108 igu_sb_id, igu_seg_id);
4109
4110 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4111
4112 /* write indecies to HW */
4113 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4114 }
4115
4116 static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4117 u8 sb_index, u8 disable, u16 usec)
4118 {
4119 int port = BP_PORT(bp);
4120 u8 ticks = usec / BNX2X_BTR;
4121
4122 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4123
4124 disable = disable ? 1 : (usec ? 0 : 1);
4125 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4126 }
4127
4128 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4129 u16 tx_usec, u16 rx_usec)
4130 {
4131 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4132 false, rx_usec);
4133 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4134 false, tx_usec);
4135 }
4136
4137 static void bnx2x_init_def_sb(struct bnx2x *bp)
4138 {
4139 struct host_sp_status_block *def_sb = bp->def_status_blk;
4140 dma_addr_t mapping = bp->def_status_blk_mapping;
4141 int igu_sp_sb_index;
4142 int igu_seg_id;
4143 int port = BP_PORT(bp);
4144 int func = BP_FUNC(bp);
4145 int reg_offset;
4146 u64 section;
4147 int index;
4148 struct hc_sp_status_block_data sp_sb_data;
4149 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4150
4151 if (CHIP_INT_MODE_IS_BC(bp)) {
4152 igu_sp_sb_index = DEF_SB_IGU_ID;
4153 igu_seg_id = HC_SEG_ACCESS_DEF;
4154 } else {
4155 igu_sp_sb_index = bp->igu_dsb_id;
4156 igu_seg_id = IGU_SEG_ACCESS_DEF;
4157 }
4158
4159 /* ATTN */
4160 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4161 atten_status_block);
4162 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4163
4164 bp->attn_state = 0;
4165
4166 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4167 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4168 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4169 int sindex;
4170 /* take care of sig[0]..sig[4] */
4171 for (sindex = 0; sindex < 4; sindex++)
4172 bp->attn_group[index].sig[sindex] =
4173 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4174
4175 if (CHIP_IS_E2(bp))
4176 /*
4177 * enable5 is separate from the rest of the registers,
4178 * and therefore the address skip is 4
4179 * and not 16 between the different groups
4180 */
4181 bp->attn_group[index].sig[4] = REG_RD(bp,
4182 reg_offset + 0x10 + 0x4*index);
4183 else
4184 bp->attn_group[index].sig[4] = 0;
4185 }
4186
4187 if (bp->common.int_block == INT_BLOCK_HC) {
4188 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4189 HC_REG_ATTN_MSG0_ADDR_L);
4190
4191 REG_WR(bp, reg_offset, U64_LO(section));
4192 REG_WR(bp, reg_offset + 4, U64_HI(section));
4193 } else if (CHIP_IS_E2(bp)) {
4194 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4195 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4196 }
4197
4198 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4199 sp_sb);
4200
4201 bnx2x_zero_sp_sb(bp);
4202
4203 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4204 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4205 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4206 sp_sb_data.igu_seg_id = igu_seg_id;
4207 sp_sb_data.p_func.pf_id = func;
4208 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4209 sp_sb_data.p_func.vf_id = 0xff;
4210
4211 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4212
4213 bp->stats_pending = 0;
4214 bp->set_mac_pending = 0;
4215
4216 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4217 }
4218
4219 void bnx2x_update_coalesce(struct bnx2x *bp)
4220 {
4221 int i;
4222
4223 for_each_eth_queue(bp, i)
4224 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4225 bp->tx_ticks, bp->rx_ticks);
4226 }
4227
4228 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4229 {
4230 spin_lock_init(&bp->spq_lock);
4231 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4232
4233 bp->spq_prod_idx = 0;
4234 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4235 bp->spq_prod_bd = bp->spq;
4236 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4237 }
4238
4239 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4240 {
4241 int i;
4242 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4243 union event_ring_elem *elem =
4244 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4245
4246 elem->next_page.addr.hi =
4247 cpu_to_le32(U64_HI(bp->eq_mapping +
4248 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4249 elem->next_page.addr.lo =
4250 cpu_to_le32(U64_LO(bp->eq_mapping +
4251 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4252 }
4253 bp->eq_cons = 0;
4254 bp->eq_prod = NUM_EQ_DESC;
4255 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4256 /* we want a warning message before it gets rought... */
4257 atomic_set(&bp->eq_spq_left,
4258 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
4259 }
4260
4261 void bnx2x_push_indir_table(struct bnx2x *bp)
4262 {
4263 int func = BP_FUNC(bp);
4264 int i;
4265
4266 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4267 return;
4268
4269 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4270 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4271 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4272 bp->fp->cl_id + bp->rx_indir_table[i]);
4273 }
4274
4275 static void bnx2x_init_ind_table(struct bnx2x *bp)
4276 {
4277 int i;
4278
4279 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4280 bp->rx_indir_table[i] = i % BNX2X_NUM_ETH_QUEUES(bp);
4281
4282 bnx2x_push_indir_table(bp);
4283 }
4284
4285 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4286 {
4287 int mode = bp->rx_mode;
4288 int port = BP_PORT(bp);
4289 u16 cl_id;
4290 u32 def_q_filters = 0;
4291
4292 /* All but management unicast packets should pass to the host as well */
4293 u32 llh_mask =
4294 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4295 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4296 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4297 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
4298
4299 switch (mode) {
4300 case BNX2X_RX_MODE_NONE: /* no Rx */
4301 def_q_filters = BNX2X_ACCEPT_NONE;
4302 #ifdef BCM_CNIC
4303 if (!NO_FCOE(bp)) {
4304 cl_id = bnx2x_fcoe(bp, cl_id);
4305 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4306 }
4307 #endif
4308 break;
4309
4310 case BNX2X_RX_MODE_NORMAL:
4311 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4312 BNX2X_ACCEPT_MULTICAST;
4313 #ifdef BCM_CNIC
4314 if (!NO_FCOE(bp)) {
4315 cl_id = bnx2x_fcoe(bp, cl_id);
4316 bnx2x_rxq_set_mac_filters(bp, cl_id,
4317 BNX2X_ACCEPT_UNICAST |
4318 BNX2X_ACCEPT_MULTICAST);
4319 }
4320 #endif
4321 break;
4322
4323 case BNX2X_RX_MODE_ALLMULTI:
4324 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4325 BNX2X_ACCEPT_ALL_MULTICAST;
4326 #ifdef BCM_CNIC
4327 /*
4328 * Prevent duplication of multicast packets by configuring FCoE
4329 * L2 Client to receive only matched unicast frames.
4330 */
4331 if (!NO_FCOE(bp)) {
4332 cl_id = bnx2x_fcoe(bp, cl_id);
4333 bnx2x_rxq_set_mac_filters(bp, cl_id,
4334 BNX2X_ACCEPT_UNICAST);
4335 }
4336 #endif
4337 break;
4338
4339 case BNX2X_RX_MODE_PROMISC:
4340 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4341 #ifdef BCM_CNIC
4342 /*
4343 * Prevent packets duplication by configuring DROP_ALL for FCoE
4344 * L2 Client.
4345 */
4346 if (!NO_FCOE(bp)) {
4347 cl_id = bnx2x_fcoe(bp, cl_id);
4348 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4349 }
4350 #endif
4351 /* pass management unicast packets as well */
4352 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
4353 break;
4354
4355 default:
4356 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4357 break;
4358 }
4359
4360 cl_id = BP_L_ID(bp);
4361 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4362
4363 REG_WR(bp,
4364 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4365 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
4366
4367 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4368 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
4369 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4370 "unmatched_ucast 0x%x\n", mode,
4371 bp->mac_filters.ucast_drop_all,
4372 bp->mac_filters.mcast_drop_all,
4373 bp->mac_filters.bcast_drop_all,
4374 bp->mac_filters.ucast_accept_all,
4375 bp->mac_filters.mcast_accept_all,
4376 bp->mac_filters.bcast_accept_all,
4377 bp->mac_filters.unmatched_unicast
4378 );
4379
4380 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
4381 }
4382
4383 static void bnx2x_init_internal_common(struct bnx2x *bp)
4384 {
4385 int i;
4386
4387 if (!CHIP_IS_E1(bp)) {
4388
4389 /* xstorm needs to know whether to add ovlan to packets or not,
4390 * in switch-independent we'll write 0 to here... */
4391 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4392 bp->mf_mode);
4393 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4394 bp->mf_mode);
4395 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4396 bp->mf_mode);
4397 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4398 bp->mf_mode);
4399 }
4400
4401 if (IS_MF_SI(bp))
4402 /*
4403 * In switch independent mode, the TSTORM needs to accept
4404 * packets that failed classification, since approximate match
4405 * mac addresses aren't written to NIG LLH
4406 */
4407 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4408 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4409
4410 /* Zero this manually as its initialization is
4411 currently missing in the initTool */
4412 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4413 REG_WR(bp, BAR_USTRORM_INTMEM +
4414 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4415 if (CHIP_IS_E2(bp)) {
4416 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4417 CHIP_INT_MODE_IS_BC(bp) ?
4418 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4419 }
4420 }
4421
4422 static void bnx2x_init_internal_port(struct bnx2x *bp)
4423 {
4424 /* port */
4425 bnx2x_dcb_init_intmem_pfc(bp);
4426 }
4427
4428 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4429 {
4430 switch (load_code) {
4431 case FW_MSG_CODE_DRV_LOAD_COMMON:
4432 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4433 bnx2x_init_internal_common(bp);
4434 /* no break */
4435
4436 case FW_MSG_CODE_DRV_LOAD_PORT:
4437 bnx2x_init_internal_port(bp);
4438 /* no break */
4439
4440 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4441 /* internal memory per function is
4442 initialized inside bnx2x_pf_init */
4443 break;
4444
4445 default:
4446 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4447 break;
4448 }
4449 }
4450
4451 static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4452 {
4453 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4454
4455 fp->state = BNX2X_FP_STATE_CLOSED;
4456
4457 fp->index = fp->cid = fp_idx;
4458 fp->cl_id = BP_L_ID(bp) + fp_idx;
4459 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4460 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4461 /* qZone id equals to FW (per path) client id */
4462 fp->cl_qzone_id = fp->cl_id +
4463 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4464 ETH_MAX_RX_CLIENTS_E1H);
4465 /* init shortcut */
4466 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4467 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
4468 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4469 /* Setup SB indicies */
4470 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4471 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4472
4473 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4474 "cl_id %d fw_sb %d igu_sb %d\n",
4475 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4476 fp->igu_sb_id);
4477 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4478 fp->fw_sb_id, fp->igu_sb_id);
4479
4480 bnx2x_update_fpsb_idx(fp);
4481 }
4482
4483 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4484 {
4485 int i;
4486
4487 for_each_eth_queue(bp, i)
4488 bnx2x_init_fp_sb(bp, i);
4489 #ifdef BCM_CNIC
4490 if (!NO_FCOE(bp))
4491 bnx2x_init_fcoe_fp(bp);
4492
4493 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4494 BNX2X_VF_ID_INVALID, false,
4495 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4496
4497 #endif
4498
4499 /* ensure status block indices were read */
4500 rmb();
4501
4502 bnx2x_init_def_sb(bp);
4503 bnx2x_update_dsb_idx(bp);
4504 bnx2x_init_rx_rings(bp);
4505 bnx2x_init_tx_rings(bp);
4506 bnx2x_init_sp_ring(bp);
4507 bnx2x_init_eq_ring(bp);
4508 bnx2x_init_internal(bp, load_code);
4509 bnx2x_pf_init(bp);
4510 bnx2x_init_ind_table(bp);
4511 bnx2x_stats_init(bp);
4512
4513 /* At this point, we are ready for interrupts */
4514 atomic_set(&bp->intr_sem, 0);
4515
4516 /* flush all before enabling interrupts */
4517 mb();
4518 mmiowb();
4519
4520 bnx2x_int_enable(bp);
4521
4522 /* Check for SPIO5 */
4523 bnx2x_attn_int_deasserted0(bp,
4524 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4525 AEU_INPUTS_ATTN_BITS_SPIO5);
4526 }
4527
4528 /* end of nic init */
4529
4530 /*
4531 * gzip service functions
4532 */
4533
4534 static int bnx2x_gunzip_init(struct bnx2x *bp)
4535 {
4536 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4537 &bp->gunzip_mapping, GFP_KERNEL);
4538 if (bp->gunzip_buf == NULL)
4539 goto gunzip_nomem1;
4540
4541 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4542 if (bp->strm == NULL)
4543 goto gunzip_nomem2;
4544
4545 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4546 GFP_KERNEL);
4547 if (bp->strm->workspace == NULL)
4548 goto gunzip_nomem3;
4549
4550 return 0;
4551
4552 gunzip_nomem3:
4553 kfree(bp->strm);
4554 bp->strm = NULL;
4555
4556 gunzip_nomem2:
4557 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4558 bp->gunzip_mapping);
4559 bp->gunzip_buf = NULL;
4560
4561 gunzip_nomem1:
4562 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4563 " un-compression\n");
4564 return -ENOMEM;
4565 }
4566
4567 static void bnx2x_gunzip_end(struct bnx2x *bp)
4568 {
4569 kfree(bp->strm->workspace);
4570 kfree(bp->strm);
4571 bp->strm = NULL;
4572
4573 if (bp->gunzip_buf) {
4574 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4575 bp->gunzip_mapping);
4576 bp->gunzip_buf = NULL;
4577 }
4578 }
4579
4580 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
4581 {
4582 int n, rc;
4583
4584 /* check gzip header */
4585 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4586 BNX2X_ERR("Bad gzip header\n");
4587 return -EINVAL;
4588 }
4589
4590 n = 10;
4591
4592 #define FNAME 0x8
4593
4594 if (zbuf[3] & FNAME)
4595 while ((zbuf[n++] != 0) && (n < len));
4596
4597 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
4598 bp->strm->avail_in = len - n;
4599 bp->strm->next_out = bp->gunzip_buf;
4600 bp->strm->avail_out = FW_BUF_SIZE;
4601
4602 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4603 if (rc != Z_OK)
4604 return rc;
4605
4606 rc = zlib_inflate(bp->strm, Z_FINISH);
4607 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4608 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4609 bp->strm->msg);
4610
4611 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4612 if (bp->gunzip_outlen & 0x3)
4613 netdev_err(bp->dev, "Firmware decompression error:"
4614 " gunzip_outlen (%d) not aligned\n",
4615 bp->gunzip_outlen);
4616 bp->gunzip_outlen >>= 2;
4617
4618 zlib_inflateEnd(bp->strm);
4619
4620 if (rc == Z_STREAM_END)
4621 return 0;
4622
4623 return rc;
4624 }
4625
4626 /* nic load/unload */
4627
4628 /*
4629 * General service functions
4630 */
4631
4632 /* send a NIG loopback debug packet */
4633 static void bnx2x_lb_pckt(struct bnx2x *bp)
4634 {
4635 u32 wb_write[3];
4636
4637 /* Ethernet source and destination addresses */
4638 wb_write[0] = 0x55555555;
4639 wb_write[1] = 0x55555555;
4640 wb_write[2] = 0x20; /* SOP */
4641 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4642
4643 /* NON-IP protocol */
4644 wb_write[0] = 0x09000000;
4645 wb_write[1] = 0x55555555;
4646 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4647 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4648 }
4649
4650 /* some of the internal memories
4651 * are not directly readable from the driver
4652 * to test them we send debug packets
4653 */
4654 static int bnx2x_int_mem_test(struct bnx2x *bp)
4655 {
4656 int factor;
4657 int count, i;
4658 u32 val = 0;
4659
4660 if (CHIP_REV_IS_FPGA(bp))
4661 factor = 120;
4662 else if (CHIP_REV_IS_EMUL(bp))
4663 factor = 200;
4664 else
4665 factor = 1;
4666
4667 /* Disable inputs of parser neighbor blocks */
4668 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4669 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4670 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4671 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4672
4673 /* Write 0 to parser credits for CFC search request */
4674 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4675
4676 /* send Ethernet packet */
4677 bnx2x_lb_pckt(bp);
4678
4679 /* TODO do i reset NIG statistic? */
4680 /* Wait until NIG register shows 1 packet of size 0x10 */
4681 count = 1000 * factor;
4682 while (count) {
4683
4684 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4685 val = *bnx2x_sp(bp, wb_data[0]);
4686 if (val == 0x10)
4687 break;
4688
4689 msleep(10);
4690 count--;
4691 }
4692 if (val != 0x10) {
4693 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4694 return -1;
4695 }
4696
4697 /* Wait until PRS register shows 1 packet */
4698 count = 1000 * factor;
4699 while (count) {
4700 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4701 if (val == 1)
4702 break;
4703
4704 msleep(10);
4705 count--;
4706 }
4707 if (val != 0x1) {
4708 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4709 return -2;
4710 }
4711
4712 /* Reset and init BRB, PRS */
4713 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4714 msleep(50);
4715 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4716 msleep(50);
4717 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4718 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4719
4720 DP(NETIF_MSG_HW, "part2\n");
4721
4722 /* Disable inputs of parser neighbor blocks */
4723 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4724 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4725 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4726 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4727
4728 /* Write 0 to parser credits for CFC search request */
4729 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4730
4731 /* send 10 Ethernet packets */
4732 for (i = 0; i < 10; i++)
4733 bnx2x_lb_pckt(bp);
4734
4735 /* Wait until NIG register shows 10 + 1
4736 packets of size 11*0x10 = 0xb0 */
4737 count = 1000 * factor;
4738 while (count) {
4739
4740 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4741 val = *bnx2x_sp(bp, wb_data[0]);
4742 if (val == 0xb0)
4743 break;
4744
4745 msleep(10);
4746 count--;
4747 }
4748 if (val != 0xb0) {
4749 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4750 return -3;
4751 }
4752
4753 /* Wait until PRS register shows 2 packets */
4754 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4755 if (val != 2)
4756 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4757
4758 /* Write 1 to parser credits for CFC search request */
4759 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4760
4761 /* Wait until PRS register shows 3 packets */
4762 msleep(10 * factor);
4763 /* Wait until NIG register shows 1 packet of size 0x10 */
4764 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4765 if (val != 3)
4766 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4767
4768 /* clear NIG EOP FIFO */
4769 for (i = 0; i < 11; i++)
4770 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4771 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4772 if (val != 1) {
4773 BNX2X_ERR("clear of NIG failed\n");
4774 return -4;
4775 }
4776
4777 /* Reset and init BRB, PRS, NIG */
4778 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4779 msleep(50);
4780 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4781 msleep(50);
4782 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4783 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4784 #ifndef BCM_CNIC
4785 /* set NIC mode */
4786 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4787 #endif
4788
4789 /* Enable inputs of parser neighbor blocks */
4790 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4791 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4792 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
4793 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
4794
4795 DP(NETIF_MSG_HW, "done\n");
4796
4797 return 0; /* OK */
4798 }
4799
4800 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
4801 {
4802 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4803 if (CHIP_IS_E2(bp))
4804 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4805 else
4806 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
4807 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4808 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
4809 /*
4810 * mask read length error interrupts in brb for parser
4811 * (parsing unit and 'checksum and crc' unit)
4812 * these errors are legal (PU reads fixed length and CAC can cause
4813 * read length error on truncated packets)
4814 */
4815 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
4816 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4817 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4818 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4819 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4820 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
4821 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4822 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
4823 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4824 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4825 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
4826 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4827 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
4828 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4829 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4830 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4831 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
4832 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4833 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
4834
4835 if (CHIP_REV_IS_FPGA(bp))
4836 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
4837 else if (CHIP_IS_E2(bp))
4838 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4839 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4840 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4841 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4842 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4843 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
4844 else
4845 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
4846 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4847 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4848 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
4849 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4850 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
4851 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4852 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
4853 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4854 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
4855 }
4856
4857 static void bnx2x_reset_common(struct bnx2x *bp)
4858 {
4859 /* reset_common */
4860 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4861 0xd3ffff7f);
4862 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4863 }
4864
4865 static void bnx2x_init_pxp(struct bnx2x *bp)
4866 {
4867 u16 devctl;
4868 int r_order, w_order;
4869
4870 pci_read_config_word(bp->pdev,
4871 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4872 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4873 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4874 if (bp->mrrs == -1)
4875 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4876 else {
4877 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4878 r_order = bp->mrrs;
4879 }
4880
4881 bnx2x_init_pxp_arb(bp, r_order, w_order);
4882 }
4883
4884 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4885 {
4886 int is_required;
4887 u32 val;
4888 int port;
4889
4890 if (BP_NOMCP(bp))
4891 return;
4892
4893 is_required = 0;
4894 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4895 SHARED_HW_CFG_FAN_FAILURE_MASK;
4896
4897 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4898 is_required = 1;
4899
4900 /*
4901 * The fan failure mechanism is usually related to the PHY type since
4902 * the power consumption of the board is affected by the PHY. Currently,
4903 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4904 */
4905 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4906 for (port = PORT_0; port < PORT_MAX; port++) {
4907 is_required |=
4908 bnx2x_fan_failure_det_req(
4909 bp,
4910 bp->common.shmem_base,
4911 bp->common.shmem2_base,
4912 port);
4913 }
4914
4915 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4916
4917 if (is_required == 0)
4918 return;
4919
4920 /* Fan failure is indicated by SPIO 5 */
4921 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4922 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4923
4924 /* set to active low mode */
4925 val = REG_RD(bp, MISC_REG_SPIO_INT);
4926 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
4927 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
4928 REG_WR(bp, MISC_REG_SPIO_INT, val);
4929
4930 /* enable interrupt to signal the IGU */
4931 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4932 val |= (1 << MISC_REGISTERS_SPIO_5);
4933 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4934 }
4935
4936 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4937 {
4938 u32 offset = 0;
4939
4940 if (CHIP_IS_E1(bp))
4941 return;
4942 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4943 return;
4944
4945 switch (BP_ABS_FUNC(bp)) {
4946 case 0:
4947 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4948 break;
4949 case 1:
4950 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4951 break;
4952 case 2:
4953 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4954 break;
4955 case 3:
4956 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4957 break;
4958 case 4:
4959 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4960 break;
4961 case 5:
4962 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4963 break;
4964 case 6:
4965 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4966 break;
4967 case 7:
4968 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4969 break;
4970 default:
4971 return;
4972 }
4973
4974 REG_WR(bp, offset, pretend_func_num);
4975 REG_RD(bp, offset);
4976 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4977 }
4978
4979 static void bnx2x_pf_disable(struct bnx2x *bp)
4980 {
4981 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4982 val &= ~IGU_PF_CONF_FUNC_EN;
4983
4984 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4985 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4986 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4987 }
4988
4989 static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
4990 {
4991 u32 val, i;
4992
4993 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
4994
4995 bnx2x_reset_common(bp);
4996 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4997 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
4998
4999 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
5000 if (!CHIP_IS_E1(bp))
5001 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
5002
5003 if (CHIP_IS_E2(bp)) {
5004 u8 fid;
5005
5006 /**
5007 * 4-port mode or 2-port mode we need to turn of master-enable
5008 * for everyone, after that, turn it back on for self.
5009 * so, we disregard multi-function or not, and always disable
5010 * for all functions on the given path, this means 0,2,4,6 for
5011 * path 0 and 1,3,5,7 for path 1
5012 */
5013 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
5014 if (fid == BP_ABS_FUNC(bp)) {
5015 REG_WR(bp,
5016 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5017 1);
5018 continue;
5019 }
5020
5021 bnx2x_pretend_func(bp, fid);
5022 /* clear pf enable */
5023 bnx2x_pf_disable(bp);
5024 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5025 }
5026 }
5027
5028 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
5029 if (CHIP_IS_E1(bp)) {
5030 /* enable HW interrupt from PXP on USDM overflow
5031 bit 16 on INT_MASK_0 */
5032 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5033 }
5034
5035 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
5036 bnx2x_init_pxp(bp);
5037
5038 #ifdef __BIG_ENDIAN
5039 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5040 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5041 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5042 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5043 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5044 /* make sure this value is 0 */
5045 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5046
5047 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5048 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5049 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5050 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5051 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5052 #endif
5053
5054 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5055
5056 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5057 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5058
5059 /* let the HW do it's magic ... */
5060 msleep(100);
5061 /* finish PXP init */
5062 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5063 if (val != 1) {
5064 BNX2X_ERR("PXP2 CFG failed\n");
5065 return -EBUSY;
5066 }
5067 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5068 if (val != 1) {
5069 BNX2X_ERR("PXP2 RD_INIT failed\n");
5070 return -EBUSY;
5071 }
5072
5073 /* Timers bug workaround E2 only. We need to set the entire ILT to
5074 * have entries with value "0" and valid bit on.
5075 * This needs to be done by the first PF that is loaded in a path
5076 * (i.e. common phase)
5077 */
5078 if (CHIP_IS_E2(bp)) {
5079 struct ilt_client_info ilt_cli;
5080 struct bnx2x_ilt ilt;
5081 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5082 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5083
5084 /* initialize dummy TM client */
5085 ilt_cli.start = 0;
5086 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5087 ilt_cli.client_num = ILT_CLIENT_TM;
5088
5089 /* Step 1: set zeroes to all ilt page entries with valid bit on
5090 * Step 2: set the timers first/last ilt entry to point
5091 * to the entire range to prevent ILT range error for 3rd/4th
5092 * vnic (this code assumes existence of the vnic)
5093 *
5094 * both steps performed by call to bnx2x_ilt_client_init_op()
5095 * with dummy TM client
5096 *
5097 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5098 * and his brother are split registers
5099 */
5100 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5101 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5102 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5103
5104 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5105 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5106 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5107 }
5108
5109
5110 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5111 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5112
5113 if (CHIP_IS_E2(bp)) {
5114 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5115 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5116 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5117
5118 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5119
5120 /* let the HW do it's magic ... */
5121 do {
5122 msleep(200);
5123 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5124 } while (factor-- && (val != 1));
5125
5126 if (val != 1) {
5127 BNX2X_ERR("ATC_INIT failed\n");
5128 return -EBUSY;
5129 }
5130 }
5131
5132 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5133
5134 /* clean the DMAE memory */
5135 bp->dmae_ready = 1;
5136 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5137
5138 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5139 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5140 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5141 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
5142
5143 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5144 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5145 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5146 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5147
5148 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
5149
5150 if (CHIP_MODE_IS_4_PORT(bp))
5151 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
5152
5153 /* QM queues pointers table */
5154 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5155
5156 /* soft reset pulse */
5157 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5158 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5159
5160 #ifdef BCM_CNIC
5161 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5162 #endif
5163
5164 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
5165 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5166
5167 if (!CHIP_REV_IS_SLOW(bp)) {
5168 /* enable hw interrupt from doorbell Q */
5169 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5170 }
5171
5172 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5173 if (CHIP_MODE_IS_4_PORT(bp)) {
5174 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5175 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5176 }
5177
5178 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5179 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5180 #ifndef BCM_CNIC
5181 /* set NIC mode */
5182 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5183 #endif
5184 if (!CHIP_IS_E1(bp))
5185 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
5186
5187 if (CHIP_IS_E2(bp)) {
5188 /* Bit-map indicating which L2 hdrs may appear after the
5189 basic Ethernet header */
5190 int has_ovlan = IS_MF_SD(bp);
5191 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5192 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5193 }
5194
5195 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5196 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5197 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5198 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5199
5200 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5201 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5202 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5203 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5204
5205 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5206 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5207 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5208 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
5209
5210 if (CHIP_MODE_IS_4_PORT(bp))
5211 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5212
5213 /* sync semi rtc */
5214 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5215 0x80000000);
5216 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5217 0x80000000);
5218
5219 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5220 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5221 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
5222
5223 if (CHIP_IS_E2(bp)) {
5224 int has_ovlan = IS_MF_SD(bp);
5225 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5226 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5227 }
5228
5229 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5230 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5231 REG_WR(bp, i, random32());
5232
5233 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5234 #ifdef BCM_CNIC
5235 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5236 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5237 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5238 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5239 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5240 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5241 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5242 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5243 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5244 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5245 #endif
5246 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5247
5248 if (sizeof(union cdu_context) != 1024)
5249 /* we currently assume that a context is 1024 bytes */
5250 dev_alert(&bp->pdev->dev, "please adjust the size "
5251 "of cdu_context(%ld)\n",
5252 (long)sizeof(union cdu_context));
5253
5254 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5255 val = (4 << 24) + (0 << 12) + 1024;
5256 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5257
5258 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5259 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5260 /* enable context validation interrupt from CFC */
5261 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5262
5263 /* set the thresholds to prevent CFC/CDU race */
5264 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5265
5266 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5267
5268 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5269 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5270
5271 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
5272 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
5273
5274 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
5275 /* Reset PCIE errors for debug */
5276 REG_WR(bp, 0x2814, 0xffffffff);
5277 REG_WR(bp, 0x3820, 0xffffffff);
5278
5279 if (CHIP_IS_E2(bp)) {
5280 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5281 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5282 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5283 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5284 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5285 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5286 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5287 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5288 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5289 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5290 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5291 }
5292
5293 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
5294 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
5295 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
5296 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
5297
5298 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
5299 if (!CHIP_IS_E1(bp)) {
5300 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5301 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5302 }
5303 if (CHIP_IS_E2(bp)) {
5304 /* Bit-map indicating which L2 hdrs may appear after the
5305 basic Ethernet header */
5306 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
5307 }
5308
5309 if (CHIP_REV_IS_SLOW(bp))
5310 msleep(200);
5311
5312 /* finish CFC init */
5313 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5314 if (val != 1) {
5315 BNX2X_ERR("CFC LL_INIT failed\n");
5316 return -EBUSY;
5317 }
5318 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5319 if (val != 1) {
5320 BNX2X_ERR("CFC AC_INIT failed\n");
5321 return -EBUSY;
5322 }
5323 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5324 if (val != 1) {
5325 BNX2X_ERR("CFC CAM_INIT failed\n");
5326 return -EBUSY;
5327 }
5328 REG_WR(bp, CFC_REG_DEBUG0, 0);
5329
5330 if (CHIP_IS_E1(bp)) {
5331 /* read NIG statistic
5332 to see if this is our first up since powerup */
5333 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5334 val = *bnx2x_sp(bp, wb_data[0]);
5335
5336 /* do internal memory self test */
5337 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5338 BNX2X_ERR("internal mem self test failed\n");
5339 return -EBUSY;
5340 }
5341 }
5342
5343 bnx2x_setup_fan_failure_detection(bp);
5344
5345 /* clear PXP2 attentions */
5346 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5347
5348 bnx2x_enable_blocks_attention(bp);
5349 if (CHIP_PARITY_ENABLED(bp))
5350 bnx2x_enable_blocks_parity(bp);
5351
5352 if (!BP_NOMCP(bp)) {
5353 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5354 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5355 CHIP_IS_E1x(bp)) {
5356 u32 shmem_base[2], shmem2_base[2];
5357 shmem_base[0] = bp->common.shmem_base;
5358 shmem2_base[0] = bp->common.shmem2_base;
5359 if (CHIP_IS_E2(bp)) {
5360 shmem_base[1] =
5361 SHMEM2_RD(bp, other_shmem_base_addr);
5362 shmem2_base[1] =
5363 SHMEM2_RD(bp, other_shmem2_base_addr);
5364 }
5365 bnx2x_acquire_phy_lock(bp);
5366 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5367 bp->common.chip_id);
5368 bnx2x_release_phy_lock(bp);
5369 }
5370 } else
5371 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5372
5373 return 0;
5374 }
5375
5376 static int bnx2x_init_hw_port(struct bnx2x *bp)
5377 {
5378 int port = BP_PORT(bp);
5379 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
5380 u32 low, high;
5381 u32 val;
5382
5383 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
5384
5385 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5386
5387 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
5388 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
5389
5390 /* Timers bug workaround: disables the pf_master bit in pglue at
5391 * common phase, we need to enable it here before any dmae access are
5392 * attempted. Therefore we manually added the enable-master to the
5393 * port phase (it also happens in the function phase)
5394 */
5395 if (CHIP_IS_E2(bp))
5396 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5397
5398 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5399 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5400 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
5401 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
5402
5403 /* QM cid (connection) count */
5404 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
5405
5406 #ifdef BCM_CNIC
5407 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
5408 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5409 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
5410 #endif
5411
5412 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
5413
5414 if (CHIP_MODE_IS_4_PORT(bp))
5415 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5416
5417 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5418 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5419 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5420 /* no pause for emulation and FPGA */
5421 low = 0;
5422 high = 513;
5423 } else {
5424 if (IS_MF(bp))
5425 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5426 else if (bp->dev->mtu > 4096) {
5427 if (bp->flags & ONE_PORT_FLAG)
5428 low = 160;
5429 else {
5430 val = bp->dev->mtu;
5431 /* (24*1024 + val*4)/256 */
5432 low = 96 + (val/64) +
5433 ((val % 64) ? 1 : 0);
5434 }
5435 } else
5436 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5437 high = low + 56; /* 14*1024/256 */
5438 }
5439 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5440 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5441 }
5442
5443 if (CHIP_MODE_IS_4_PORT(bp)) {
5444 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5445 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5446 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5447 BRB1_REG_MAC_GUARANTIED_0), 40);
5448 }
5449
5450 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
5451
5452 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
5453 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
5454 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
5455 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
5456
5457 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5458 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5459 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5460 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5461 if (CHIP_MODE_IS_4_PORT(bp))
5462 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
5463
5464 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
5465 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
5466
5467 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
5468
5469 if (!CHIP_IS_E2(bp)) {
5470 /* configure PBF to work without PAUSE mtu 9000 */
5471 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5472
5473 /* update threshold */
5474 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5475 /* update init credit */
5476 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5477
5478 /* probe changes */
5479 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5480 udelay(50);
5481 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5482 }
5483
5484 #ifdef BCM_CNIC
5485 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
5486 #endif
5487 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
5488 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
5489
5490 if (CHIP_IS_E1(bp)) {
5491 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5492 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5493 }
5494 bnx2x_init_block(bp, HC_BLOCK, init_stage);
5495
5496 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5497
5498 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
5499 /* init aeu_mask_attn_func_0/1:
5500 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5501 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5502 * bits 4-7 are used for "per vn group attention" */
5503 val = IS_MF(bp) ? 0xF7 : 0x7;
5504 /* Enable DCBX attention for all but E1 */
5505 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5506 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
5507
5508 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5509 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
5510 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
5511 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
5512 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
5513
5514 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
5515
5516 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5517
5518 if (!CHIP_IS_E1(bp)) {
5519 /* 0x2 disable mf_ov, 0x1 enable */
5520 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5521 (IS_MF_SD(bp) ? 0x1 : 0x2));
5522
5523 if (CHIP_IS_E2(bp)) {
5524 val = 0;
5525 switch (bp->mf_mode) {
5526 case MULTI_FUNCTION_SD:
5527 val = 1;
5528 break;
5529 case MULTI_FUNCTION_SI:
5530 val = 2;
5531 break;
5532 }
5533
5534 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5535 NIG_REG_LLH0_CLS_TYPE), val);
5536 }
5537 {
5538 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5539 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5540 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5541 }
5542 }
5543
5544 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
5545 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
5546 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
5547 bp->common.shmem2_base, port)) {
5548 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5549 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5550 val = REG_RD(bp, reg_addr);
5551 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5552 REG_WR(bp, reg_addr, val);
5553 }
5554 bnx2x__link_reset(bp);
5555
5556 return 0;
5557 }
5558
5559 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5560 {
5561 int reg;
5562
5563 if (CHIP_IS_E1(bp))
5564 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5565 else
5566 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5567
5568 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5569 }
5570
5571 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5572 {
5573 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5574 }
5575
5576 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5577 {
5578 u32 i, base = FUNC_ILT_BASE(func);
5579 for (i = base; i < base + ILT_PER_FUNC; i++)
5580 bnx2x_ilt_wr(bp, i, 0);
5581 }
5582
5583 static int bnx2x_init_hw_func(struct bnx2x *bp)
5584 {
5585 int port = BP_PORT(bp);
5586 int func = BP_FUNC(bp);
5587 struct bnx2x_ilt *ilt = BP_ILT(bp);
5588 u16 cdu_ilt_start;
5589 u32 addr, val;
5590 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5591 int i, main_mem_width;
5592
5593 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
5594
5595 /* set MSI reconfigure capability */
5596 if (bp->common.int_block == INT_BLOCK_HC) {
5597 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5598 val = REG_RD(bp, addr);
5599 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5600 REG_WR(bp, addr, val);
5601 }
5602
5603 ilt = BP_ILT(bp);
5604 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
5605
5606 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5607 ilt->lines[cdu_ilt_start + i].page =
5608 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5609 ilt->lines[cdu_ilt_start + i].page_mapping =
5610 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5611 /* cdu ilt pages are allocated manually so there's no need to
5612 set the size */
5613 }
5614 bnx2x_ilt_init_op(bp, INITOP_SET);
5615
5616 #ifdef BCM_CNIC
5617 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
5618
5619 /* T1 hash bits value determines the T1 number of entries */
5620 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5621 #endif
5622
5623 #ifndef BCM_CNIC
5624 /* set NIC mode */
5625 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5626 #endif /* BCM_CNIC */
5627
5628 if (CHIP_IS_E2(bp)) {
5629 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5630
5631 /* Turn on a single ISR mode in IGU if driver is going to use
5632 * INT#x or MSI
5633 */
5634 if (!(bp->flags & USING_MSIX_FLAG))
5635 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5636 /*
5637 * Timers workaround bug: function init part.
5638 * Need to wait 20msec after initializing ILT,
5639 * needed to make sure there are no requests in
5640 * one of the PXP internal queues with "old" ILT addresses
5641 */
5642 msleep(20);
5643 /*
5644 * Master enable - Due to WB DMAE writes performed before this
5645 * register is re-initialized as part of the regular function
5646 * init
5647 */
5648 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5649 /* Enable the function in IGU */
5650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5651 }
5652
5653 bp->dmae_ready = 1;
5654
5655 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5656
5657 if (CHIP_IS_E2(bp))
5658 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5659
5660 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5661 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5662 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5663 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5664 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5665 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5666 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5667 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5668 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5669
5670 if (CHIP_IS_E2(bp)) {
5671 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5672 BP_PATH(bp));
5673 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5674 BP_PATH(bp));
5675 }
5676
5677 if (CHIP_MODE_IS_4_PORT(bp))
5678 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5679
5680 if (CHIP_IS_E2(bp))
5681 REG_WR(bp, QM_REG_PF_EN, 1);
5682
5683 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
5684
5685 if (CHIP_MODE_IS_4_PORT(bp))
5686 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5687
5688 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5689 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5690 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5691 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5692 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5693 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5694 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5695 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5696 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5697 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5698 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
5699 if (CHIP_IS_E2(bp))
5700 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5701
5702 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5703
5704 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
5705
5706 if (CHIP_IS_E2(bp))
5707 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5708
5709 if (IS_MF(bp)) {
5710 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5711 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
5712 }
5713
5714 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5715
5716 /* HC init per function */
5717 if (bp->common.int_block == INT_BLOCK_HC) {
5718 if (CHIP_IS_E1H(bp)) {
5719 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5720
5721 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5722 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5723 }
5724 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5725
5726 } else {
5727 int num_segs, sb_idx, prod_offset;
5728
5729 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5730
5731 if (CHIP_IS_E2(bp)) {
5732 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5733 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5734 }
5735
5736 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5737
5738 if (CHIP_IS_E2(bp)) {
5739 int dsb_idx = 0;
5740 /**
5741 * Producer memory:
5742 * E2 mode: address 0-135 match to the mapping memory;
5743 * 136 - PF0 default prod; 137 - PF1 default prod;
5744 * 138 - PF2 default prod; 139 - PF3 default prod;
5745 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5746 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5747 * 144-147 reserved.
5748 *
5749 * E1.5 mode - In backward compatible mode;
5750 * for non default SB; each even line in the memory
5751 * holds the U producer and each odd line hold
5752 * the C producer. The first 128 producers are for
5753 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5754 * producers are for the DSB for each PF.
5755 * Each PF has five segments: (the order inside each
5756 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5757 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5758 * 144-147 attn prods;
5759 */
5760 /* non-default-status-blocks */
5761 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5762 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5763 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5764 prod_offset = (bp->igu_base_sb + sb_idx) *
5765 num_segs;
5766
5767 for (i = 0; i < num_segs; i++) {
5768 addr = IGU_REG_PROD_CONS_MEMORY +
5769 (prod_offset + i) * 4;
5770 REG_WR(bp, addr, 0);
5771 }
5772 /* send consumer update with value 0 */
5773 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5774 USTORM_ID, 0, IGU_INT_NOP, 1);
5775 bnx2x_igu_clear_sb(bp,
5776 bp->igu_base_sb + sb_idx);
5777 }
5778
5779 /* default-status-blocks */
5780 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5781 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5782
5783 if (CHIP_MODE_IS_4_PORT(bp))
5784 dsb_idx = BP_FUNC(bp);
5785 else
5786 dsb_idx = BP_E1HVN(bp);
5787
5788 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5789 IGU_BC_BASE_DSB_PROD + dsb_idx :
5790 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5791
5792 for (i = 0; i < (num_segs * E1HVN_MAX);
5793 i += E1HVN_MAX) {
5794 addr = IGU_REG_PROD_CONS_MEMORY +
5795 (prod_offset + i)*4;
5796 REG_WR(bp, addr, 0);
5797 }
5798 /* send consumer update with 0 */
5799 if (CHIP_INT_MODE_IS_BC(bp)) {
5800 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5801 USTORM_ID, 0, IGU_INT_NOP, 1);
5802 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5803 CSTORM_ID, 0, IGU_INT_NOP, 1);
5804 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5805 XSTORM_ID, 0, IGU_INT_NOP, 1);
5806 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5807 TSTORM_ID, 0, IGU_INT_NOP, 1);
5808 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5809 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5810 } else {
5811 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5812 USTORM_ID, 0, IGU_INT_NOP, 1);
5813 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5814 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5815 }
5816 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5817
5818 /* !!! these should become driver const once
5819 rf-tool supports split-68 const */
5820 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5821 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5822 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5823 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5824 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5825 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5826 }
5827 }
5828
5829 /* Reset PCIE errors for debug */
5830 REG_WR(bp, 0x2114, 0xffffffff);
5831 REG_WR(bp, 0x2120, 0xffffffff);
5832
5833 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5834 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5835 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5836 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5837 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5838 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5839
5840 if (CHIP_IS_E1x(bp)) {
5841 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5842 main_mem_base = HC_REG_MAIN_MEMORY +
5843 BP_PORT(bp) * (main_mem_size * 4);
5844 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5845 main_mem_width = 8;
5846
5847 val = REG_RD(bp, main_mem_prty_clr);
5848 if (val)
5849 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5850 "block during "
5851 "function init (0x%x)!\n", val);
5852
5853 /* Clear "false" parity errors in MSI-X table */
5854 for (i = main_mem_base;
5855 i < main_mem_base + main_mem_size * 4;
5856 i += main_mem_width) {
5857 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5858 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5859 i, main_mem_width / 4);
5860 }
5861 /* Clear HC parity attention */
5862 REG_RD(bp, main_mem_prty_clr);
5863 }
5864
5865 bnx2x_phy_probe(&bp->link_params);
5866
5867 return 0;
5868 }
5869
5870 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5871 {
5872 int rc = 0;
5873
5874 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5875 BP_ABS_FUNC(bp), load_code);
5876
5877 bp->dmae_ready = 0;
5878 spin_lock_init(&bp->dmae_lock);
5879 rc = bnx2x_gunzip_init(bp);
5880 if (rc)
5881 return rc;
5882
5883 switch (load_code) {
5884 case FW_MSG_CODE_DRV_LOAD_COMMON:
5885 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5886 rc = bnx2x_init_hw_common(bp, load_code);
5887 if (rc)
5888 goto init_hw_err;
5889 /* no break */
5890
5891 case FW_MSG_CODE_DRV_LOAD_PORT:
5892 rc = bnx2x_init_hw_port(bp);
5893 if (rc)
5894 goto init_hw_err;
5895 /* no break */
5896
5897 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5898 rc = bnx2x_init_hw_func(bp);
5899 if (rc)
5900 goto init_hw_err;
5901 break;
5902
5903 default:
5904 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5905 break;
5906 }
5907
5908 if (!BP_NOMCP(bp)) {
5909 int mb_idx = BP_FW_MB_IDX(bp);
5910
5911 bp->fw_drv_pulse_wr_seq =
5912 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
5913 DRV_PULSE_SEQ_MASK);
5914 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5915 }
5916
5917 init_hw_err:
5918 bnx2x_gunzip_end(bp);
5919
5920 return rc;
5921 }
5922
5923 void bnx2x_free_mem(struct bnx2x *bp)
5924 {
5925
5926 #define BNX2X_PCI_FREE(x, y, size) \
5927 do { \
5928 if (x) { \
5929 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
5930 x = NULL; \
5931 y = 0; \
5932 } \
5933 } while (0)
5934
5935 #define BNX2X_FREE(x) \
5936 do { \
5937 if (x) { \
5938 kfree((void *)x); \
5939 x = NULL; \
5940 } \
5941 } while (0)
5942
5943 int i;
5944
5945 /* fastpath */
5946 /* Common */
5947 for_each_queue(bp, i) {
5948 #ifdef BCM_CNIC
5949 /* FCoE client uses default status block */
5950 if (IS_FCOE_IDX(i)) {
5951 union host_hc_status_block *sb =
5952 &bnx2x_fp(bp, i, status_blk);
5953 memset(sb, 0, sizeof(union host_hc_status_block));
5954 bnx2x_fp(bp, i, status_blk_mapping) = 0;
5955 } else {
5956 #endif
5957 /* status blocks */
5958 if (CHIP_IS_E2(bp))
5959 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),
5960 bnx2x_fp(bp, i, status_blk_mapping),
5961 sizeof(struct host_hc_status_block_e2));
5962 else
5963 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),
5964 bnx2x_fp(bp, i, status_blk_mapping),
5965 sizeof(struct host_hc_status_block_e1x));
5966 #ifdef BCM_CNIC
5967 }
5968 #endif
5969 }
5970 /* Rx */
5971 for_each_rx_queue(bp, i) {
5972
5973 /* fastpath rx rings: rx_buf rx_desc rx_comp */
5974 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5975 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5976 bnx2x_fp(bp, i, rx_desc_mapping),
5977 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5978
5979 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5980 bnx2x_fp(bp, i, rx_comp_mapping),
5981 sizeof(struct eth_fast_path_rx_cqe) *
5982 NUM_RCQ_BD);
5983
5984 /* SGE ring */
5985 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5986 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5987 bnx2x_fp(bp, i, rx_sge_mapping),
5988 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5989 }
5990 /* Tx */
5991 for_each_tx_queue(bp, i) {
5992
5993 /* fastpath tx rings: tx_buf tx_desc */
5994 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5995 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5996 bnx2x_fp(bp, i, tx_desc_mapping),
5997 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
5998 }
5999 /* end of fastpath */
6000
6001 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6002 sizeof(struct host_sp_status_block));
6003
6004 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6005 sizeof(struct bnx2x_slowpath));
6006
6007 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6008 bp->context.size);
6009
6010 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6011
6012 BNX2X_FREE(bp->ilt->lines);
6013
6014 #ifdef BCM_CNIC
6015 if (CHIP_IS_E2(bp))
6016 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6017 sizeof(struct host_hc_status_block_e2));
6018 else
6019 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6020 sizeof(struct host_hc_status_block_e1x));
6021
6022 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6023 #endif
6024
6025 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6026
6027 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6028 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6029
6030 BNX2X_FREE(bp->rx_indir_table);
6031
6032 #undef BNX2X_PCI_FREE
6033 #undef BNX2X_KFREE
6034 }
6035
6036 static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
6037 {
6038 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
6039 if (CHIP_IS_E2(bp)) {
6040 bnx2x_fp(bp, index, sb_index_values) =
6041 (__le16 *)status_blk.e2_sb->sb.index_values;
6042 bnx2x_fp(bp, index, sb_running_index) =
6043 (__le16 *)status_blk.e2_sb->sb.running_index;
6044 } else {
6045 bnx2x_fp(bp, index, sb_index_values) =
6046 (__le16 *)status_blk.e1x_sb->sb.index_values;
6047 bnx2x_fp(bp, index, sb_running_index) =
6048 (__le16 *)status_blk.e1x_sb->sb.running_index;
6049 }
6050 }
6051
6052 int bnx2x_alloc_mem(struct bnx2x *bp)
6053 {
6054 #define BNX2X_PCI_ALLOC(x, y, size) \
6055 do { \
6056 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
6057 if (x == NULL) \
6058 goto alloc_mem_err; \
6059 memset(x, 0, size); \
6060 } while (0)
6061
6062 #define BNX2X_ALLOC(x, size) \
6063 do { \
6064 x = kzalloc(size, GFP_KERNEL); \
6065 if (x == NULL) \
6066 goto alloc_mem_err; \
6067 } while (0)
6068
6069 int i;
6070
6071 /* fastpath */
6072 /* Common */
6073 for_each_queue(bp, i) {
6074 union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);
6075 bnx2x_fp(bp, i, bp) = bp;
6076 /* status blocks */
6077 #ifdef BCM_CNIC
6078 if (!IS_FCOE_IDX(i)) {
6079 #endif
6080 if (CHIP_IS_E2(bp))
6081 BNX2X_PCI_ALLOC(sb->e2_sb,
6082 &bnx2x_fp(bp, i, status_blk_mapping),
6083 sizeof(struct host_hc_status_block_e2));
6084 else
6085 BNX2X_PCI_ALLOC(sb->e1x_sb,
6086 &bnx2x_fp(bp, i, status_blk_mapping),
6087 sizeof(struct host_hc_status_block_e1x));
6088 #ifdef BCM_CNIC
6089 }
6090 #endif
6091 set_sb_shortcuts(bp, i);
6092 }
6093 /* Rx */
6094 for_each_queue(bp, i) {
6095
6096 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6097 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6098 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6099 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6100 &bnx2x_fp(bp, i, rx_desc_mapping),
6101 sizeof(struct eth_rx_bd) * NUM_RX_BD);
6102
6103 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6104 &bnx2x_fp(bp, i, rx_comp_mapping),
6105 sizeof(struct eth_fast_path_rx_cqe) *
6106 NUM_RCQ_BD);
6107
6108 /* SGE ring */
6109 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
6110 sizeof(struct sw_rx_page) * NUM_RX_SGE);
6111 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
6112 &bnx2x_fp(bp, i, rx_sge_mapping),
6113 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6114 }
6115 /* Tx */
6116 for_each_queue(bp, i) {
6117
6118 /* fastpath tx rings: tx_buf tx_desc */
6119 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6120 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6121 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6122 &bnx2x_fp(bp, i, tx_desc_mapping),
6123 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
6124 }
6125 /* end of fastpath */
6126
6127 #ifdef BCM_CNIC
6128 if (CHIP_IS_E2(bp))
6129 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6130 sizeof(struct host_hc_status_block_e2));
6131 else
6132 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6133 sizeof(struct host_hc_status_block_e1x));
6134
6135 /* allocate searcher T2 table */
6136 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6137 #endif
6138
6139
6140 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6141 sizeof(struct host_sp_status_block));
6142
6143 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6144 sizeof(struct bnx2x_slowpath));
6145
6146 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
6147
6148 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6149 bp->context.size);
6150
6151 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6152
6153 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6154 goto alloc_mem_err;
6155
6156 /* Slow path ring */
6157 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6158
6159 /* EQ */
6160 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6161 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6162
6163 BNX2X_ALLOC(bp->rx_indir_table, sizeof(bp->rx_indir_table[0]) *
6164 TSTORM_INDIRECTION_TABLE_SIZE);
6165 return 0;
6166
6167 alloc_mem_err:
6168 bnx2x_free_mem(bp);
6169 return -ENOMEM;
6170
6171 #undef BNX2X_PCI_ALLOC
6172 #undef BNX2X_ALLOC
6173 }
6174
6175 /*
6176 * Init service functions
6177 */
6178 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6179 int *state_p, int flags);
6180
6181 int bnx2x_func_start(struct bnx2x *bp)
6182 {
6183 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
6184
6185 /* Wait for completion */
6186 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6187 WAIT_RAMROD_COMMON);
6188 }
6189
6190 static int bnx2x_func_stop(struct bnx2x *bp)
6191 {
6192 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
6193
6194 /* Wait for completion */
6195 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6196 0, &(bp->state), WAIT_RAMROD_COMMON);
6197 }
6198
6199 /**
6200 * Sets a MAC in a CAM for a few L2 Clients for E1x chips
6201 *
6202 * @param bp driver descriptor
6203 * @param set set or clear an entry (1 or 0)
6204 * @param mac pointer to a buffer containing a MAC
6205 * @param cl_bit_vec bit vector of clients to register a MAC for
6206 * @param cam_offset offset in a CAM to use
6207 * @param is_bcast is the set MAC a broadcast address (for E1 only)
6208 */
6209 static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
6210 u32 cl_bit_vec, u8 cam_offset,
6211 u8 is_bcast)
6212 {
6213 struct mac_configuration_cmd *config =
6214 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6215 int ramrod_flags = WAIT_RAMROD_COMMON;
6216
6217 bp->set_mac_pending = 1;
6218
6219 config->hdr.length = 1;
6220 config->hdr.offset = cam_offset;
6221 config->hdr.client_id = 0xff;
6222 /* Mark the single MAC configuration ramrod as opposed to a
6223 * UC/MC list configuration).
6224 */
6225 config->hdr.echo = 1;
6226
6227 /* primary MAC */
6228 config->config_table[0].msb_mac_addr =
6229 swab16(*(u16 *)&mac[0]);
6230 config->config_table[0].middle_mac_addr =
6231 swab16(*(u16 *)&mac[2]);
6232 config->config_table[0].lsb_mac_addr =
6233 swab16(*(u16 *)&mac[4]);
6234 config->config_table[0].clients_bit_vector =
6235 cpu_to_le32(cl_bit_vec);
6236 config->config_table[0].vlan_id = 0;
6237 config->config_table[0].pf_id = BP_FUNC(bp);
6238 if (set)
6239 SET_FLAG(config->config_table[0].flags,
6240 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6241 T_ETH_MAC_COMMAND_SET);
6242 else
6243 SET_FLAG(config->config_table[0].flags,
6244 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6245 T_ETH_MAC_COMMAND_INVALIDATE);
6246
6247 if (is_bcast)
6248 SET_FLAG(config->config_table[0].flags,
6249 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6250
6251 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
6252 (set ? "setting" : "clearing"),
6253 config->config_table[0].msb_mac_addr,
6254 config->config_table[0].middle_mac_addr,
6255 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
6256
6257 mb();
6258
6259 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6260 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6261 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6262
6263 /* Wait for a completion */
6264 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
6265 }
6266
6267 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6268 int *state_p, int flags)
6269 {
6270 /* can take a while if any port is running */
6271 int cnt = 5000;
6272 u8 poll = flags & WAIT_RAMROD_POLL;
6273 u8 common = flags & WAIT_RAMROD_COMMON;
6274
6275 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6276 poll ? "polling" : "waiting", state, idx);
6277
6278 might_sleep();
6279 while (cnt--) {
6280 if (poll) {
6281 if (common)
6282 bnx2x_eq_int(bp);
6283 else {
6284 bnx2x_rx_int(bp->fp, 10);
6285 /* if index is different from 0
6286 * the reply for some commands will
6287 * be on the non default queue
6288 */
6289 if (idx)
6290 bnx2x_rx_int(&bp->fp[idx], 10);
6291 }
6292 }
6293
6294 mb(); /* state is changed by bnx2x_sp_event() */
6295 if (*state_p == state) {
6296 #ifdef BNX2X_STOP_ON_ERROR
6297 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6298 #endif
6299 return 0;
6300 }
6301
6302 msleep(1);
6303
6304 if (bp->panic)
6305 return -EIO;
6306 }
6307
6308 /* timeout! */
6309 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6310 poll ? "polling" : "waiting", state, idx);
6311 #ifdef BNX2X_STOP_ON_ERROR
6312 bnx2x_panic();
6313 #endif
6314
6315 return -EBUSY;
6316 }
6317
6318 static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
6319 {
6320 if (CHIP_IS_E1H(bp))
6321 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6322 else if (CHIP_MODE_IS_4_PORT(bp))
6323 return E2_FUNC_MAX * rel_offset + BP_FUNC(bp);
6324 else
6325 return E2_FUNC_MAX * rel_offset + BP_VN(bp);
6326 }
6327
6328 /**
6329 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6330 * relevant. In addition, current implementation is tuned for a
6331 * single ETH MAC.
6332 */
6333 enum {
6334 LLH_CAM_ISCSI_ETH_LINE = 0,
6335 LLH_CAM_ETH_LINE,
6336 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6337 };
6338
6339 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6340 int set,
6341 unsigned char *dev_addr,
6342 int index)
6343 {
6344 u32 wb_data[2];
6345 u32 mem_offset, ena_offset, mem_index;
6346 /**
6347 * indexes mapping:
6348 * 0..7 - goes to MEM
6349 * 8..15 - goes to MEM2
6350 */
6351
6352 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6353 return;
6354
6355 /* calculate memory start offset according to the mapping
6356 * and index in the memory */
6357 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6358 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6359 NIG_REG_LLH0_FUNC_MEM;
6360 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6361 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6362 mem_index = index;
6363 } else {
6364 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6365 NIG_REG_P0_LLH_FUNC_MEM2;
6366 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6367 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6368 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6369 }
6370
6371 if (set) {
6372 /* LLH_FUNC_MEM is a u64 WB register */
6373 mem_offset += 8*mem_index;
6374
6375 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6376 (dev_addr[4] << 8) | dev_addr[5]);
6377 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6378
6379 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6380 }
6381
6382 /* enable/disable the entry */
6383 REG_WR(bp, ena_offset + 4*mem_index, set);
6384
6385 }
6386
6387 void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6388 {
6389 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6390 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
6391
6392 /* networking MAC */
6393 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6394 (1 << bp->fp->cl_id), cam_offset , 0);
6395
6396 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6397
6398 if (CHIP_IS_E1(bp)) {
6399 /* broadcast MAC */
6400 static const u8 bcast[ETH_ALEN] = {
6401 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6402 };
6403 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6404 }
6405 }
6406
6407 static inline u8 bnx2x_e1_cam_mc_offset(struct bnx2x *bp)
6408 {
6409 return CHIP_REV_IS_SLOW(bp) ?
6410 (BNX2X_MAX_EMUL_MULTI * (1 + BP_PORT(bp))) :
6411 (BNX2X_MAX_MULTICAST * (1 + BP_PORT(bp)));
6412 }
6413
6414 /* set mc list, do not wait as wait implies sleep and
6415 * set_rx_mode can be invoked from non-sleepable context.
6416 *
6417 * Instead we use the same ramrod data buffer each time we need
6418 * to configure a list of addresses, and use the fact that the
6419 * list of MACs is changed in an incremental way and that the
6420 * function is called under the netif_addr_lock. A temporary
6421 * inconsistent CAM configuration (possible in case of a very fast
6422 * sequence of add/del/add on the host side) will shortly be
6423 * restored by the handler of the last ramrod.
6424 */
6425 static int bnx2x_set_e1_mc_list(struct bnx2x *bp)
6426 {
6427 int i = 0, old;
6428 struct net_device *dev = bp->dev;
6429 u8 offset = bnx2x_e1_cam_mc_offset(bp);
6430 struct netdev_hw_addr *ha;
6431 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6432 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6433
6434 if (netdev_mc_count(dev) > BNX2X_MAX_MULTICAST)
6435 return -EINVAL;
6436
6437 netdev_for_each_mc_addr(ha, dev) {
6438 /* copy mac */
6439 config_cmd->config_table[i].msb_mac_addr =
6440 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6441 config_cmd->config_table[i].middle_mac_addr =
6442 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6443 config_cmd->config_table[i].lsb_mac_addr =
6444 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
6445
6446 config_cmd->config_table[i].vlan_id = 0;
6447 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6448 config_cmd->config_table[i].clients_bit_vector =
6449 cpu_to_le32(1 << BP_L_ID(bp));
6450
6451 SET_FLAG(config_cmd->config_table[i].flags,
6452 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6453 T_ETH_MAC_COMMAND_SET);
6454
6455 DP(NETIF_MSG_IFUP,
6456 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6457 config_cmd->config_table[i].msb_mac_addr,
6458 config_cmd->config_table[i].middle_mac_addr,
6459 config_cmd->config_table[i].lsb_mac_addr);
6460 i++;
6461 }
6462 old = config_cmd->hdr.length;
6463 if (old > i) {
6464 for (; i < old; i++) {
6465 if (CAM_IS_INVALID(config_cmd->
6466 config_table[i])) {
6467 /* already invalidated */
6468 break;
6469 }
6470 /* invalidate */
6471 SET_FLAG(config_cmd->config_table[i].flags,
6472 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6473 T_ETH_MAC_COMMAND_INVALIDATE);
6474 }
6475 }
6476
6477 wmb();
6478
6479 config_cmd->hdr.length = i;
6480 config_cmd->hdr.offset = offset;
6481 config_cmd->hdr.client_id = 0xff;
6482 /* Mark that this ramrod doesn't use bp->set_mac_pending for
6483 * synchronization.
6484 */
6485 config_cmd->hdr.echo = 0;
6486
6487 mb();
6488
6489 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6490 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6491 }
6492
6493 void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp)
6494 {
6495 int i;
6496 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6497 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6498 int ramrod_flags = WAIT_RAMROD_COMMON;
6499 u8 offset = bnx2x_e1_cam_mc_offset(bp);
6500
6501 for (i = 0; i < BNX2X_MAX_MULTICAST; i++)
6502 SET_FLAG(config_cmd->config_table[i].flags,
6503 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6504 T_ETH_MAC_COMMAND_INVALIDATE);
6505
6506 wmb();
6507
6508 config_cmd->hdr.length = BNX2X_MAX_MULTICAST;
6509 config_cmd->hdr.offset = offset;
6510 config_cmd->hdr.client_id = 0xff;
6511 /* We'll wait for a completion this time... */
6512 config_cmd->hdr.echo = 1;
6513
6514 bp->set_mac_pending = 1;
6515
6516 mb();
6517
6518 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6519 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6520
6521 /* Wait for a completion */
6522 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6523 ramrod_flags);
6524
6525 }
6526
6527 /* Accept one or more multicasts */
6528 static int bnx2x_set_e1h_mc_list(struct bnx2x *bp)
6529 {
6530 struct net_device *dev = bp->dev;
6531 struct netdev_hw_addr *ha;
6532 u32 mc_filter[MC_HASH_SIZE];
6533 u32 crc, bit, regidx;
6534 int i;
6535
6536 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
6537
6538 netdev_for_each_mc_addr(ha, dev) {
6539 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
6540 bnx2x_mc_addr(ha));
6541
6542 crc = crc32c_le(0, bnx2x_mc_addr(ha),
6543 ETH_ALEN);
6544 bit = (crc >> 24) & 0xff;
6545 regidx = bit >> 5;
6546 bit &= 0x1f;
6547 mc_filter[regidx] |= (1 << bit);
6548 }
6549
6550 for (i = 0; i < MC_HASH_SIZE; i++)
6551 REG_WR(bp, MC_HASH_OFFSET(bp, i),
6552 mc_filter[i]);
6553
6554 return 0;
6555 }
6556
6557 void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp)
6558 {
6559 int i;
6560
6561 for (i = 0; i < MC_HASH_SIZE; i++)
6562 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6563 }
6564
6565 #ifdef BCM_CNIC
6566 /**
6567 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
6568 * MAC(s). This function will wait until the ramdord completion
6569 * returns.
6570 *
6571 * @param bp driver handle
6572 * @param set set or clear the CAM entry
6573 *
6574 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6575 */
6576 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
6577 {
6578 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6579 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
6580 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6581 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
6582 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
6583 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
6584
6585 /* Send a SET_MAC ramrod */
6586 bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,
6587 cam_offset, 0);
6588
6589 bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
6590
6591 return 0;
6592 }
6593
6594 /**
6595 * Set FCoE L2 MAC(s) at the next enties in the CAM after the
6596 * ETH MAC(s). This function will wait until the ramdord
6597 * completion returns.
6598 *
6599 * @param bp driver handle
6600 * @param set set or clear the CAM entry
6601 *
6602 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6603 */
6604 int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6605 {
6606 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6607 /**
6608 * CAM allocation for E1H
6609 * eth unicasts: by func number
6610 * iscsi: by func number
6611 * fip unicast: by func number
6612 * fip multicast: by func number
6613 */
6614 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6615 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6616
6617 return 0;
6618 }
6619
6620 int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6621 {
6622 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6623
6624 /**
6625 * CAM allocation for E1H
6626 * eth unicasts: by func number
6627 * iscsi: by func number
6628 * fip unicast: by func number
6629 * fip multicast: by func number
6630 */
6631 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6632 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6633
6634 return 0;
6635 }
6636 #endif
6637
6638 static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6639 struct bnx2x_client_init_params *params,
6640 u8 activate,
6641 struct client_init_ramrod_data *data)
6642 {
6643 /* Clear the buffer */
6644 memset(data, 0, sizeof(*data));
6645
6646 /* general */
6647 data->general.client_id = params->rxq_params.cl_id;
6648 data->general.statistics_counter_id = params->rxq_params.stat_id;
6649 data->general.statistics_en_flg =
6650 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
6651 data->general.is_fcoe_flg =
6652 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
6653 data->general.activate_flg = activate;
6654 data->general.sp_client_id = params->rxq_params.spcl_id;
6655
6656 /* Rx data */
6657 data->rx.tpa_en_flg =
6658 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6659 data->rx.vmqueue_mode_en_flg = 0;
6660 data->rx.cache_line_alignment_log_size =
6661 params->rxq_params.cache_line_log;
6662 data->rx.enable_dynamic_hc =
6663 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6664 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6665 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6666 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6667
6668 /* We don't set drop flags */
6669 data->rx.drop_ip_cs_err_flg = 0;
6670 data->rx.drop_tcp_cs_err_flg = 0;
6671 data->rx.drop_ttl0_flg = 0;
6672 data->rx.drop_udp_cs_err_flg = 0;
6673
6674 data->rx.inner_vlan_removal_enable_flg =
6675 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6676 data->rx.outer_vlan_removal_enable_flg =
6677 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6678 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6679 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6680 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6681 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6682 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6683 data->rx.bd_page_base.lo =
6684 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6685 data->rx.bd_page_base.hi =
6686 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6687 data->rx.sge_page_base.lo =
6688 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6689 data->rx.sge_page_base.hi =
6690 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6691 data->rx.cqe_page_base.lo =
6692 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6693 data->rx.cqe_page_base.hi =
6694 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6695 data->rx.is_leading_rss =
6696 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6697 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6698
6699 /* Tx data */
6700 data->tx.enforce_security_flg = 0; /* VF specific */
6701 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6702 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6703 data->tx.mtu = 0; /* VF specific */
6704 data->tx.tx_bd_page_base.lo =
6705 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6706 data->tx.tx_bd_page_base.hi =
6707 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6708
6709 /* flow control data */
6710 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6711 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6712 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6713 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6714 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6715 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6716 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6717
6718 data->fc.safc_group_num = params->txq_params.cos;
6719 data->fc.safc_group_en_flg =
6720 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
6721 data->fc.traffic_type =
6722 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6723 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
6724 }
6725
6726 static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6727 {
6728 /* ustorm cxt validation */
6729 cxt->ustorm_ag_context.cdu_usage =
6730 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6731 ETH_CONNECTION_TYPE);
6732 /* xcontext validation */
6733 cxt->xstorm_ag_context.cdu_reserved =
6734 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6735 ETH_CONNECTION_TYPE);
6736 }
6737
6738 static int bnx2x_setup_fw_client(struct bnx2x *bp,
6739 struct bnx2x_client_init_params *params,
6740 u8 activate,
6741 struct client_init_ramrod_data *data,
6742 dma_addr_t data_mapping)
6743 {
6744 u16 hc_usec;
6745 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6746 int ramrod_flags = 0, rc;
6747
6748 /* HC and context validation values */
6749 hc_usec = params->txq_params.hc_rate ?
6750 1000000 / params->txq_params.hc_rate : 0;
6751 bnx2x_update_coalesce_sb_index(bp,
6752 params->txq_params.fw_sb_id,
6753 params->txq_params.sb_cq_index,
6754 !(params->txq_params.flags & QUEUE_FLG_HC),
6755 hc_usec);
6756
6757 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6758
6759 hc_usec = params->rxq_params.hc_rate ?
6760 1000000 / params->rxq_params.hc_rate : 0;
6761 bnx2x_update_coalesce_sb_index(bp,
6762 params->rxq_params.fw_sb_id,
6763 params->rxq_params.sb_cq_index,
6764 !(params->rxq_params.flags & QUEUE_FLG_HC),
6765 hc_usec);
6766
6767 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6768 params->rxq_params.cid);
6769
6770 /* zero stats */
6771 if (params->txq_params.flags & QUEUE_FLG_STATS)
6772 storm_memset_xstats_zero(bp, BP_PORT(bp),
6773 params->txq_params.stat_id);
6774
6775 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6776 storm_memset_ustats_zero(bp, BP_PORT(bp),
6777 params->rxq_params.stat_id);
6778 storm_memset_tstats_zero(bp, BP_PORT(bp),
6779 params->rxq_params.stat_id);
6780 }
6781
6782 /* Fill the ramrod data */
6783 bnx2x_fill_cl_init_data(bp, params, activate, data);
6784
6785 /* SETUP ramrod.
6786 *
6787 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6788 * barrier except from mmiowb() is needed to impose a
6789 * proper ordering of memory operations.
6790 */
6791 mmiowb();
6792
6793
6794 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6795 U64_HI(data_mapping), U64_LO(data_mapping), 0);
6796
6797 /* Wait for completion */
6798 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6799 params->ramrod_params.index,
6800 params->ramrod_params.pstate,
6801 ramrod_flags);
6802 return rc;
6803 }
6804
6805 /**
6806 * Configure interrupt mode according to current configuration.
6807 * In case of MSI-X it will also try to enable MSI-X.
6808 *
6809 * @param bp
6810 *
6811 * @return int
6812 */
6813 static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6814 {
6815 int rc = 0;
6816
6817 switch (bp->int_mode) {
6818 case INT_MODE_MSI:
6819 bnx2x_enable_msi(bp);
6820 /* falling through... */
6821 case INT_MODE_INTx:
6822 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6823 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6824 break;
6825 default:
6826 /* Set number of queues according to bp->multi_mode value */
6827 bnx2x_set_num_queues(bp);
6828
6829 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6830 bp->num_queues);
6831
6832 /* if we can't use MSI-X we only need one fp,
6833 * so try to enable MSI-X with the requested number of fp's
6834 * and fallback to MSI or legacy INTx with one fp
6835 */
6836 rc = bnx2x_enable_msix(bp);
6837 if (rc) {
6838 /* failed to enable MSI-X */
6839 if (bp->multi_mode)
6840 DP(NETIF_MSG_IFUP,
6841 "Multi requested but failed to "
6842 "enable MSI-X (%d), "
6843 "set number of queues to %d\n",
6844 bp->num_queues,
6845 1 + NONE_ETH_CONTEXT_USE);
6846 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6847
6848 if (!(bp->flags & DISABLE_MSI_FLAG))
6849 bnx2x_enable_msi(bp);
6850 }
6851
6852 break;
6853 }
6854
6855 return rc;
6856 }
6857
6858 /* must be called prioir to any HW initializations */
6859 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6860 {
6861 return L2_ILT_LINES(bp);
6862 }
6863
6864 void bnx2x_ilt_set_info(struct bnx2x *bp)
6865 {
6866 struct ilt_client_info *ilt_client;
6867 struct bnx2x_ilt *ilt = BP_ILT(bp);
6868 u16 line = 0;
6869
6870 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6871 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6872
6873 /* CDU */
6874 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6875 ilt_client->client_num = ILT_CLIENT_CDU;
6876 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6877 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6878 ilt_client->start = line;
6879 line += L2_ILT_LINES(bp);
6880 #ifdef BCM_CNIC
6881 line += CNIC_ILT_LINES;
6882 #endif
6883 ilt_client->end = line - 1;
6884
6885 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6886 "flags 0x%x, hw psz %d\n",
6887 ilt_client->start,
6888 ilt_client->end,
6889 ilt_client->page_size,
6890 ilt_client->flags,
6891 ilog2(ilt_client->page_size >> 12));
6892
6893 /* QM */
6894 if (QM_INIT(bp->qm_cid_count)) {
6895 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6896 ilt_client->client_num = ILT_CLIENT_QM;
6897 ilt_client->page_size = QM_ILT_PAGE_SZ;
6898 ilt_client->flags = 0;
6899 ilt_client->start = line;
6900
6901 /* 4 bytes for each cid */
6902 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6903 QM_ILT_PAGE_SZ);
6904
6905 ilt_client->end = line - 1;
6906
6907 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6908 "flags 0x%x, hw psz %d\n",
6909 ilt_client->start,
6910 ilt_client->end,
6911 ilt_client->page_size,
6912 ilt_client->flags,
6913 ilog2(ilt_client->page_size >> 12));
6914
6915 }
6916 /* SRC */
6917 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6918 #ifdef BCM_CNIC
6919 ilt_client->client_num = ILT_CLIENT_SRC;
6920 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6921 ilt_client->flags = 0;
6922 ilt_client->start = line;
6923 line += SRC_ILT_LINES;
6924 ilt_client->end = line - 1;
6925
6926 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6927 "flags 0x%x, hw psz %d\n",
6928 ilt_client->start,
6929 ilt_client->end,
6930 ilt_client->page_size,
6931 ilt_client->flags,
6932 ilog2(ilt_client->page_size >> 12));
6933
6934 #else
6935 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6936 #endif
6937
6938 /* TM */
6939 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6940 #ifdef BCM_CNIC
6941 ilt_client->client_num = ILT_CLIENT_TM;
6942 ilt_client->page_size = TM_ILT_PAGE_SZ;
6943 ilt_client->flags = 0;
6944 ilt_client->start = line;
6945 line += TM_ILT_LINES;
6946 ilt_client->end = line - 1;
6947
6948 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6949 "flags 0x%x, hw psz %d\n",
6950 ilt_client->start,
6951 ilt_client->end,
6952 ilt_client->page_size,
6953 ilt_client->flags,
6954 ilog2(ilt_client->page_size >> 12));
6955
6956 #else
6957 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6958 #endif
6959 }
6960
6961 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6962 int is_leading)
6963 {
6964 struct bnx2x_client_init_params params = { {0} };
6965 int rc;
6966
6967 /* reset IGU state skip FCoE L2 queue */
6968 if (!IS_FCOE_FP(fp))
6969 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6970 IGU_INT_ENABLE, 0);
6971
6972 params.ramrod_params.pstate = &fp->state;
6973 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6974 params.ramrod_params.index = fp->index;
6975 params.ramrod_params.cid = fp->cid;
6976
6977 #ifdef BCM_CNIC
6978 if (IS_FCOE_FP(fp))
6979 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6980
6981 #endif
6982
6983 if (is_leading)
6984 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
6985
6986 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6987
6988 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6989
6990 rc = bnx2x_setup_fw_client(bp, &params, 1,
6991 bnx2x_sp(bp, client_init_data),
6992 bnx2x_sp_mapping(bp, client_init_data));
6993 return rc;
6994 }
6995
6996 static int bnx2x_stop_fw_client(struct bnx2x *bp,
6997 struct bnx2x_client_ramrod_params *p)
6998 {
6999 int rc;
7000
7001 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
7002
7003 /* halt the connection */
7004 *p->pstate = BNX2X_FP_STATE_HALTING;
7005 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
7006 p->cl_id, 0);
7007
7008 /* Wait for completion */
7009 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
7010 p->pstate, poll_flag);
7011 if (rc) /* timeout */
7012 return rc;
7013
7014 *p->pstate = BNX2X_FP_STATE_TERMINATING;
7015 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
7016 p->cl_id, 0);
7017 /* Wait for completion */
7018 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
7019 p->pstate, poll_flag);
7020 if (rc) /* timeout */
7021 return rc;
7022
7023
7024 /* delete cfc entry */
7025 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
7026
7027 /* Wait for completion */
7028 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
7029 p->pstate, WAIT_RAMROD_COMMON);
7030 return rc;
7031 }
7032
7033 static int bnx2x_stop_client(struct bnx2x *bp, int index)
7034 {
7035 struct bnx2x_client_ramrod_params client_stop = {0};
7036 struct bnx2x_fastpath *fp = &bp->fp[index];
7037
7038 client_stop.index = index;
7039 client_stop.cid = fp->cid;
7040 client_stop.cl_id = fp->cl_id;
7041 client_stop.pstate = &(fp->state);
7042 client_stop.poll = 0;
7043
7044 return bnx2x_stop_fw_client(bp, &client_stop);
7045 }
7046
7047
7048 static void bnx2x_reset_func(struct bnx2x *bp)
7049 {
7050 int port = BP_PORT(bp);
7051 int func = BP_FUNC(bp);
7052 int i;
7053 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
7054 (CHIP_IS_E2(bp) ?
7055 offsetof(struct hc_status_block_data_e2, common) :
7056 offsetof(struct hc_status_block_data_e1x, common));
7057 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
7058 int pfid_offset = offsetof(struct pci_entity, pf_id);
7059
7060 /* Disable the function in the FW */
7061 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7062 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7063 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7064 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7065
7066 /* FP SBs */
7067 for_each_eth_queue(bp, i) {
7068 struct bnx2x_fastpath *fp = &bp->fp[i];
7069 REG_WR8(bp,
7070 BAR_CSTRORM_INTMEM +
7071 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
7072 + pfunc_offset_fp + pfid_offset,
7073 HC_FUNCTION_DISABLED);
7074 }
7075
7076 /* SP SB */
7077 REG_WR8(bp,
7078 BAR_CSTRORM_INTMEM +
7079 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
7080 pfunc_offset_sp + pfid_offset,
7081 HC_FUNCTION_DISABLED);
7082
7083
7084 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7085 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7086 0);
7087
7088 /* Configure IGU */
7089 if (bp->common.int_block == INT_BLOCK_HC) {
7090 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7091 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7092 } else {
7093 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7094 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7095 }
7096
7097 #ifdef BCM_CNIC
7098 /* Disable Timer scan */
7099 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7100 /*
7101 * Wait for at least 10ms and up to 2 second for the timers scan to
7102 * complete
7103 */
7104 for (i = 0; i < 200; i++) {
7105 msleep(10);
7106 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7107 break;
7108 }
7109 #endif
7110 /* Clear ILT */
7111 bnx2x_clear_func_ilt(bp, func);
7112
7113 /* Timers workaround bug for E2: if this is vnic-3,
7114 * we need to set the entire ilt range for this timers.
7115 */
7116 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
7117 struct ilt_client_info ilt_cli;
7118 /* use dummy TM client */
7119 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7120 ilt_cli.start = 0;
7121 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7122 ilt_cli.client_num = ILT_CLIENT_TM;
7123
7124 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7125 }
7126
7127 /* this assumes that reset_port() called before reset_func()*/
7128 if (CHIP_IS_E2(bp))
7129 bnx2x_pf_disable(bp);
7130
7131 bp->dmae_ready = 0;
7132 }
7133
7134 static void bnx2x_reset_port(struct bnx2x *bp)
7135 {
7136 int port = BP_PORT(bp);
7137 u32 val;
7138
7139 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7140
7141 /* Do not rcv packets to BRB */
7142 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7143 /* Do not direct rcv packets that are not for MCP to the BRB */
7144 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7145 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7146
7147 /* Configure AEU */
7148 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7149
7150 msleep(100);
7151 /* Check for BRB port occupancy */
7152 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7153 if (val)
7154 DP(NETIF_MSG_IFDOWN,
7155 "BRB1 is not empty %d blocks are occupied\n", val);
7156
7157 /* TODO: Close Doorbell port? */
7158 }
7159
7160 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7161 {
7162 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
7163 BP_ABS_FUNC(bp), reset_code);
7164
7165 switch (reset_code) {
7166 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7167 bnx2x_reset_port(bp);
7168 bnx2x_reset_func(bp);
7169 bnx2x_reset_common(bp);
7170 break;
7171
7172 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7173 bnx2x_reset_port(bp);
7174 bnx2x_reset_func(bp);
7175 break;
7176
7177 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7178 bnx2x_reset_func(bp);
7179 break;
7180
7181 default:
7182 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7183 break;
7184 }
7185 }
7186
7187 #ifdef BCM_CNIC
7188 static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7189 {
7190 if (bp->flags & FCOE_MACS_SET) {
7191 if (!IS_MF_SD(bp))
7192 bnx2x_set_fip_eth_mac_addr(bp, 0);
7193
7194 bnx2x_set_all_enode_macs(bp, 0);
7195
7196 bp->flags &= ~FCOE_MACS_SET;
7197 }
7198 }
7199 #endif
7200
7201 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7202 {
7203 int port = BP_PORT(bp);
7204 u32 reset_code = 0;
7205 int i, cnt, rc;
7206
7207 /* Wait until tx fastpath tasks complete */
7208 for_each_tx_queue(bp, i) {
7209 struct bnx2x_fastpath *fp = &bp->fp[i];
7210
7211 cnt = 1000;
7212 while (bnx2x_has_tx_work_unload(fp)) {
7213
7214 if (!cnt) {
7215 BNX2X_ERR("timeout waiting for queue[%d]\n",
7216 i);
7217 #ifdef BNX2X_STOP_ON_ERROR
7218 bnx2x_panic();
7219 return -EBUSY;
7220 #else
7221 break;
7222 #endif
7223 }
7224 cnt--;
7225 msleep(1);
7226 }
7227 }
7228 /* Give HW time to discard old tx messages */
7229 msleep(1);
7230
7231 bnx2x_set_eth_mac(bp, 0);
7232
7233 bnx2x_invalidate_uc_list(bp);
7234
7235 if (CHIP_IS_E1(bp))
7236 bnx2x_invalidate_e1_mc_list(bp);
7237 else {
7238 bnx2x_invalidate_e1h_mc_list(bp);
7239 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7240 }
7241
7242 #ifdef BCM_CNIC
7243 bnx2x_del_fcoe_eth_macs(bp);
7244 #endif
7245
7246 if (unload_mode == UNLOAD_NORMAL)
7247 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7248
7249 else if (bp->flags & NO_WOL_FLAG)
7250 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7251
7252 else if (bp->wol) {
7253 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7254 u8 *mac_addr = bp->dev->dev_addr;
7255 u32 val;
7256 /* The mac address is written to entries 1-4 to
7257 preserve entry 0 which is used by the PMF */
7258 u8 entry = (BP_E1HVN(bp) + 1)*8;
7259
7260 val = (mac_addr[0] << 8) | mac_addr[1];
7261 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7262
7263 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7264 (mac_addr[4] << 8) | mac_addr[5];
7265 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7266
7267 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7268
7269 } else
7270 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7271
7272 /* Close multi and leading connections
7273 Completions for ramrods are collected in a synchronous way */
7274 for_each_queue(bp, i)
7275
7276 if (bnx2x_stop_client(bp, i))
7277 #ifdef BNX2X_STOP_ON_ERROR
7278 return;
7279 #else
7280 goto unload_error;
7281 #endif
7282
7283 rc = bnx2x_func_stop(bp);
7284 if (rc) {
7285 BNX2X_ERR("Function stop failed!\n");
7286 #ifdef BNX2X_STOP_ON_ERROR
7287 return;
7288 #else
7289 goto unload_error;
7290 #endif
7291 }
7292 #ifndef BNX2X_STOP_ON_ERROR
7293 unload_error:
7294 #endif
7295 if (!BP_NOMCP(bp))
7296 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7297 else {
7298 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7299 "%d, %d, %d\n", BP_PATH(bp),
7300 load_count[BP_PATH(bp)][0],
7301 load_count[BP_PATH(bp)][1],
7302 load_count[BP_PATH(bp)][2]);
7303 load_count[BP_PATH(bp)][0]--;
7304 load_count[BP_PATH(bp)][1 + port]--;
7305 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7306 "%d, %d, %d\n", BP_PATH(bp),
7307 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7308 load_count[BP_PATH(bp)][2]);
7309 if (load_count[BP_PATH(bp)][0] == 0)
7310 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7311 else if (load_count[BP_PATH(bp)][1 + port] == 0)
7312 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7313 else
7314 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7315 }
7316
7317 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7318 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7319 bnx2x__link_reset(bp);
7320
7321 /* Disable HW interrupts, NAPI */
7322 bnx2x_netif_stop(bp, 1);
7323
7324 /* Release IRQs */
7325 bnx2x_free_irq(bp);
7326
7327 /* Reset the chip */
7328 bnx2x_reset_chip(bp, reset_code);
7329
7330 /* Report UNLOAD_DONE to MCP */
7331 if (!BP_NOMCP(bp))
7332 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7333
7334 }
7335
7336 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7337 {
7338 u32 val;
7339
7340 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7341
7342 if (CHIP_IS_E1(bp)) {
7343 int port = BP_PORT(bp);
7344 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7345 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7346
7347 val = REG_RD(bp, addr);
7348 val &= ~(0x300);
7349 REG_WR(bp, addr, val);
7350 } else if (CHIP_IS_E1H(bp)) {
7351 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7352 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7353 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7354 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7355 }
7356 }
7357
7358 /* Close gates #2, #3 and #4: */
7359 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7360 {
7361 u32 val, addr;
7362
7363 /* Gates #2 and #4a are closed/opened for "not E1" only */
7364 if (!CHIP_IS_E1(bp)) {
7365 /* #4 */
7366 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7367 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7368 close ? (val | 0x1) : (val & (~(u32)1)));
7369 /* #2 */
7370 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7371 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7372 close ? (val | 0x1) : (val & (~(u32)1)));
7373 }
7374
7375 /* #3 */
7376 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7377 val = REG_RD(bp, addr);
7378 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7379
7380 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7381 close ? "closing" : "opening");
7382 mmiowb();
7383 }
7384
7385 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7386
7387 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7388 {
7389 /* Do some magic... */
7390 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7391 *magic_val = val & SHARED_MF_CLP_MAGIC;
7392 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7393 }
7394
7395 /* Restore the value of the `magic' bit.
7396 *
7397 * @param pdev Device handle.
7398 * @param magic_val Old value of the `magic' bit.
7399 */
7400 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7401 {
7402 /* Restore the `magic' bit value... */
7403 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7404 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7405 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7406 }
7407
7408 /**
7409 * Prepares for MCP reset: takes care of CLP configurations.
7410 *
7411 * @param bp
7412 * @param magic_val Old value of 'magic' bit.
7413 */
7414 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7415 {
7416 u32 shmem;
7417 u32 validity_offset;
7418
7419 DP(NETIF_MSG_HW, "Starting\n");
7420
7421 /* Set `magic' bit in order to save MF config */
7422 if (!CHIP_IS_E1(bp))
7423 bnx2x_clp_reset_prep(bp, magic_val);
7424
7425 /* Get shmem offset */
7426 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7427 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7428
7429 /* Clear validity map flags */
7430 if (shmem > 0)
7431 REG_WR(bp, shmem + validity_offset, 0);
7432 }
7433
7434 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7435 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7436
7437 /* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,
7438 * depending on the HW type.
7439 *
7440 * @param bp
7441 */
7442 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7443 {
7444 /* special handling for emulation and FPGA,
7445 wait 10 times longer */
7446 if (CHIP_REV_IS_SLOW(bp))
7447 msleep(MCP_ONE_TIMEOUT*10);
7448 else
7449 msleep(MCP_ONE_TIMEOUT);
7450 }
7451
7452 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7453 {
7454 u32 shmem, cnt, validity_offset, val;
7455 int rc = 0;
7456
7457 msleep(100);
7458
7459 /* Get shmem offset */
7460 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7461 if (shmem == 0) {
7462 BNX2X_ERR("Shmem 0 return failure\n");
7463 rc = -ENOTTY;
7464 goto exit_lbl;
7465 }
7466
7467 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7468
7469 /* Wait for MCP to come up */
7470 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7471 /* TBD: its best to check validity map of last port.
7472 * currently checks on port 0.
7473 */
7474 val = REG_RD(bp, shmem + validity_offset);
7475 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7476 shmem + validity_offset, val);
7477
7478 /* check that shared memory is valid. */
7479 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7480 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7481 break;
7482
7483 bnx2x_mcp_wait_one(bp);
7484 }
7485
7486 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7487
7488 /* Check that shared memory is valid. This indicates that MCP is up. */
7489 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7490 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7491 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7492 rc = -ENOTTY;
7493 goto exit_lbl;
7494 }
7495
7496 exit_lbl:
7497 /* Restore the `magic' bit value */
7498 if (!CHIP_IS_E1(bp))
7499 bnx2x_clp_reset_done(bp, magic_val);
7500
7501 return rc;
7502 }
7503
7504 static void bnx2x_pxp_prep(struct bnx2x *bp)
7505 {
7506 if (!CHIP_IS_E1(bp)) {
7507 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7508 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7509 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7510 mmiowb();
7511 }
7512 }
7513
7514 /*
7515 * Reset the whole chip except for:
7516 * - PCIE core
7517 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7518 * one reset bit)
7519 * - IGU
7520 * - MISC (including AEU)
7521 * - GRC
7522 * - RBCN, RBCP
7523 */
7524 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7525 {
7526 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7527
7528 not_reset_mask1 =
7529 MISC_REGISTERS_RESET_REG_1_RST_HC |
7530 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7531 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7532
7533 not_reset_mask2 =
7534 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7535 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7536 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7537 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7538 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7539 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7540 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7541 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7542
7543 reset_mask1 = 0xffffffff;
7544
7545 if (CHIP_IS_E1(bp))
7546 reset_mask2 = 0xffff;
7547 else
7548 reset_mask2 = 0x1ffff;
7549
7550 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7551 reset_mask1 & (~not_reset_mask1));
7552 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7553 reset_mask2 & (~not_reset_mask2));
7554
7555 barrier();
7556 mmiowb();
7557
7558 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7559 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7560 mmiowb();
7561 }
7562
7563 static int bnx2x_process_kill(struct bnx2x *bp)
7564 {
7565 int cnt = 1000;
7566 u32 val = 0;
7567 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7568
7569
7570 /* Empty the Tetris buffer, wait for 1s */
7571 do {
7572 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7573 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7574 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7575 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7576 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7577 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7578 ((port_is_idle_0 & 0x1) == 0x1) &&
7579 ((port_is_idle_1 & 0x1) == 0x1) &&
7580 (pgl_exp_rom2 == 0xffffffff))
7581 break;
7582 msleep(1);
7583 } while (cnt-- > 0);
7584
7585 if (cnt <= 0) {
7586 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7587 " are still"
7588 " outstanding read requests after 1s!\n");
7589 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7590 " port_is_idle_0=0x%08x,"
7591 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7592 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7593 pgl_exp_rom2);
7594 return -EAGAIN;
7595 }
7596
7597 barrier();
7598
7599 /* Close gates #2, #3 and #4 */
7600 bnx2x_set_234_gates(bp, true);
7601
7602 /* TBD: Indicate that "process kill" is in progress to MCP */
7603
7604 /* Clear "unprepared" bit */
7605 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7606 barrier();
7607
7608 /* Make sure all is written to the chip before the reset */
7609 mmiowb();
7610
7611 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7612 * PSWHST, GRC and PSWRD Tetris buffer.
7613 */
7614 msleep(1);
7615
7616 /* Prepare to chip reset: */
7617 /* MCP */
7618 bnx2x_reset_mcp_prep(bp, &val);
7619
7620 /* PXP */
7621 bnx2x_pxp_prep(bp);
7622 barrier();
7623
7624 /* reset the chip */
7625 bnx2x_process_kill_chip_reset(bp);
7626 barrier();
7627
7628 /* Recover after reset: */
7629 /* MCP */
7630 if (bnx2x_reset_mcp_comp(bp, val))
7631 return -EAGAIN;
7632
7633 /* PXP */
7634 bnx2x_pxp_prep(bp);
7635
7636 /* Open the gates #2, #3 and #4 */
7637 bnx2x_set_234_gates(bp, false);
7638
7639 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7640 * reset state, re-enable attentions. */
7641
7642 return 0;
7643 }
7644
7645 static int bnx2x_leader_reset(struct bnx2x *bp)
7646 {
7647 int rc = 0;
7648 /* Try to recover after the failure */
7649 if (bnx2x_process_kill(bp)) {
7650 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7651 bp->dev->name);
7652 rc = -EAGAIN;
7653 goto exit_leader_reset;
7654 }
7655
7656 /* Clear "reset is in progress" bit and update the driver state */
7657 bnx2x_set_reset_done(bp);
7658 bp->recovery_state = BNX2X_RECOVERY_DONE;
7659
7660 exit_leader_reset:
7661 bp->is_leader = 0;
7662 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7663 smp_wmb();
7664 return rc;
7665 }
7666
7667 /* Assumption: runs under rtnl lock. This together with the fact
7668 * that it's called only from bnx2x_reset_task() ensure that it
7669 * will never be called when netif_running(bp->dev) is false.
7670 */
7671 static void bnx2x_parity_recover(struct bnx2x *bp)
7672 {
7673 DP(NETIF_MSG_HW, "Handling parity\n");
7674 while (1) {
7675 switch (bp->recovery_state) {
7676 case BNX2X_RECOVERY_INIT:
7677 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7678 /* Try to get a LEADER_LOCK HW lock */
7679 if (bnx2x_trylock_hw_lock(bp,
7680 HW_LOCK_RESOURCE_RESERVED_08))
7681 bp->is_leader = 1;
7682
7683 /* Stop the driver */
7684 /* If interface has been removed - break */
7685 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7686 return;
7687
7688 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7689 /* Ensure "is_leader" and "recovery_state"
7690 * update values are seen on other CPUs
7691 */
7692 smp_wmb();
7693 break;
7694
7695 case BNX2X_RECOVERY_WAIT:
7696 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7697 if (bp->is_leader) {
7698 u32 load_counter = bnx2x_get_load_cnt(bp);
7699 if (load_counter) {
7700 /* Wait until all other functions get
7701 * down.
7702 */
7703 schedule_delayed_work(&bp->reset_task,
7704 HZ/10);
7705 return;
7706 } else {
7707 /* If all other functions got down -
7708 * try to bring the chip back to
7709 * normal. In any case it's an exit
7710 * point for a leader.
7711 */
7712 if (bnx2x_leader_reset(bp) ||
7713 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7714 printk(KERN_ERR"%s: Recovery "
7715 "has failed. Power cycle is "
7716 "needed.\n", bp->dev->name);
7717 /* Disconnect this device */
7718 netif_device_detach(bp->dev);
7719 /* Block ifup for all function
7720 * of this ASIC until
7721 * "process kill" or power
7722 * cycle.
7723 */
7724 bnx2x_set_reset_in_progress(bp);
7725 /* Shut down the power */
7726 bnx2x_set_power_state(bp,
7727 PCI_D3hot);
7728 return;
7729 }
7730
7731 return;
7732 }
7733 } else { /* non-leader */
7734 if (!bnx2x_reset_is_done(bp)) {
7735 /* Try to get a LEADER_LOCK HW lock as
7736 * long as a former leader may have
7737 * been unloaded by the user or
7738 * released a leadership by another
7739 * reason.
7740 */
7741 if (bnx2x_trylock_hw_lock(bp,
7742 HW_LOCK_RESOURCE_RESERVED_08)) {
7743 /* I'm a leader now! Restart a
7744 * switch case.
7745 */
7746 bp->is_leader = 1;
7747 break;
7748 }
7749
7750 schedule_delayed_work(&bp->reset_task,
7751 HZ/10);
7752 return;
7753
7754 } else { /* A leader has completed
7755 * the "process kill". It's an exit
7756 * point for a non-leader.
7757 */
7758 bnx2x_nic_load(bp, LOAD_NORMAL);
7759 bp->recovery_state =
7760 BNX2X_RECOVERY_DONE;
7761 smp_wmb();
7762 return;
7763 }
7764 }
7765 default:
7766 return;
7767 }
7768 }
7769 }
7770
7771 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7772 * scheduled on a general queue in order to prevent a dead lock.
7773 */
7774 static void bnx2x_reset_task(struct work_struct *work)
7775 {
7776 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
7777
7778 #ifdef BNX2X_STOP_ON_ERROR
7779 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7780 " so reset not done to allow debug dump,\n"
7781 KERN_ERR " you will need to reboot when done\n");
7782 return;
7783 #endif
7784
7785 rtnl_lock();
7786
7787 if (!netif_running(bp->dev))
7788 goto reset_task_exit;
7789
7790 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7791 bnx2x_parity_recover(bp);
7792 else {
7793 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7794 bnx2x_nic_load(bp, LOAD_NORMAL);
7795 }
7796
7797 reset_task_exit:
7798 rtnl_unlock();
7799 }
7800
7801 /* end of nic load/unload */
7802
7803 /*
7804 * Init service functions
7805 */
7806
7807 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
7808 {
7809 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7810 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7811 return base + (BP_ABS_FUNC(bp)) * stride;
7812 }
7813
7814 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
7815 {
7816 u32 reg = bnx2x_get_pretend_reg(bp);
7817
7818 /* Flush all outstanding writes */
7819 mmiowb();
7820
7821 /* Pretend to be function 0 */
7822 REG_WR(bp, reg, 0);
7823 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
7824
7825 /* From now we are in the "like-E1" mode */
7826 bnx2x_int_disable(bp);
7827
7828 /* Flush all outstanding writes */
7829 mmiowb();
7830
7831 /* Restore the original function */
7832 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7833 REG_RD(bp, reg);
7834 }
7835
7836 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
7837 {
7838 if (CHIP_IS_E1(bp))
7839 bnx2x_int_disable(bp);
7840 else
7841 bnx2x_undi_int_disable_e1h(bp);
7842 }
7843
7844 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7845 {
7846 u32 val;
7847
7848 /* Check if there is any driver already loaded */
7849 val = REG_RD(bp, MISC_REG_UNPREPARED);
7850 if (val == 0x1) {
7851 /* Check if it is the UNDI driver
7852 * UNDI driver initializes CID offset for normal bell to 0x7
7853 */
7854 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7855 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7856 if (val == 0x7) {
7857 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7858 /* save our pf_num */
7859 int orig_pf_num = bp->pf_num;
7860 u32 swap_en;
7861 u32 swap_val;
7862
7863 /* clear the UNDI indication */
7864 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7865
7866 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7867
7868 /* try unload UNDI on port 0 */
7869 bp->pf_num = 0;
7870 bp->fw_seq =
7871 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7872 DRV_MSG_SEQ_NUMBER_MASK);
7873 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7874
7875 /* if UNDI is loaded on the other port */
7876 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7877
7878 /* send "DONE" for previous unload */
7879 bnx2x_fw_command(bp,
7880 DRV_MSG_CODE_UNLOAD_DONE, 0);
7881
7882 /* unload UNDI on port 1 */
7883 bp->pf_num = 1;
7884 bp->fw_seq =
7885 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7886 DRV_MSG_SEQ_NUMBER_MASK);
7887 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7888
7889 bnx2x_fw_command(bp, reset_code, 0);
7890 }
7891
7892 /* now it's safe to release the lock */
7893 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7894
7895 bnx2x_undi_int_disable(bp);
7896
7897 /* close input traffic and wait for it */
7898 /* Do not rcv packets to BRB */
7899 REG_WR(bp,
7900 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7901 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7902 /* Do not direct rcv packets that are not for MCP to
7903 * the BRB */
7904 REG_WR(bp,
7905 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7906 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7907 /* clear AEU */
7908 REG_WR(bp,
7909 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7910 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7911 msleep(10);
7912
7913 /* save NIG port swap info */
7914 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7915 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7916 /* reset device */
7917 REG_WR(bp,
7918 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7919 0xd3ffffff);
7920 REG_WR(bp,
7921 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7922 0x1403);
7923 /* take the NIG out of reset and restore swap values */
7924 REG_WR(bp,
7925 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7926 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7927 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7928 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7929
7930 /* send unload done to the MCP */
7931 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7932
7933 /* restore our func and fw_seq */
7934 bp->pf_num = orig_pf_num;
7935 bp->fw_seq =
7936 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7937 DRV_MSG_SEQ_NUMBER_MASK);
7938 } else
7939 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7940 }
7941 }
7942
7943 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7944 {
7945 u32 val, val2, val3, val4, id;
7946 u16 pmc;
7947
7948 /* Get the chip revision id and number. */
7949 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7950 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7951 id = ((val & 0xffff) << 16);
7952 val = REG_RD(bp, MISC_REG_CHIP_REV);
7953 id |= ((val & 0xf) << 12);
7954 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7955 id |= ((val & 0xff) << 4);
7956 val = REG_RD(bp, MISC_REG_BOND_ID);
7957 id |= (val & 0xf);
7958 bp->common.chip_id = id;
7959
7960 /* Set doorbell size */
7961 bp->db_size = (1 << BNX2X_DB_SHIFT);
7962
7963 if (CHIP_IS_E2(bp)) {
7964 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7965 if ((val & 1) == 0)
7966 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7967 else
7968 val = (val >> 1) & 1;
7969 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7970 "2_PORT_MODE");
7971 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7972 CHIP_2_PORT_MODE;
7973
7974 if (CHIP_MODE_IS_4_PORT(bp))
7975 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7976 else
7977 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7978 } else {
7979 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7980 bp->pfid = bp->pf_num; /* 0..7 */
7981 }
7982
7983 /*
7984 * set base FW non-default (fast path) status block id, this value is
7985 * used to initialize the fw_sb_id saved on the fp/queue structure to
7986 * determine the id used by the FW.
7987 */
7988 if (CHIP_IS_E1x(bp))
7989 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7990 else /* E2 */
7991 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7992
7993 bp->link_params.chip_id = bp->common.chip_id;
7994 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
7995
7996 val = (REG_RD(bp, 0x2874) & 0x55);
7997 if ((bp->common.chip_id & 0x1) ||
7998 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7999 bp->flags |= ONE_PORT_FLAG;
8000 BNX2X_DEV_INFO("single port device\n");
8001 }
8002
8003 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8004 bp->common.flash_size = (NVRAM_1MB_SIZE <<
8005 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8006 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8007 bp->common.flash_size, bp->common.flash_size);
8008
8009 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8010 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8011 MISC_REG_GENERIC_CR_1 :
8012 MISC_REG_GENERIC_CR_0));
8013 bp->link_params.shmem_base = bp->common.shmem_base;
8014 bp->link_params.shmem2_base = bp->common.shmem2_base;
8015 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8016 bp->common.shmem_base, bp->common.shmem2_base);
8017
8018 if (!bp->common.shmem_base) {
8019 BNX2X_DEV_INFO("MCP not active\n");
8020 bp->flags |= NO_MCP_FLAG;
8021 return;
8022 }
8023
8024 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8025 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
8026 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
8027 BNX2X_ERR("BAD MCP validity signature\n");
8028
8029 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8030 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8031
8032 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8033 SHARED_HW_CFG_LED_MODE_MASK) >>
8034 SHARED_HW_CFG_LED_MODE_SHIFT);
8035
8036 bp->link_params.feature_config_flags = 0;
8037 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8038 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8039 bp->link_params.feature_config_flags |=
8040 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8041 else
8042 bp->link_params.feature_config_flags &=
8043 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8044
8045 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8046 bp->common.bc_ver = val;
8047 BNX2X_DEV_INFO("bc_ver %X\n", val);
8048 if (val < BNX2X_BC_VER) {
8049 /* for now only warn
8050 * later we might need to enforce this */
8051 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8052 "please upgrade BC\n", BNX2X_BC_VER, val);
8053 }
8054 bp->link_params.feature_config_flags |=
8055 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8056 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8057
8058 bp->link_params.feature_config_flags |=
8059 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8060 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8061
8062 if (BP_E1HVN(bp) == 0) {
8063 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8064 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8065 } else {
8066 /* no WOL capability for E1HVN != 0 */
8067 bp->flags |= NO_WOL_FLAG;
8068 }
8069 BNX2X_DEV_INFO("%sWoL capable\n",
8070 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8071
8072 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8073 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8074 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8075 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8076
8077 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8078 val, val2, val3, val4);
8079 }
8080
8081 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8082 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8083
8084 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8085 {
8086 int pfid = BP_FUNC(bp);
8087 int vn = BP_E1HVN(bp);
8088 int igu_sb_id;
8089 u32 val;
8090 u8 fid;
8091
8092 bp->igu_base_sb = 0xff;
8093 bp->igu_sb_cnt = 0;
8094 if (CHIP_INT_MODE_IS_BC(bp)) {
8095 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8096 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8097
8098 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8099 FP_SB_MAX_E1x;
8100
8101 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8102 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8103
8104 return;
8105 }
8106
8107 /* IGU in normal mode - read CAM */
8108 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8109 igu_sb_id++) {
8110 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8111 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8112 continue;
8113 fid = IGU_FID(val);
8114 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8115 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8116 continue;
8117 if (IGU_VEC(val) == 0)
8118 /* default status block */
8119 bp->igu_dsb_id = igu_sb_id;
8120 else {
8121 if (bp->igu_base_sb == 0xff)
8122 bp->igu_base_sb = igu_sb_id;
8123 bp->igu_sb_cnt++;
8124 }
8125 }
8126 }
8127 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8128 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8129 if (bp->igu_sb_cnt == 0)
8130 BNX2X_ERR("CAM configuration error\n");
8131 }
8132
8133 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8134 u32 switch_cfg)
8135 {
8136 int cfg_size = 0, idx, port = BP_PORT(bp);
8137
8138 /* Aggregation of supported attributes of all external phys */
8139 bp->port.supported[0] = 0;
8140 bp->port.supported[1] = 0;
8141 switch (bp->link_params.num_phys) {
8142 case 1:
8143 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8144 cfg_size = 1;
8145 break;
8146 case 2:
8147 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8148 cfg_size = 1;
8149 break;
8150 case 3:
8151 if (bp->link_params.multi_phy_config &
8152 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8153 bp->port.supported[1] =
8154 bp->link_params.phy[EXT_PHY1].supported;
8155 bp->port.supported[0] =
8156 bp->link_params.phy[EXT_PHY2].supported;
8157 } else {
8158 bp->port.supported[0] =
8159 bp->link_params.phy[EXT_PHY1].supported;
8160 bp->port.supported[1] =
8161 bp->link_params.phy[EXT_PHY2].supported;
8162 }
8163 cfg_size = 2;
8164 break;
8165 }
8166
8167 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8168 BNX2X_ERR("NVRAM config error. BAD phy config."
8169 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8170 SHMEM_RD(bp,
8171 dev_info.port_hw_config[port].external_phy_config),
8172 SHMEM_RD(bp,
8173 dev_info.port_hw_config[port].external_phy_config2));
8174 return;
8175 }
8176
8177 switch (switch_cfg) {
8178 case SWITCH_CFG_1G:
8179 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8180 port*0x10);
8181 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8182 break;
8183
8184 case SWITCH_CFG_10G:
8185 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8186 port*0x18);
8187 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8188 break;
8189
8190 default:
8191 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8192 bp->port.link_config[0]);
8193 return;
8194 }
8195 /* mask what we support according to speed_cap_mask per configuration */
8196 for (idx = 0; idx < cfg_size; idx++) {
8197 if (!(bp->link_params.speed_cap_mask[idx] &
8198 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8199 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8200
8201 if (!(bp->link_params.speed_cap_mask[idx] &
8202 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8203 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8204
8205 if (!(bp->link_params.speed_cap_mask[idx] &
8206 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8207 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8208
8209 if (!(bp->link_params.speed_cap_mask[idx] &
8210 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8211 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8212
8213 if (!(bp->link_params.speed_cap_mask[idx] &
8214 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8215 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8216 SUPPORTED_1000baseT_Full);
8217
8218 if (!(bp->link_params.speed_cap_mask[idx] &
8219 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8220 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8221
8222 if (!(bp->link_params.speed_cap_mask[idx] &
8223 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8224 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8225
8226 }
8227
8228 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8229 bp->port.supported[1]);
8230 }
8231
8232 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8233 {
8234 u32 link_config, idx, cfg_size = 0;
8235 bp->port.advertising[0] = 0;
8236 bp->port.advertising[1] = 0;
8237 switch (bp->link_params.num_phys) {
8238 case 1:
8239 case 2:
8240 cfg_size = 1;
8241 break;
8242 case 3:
8243 cfg_size = 2;
8244 break;
8245 }
8246 for (idx = 0; idx < cfg_size; idx++) {
8247 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8248 link_config = bp->port.link_config[idx];
8249 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8250 case PORT_FEATURE_LINK_SPEED_AUTO:
8251 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8252 bp->link_params.req_line_speed[idx] =
8253 SPEED_AUTO_NEG;
8254 bp->port.advertising[idx] |=
8255 bp->port.supported[idx];
8256 } else {
8257 /* force 10G, no AN */
8258 bp->link_params.req_line_speed[idx] =
8259 SPEED_10000;
8260 bp->port.advertising[idx] |=
8261 (ADVERTISED_10000baseT_Full |
8262 ADVERTISED_FIBRE);
8263 continue;
8264 }
8265 break;
8266
8267 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8268 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8269 bp->link_params.req_line_speed[idx] =
8270 SPEED_10;
8271 bp->port.advertising[idx] |=
8272 (ADVERTISED_10baseT_Full |
8273 ADVERTISED_TP);
8274 } else {
8275 BNX2X_ERROR("NVRAM config error. "
8276 "Invalid link_config 0x%x"
8277 " speed_cap_mask 0x%x\n",
8278 link_config,
8279 bp->link_params.speed_cap_mask[idx]);
8280 return;
8281 }
8282 break;
8283
8284 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8285 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8286 bp->link_params.req_line_speed[idx] =
8287 SPEED_10;
8288 bp->link_params.req_duplex[idx] =
8289 DUPLEX_HALF;
8290 bp->port.advertising[idx] |=
8291 (ADVERTISED_10baseT_Half |
8292 ADVERTISED_TP);
8293 } else {
8294 BNX2X_ERROR("NVRAM config error. "
8295 "Invalid link_config 0x%x"
8296 " speed_cap_mask 0x%x\n",
8297 link_config,
8298 bp->link_params.speed_cap_mask[idx]);
8299 return;
8300 }
8301 break;
8302
8303 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8304 if (bp->port.supported[idx] &
8305 SUPPORTED_100baseT_Full) {
8306 bp->link_params.req_line_speed[idx] =
8307 SPEED_100;
8308 bp->port.advertising[idx] |=
8309 (ADVERTISED_100baseT_Full |
8310 ADVERTISED_TP);
8311 } else {
8312 BNX2X_ERROR("NVRAM config error. "
8313 "Invalid link_config 0x%x"
8314 " speed_cap_mask 0x%x\n",
8315 link_config,
8316 bp->link_params.speed_cap_mask[idx]);
8317 return;
8318 }
8319 break;
8320
8321 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8322 if (bp->port.supported[idx] &
8323 SUPPORTED_100baseT_Half) {
8324 bp->link_params.req_line_speed[idx] =
8325 SPEED_100;
8326 bp->link_params.req_duplex[idx] =
8327 DUPLEX_HALF;
8328 bp->port.advertising[idx] |=
8329 (ADVERTISED_100baseT_Half |
8330 ADVERTISED_TP);
8331 } else {
8332 BNX2X_ERROR("NVRAM config error. "
8333 "Invalid link_config 0x%x"
8334 " speed_cap_mask 0x%x\n",
8335 link_config,
8336 bp->link_params.speed_cap_mask[idx]);
8337 return;
8338 }
8339 break;
8340
8341 case PORT_FEATURE_LINK_SPEED_1G:
8342 if (bp->port.supported[idx] &
8343 SUPPORTED_1000baseT_Full) {
8344 bp->link_params.req_line_speed[idx] =
8345 SPEED_1000;
8346 bp->port.advertising[idx] |=
8347 (ADVERTISED_1000baseT_Full |
8348 ADVERTISED_TP);
8349 } else {
8350 BNX2X_ERROR("NVRAM config error. "
8351 "Invalid link_config 0x%x"
8352 " speed_cap_mask 0x%x\n",
8353 link_config,
8354 bp->link_params.speed_cap_mask[idx]);
8355 return;
8356 }
8357 break;
8358
8359 case PORT_FEATURE_LINK_SPEED_2_5G:
8360 if (bp->port.supported[idx] &
8361 SUPPORTED_2500baseX_Full) {
8362 bp->link_params.req_line_speed[idx] =
8363 SPEED_2500;
8364 bp->port.advertising[idx] |=
8365 (ADVERTISED_2500baseX_Full |
8366 ADVERTISED_TP);
8367 } else {
8368 BNX2X_ERROR("NVRAM config error. "
8369 "Invalid link_config 0x%x"
8370 " speed_cap_mask 0x%x\n",
8371 link_config,
8372 bp->link_params.speed_cap_mask[idx]);
8373 return;
8374 }
8375 break;
8376
8377 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8378 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8379 case PORT_FEATURE_LINK_SPEED_10G_KR:
8380 if (bp->port.supported[idx] &
8381 SUPPORTED_10000baseT_Full) {
8382 bp->link_params.req_line_speed[idx] =
8383 SPEED_10000;
8384 bp->port.advertising[idx] |=
8385 (ADVERTISED_10000baseT_Full |
8386 ADVERTISED_FIBRE);
8387 } else {
8388 BNX2X_ERROR("NVRAM config error. "
8389 "Invalid link_config 0x%x"
8390 " speed_cap_mask 0x%x\n",
8391 link_config,
8392 bp->link_params.speed_cap_mask[idx]);
8393 return;
8394 }
8395 break;
8396
8397 default:
8398 BNX2X_ERROR("NVRAM config error. "
8399 "BAD link speed link_config 0x%x\n",
8400 link_config);
8401 bp->link_params.req_line_speed[idx] =
8402 SPEED_AUTO_NEG;
8403 bp->port.advertising[idx] =
8404 bp->port.supported[idx];
8405 break;
8406 }
8407
8408 bp->link_params.req_flow_ctrl[idx] = (link_config &
8409 PORT_FEATURE_FLOW_CONTROL_MASK);
8410 if ((bp->link_params.req_flow_ctrl[idx] ==
8411 BNX2X_FLOW_CTRL_AUTO) &&
8412 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8413 bp->link_params.req_flow_ctrl[idx] =
8414 BNX2X_FLOW_CTRL_NONE;
8415 }
8416
8417 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8418 " 0x%x advertising 0x%x\n",
8419 bp->link_params.req_line_speed[idx],
8420 bp->link_params.req_duplex[idx],
8421 bp->link_params.req_flow_ctrl[idx],
8422 bp->port.advertising[idx]);
8423 }
8424 }
8425
8426 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8427 {
8428 mac_hi = cpu_to_be16(mac_hi);
8429 mac_lo = cpu_to_be32(mac_lo);
8430 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8431 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8432 }
8433
8434 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8435 {
8436 int port = BP_PORT(bp);
8437 u32 config;
8438 u32 ext_phy_type, ext_phy_config;
8439
8440 bp->link_params.bp = bp;
8441 bp->link_params.port = port;
8442
8443 bp->link_params.lane_config =
8444 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8445
8446 bp->link_params.speed_cap_mask[0] =
8447 SHMEM_RD(bp,
8448 dev_info.port_hw_config[port].speed_capability_mask);
8449 bp->link_params.speed_cap_mask[1] =
8450 SHMEM_RD(bp,
8451 dev_info.port_hw_config[port].speed_capability_mask2);
8452 bp->port.link_config[0] =
8453 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8454
8455 bp->port.link_config[1] =
8456 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8457
8458 bp->link_params.multi_phy_config =
8459 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8460 /* If the device is capable of WoL, set the default state according
8461 * to the HW
8462 */
8463 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8464 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8465 (config & PORT_FEATURE_WOL_ENABLED));
8466
8467 BNX2X_DEV_INFO("lane_config 0x%08x "
8468 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
8469 bp->link_params.lane_config,
8470 bp->link_params.speed_cap_mask[0],
8471 bp->port.link_config[0]);
8472
8473 bp->link_params.switch_cfg = (bp->port.link_config[0] &
8474 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8475 bnx2x_phy_probe(&bp->link_params);
8476 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8477
8478 bnx2x_link_settings_requested(bp);
8479
8480 /*
8481 * If connected directly, work with the internal PHY, otherwise, work
8482 * with the external PHY
8483 */
8484 ext_phy_config =
8485 SHMEM_RD(bp,
8486 dev_info.port_hw_config[port].external_phy_config);
8487 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8488 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8489 bp->mdio.prtad = bp->port.phy_addr;
8490
8491 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8492 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8493 bp->mdio.prtad =
8494 XGXS_EXT_PHY_ADDR(ext_phy_config);
8495
8496 /*
8497 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8498 * In MF mode, it is set to cover self test cases
8499 */
8500 if (IS_MF(bp))
8501 bp->port.need_hw_lock = 1;
8502 else
8503 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8504 bp->common.shmem_base,
8505 bp->common.shmem2_base);
8506 }
8507
8508 #ifdef BCM_CNIC
8509 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8510 {
8511 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8512 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8513 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8514 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8515
8516 /* Get the number of maximum allowed iSCSI and FCoE connections */
8517 bp->cnic_eth_dev.max_iscsi_conn =
8518 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8519 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8520
8521 bp->cnic_eth_dev.max_fcoe_conn =
8522 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8523 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8524
8525 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8526 bp->cnic_eth_dev.max_iscsi_conn,
8527 bp->cnic_eth_dev.max_fcoe_conn);
8528
8529 /* If mamimum allowed number of connections is zero -
8530 * disable the feature.
8531 */
8532 if (!bp->cnic_eth_dev.max_iscsi_conn)
8533 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8534
8535 if (!bp->cnic_eth_dev.max_fcoe_conn)
8536 bp->flags |= NO_FCOE_FLAG;
8537 }
8538 #endif
8539
8540 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8541 {
8542 u32 val, val2;
8543 int func = BP_ABS_FUNC(bp);
8544 int port = BP_PORT(bp);
8545 #ifdef BCM_CNIC
8546 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8547 u8 *fip_mac = bp->fip_mac;
8548 #endif
8549
8550 if (BP_NOMCP(bp)) {
8551 BNX2X_ERROR("warning: random MAC workaround active\n");
8552 random_ether_addr(bp->dev->dev_addr);
8553 } else if (IS_MF(bp)) {
8554 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8555 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8556 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8557 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8558 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8559
8560 #ifdef BCM_CNIC
8561 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8562 * FCoE MAC then the appropriate feature should be disabled.
8563 */
8564 if (IS_MF_SI(bp)) {
8565 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8566 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8567 val2 = MF_CFG_RD(bp, func_ext_config[func].
8568 iscsi_mac_addr_upper);
8569 val = MF_CFG_RD(bp, func_ext_config[func].
8570 iscsi_mac_addr_lower);
8571 BNX2X_DEV_INFO("Read iSCSI MAC: "
8572 "0x%x:0x%04x\n", val2, val);
8573 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8574
8575 /* Disable iSCSI OOO if MAC configuration is
8576 * invalid.
8577 */
8578 if (!is_valid_ether_addr(iscsi_mac)) {
8579 bp->flags |= NO_ISCSI_OOO_FLAG |
8580 NO_ISCSI_FLAG;
8581 memset(iscsi_mac, 0, ETH_ALEN);
8582 }
8583 } else
8584 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8585
8586 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8587 val2 = MF_CFG_RD(bp, func_ext_config[func].
8588 fcoe_mac_addr_upper);
8589 val = MF_CFG_RD(bp, func_ext_config[func].
8590 fcoe_mac_addr_lower);
8591 BNX2X_DEV_INFO("Read FCoE MAC to "
8592 "0x%x:0x%04x\n", val2, val);
8593 bnx2x_set_mac_buf(fip_mac, val, val2);
8594
8595 /* Disable FCoE if MAC configuration is
8596 * invalid.
8597 */
8598 if (!is_valid_ether_addr(fip_mac)) {
8599 bp->flags |= NO_FCOE_FLAG;
8600 memset(bp->fip_mac, 0, ETH_ALEN);
8601 }
8602 } else
8603 bp->flags |= NO_FCOE_FLAG;
8604 }
8605 #endif
8606 } else {
8607 /* in SF read MACs from port configuration */
8608 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8609 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8610 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8611
8612 #ifdef BCM_CNIC
8613 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8614 iscsi_mac_upper);
8615 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8616 iscsi_mac_lower);
8617 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8618 #endif
8619 }
8620
8621 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8622 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8623
8624 #ifdef BCM_CNIC
8625 /* Set the FCoE MAC in modes other then MF_SI */
8626 if (!CHIP_IS_E1x(bp)) {
8627 if (IS_MF_SD(bp))
8628 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8629 else if (!IS_MF(bp))
8630 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
8631 }
8632 #endif
8633 }
8634
8635 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8636 {
8637 int /*abs*/func = BP_ABS_FUNC(bp);
8638 int vn, port;
8639 u32 val = 0;
8640 int rc = 0;
8641
8642 bnx2x_get_common_hwinfo(bp);
8643
8644 if (CHIP_IS_E1x(bp)) {
8645 bp->common.int_block = INT_BLOCK_HC;
8646
8647 bp->igu_dsb_id = DEF_SB_IGU_ID;
8648 bp->igu_base_sb = 0;
8649 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8650 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8651 } else {
8652 bp->common.int_block = INT_BLOCK_IGU;
8653 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8654 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8655 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8656 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8657 } else
8658 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
8659
8660 bnx2x_get_igu_cam_info(bp);
8661
8662 }
8663 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8664 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8665
8666 /*
8667 * Initialize MF configuration
8668 */
8669
8670 bp->mf_ov = 0;
8671 bp->mf_mode = 0;
8672 vn = BP_E1HVN(bp);
8673 port = BP_PORT(bp);
8674
8675 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8676 DP(NETIF_MSG_PROBE,
8677 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8678 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8679 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8680 if (SHMEM2_HAS(bp, mf_cfg_addr))
8681 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8682 else
8683 bp->common.mf_cfg_base = bp->common.shmem_base +
8684 offsetof(struct shmem_region, func_mb) +
8685 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8686 /*
8687 * get mf configuration:
8688 * 1. existence of MF configuration
8689 * 2. MAC address must be legal (check only upper bytes)
8690 * for Switch-Independent mode;
8691 * OVLAN must be legal for Switch-Dependent mode
8692 * 3. SF_MODE configures specific MF mode
8693 */
8694 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8695 /* get mf configuration */
8696 val = SHMEM_RD(bp,
8697 dev_info.shared_feature_config.config);
8698 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8699
8700 switch (val) {
8701 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8702 val = MF_CFG_RD(bp, func_mf_config[func].
8703 mac_upper);
8704 /* check for legal mac (upper bytes)*/
8705 if (val != 0xffff) {
8706 bp->mf_mode = MULTI_FUNCTION_SI;
8707 bp->mf_config[vn] = MF_CFG_RD(bp,
8708 func_mf_config[func].config);
8709 } else
8710 DP(NETIF_MSG_PROBE, "illegal MAC "
8711 "address for SI\n");
8712 break;
8713 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8714 /* get OV configuration */
8715 val = MF_CFG_RD(bp,
8716 func_mf_config[FUNC_0].e1hov_tag);
8717 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8718
8719 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8720 bp->mf_mode = MULTI_FUNCTION_SD;
8721 bp->mf_config[vn] = MF_CFG_RD(bp,
8722 func_mf_config[func].config);
8723 } else
8724 DP(NETIF_MSG_PROBE, "illegal OV for "
8725 "SD\n");
8726 break;
8727 default:
8728 /* Unknown configuration: reset mf_config */
8729 bp->mf_config[vn] = 0;
8730 DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
8731 val);
8732 }
8733 }
8734
8735 BNX2X_DEV_INFO("%s function mode\n",
8736 IS_MF(bp) ? "multi" : "single");
8737
8738 switch (bp->mf_mode) {
8739 case MULTI_FUNCTION_SD:
8740 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8741 FUNC_MF_CFG_E1HOV_TAG_MASK;
8742 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8743 bp->mf_ov = val;
8744 BNX2X_DEV_INFO("MF OV for func %d is %d"
8745 " (0x%04x)\n", func,
8746 bp->mf_ov, bp->mf_ov);
8747 } else {
8748 BNX2X_ERR("No valid MF OV for func %d,"
8749 " aborting\n", func);
8750 rc = -EPERM;
8751 }
8752 break;
8753 case MULTI_FUNCTION_SI:
8754 BNX2X_DEV_INFO("func %d is in MF "
8755 "switch-independent mode\n", func);
8756 break;
8757 default:
8758 if (vn) {
8759 BNX2X_ERR("VN %d in single function mode,"
8760 " aborting\n", vn);
8761 rc = -EPERM;
8762 }
8763 break;
8764 }
8765
8766 }
8767
8768 /* adjust igu_sb_cnt to MF for E1x */
8769 if (CHIP_IS_E1x(bp) && IS_MF(bp))
8770 bp->igu_sb_cnt /= E1HVN_MAX;
8771
8772 /*
8773 * adjust E2 sb count: to be removed when FW will support
8774 * more then 16 L2 clients
8775 */
8776 #define MAX_L2_CLIENTS 16
8777 if (CHIP_IS_E2(bp))
8778 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8779 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8780
8781 if (!BP_NOMCP(bp)) {
8782 bnx2x_get_port_hwinfo(bp);
8783
8784 bp->fw_seq =
8785 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8786 DRV_MSG_SEQ_NUMBER_MASK);
8787 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8788 }
8789
8790 /* Get MAC addresses */
8791 bnx2x_get_mac_hwinfo(bp);
8792
8793 #ifdef BCM_CNIC
8794 bnx2x_get_cnic_info(bp);
8795 #endif
8796
8797 return rc;
8798 }
8799
8800 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8801 {
8802 int cnt, i, block_end, rodi;
8803 char vpd_data[BNX2X_VPD_LEN+1];
8804 char str_id_reg[VENDOR_ID_LEN+1];
8805 char str_id_cap[VENDOR_ID_LEN+1];
8806 u8 len;
8807
8808 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8809 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8810
8811 if (cnt < BNX2X_VPD_LEN)
8812 goto out_not_found;
8813
8814 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8815 PCI_VPD_LRDT_RO_DATA);
8816 if (i < 0)
8817 goto out_not_found;
8818
8819
8820 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8821 pci_vpd_lrdt_size(&vpd_data[i]);
8822
8823 i += PCI_VPD_LRDT_TAG_SIZE;
8824
8825 if (block_end > BNX2X_VPD_LEN)
8826 goto out_not_found;
8827
8828 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8829 PCI_VPD_RO_KEYWORD_MFR_ID);
8830 if (rodi < 0)
8831 goto out_not_found;
8832
8833 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8834
8835 if (len != VENDOR_ID_LEN)
8836 goto out_not_found;
8837
8838 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8839
8840 /* vendor specific info */
8841 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8842 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8843 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8844 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8845
8846 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8847 PCI_VPD_RO_KEYWORD_VENDOR0);
8848 if (rodi >= 0) {
8849 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8850
8851 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8852
8853 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8854 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8855 bp->fw_ver[len] = ' ';
8856 }
8857 }
8858 return;
8859 }
8860 out_not_found:
8861 return;
8862 }
8863
8864 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8865 {
8866 int func;
8867 int timer_interval;
8868 int rc;
8869
8870 /* Disable interrupt handling until HW is initialized */
8871 atomic_set(&bp->intr_sem, 1);
8872 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
8873
8874 mutex_init(&bp->port.phy_mutex);
8875 mutex_init(&bp->fw_mb_mutex);
8876 spin_lock_init(&bp->stats_lock);
8877 #ifdef BCM_CNIC
8878 mutex_init(&bp->cnic_mutex);
8879 #endif
8880
8881 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
8882 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
8883
8884 rc = bnx2x_get_hwinfo(bp);
8885
8886 if (!rc)
8887 rc = bnx2x_alloc_mem_bp(bp);
8888
8889 bnx2x_read_fwinfo(bp);
8890
8891 func = BP_FUNC(bp);
8892
8893 /* need to reset chip if undi was active */
8894 if (!BP_NOMCP(bp))
8895 bnx2x_undi_unload(bp);
8896
8897 if (CHIP_REV_IS_FPGA(bp))
8898 dev_err(&bp->pdev->dev, "FPGA detected\n");
8899
8900 if (BP_NOMCP(bp) && (func == 0))
8901 dev_err(&bp->pdev->dev, "MCP disabled, "
8902 "must load devices in order!\n");
8903
8904 bp->multi_mode = multi_mode;
8905 bp->int_mode = int_mode;
8906
8907 bp->dev->features |= NETIF_F_GRO;
8908
8909 /* Set TPA flags */
8910 if (disable_tpa) {
8911 bp->flags &= ~TPA_ENABLE_FLAG;
8912 bp->dev->features &= ~NETIF_F_LRO;
8913 } else {
8914 bp->flags |= TPA_ENABLE_FLAG;
8915 bp->dev->features |= NETIF_F_LRO;
8916 }
8917 bp->disable_tpa = disable_tpa;
8918
8919 if (CHIP_IS_E1(bp))
8920 bp->dropless_fc = 0;
8921 else
8922 bp->dropless_fc = dropless_fc;
8923
8924 bp->mrrs = mrrs;
8925
8926 bp->tx_ring_size = MAX_TX_AVAIL;
8927
8928 bp->rx_csum = 1;
8929
8930 /* make sure that the numbers are in the right granularity */
8931 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8932 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
8933
8934 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8935 bp->current_interval = (poll ? poll : timer_interval);
8936
8937 init_timer(&bp->timer);
8938 bp->timer.expires = jiffies + bp->current_interval;
8939 bp->timer.data = (unsigned long) bp;
8940 bp->timer.function = bnx2x_timer;
8941
8942 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
8943 bnx2x_dcbx_init_params(bp);
8944
8945 return rc;
8946 }
8947
8948
8949 /****************************************************************************
8950 * General service functions
8951 ****************************************************************************/
8952
8953 /* called with rtnl_lock */
8954 static int bnx2x_open(struct net_device *dev)
8955 {
8956 struct bnx2x *bp = netdev_priv(dev);
8957
8958 netif_carrier_off(dev);
8959
8960 bnx2x_set_power_state(bp, PCI_D0);
8961
8962 if (!bnx2x_reset_is_done(bp)) {
8963 do {
8964 /* Reset MCP mail box sequence if there is on going
8965 * recovery
8966 */
8967 bp->fw_seq = 0;
8968
8969 /* If it's the first function to load and reset done
8970 * is still not cleared it may mean that. We don't
8971 * check the attention state here because it may have
8972 * already been cleared by a "common" reset but we
8973 * shell proceed with "process kill" anyway.
8974 */
8975 if ((bnx2x_get_load_cnt(bp) == 0) &&
8976 bnx2x_trylock_hw_lock(bp,
8977 HW_LOCK_RESOURCE_RESERVED_08) &&
8978 (!bnx2x_leader_reset(bp))) {
8979 DP(NETIF_MSG_HW, "Recovered in open\n");
8980 break;
8981 }
8982
8983 bnx2x_set_power_state(bp, PCI_D3hot);
8984
8985 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8986 " completed yet. Try again later. If u still see this"
8987 " message after a few retries then power cycle is"
8988 " required.\n", bp->dev->name);
8989
8990 return -EAGAIN;
8991 } while (0);
8992 }
8993
8994 bp->recovery_state = BNX2X_RECOVERY_DONE;
8995
8996 return bnx2x_nic_load(bp, LOAD_OPEN);
8997 }
8998
8999 /* called with rtnl_lock */
9000 static int bnx2x_close(struct net_device *dev)
9001 {
9002 struct bnx2x *bp = netdev_priv(dev);
9003
9004 /* Unload the driver, release IRQs */
9005 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9006 bnx2x_set_power_state(bp, PCI_D3hot);
9007
9008 return 0;
9009 }
9010
9011 #define E1_MAX_UC_LIST 29
9012 #define E1H_MAX_UC_LIST 30
9013 #define E2_MAX_UC_LIST 14
9014 static inline u8 bnx2x_max_uc_list(struct bnx2x *bp)
9015 {
9016 if (CHIP_IS_E1(bp))
9017 return E1_MAX_UC_LIST;
9018 else if (CHIP_IS_E1H(bp))
9019 return E1H_MAX_UC_LIST;
9020 else
9021 return E2_MAX_UC_LIST;
9022 }
9023
9024
9025 static inline u8 bnx2x_uc_list_cam_offset(struct bnx2x *bp)
9026 {
9027 if (CHIP_IS_E1(bp))
9028 /* CAM Entries for Port0:
9029 * 0 - prim ETH MAC
9030 * 1 - BCAST MAC
9031 * 2 - iSCSI L2 ring ETH MAC
9032 * 3-31 - UC MACs
9033 *
9034 * Port1 entries are allocated the same way starting from
9035 * entry 32.
9036 */
9037 return 3 + 32 * BP_PORT(bp);
9038 else if (CHIP_IS_E1H(bp)) {
9039 /* CAM Entries:
9040 * 0-7 - prim ETH MAC for each function
9041 * 8-15 - iSCSI L2 ring ETH MAC for each function
9042 * 16 till 255 UC MAC lists for each function
9043 *
9044 * Remark: There is no FCoE support for E1H, thus FCoE related
9045 * MACs are not considered.
9046 */
9047 return E1H_FUNC_MAX * (CAM_ISCSI_ETH_LINE + 1) +
9048 bnx2x_max_uc_list(bp) * BP_FUNC(bp);
9049 } else {
9050 /* CAM Entries (there is a separate CAM per engine):
9051 * 0-4 - prim ETH MAC for each function
9052 * 4-7 - iSCSI L2 ring ETH MAC for each function
9053 * 8-11 - FIP ucast L2 MAC for each function
9054 * 12-15 - ALL_ENODE_MACS mcast MAC for each function
9055 * 16 till 71 UC MAC lists for each function
9056 */
9057 u8 func_idx =
9058 (CHIP_MODE_IS_4_PORT(bp) ? BP_FUNC(bp) : BP_VN(bp));
9059
9060 return E2_FUNC_MAX * (CAM_MAX_PF_LINE + 1) +
9061 bnx2x_max_uc_list(bp) * func_idx;
9062 }
9063 }
9064
9065 /* set uc list, do not wait as wait implies sleep and
9066 * set_rx_mode can be invoked from non-sleepable context.
9067 *
9068 * Instead we use the same ramrod data buffer each time we need
9069 * to configure a list of addresses, and use the fact that the
9070 * list of MACs is changed in an incremental way and that the
9071 * function is called under the netif_addr_lock. A temporary
9072 * inconsistent CAM configuration (possible in case of very fast
9073 * sequence of add/del/add on the host side) will shortly be
9074 * restored by the handler of the last ramrod.
9075 */
9076 static int bnx2x_set_uc_list(struct bnx2x *bp)
9077 {
9078 int i = 0, old;
9079 struct net_device *dev = bp->dev;
9080 u8 offset = bnx2x_uc_list_cam_offset(bp);
9081 struct netdev_hw_addr *ha;
9082 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
9083 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
9084
9085 if (netdev_uc_count(dev) > bnx2x_max_uc_list(bp))
9086 return -EINVAL;
9087
9088 netdev_for_each_uc_addr(ha, dev) {
9089 /* copy mac */
9090 config_cmd->config_table[i].msb_mac_addr =
9091 swab16(*(u16 *)&bnx2x_uc_addr(ha)[0]);
9092 config_cmd->config_table[i].middle_mac_addr =
9093 swab16(*(u16 *)&bnx2x_uc_addr(ha)[2]);
9094 config_cmd->config_table[i].lsb_mac_addr =
9095 swab16(*(u16 *)&bnx2x_uc_addr(ha)[4]);
9096
9097 config_cmd->config_table[i].vlan_id = 0;
9098 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
9099 config_cmd->config_table[i].clients_bit_vector =
9100 cpu_to_le32(1 << BP_L_ID(bp));
9101
9102 SET_FLAG(config_cmd->config_table[i].flags,
9103 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
9104 T_ETH_MAC_COMMAND_SET);
9105
9106 DP(NETIF_MSG_IFUP,
9107 "setting UCAST[%d] (%04x:%04x:%04x)\n", i,
9108 config_cmd->config_table[i].msb_mac_addr,
9109 config_cmd->config_table[i].middle_mac_addr,
9110 config_cmd->config_table[i].lsb_mac_addr);
9111
9112 i++;
9113
9114 /* Set uc MAC in NIG */
9115 bnx2x_set_mac_in_nig(bp, 1, bnx2x_uc_addr(ha),
9116 LLH_CAM_ETH_LINE + i);
9117 }
9118 old = config_cmd->hdr.length;
9119 if (old > i) {
9120 for (; i < old; i++) {
9121 if (CAM_IS_INVALID(config_cmd->
9122 config_table[i])) {
9123 /* already invalidated */
9124 break;
9125 }
9126 /* invalidate */
9127 SET_FLAG(config_cmd->config_table[i].flags,
9128 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
9129 T_ETH_MAC_COMMAND_INVALIDATE);
9130 }
9131 }
9132
9133 wmb();
9134
9135 config_cmd->hdr.length = i;
9136 config_cmd->hdr.offset = offset;
9137 config_cmd->hdr.client_id = 0xff;
9138 /* Mark that this ramrod doesn't use bp->set_mac_pending for
9139 * synchronization.
9140 */
9141 config_cmd->hdr.echo = 0;
9142
9143 mb();
9144
9145 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
9146 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
9147
9148 }
9149
9150 void bnx2x_invalidate_uc_list(struct bnx2x *bp)
9151 {
9152 int i;
9153 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
9154 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
9155 int ramrod_flags = WAIT_RAMROD_COMMON;
9156 u8 offset = bnx2x_uc_list_cam_offset(bp);
9157 u8 max_list_size = bnx2x_max_uc_list(bp);
9158
9159 for (i = 0; i < max_list_size; i++) {
9160 SET_FLAG(config_cmd->config_table[i].flags,
9161 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
9162 T_ETH_MAC_COMMAND_INVALIDATE);
9163 bnx2x_set_mac_in_nig(bp, 0, NULL, LLH_CAM_ETH_LINE + 1 + i);
9164 }
9165
9166 wmb();
9167
9168 config_cmd->hdr.length = max_list_size;
9169 config_cmd->hdr.offset = offset;
9170 config_cmd->hdr.client_id = 0xff;
9171 /* We'll wait for a completion this time... */
9172 config_cmd->hdr.echo = 1;
9173
9174 bp->set_mac_pending = 1;
9175
9176 mb();
9177
9178 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
9179 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
9180
9181 /* Wait for a completion */
9182 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
9183 ramrod_flags);
9184
9185 }
9186
9187 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9188 {
9189 /* some multicasts */
9190 if (CHIP_IS_E1(bp)) {
9191 return bnx2x_set_e1_mc_list(bp);
9192 } else { /* E1H and newer */
9193 return bnx2x_set_e1h_mc_list(bp);
9194 }
9195 }
9196
9197 /* called with netif_tx_lock from dev_mcast.c */
9198 void bnx2x_set_rx_mode(struct net_device *dev)
9199 {
9200 struct bnx2x *bp = netdev_priv(dev);
9201 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9202
9203 if (bp->state != BNX2X_STATE_OPEN) {
9204 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9205 return;
9206 }
9207
9208 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
9209
9210 if (dev->flags & IFF_PROMISC)
9211 rx_mode = BNX2X_RX_MODE_PROMISC;
9212 else if (dev->flags & IFF_ALLMULTI)
9213 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9214 else {
9215 /* some multicasts */
9216 if (bnx2x_set_mc_list(bp))
9217 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9218
9219 /* some unicasts */
9220 if (bnx2x_set_uc_list(bp))
9221 rx_mode = BNX2X_RX_MODE_PROMISC;
9222 }
9223
9224 bp->rx_mode = rx_mode;
9225 bnx2x_set_storm_rx_mode(bp);
9226 }
9227
9228 /* called with rtnl_lock */
9229 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9230 int devad, u16 addr)
9231 {
9232 struct bnx2x *bp = netdev_priv(netdev);
9233 u16 value;
9234 int rc;
9235
9236 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9237 prtad, devad, addr);
9238
9239 /* The HW expects different devad if CL22 is used */
9240 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9241
9242 bnx2x_acquire_phy_lock(bp);
9243 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
9244 bnx2x_release_phy_lock(bp);
9245 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
9246
9247 if (!rc)
9248 rc = value;
9249 return rc;
9250 }
9251
9252 /* called with rtnl_lock */
9253 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9254 u16 addr, u16 value)
9255 {
9256 struct bnx2x *bp = netdev_priv(netdev);
9257 int rc;
9258
9259 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9260 " value 0x%x\n", prtad, devad, addr, value);
9261
9262 /* The HW expects different devad if CL22 is used */
9263 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9264
9265 bnx2x_acquire_phy_lock(bp);
9266 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
9267 bnx2x_release_phy_lock(bp);
9268 return rc;
9269 }
9270
9271 /* called with rtnl_lock */
9272 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9273 {
9274 struct bnx2x *bp = netdev_priv(dev);
9275 struct mii_ioctl_data *mdio = if_mii(ifr);
9276
9277 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9278 mdio->phy_id, mdio->reg_num, mdio->val_in);
9279
9280 if (!netif_running(dev))
9281 return -EAGAIN;
9282
9283 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
9284 }
9285
9286 #ifdef CONFIG_NET_POLL_CONTROLLER
9287 static void poll_bnx2x(struct net_device *dev)
9288 {
9289 struct bnx2x *bp = netdev_priv(dev);
9290
9291 disable_irq(bp->pdev->irq);
9292 bnx2x_interrupt(bp->pdev->irq, dev);
9293 enable_irq(bp->pdev->irq);
9294 }
9295 #endif
9296
9297 static const struct net_device_ops bnx2x_netdev_ops = {
9298 .ndo_open = bnx2x_open,
9299 .ndo_stop = bnx2x_close,
9300 .ndo_start_xmit = bnx2x_start_xmit,
9301 .ndo_select_queue = bnx2x_select_queue,
9302 .ndo_set_rx_mode = bnx2x_set_rx_mode,
9303 .ndo_set_mac_address = bnx2x_change_mac_addr,
9304 .ndo_validate_addr = eth_validate_addr,
9305 .ndo_do_ioctl = bnx2x_ioctl,
9306 .ndo_change_mtu = bnx2x_change_mtu,
9307 .ndo_tx_timeout = bnx2x_tx_timeout,
9308 #ifdef CONFIG_NET_POLL_CONTROLLER
9309 .ndo_poll_controller = poll_bnx2x,
9310 #endif
9311 };
9312
9313 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9314 struct net_device *dev)
9315 {
9316 struct bnx2x *bp;
9317 int rc;
9318
9319 SET_NETDEV_DEV(dev, &pdev->dev);
9320 bp = netdev_priv(dev);
9321
9322 bp->dev = dev;
9323 bp->pdev = pdev;
9324 bp->flags = 0;
9325 bp->pf_num = PCI_FUNC(pdev->devfn);
9326
9327 rc = pci_enable_device(pdev);
9328 if (rc) {
9329 dev_err(&bp->pdev->dev,
9330 "Cannot enable PCI device, aborting\n");
9331 goto err_out;
9332 }
9333
9334 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9335 dev_err(&bp->pdev->dev,
9336 "Cannot find PCI device base address, aborting\n");
9337 rc = -ENODEV;
9338 goto err_out_disable;
9339 }
9340
9341 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9342 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9343 " base address, aborting\n");
9344 rc = -ENODEV;
9345 goto err_out_disable;
9346 }
9347
9348 if (atomic_read(&pdev->enable_cnt) == 1) {
9349 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9350 if (rc) {
9351 dev_err(&bp->pdev->dev,
9352 "Cannot obtain PCI resources, aborting\n");
9353 goto err_out_disable;
9354 }
9355
9356 pci_set_master(pdev);
9357 pci_save_state(pdev);
9358 }
9359
9360 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9361 if (bp->pm_cap == 0) {
9362 dev_err(&bp->pdev->dev,
9363 "Cannot find power management capability, aborting\n");
9364 rc = -EIO;
9365 goto err_out_release;
9366 }
9367
9368 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9369 if (bp->pcie_cap == 0) {
9370 dev_err(&bp->pdev->dev,
9371 "Cannot find PCI Express capability, aborting\n");
9372 rc = -EIO;
9373 goto err_out_release;
9374 }
9375
9376 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
9377 bp->flags |= USING_DAC_FLAG;
9378 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
9379 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9380 " failed, aborting\n");
9381 rc = -EIO;
9382 goto err_out_release;
9383 }
9384
9385 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9386 dev_err(&bp->pdev->dev,
9387 "System does not support DMA, aborting\n");
9388 rc = -EIO;
9389 goto err_out_release;
9390 }
9391
9392 dev->mem_start = pci_resource_start(pdev, 0);
9393 dev->base_addr = dev->mem_start;
9394 dev->mem_end = pci_resource_end(pdev, 0);
9395
9396 dev->irq = pdev->irq;
9397
9398 bp->regview = pci_ioremap_bar(pdev, 0);
9399 if (!bp->regview) {
9400 dev_err(&bp->pdev->dev,
9401 "Cannot map register space, aborting\n");
9402 rc = -ENOMEM;
9403 goto err_out_release;
9404 }
9405
9406 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9407 min_t(u64, BNX2X_DB_SIZE(bp),
9408 pci_resource_len(pdev, 2)));
9409 if (!bp->doorbells) {
9410 dev_err(&bp->pdev->dev,
9411 "Cannot map doorbell space, aborting\n");
9412 rc = -ENOMEM;
9413 goto err_out_unmap;
9414 }
9415
9416 bnx2x_set_power_state(bp, PCI_D0);
9417
9418 /* clean indirect addresses */
9419 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9420 PCICFG_VENDOR_ID_OFFSET);
9421 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9422 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9423 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9424 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9425
9426 /* Reset the load counter */
9427 bnx2x_clear_load_cnt(bp);
9428
9429 dev->watchdog_timeo = TX_TIMEOUT;
9430
9431 dev->netdev_ops = &bnx2x_netdev_ops;
9432 bnx2x_set_ethtool_ops(dev);
9433 dev->features |= NETIF_F_SG;
9434 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9435 if (bp->flags & USING_DAC_FLAG)
9436 dev->features |= NETIF_F_HIGHDMA;
9437 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9438 dev->features |= NETIF_F_TSO6;
9439 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
9440
9441 dev->vlan_features |= NETIF_F_SG;
9442 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9443 if (bp->flags & USING_DAC_FLAG)
9444 dev->vlan_features |= NETIF_F_HIGHDMA;
9445 dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9446 dev->vlan_features |= NETIF_F_TSO6;
9447
9448 #ifdef BCM_DCBNL
9449 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9450 #endif
9451
9452 /* get_port_hwinfo() will set prtad and mmds properly */
9453 bp->mdio.prtad = MDIO_PRTAD_NONE;
9454 bp->mdio.mmds = 0;
9455 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9456 bp->mdio.dev = dev;
9457 bp->mdio.mdio_read = bnx2x_mdio_read;
9458 bp->mdio.mdio_write = bnx2x_mdio_write;
9459
9460 return 0;
9461
9462 err_out_unmap:
9463 if (bp->regview) {
9464 iounmap(bp->regview);
9465 bp->regview = NULL;
9466 }
9467 if (bp->doorbells) {
9468 iounmap(bp->doorbells);
9469 bp->doorbells = NULL;
9470 }
9471
9472 err_out_release:
9473 if (atomic_read(&pdev->enable_cnt) == 1)
9474 pci_release_regions(pdev);
9475
9476 err_out_disable:
9477 pci_disable_device(pdev);
9478 pci_set_drvdata(pdev, NULL);
9479
9480 err_out:
9481 return rc;
9482 }
9483
9484 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9485 int *width, int *speed)
9486 {
9487 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9488
9489 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9490
9491 /* return value of 1=2.5GHz 2=5GHz */
9492 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9493 }
9494
9495 static int bnx2x_check_firmware(struct bnx2x *bp)
9496 {
9497 const struct firmware *firmware = bp->firmware;
9498 struct bnx2x_fw_file_hdr *fw_hdr;
9499 struct bnx2x_fw_file_section *sections;
9500 u32 offset, len, num_ops;
9501 u16 *ops_offsets;
9502 int i;
9503 const u8 *fw_ver;
9504
9505 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9506 return -EINVAL;
9507
9508 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9509 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9510
9511 /* Make sure none of the offsets and sizes make us read beyond
9512 * the end of the firmware data */
9513 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9514 offset = be32_to_cpu(sections[i].offset);
9515 len = be32_to_cpu(sections[i].len);
9516 if (offset + len > firmware->size) {
9517 dev_err(&bp->pdev->dev,
9518 "Section %d length is out of bounds\n", i);
9519 return -EINVAL;
9520 }
9521 }
9522
9523 /* Likewise for the init_ops offsets */
9524 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9525 ops_offsets = (u16 *)(firmware->data + offset);
9526 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9527
9528 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9529 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9530 dev_err(&bp->pdev->dev,
9531 "Section offset %d is out of bounds\n", i);
9532 return -EINVAL;
9533 }
9534 }
9535
9536 /* Check FW version */
9537 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9538 fw_ver = firmware->data + offset;
9539 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9540 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9541 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9542 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9543 dev_err(&bp->pdev->dev,
9544 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9545 fw_ver[0], fw_ver[1], fw_ver[2],
9546 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9547 BCM_5710_FW_MINOR_VERSION,
9548 BCM_5710_FW_REVISION_VERSION,
9549 BCM_5710_FW_ENGINEERING_VERSION);
9550 return -EINVAL;
9551 }
9552
9553 return 0;
9554 }
9555
9556 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9557 {
9558 const __be32 *source = (const __be32 *)_source;
9559 u32 *target = (u32 *)_target;
9560 u32 i;
9561
9562 for (i = 0; i < n/4; i++)
9563 target[i] = be32_to_cpu(source[i]);
9564 }
9565
9566 /*
9567 Ops array is stored in the following format:
9568 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9569 */
9570 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9571 {
9572 const __be32 *source = (const __be32 *)_source;
9573 struct raw_op *target = (struct raw_op *)_target;
9574 u32 i, j, tmp;
9575
9576 for (i = 0, j = 0; i < n/8; i++, j += 2) {
9577 tmp = be32_to_cpu(source[j]);
9578 target[i].op = (tmp >> 24) & 0xff;
9579 target[i].offset = tmp & 0xffffff;
9580 target[i].raw_data = be32_to_cpu(source[j + 1]);
9581 }
9582 }
9583
9584 /**
9585 * IRO array is stored in the following format:
9586 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9587 */
9588 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9589 {
9590 const __be32 *source = (const __be32 *)_source;
9591 struct iro *target = (struct iro *)_target;
9592 u32 i, j, tmp;
9593
9594 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9595 target[i].base = be32_to_cpu(source[j]);
9596 j++;
9597 tmp = be32_to_cpu(source[j]);
9598 target[i].m1 = (tmp >> 16) & 0xffff;
9599 target[i].m2 = tmp & 0xffff;
9600 j++;
9601 tmp = be32_to_cpu(source[j]);
9602 target[i].m3 = (tmp >> 16) & 0xffff;
9603 target[i].size = tmp & 0xffff;
9604 j++;
9605 }
9606 }
9607
9608 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9609 {
9610 const __be16 *source = (const __be16 *)_source;
9611 u16 *target = (u16 *)_target;
9612 u32 i;
9613
9614 for (i = 0; i < n/2; i++)
9615 target[i] = be16_to_cpu(source[i]);
9616 }
9617
9618 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9619 do { \
9620 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9621 bp->arr = kmalloc(len, GFP_KERNEL); \
9622 if (!bp->arr) { \
9623 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9624 goto lbl; \
9625 } \
9626 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9627 (u8 *)bp->arr, len); \
9628 } while (0)
9629
9630 int bnx2x_init_firmware(struct bnx2x *bp)
9631 {
9632 const char *fw_file_name;
9633 struct bnx2x_fw_file_hdr *fw_hdr;
9634 int rc;
9635
9636 if (CHIP_IS_E1(bp))
9637 fw_file_name = FW_FILE_NAME_E1;
9638 else if (CHIP_IS_E1H(bp))
9639 fw_file_name = FW_FILE_NAME_E1H;
9640 else if (CHIP_IS_E2(bp))
9641 fw_file_name = FW_FILE_NAME_E2;
9642 else {
9643 BNX2X_ERR("Unsupported chip revision\n");
9644 return -EINVAL;
9645 }
9646
9647 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9648
9649 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9650 if (rc) {
9651 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9652 goto request_firmware_exit;
9653 }
9654
9655 rc = bnx2x_check_firmware(bp);
9656 if (rc) {
9657 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9658 goto request_firmware_exit;
9659 }
9660
9661 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9662
9663 /* Initialize the pointers to the init arrays */
9664 /* Blob */
9665 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9666
9667 /* Opcodes */
9668 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9669
9670 /* Offsets */
9671 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9672 be16_to_cpu_n);
9673
9674 /* STORMs firmware */
9675 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9676 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9677 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9678 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9679 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9680 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9681 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9682 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9683 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9684 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9685 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9686 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9687 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9688 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9689 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9690 be32_to_cpu(fw_hdr->csem_pram_data.offset);
9691 /* IRO */
9692 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
9693
9694 return 0;
9695
9696 iro_alloc_err:
9697 kfree(bp->init_ops_offsets);
9698 init_offsets_alloc_err:
9699 kfree(bp->init_ops);
9700 init_ops_alloc_err:
9701 kfree(bp->init_data);
9702 request_firmware_exit:
9703 release_firmware(bp->firmware);
9704
9705 return rc;
9706 }
9707
9708 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9709 {
9710 int cid_count = L2_FP_COUNT(l2_cid_count);
9711
9712 #ifdef BCM_CNIC
9713 cid_count += CNIC_CID_MAX;
9714 #endif
9715 return roundup(cid_count, QM_CID_ROUND);
9716 }
9717
9718 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9719 const struct pci_device_id *ent)
9720 {
9721 struct net_device *dev = NULL;
9722 struct bnx2x *bp;
9723 int pcie_width, pcie_speed;
9724 int rc, cid_count;
9725
9726 switch (ent->driver_data) {
9727 case BCM57710:
9728 case BCM57711:
9729 case BCM57711E:
9730 cid_count = FP_SB_MAX_E1x;
9731 break;
9732
9733 case BCM57712:
9734 case BCM57712E:
9735 cid_count = FP_SB_MAX_E2;
9736 break;
9737
9738 default:
9739 pr_err("Unknown board_type (%ld), aborting\n",
9740 ent->driver_data);
9741 return -ENODEV;
9742 }
9743
9744 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
9745
9746 /* dev zeroed in init_etherdev */
9747 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
9748 if (!dev) {
9749 dev_err(&pdev->dev, "Cannot allocate net device\n");
9750 return -ENOMEM;
9751 }
9752
9753 bp = netdev_priv(dev);
9754 bp->msg_enable = debug;
9755
9756 pci_set_drvdata(pdev, dev);
9757
9758 bp->l2_cid_count = cid_count;
9759
9760 rc = bnx2x_init_dev(pdev, dev);
9761 if (rc < 0) {
9762 free_netdev(dev);
9763 return rc;
9764 }
9765
9766 rc = bnx2x_init_bp(bp);
9767 if (rc)
9768 goto init_one_exit;
9769
9770 /* calc qm_cid_count */
9771 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9772
9773 #ifdef BCM_CNIC
9774 /* disable FCOE L2 queue for E1x*/
9775 if (CHIP_IS_E1x(bp))
9776 bp->flags |= NO_FCOE_FLAG;
9777
9778 #endif
9779
9780 /* Configure interrupt mode: try to enable MSI-X/MSI if
9781 * needed, set bp->num_queues appropriately.
9782 */
9783 bnx2x_set_int_mode(bp);
9784
9785 /* Add all NAPI objects */
9786 bnx2x_add_all_napi(bp);
9787
9788 rc = register_netdev(dev);
9789 if (rc) {
9790 dev_err(&pdev->dev, "Cannot register net device\n");
9791 goto init_one_exit;
9792 }
9793
9794 #ifdef BCM_CNIC
9795 if (!NO_FCOE(bp)) {
9796 /* Add storage MAC address */
9797 rtnl_lock();
9798 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9799 rtnl_unlock();
9800 }
9801 #endif
9802
9803 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
9804
9805 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9806 " IRQ %d, ", board_info[ent->driver_data].name,
9807 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
9808 pcie_width,
9809 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9810 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9811 "5GHz (Gen2)" : "2.5GHz",
9812 dev->base_addr, bp->pdev->irq);
9813 pr_cont("node addr %pM\n", dev->dev_addr);
9814
9815 return 0;
9816
9817 init_one_exit:
9818 if (bp->regview)
9819 iounmap(bp->regview);
9820
9821 if (bp->doorbells)
9822 iounmap(bp->doorbells);
9823
9824 free_netdev(dev);
9825
9826 if (atomic_read(&pdev->enable_cnt) == 1)
9827 pci_release_regions(pdev);
9828
9829 pci_disable_device(pdev);
9830 pci_set_drvdata(pdev, NULL);
9831
9832 return rc;
9833 }
9834
9835 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9836 {
9837 struct net_device *dev = pci_get_drvdata(pdev);
9838 struct bnx2x *bp;
9839
9840 if (!dev) {
9841 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
9842 return;
9843 }
9844 bp = netdev_priv(dev);
9845
9846 #ifdef BCM_CNIC
9847 /* Delete storage MAC address */
9848 if (!NO_FCOE(bp)) {
9849 rtnl_lock();
9850 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9851 rtnl_unlock();
9852 }
9853 #endif
9854
9855 #ifdef BCM_DCBNL
9856 /* Delete app tlvs from dcbnl */
9857 bnx2x_dcbnl_update_applist(bp, true);
9858 #endif
9859
9860 unregister_netdev(dev);
9861
9862 /* Delete all NAPI objects */
9863 bnx2x_del_all_napi(bp);
9864
9865 /* Power on: we can't let PCI layer write to us while we are in D3 */
9866 bnx2x_set_power_state(bp, PCI_D0);
9867
9868 /* Disable MSI/MSI-X */
9869 bnx2x_disable_msi(bp);
9870
9871 /* Power off */
9872 bnx2x_set_power_state(bp, PCI_D3hot);
9873
9874 /* Make sure RESET task is not scheduled before continuing */
9875 cancel_delayed_work_sync(&bp->reset_task);
9876
9877 if (bp->regview)
9878 iounmap(bp->regview);
9879
9880 if (bp->doorbells)
9881 iounmap(bp->doorbells);
9882
9883 bnx2x_free_mem_bp(bp);
9884
9885 free_netdev(dev);
9886
9887 if (atomic_read(&pdev->enable_cnt) == 1)
9888 pci_release_regions(pdev);
9889
9890 pci_disable_device(pdev);
9891 pci_set_drvdata(pdev, NULL);
9892 }
9893
9894 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9895 {
9896 int i;
9897
9898 bp->state = BNX2X_STATE_ERROR;
9899
9900 bp->rx_mode = BNX2X_RX_MODE_NONE;
9901
9902 bnx2x_netif_stop(bp, 0);
9903 netif_carrier_off(bp->dev);
9904
9905 del_timer_sync(&bp->timer);
9906 bp->stats_state = STATS_STATE_DISABLED;
9907 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9908
9909 /* Release IRQs */
9910 bnx2x_free_irq(bp);
9911
9912 /* Free SKBs, SGEs, TPA pool and driver internals */
9913 bnx2x_free_skbs(bp);
9914
9915 for_each_rx_queue(bp, i)
9916 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
9917
9918 bnx2x_free_mem(bp);
9919
9920 bp->state = BNX2X_STATE_CLOSED;
9921
9922 return 0;
9923 }
9924
9925 static void bnx2x_eeh_recover(struct bnx2x *bp)
9926 {
9927 u32 val;
9928
9929 mutex_init(&bp->port.phy_mutex);
9930
9931 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9932 bp->link_params.shmem_base = bp->common.shmem_base;
9933 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9934
9935 if (!bp->common.shmem_base ||
9936 (bp->common.shmem_base < 0xA0000) ||
9937 (bp->common.shmem_base >= 0xC0000)) {
9938 BNX2X_DEV_INFO("MCP not active\n");
9939 bp->flags |= NO_MCP_FLAG;
9940 return;
9941 }
9942
9943 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9944 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9945 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9946 BNX2X_ERR("BAD MCP validity signature\n");
9947
9948 if (!BP_NOMCP(bp)) {
9949 bp->fw_seq =
9950 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9951 DRV_MSG_SEQ_NUMBER_MASK);
9952 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9953 }
9954 }
9955
9956 /**
9957 * bnx2x_io_error_detected - called when PCI error is detected
9958 * @pdev: Pointer to PCI device
9959 * @state: The current pci connection state
9960 *
9961 * This function is called after a PCI bus error affecting
9962 * this device has been detected.
9963 */
9964 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9965 pci_channel_state_t state)
9966 {
9967 struct net_device *dev = pci_get_drvdata(pdev);
9968 struct bnx2x *bp = netdev_priv(dev);
9969
9970 rtnl_lock();
9971
9972 netif_device_detach(dev);
9973
9974 if (state == pci_channel_io_perm_failure) {
9975 rtnl_unlock();
9976 return PCI_ERS_RESULT_DISCONNECT;
9977 }
9978
9979 if (netif_running(dev))
9980 bnx2x_eeh_nic_unload(bp);
9981
9982 pci_disable_device(pdev);
9983
9984 rtnl_unlock();
9985
9986 /* Request a slot reset */
9987 return PCI_ERS_RESULT_NEED_RESET;
9988 }
9989
9990 /**
9991 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9992 * @pdev: Pointer to PCI device
9993 *
9994 * Restart the card from scratch, as if from a cold-boot.
9995 */
9996 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9997 {
9998 struct net_device *dev = pci_get_drvdata(pdev);
9999 struct bnx2x *bp = netdev_priv(dev);
10000
10001 rtnl_lock();
10002
10003 if (pci_enable_device(pdev)) {
10004 dev_err(&pdev->dev,
10005 "Cannot re-enable PCI device after reset\n");
10006 rtnl_unlock();
10007 return PCI_ERS_RESULT_DISCONNECT;
10008 }
10009
10010 pci_set_master(pdev);
10011 pci_restore_state(pdev);
10012
10013 if (netif_running(dev))
10014 bnx2x_set_power_state(bp, PCI_D0);
10015
10016 rtnl_unlock();
10017
10018 return PCI_ERS_RESULT_RECOVERED;
10019 }
10020
10021 /**
10022 * bnx2x_io_resume - called when traffic can start flowing again
10023 * @pdev: Pointer to PCI device
10024 *
10025 * This callback is called when the error recovery driver tells us that
10026 * its OK to resume normal operation.
10027 */
10028 static void bnx2x_io_resume(struct pci_dev *pdev)
10029 {
10030 struct net_device *dev = pci_get_drvdata(pdev);
10031 struct bnx2x *bp = netdev_priv(dev);
10032
10033 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10034 printk(KERN_ERR "Handling parity error recovery. "
10035 "Try again later\n");
10036 return;
10037 }
10038
10039 rtnl_lock();
10040
10041 bnx2x_eeh_recover(bp);
10042
10043 if (netif_running(dev))
10044 bnx2x_nic_load(bp, LOAD_NORMAL);
10045
10046 netif_device_attach(dev);
10047
10048 rtnl_unlock();
10049 }
10050
10051 static struct pci_error_handlers bnx2x_err_handler = {
10052 .error_detected = bnx2x_io_error_detected,
10053 .slot_reset = bnx2x_io_slot_reset,
10054 .resume = bnx2x_io_resume,
10055 };
10056
10057 static struct pci_driver bnx2x_pci_driver = {
10058 .name = DRV_MODULE_NAME,
10059 .id_table = bnx2x_pci_tbl,
10060 .probe = bnx2x_init_one,
10061 .remove = __devexit_p(bnx2x_remove_one),
10062 .suspend = bnx2x_suspend,
10063 .resume = bnx2x_resume,
10064 .err_handler = &bnx2x_err_handler,
10065 };
10066
10067 static int __init bnx2x_init(void)
10068 {
10069 int ret;
10070
10071 pr_info("%s", version);
10072
10073 bnx2x_wq = create_singlethread_workqueue("bnx2x");
10074 if (bnx2x_wq == NULL) {
10075 pr_err("Cannot create workqueue\n");
10076 return -ENOMEM;
10077 }
10078
10079 ret = pci_register_driver(&bnx2x_pci_driver);
10080 if (ret) {
10081 pr_err("Cannot register driver\n");
10082 destroy_workqueue(bnx2x_wq);
10083 }
10084 return ret;
10085 }
10086
10087 static void __exit bnx2x_cleanup(void)
10088 {
10089 pci_unregister_driver(&bnx2x_pci_driver);
10090
10091 destroy_workqueue(bnx2x_wq);
10092 }
10093
10094 module_init(bnx2x_init);
10095 module_exit(bnx2x_cleanup);
10096
10097 #ifdef BCM_CNIC
10098
10099 /* count denotes the number of new completions we have seen */
10100 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
10101 {
10102 struct eth_spe *spe;
10103
10104 #ifdef BNX2X_STOP_ON_ERROR
10105 if (unlikely(bp->panic))
10106 return;
10107 #endif
10108
10109 spin_lock_bh(&bp->spq_lock);
10110 BUG_ON(bp->cnic_spq_pending < count);
10111 bp->cnic_spq_pending -= count;
10112
10113
10114 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
10115 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
10116 & SPE_HDR_CONN_TYPE) >>
10117 SPE_HDR_CONN_TYPE_SHIFT;
10118
10119 /* Set validation for iSCSI L2 client before sending SETUP
10120 * ramrod
10121 */
10122 if (type == ETH_CONNECTION_TYPE) {
10123 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
10124 hdr.conn_and_cmd_data) >>
10125 SPE_HDR_CMD_ID_SHIFT) & 0xff;
10126
10127 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
10128 bnx2x_set_ctx_validation(&bp->context.
10129 vcxt[BNX2X_ISCSI_ETH_CID].eth,
10130 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
10131 }
10132
10133 /* There may be not more than 8 L2 and not more than 8 L5 SPEs
10134 * We also check that the number of outstanding
10135 * COMMON ramrods is not more than the EQ and SPQ can
10136 * accommodate.
10137 */
10138 if (type == ETH_CONNECTION_TYPE) {
10139 if (!atomic_read(&bp->cq_spq_left))
10140 break;
10141 else
10142 atomic_dec(&bp->cq_spq_left);
10143 } else if (type == NONE_CONNECTION_TYPE) {
10144 if (!atomic_read(&bp->eq_spq_left))
10145 break;
10146 else
10147 atomic_dec(&bp->eq_spq_left);
10148 } else if ((type == ISCSI_CONNECTION_TYPE) ||
10149 (type == FCOE_CONNECTION_TYPE)) {
10150 if (bp->cnic_spq_pending >=
10151 bp->cnic_eth_dev.max_kwqe_pending)
10152 break;
10153 else
10154 bp->cnic_spq_pending++;
10155 } else {
10156 BNX2X_ERR("Unknown SPE type: %d\n", type);
10157 bnx2x_panic();
10158 break;
10159 }
10160
10161 spe = bnx2x_sp_get_next(bp);
10162 *spe = *bp->cnic_kwq_cons;
10163
10164 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
10165 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
10166
10167 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
10168 bp->cnic_kwq_cons = bp->cnic_kwq;
10169 else
10170 bp->cnic_kwq_cons++;
10171 }
10172 bnx2x_sp_prod_update(bp);
10173 spin_unlock_bh(&bp->spq_lock);
10174 }
10175
10176 static int bnx2x_cnic_sp_queue(struct net_device *dev,
10177 struct kwqe_16 *kwqes[], u32 count)
10178 {
10179 struct bnx2x *bp = netdev_priv(dev);
10180 int i;
10181
10182 #ifdef BNX2X_STOP_ON_ERROR
10183 if (unlikely(bp->panic))
10184 return -EIO;
10185 #endif
10186
10187 spin_lock_bh(&bp->spq_lock);
10188
10189 for (i = 0; i < count; i++) {
10190 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10191
10192 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10193 break;
10194
10195 *bp->cnic_kwq_prod = *spe;
10196
10197 bp->cnic_kwq_pending++;
10198
10199 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10200 spe->hdr.conn_and_cmd_data, spe->hdr.type,
10201 spe->data.update_data_addr.hi,
10202 spe->data.update_data_addr.lo,
10203 bp->cnic_kwq_pending);
10204
10205 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10206 bp->cnic_kwq_prod = bp->cnic_kwq;
10207 else
10208 bp->cnic_kwq_prod++;
10209 }
10210
10211 spin_unlock_bh(&bp->spq_lock);
10212
10213 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10214 bnx2x_cnic_sp_post(bp, 0);
10215
10216 return i;
10217 }
10218
10219 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10220 {
10221 struct cnic_ops *c_ops;
10222 int rc = 0;
10223
10224 mutex_lock(&bp->cnic_mutex);
10225 c_ops = rcu_dereference_protected(bp->cnic_ops,
10226 lockdep_is_held(&bp->cnic_mutex));
10227 if (c_ops)
10228 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10229 mutex_unlock(&bp->cnic_mutex);
10230
10231 return rc;
10232 }
10233
10234 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10235 {
10236 struct cnic_ops *c_ops;
10237 int rc = 0;
10238
10239 rcu_read_lock();
10240 c_ops = rcu_dereference(bp->cnic_ops);
10241 if (c_ops)
10242 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10243 rcu_read_unlock();
10244
10245 return rc;
10246 }
10247
10248 /*
10249 * for commands that have no data
10250 */
10251 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
10252 {
10253 struct cnic_ctl_info ctl = {0};
10254
10255 ctl.cmd = cmd;
10256
10257 return bnx2x_cnic_ctl_send(bp, &ctl);
10258 }
10259
10260 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
10261 {
10262 struct cnic_ctl_info ctl;
10263
10264 /* first we tell CNIC and only then we count this as a completion */
10265 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10266 ctl.data.comp.cid = cid;
10267
10268 bnx2x_cnic_ctl_send_bh(bp, &ctl);
10269 bnx2x_cnic_sp_post(bp, 0);
10270 }
10271
10272 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10273 {
10274 struct bnx2x *bp = netdev_priv(dev);
10275 int rc = 0;
10276
10277 switch (ctl->cmd) {
10278 case DRV_CTL_CTXTBL_WR_CMD: {
10279 u32 index = ctl->data.io.offset;
10280 dma_addr_t addr = ctl->data.io.dma_addr;
10281
10282 bnx2x_ilt_wr(bp, index, addr);
10283 break;
10284 }
10285
10286 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10287 int count = ctl->data.credit.credit_count;
10288
10289 bnx2x_cnic_sp_post(bp, count);
10290 break;
10291 }
10292
10293 /* rtnl_lock is held. */
10294 case DRV_CTL_START_L2_CMD: {
10295 u32 cli = ctl->data.ring.client_id;
10296
10297 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
10298 bnx2x_del_fcoe_eth_macs(bp);
10299
10300 /* Set iSCSI MAC address */
10301 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
10302
10303 mmiowb();
10304 barrier();
10305
10306 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10307 * because it's the only way for UIO Client to accept
10308 * multicasts (in non-promiscuous mode only one Client per
10309 * function will receive multicast packets (leading in our
10310 * case).
10311 */
10312 bnx2x_rxq_set_mac_filters(bp, cli,
10313 BNX2X_ACCEPT_UNICAST |
10314 BNX2X_ACCEPT_BROADCAST |
10315 BNX2X_ACCEPT_ALL_MULTICAST);
10316 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10317
10318 break;
10319 }
10320
10321 /* rtnl_lock is held. */
10322 case DRV_CTL_STOP_L2_CMD: {
10323 u32 cli = ctl->data.ring.client_id;
10324
10325 /* Stop accepting on iSCSI L2 ring */
10326 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10327 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10328
10329 mmiowb();
10330 barrier();
10331
10332 /* Unset iSCSI L2 MAC */
10333 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
10334 break;
10335 }
10336 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10337 int count = ctl->data.credit.credit_count;
10338
10339 smp_mb__before_atomic_inc();
10340 atomic_add(count, &bp->cq_spq_left);
10341 smp_mb__after_atomic_inc();
10342 break;
10343 }
10344
10345 default:
10346 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10347 rc = -EINVAL;
10348 }
10349
10350 return rc;
10351 }
10352
10353 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
10354 {
10355 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10356
10357 if (bp->flags & USING_MSIX_FLAG) {
10358 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10359 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10360 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10361 } else {
10362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10363 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10364 }
10365 if (CHIP_IS_E2(bp))
10366 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10367 else
10368 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10369
10370 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
10371 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
10372 cp->irq_arr[1].status_blk = bp->def_status_blk;
10373 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10374 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10375
10376 cp->num_irq = 2;
10377 }
10378
10379 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10380 void *data)
10381 {
10382 struct bnx2x *bp = netdev_priv(dev);
10383 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10384
10385 if (ops == NULL)
10386 return -EINVAL;
10387
10388 if (atomic_read(&bp->intr_sem) != 0)
10389 return -EBUSY;
10390
10391 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10392 if (!bp->cnic_kwq)
10393 return -ENOMEM;
10394
10395 bp->cnic_kwq_cons = bp->cnic_kwq;
10396 bp->cnic_kwq_prod = bp->cnic_kwq;
10397 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10398
10399 bp->cnic_spq_pending = 0;
10400 bp->cnic_kwq_pending = 0;
10401
10402 bp->cnic_data = data;
10403
10404 cp->num_irq = 0;
10405 cp->drv_state = CNIC_DRV_STATE_REGD;
10406 cp->iro_arr = bp->iro_arr;
10407
10408 bnx2x_setup_cnic_irq_info(bp);
10409
10410 rcu_assign_pointer(bp->cnic_ops, ops);
10411
10412 return 0;
10413 }
10414
10415 static int bnx2x_unregister_cnic(struct net_device *dev)
10416 {
10417 struct bnx2x *bp = netdev_priv(dev);
10418 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10419
10420 mutex_lock(&bp->cnic_mutex);
10421 cp->drv_state = 0;
10422 rcu_assign_pointer(bp->cnic_ops, NULL);
10423 mutex_unlock(&bp->cnic_mutex);
10424 synchronize_rcu();
10425 kfree(bp->cnic_kwq);
10426 bp->cnic_kwq = NULL;
10427
10428 return 0;
10429 }
10430
10431 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10432 {
10433 struct bnx2x *bp = netdev_priv(dev);
10434 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10435
10436 /* If both iSCSI and FCoE are disabled - return NULL in
10437 * order to indicate CNIC that it should not try to work
10438 * with this device.
10439 */
10440 if (NO_ISCSI(bp) && NO_FCOE(bp))
10441 return NULL;
10442
10443 cp->drv_owner = THIS_MODULE;
10444 cp->chip_id = CHIP_ID(bp);
10445 cp->pdev = bp->pdev;
10446 cp->io_base = bp->regview;
10447 cp->io_base2 = bp->doorbells;
10448 cp->max_kwqe_pending = 8;
10449 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10450 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10451 bnx2x_cid_ilt_lines(bp);
10452 cp->ctx_tbl_len = CNIC_ILT_LINES;
10453 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10454 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10455 cp->drv_ctl = bnx2x_drv_ctl;
10456 cp->drv_register_cnic = bnx2x_register_cnic;
10457 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10458 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10459 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10460 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
10461 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10462
10463 if (NO_ISCSI_OOO(bp))
10464 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10465
10466 if (NO_ISCSI(bp))
10467 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10468
10469 if (NO_FCOE(bp))
10470 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10471
10472 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10473 "starting cid %d\n",
10474 cp->ctx_blk_size,
10475 cp->ctx_tbl_offset,
10476 cp->ctx_tbl_len,
10477 cp->starting_cid);
10478 return cp;
10479 }
10480 EXPORT_SYMBOL(bnx2x_cnic_probe);
10481
10482 #endif /* BCM_CNIC */
10483
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