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Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
41 #include <net/ip.h>
42 #include <net/tcp.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/crc32c.h>
48 #include <linux/prefetch.h>
49 #include <linux/zlib.h>
50 #include <linux/io.h>
51 #include <linux/stringify.h>
52
53 #define BNX2X_MAIN
54 #include "bnx2x.h"
55 #include "bnx2x_init.h"
56 #include "bnx2x_init_ops.h"
57 #include "bnx2x_cmn.h"
58 #include "bnx2x_dcb.h"
59
60 #include <linux/firmware.h>
61 #include "bnx2x_fw_file_hdr.h"
62 /* FW files */
63 #define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
68 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
70 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
71
72 /* Time in jiffies before concluding the transmitter is hung */
73 #define TX_TIMEOUT (5*HZ)
74
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78
79 MODULE_AUTHOR("Eliezer Tamir");
80 MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
84 MODULE_FIRMWARE(FW_FILE_NAME_E1);
85 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
86 MODULE_FIRMWARE(FW_FILE_NAME_E2);
87
88 static int multi_mode = 1;
89 module_param(multi_mode, int, 0);
90 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
92
93 int num_queues;
94 module_param(num_queues, int, 0);
95 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
97
98 static int disable_tpa;
99 module_param(disable_tpa, int, 0);
100 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
101
102 static int int_mode;
103 module_param(int_mode, int, 0);
104 MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
105 "(1 INT#x; 2 MSI)");
106
107 static int dropless_fc;
108 module_param(dropless_fc, int, 0);
109 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
111 static int poll;
112 module_param(poll, int, 0);
113 MODULE_PARM_DESC(poll, " Use polling (for debug)");
114
115 static int mrrs = -1;
116 module_param(mrrs, int, 0);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
119 static int debug;
120 module_param(debug, int, 0);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
122
123 static struct workqueue_struct *bnx2x_wq;
124
125 #ifdef BCM_CNIC
126 static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
127 #endif
128
129 enum bnx2x_board_type {
130 BCM57710 = 0,
131 BCM57711 = 1,
132 BCM57711E = 2,
133 BCM57712 = 3,
134 BCM57712E = 4
135 };
136
137 /* indexed by board_type, above */
138 static struct {
139 char *name;
140 } board_info[] __devinitdata = {
141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
146 };
147
148 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
149 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
150 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
151 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
152 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
153 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
154 { 0 }
155 };
156
157 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
158
159 /****************************************************************************
160 * General service functions
161 ****************************************************************************/
162
163 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
164 u32 addr, dma_addr_t mapping)
165 {
166 REG_WR(bp, addr, U64_LO(mapping));
167 REG_WR(bp, addr + 4, U64_HI(mapping));
168 }
169
170 static inline void __storm_memset_fill(struct bnx2x *bp,
171 u32 addr, size_t size, u32 val)
172 {
173 int i;
174 for (i = 0; i < size/4; i++)
175 REG_WR(bp, addr + (i * 4), val);
176 }
177
178 static inline void storm_memset_ustats_zero(struct bnx2x *bp,
179 u8 port, u16 stat_id)
180 {
181 size_t size = sizeof(struct ustorm_per_client_stats);
182
183 u32 addr = BAR_USTRORM_INTMEM +
184 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
185
186 __storm_memset_fill(bp, addr, size, 0);
187 }
188
189 static inline void storm_memset_tstats_zero(struct bnx2x *bp,
190 u8 port, u16 stat_id)
191 {
192 size_t size = sizeof(struct tstorm_per_client_stats);
193
194 u32 addr = BAR_TSTRORM_INTMEM +
195 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
196
197 __storm_memset_fill(bp, addr, size, 0);
198 }
199
200 static inline void storm_memset_xstats_zero(struct bnx2x *bp,
201 u8 port, u16 stat_id)
202 {
203 size_t size = sizeof(struct xstorm_per_client_stats);
204
205 u32 addr = BAR_XSTRORM_INTMEM +
206 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
207
208 __storm_memset_fill(bp, addr, size, 0);
209 }
210
211
212 static inline void storm_memset_spq_addr(struct bnx2x *bp,
213 dma_addr_t mapping, u16 abs_fid)
214 {
215 u32 addr = XSEM_REG_FAST_MEMORY +
216 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
217
218 __storm_memset_dma_mapping(bp, addr, mapping);
219 }
220
221 static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
222 {
223 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
224 }
225
226 static inline void storm_memset_func_cfg(struct bnx2x *bp,
227 struct tstorm_eth_function_common_config *tcfg,
228 u16 abs_fid)
229 {
230 size_t size = sizeof(struct tstorm_eth_function_common_config);
231
232 u32 addr = BAR_TSTRORM_INTMEM +
233 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
234
235 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
236 }
237
238 static inline void storm_memset_xstats_flags(struct bnx2x *bp,
239 struct stats_indication_flags *flags,
240 u16 abs_fid)
241 {
242 size_t size = sizeof(struct stats_indication_flags);
243
244 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
245
246 __storm_memset_struct(bp, addr, size, (u32 *)flags);
247 }
248
249 static inline void storm_memset_tstats_flags(struct bnx2x *bp,
250 struct stats_indication_flags *flags,
251 u16 abs_fid)
252 {
253 size_t size = sizeof(struct stats_indication_flags);
254
255 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
256
257 __storm_memset_struct(bp, addr, size, (u32 *)flags);
258 }
259
260 static inline void storm_memset_ustats_flags(struct bnx2x *bp,
261 struct stats_indication_flags *flags,
262 u16 abs_fid)
263 {
264 size_t size = sizeof(struct stats_indication_flags);
265
266 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
267
268 __storm_memset_struct(bp, addr, size, (u32 *)flags);
269 }
270
271 static inline void storm_memset_cstats_flags(struct bnx2x *bp,
272 struct stats_indication_flags *flags,
273 u16 abs_fid)
274 {
275 size_t size = sizeof(struct stats_indication_flags);
276
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
278
279 __storm_memset_struct(bp, addr, size, (u32 *)flags);
280 }
281
282 static inline void storm_memset_xstats_addr(struct bnx2x *bp,
283 dma_addr_t mapping, u16 abs_fid)
284 {
285 u32 addr = BAR_XSTRORM_INTMEM +
286 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
287
288 __storm_memset_dma_mapping(bp, addr, mapping);
289 }
290
291 static inline void storm_memset_tstats_addr(struct bnx2x *bp,
292 dma_addr_t mapping, u16 abs_fid)
293 {
294 u32 addr = BAR_TSTRORM_INTMEM +
295 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
296
297 __storm_memset_dma_mapping(bp, addr, mapping);
298 }
299
300 static inline void storm_memset_ustats_addr(struct bnx2x *bp,
301 dma_addr_t mapping, u16 abs_fid)
302 {
303 u32 addr = BAR_USTRORM_INTMEM +
304 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
305
306 __storm_memset_dma_mapping(bp, addr, mapping);
307 }
308
309 static inline void storm_memset_cstats_addr(struct bnx2x *bp,
310 dma_addr_t mapping, u16 abs_fid)
311 {
312 u32 addr = BAR_CSTRORM_INTMEM +
313 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
314
315 __storm_memset_dma_mapping(bp, addr, mapping);
316 }
317
318 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
319 u16 pf_id)
320 {
321 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
322 pf_id);
323 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
324 pf_id);
325 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
326 pf_id);
327 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
328 pf_id);
329 }
330
331 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
332 u8 enable)
333 {
334 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
335 enable);
336 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
337 enable);
338 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
339 enable);
340 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
341 enable);
342 }
343
344 static inline void storm_memset_eq_data(struct bnx2x *bp,
345 struct event_ring_data *eq_data,
346 u16 pfid)
347 {
348 size_t size = sizeof(struct event_ring_data);
349
350 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
351
352 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
353 }
354
355 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
356 u16 pfid)
357 {
358 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
359 REG_WR16(bp, addr, eq_prod);
360 }
361
362 static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
363 u16 fw_sb_id, u8 sb_index,
364 u8 ticks)
365 {
366
367 int index_offset = CHIP_IS_E2(bp) ?
368 offsetof(struct hc_status_block_data_e2, index_data) :
369 offsetof(struct hc_status_block_data_e1x, index_data);
370 u32 addr = BAR_CSTRORM_INTMEM +
371 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
372 index_offset +
373 sizeof(struct hc_index_data)*sb_index +
374 offsetof(struct hc_index_data, timeout);
375 REG_WR8(bp, addr, ticks);
376 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
377 port, fw_sb_id, sb_index, ticks);
378 }
379 static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
380 u16 fw_sb_id, u8 sb_index,
381 u8 disable)
382 {
383 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
384 int index_offset = CHIP_IS_E2(bp) ?
385 offsetof(struct hc_status_block_data_e2, index_data) :
386 offsetof(struct hc_status_block_data_e1x, index_data);
387 u32 addr = BAR_CSTRORM_INTMEM +
388 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
389 index_offset +
390 sizeof(struct hc_index_data)*sb_index +
391 offsetof(struct hc_index_data, flags);
392 u16 flags = REG_RD16(bp, addr);
393 /* clear and set */
394 flags &= ~HC_INDEX_DATA_HC_ENABLED;
395 flags |= enable_flag;
396 REG_WR16(bp, addr, flags);
397 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
398 port, fw_sb_id, sb_index, disable);
399 }
400
401 /* used only at init
402 * locking is done by mcp
403 */
404 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
405 {
406 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
407 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
408 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
409 PCICFG_VENDOR_ID_OFFSET);
410 }
411
412 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
413 {
414 u32 val;
415
416 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
417 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
418 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
419 PCICFG_VENDOR_ID_OFFSET);
420
421 return val;
422 }
423
424 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
425 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
426 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
427 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
428 #define DMAE_DP_DST_NONE "dst_addr [none]"
429
430 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
431 int msglvl)
432 {
433 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
434
435 switch (dmae->opcode & DMAE_COMMAND_DST) {
436 case DMAE_CMD_DST_PCI:
437 if (src_type == DMAE_CMD_SRC_PCI)
438 DP(msglvl, "DMAE: opcode 0x%08x\n"
439 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
440 "comp_addr [%x:%08x], comp_val 0x%08x\n",
441 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
442 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
443 dmae->comp_addr_hi, dmae->comp_addr_lo,
444 dmae->comp_val);
445 else
446 DP(msglvl, "DMAE: opcode 0x%08x\n"
447 "src [%08x], len [%d*4], dst [%x:%08x]\n"
448 "comp_addr [%x:%08x], comp_val 0x%08x\n",
449 dmae->opcode, dmae->src_addr_lo >> 2,
450 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
451 dmae->comp_addr_hi, dmae->comp_addr_lo,
452 dmae->comp_val);
453 break;
454 case DMAE_CMD_DST_GRC:
455 if (src_type == DMAE_CMD_SRC_PCI)
456 DP(msglvl, "DMAE: opcode 0x%08x\n"
457 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
458 "comp_addr [%x:%08x], comp_val 0x%08x\n",
459 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
460 dmae->len, dmae->dst_addr_lo >> 2,
461 dmae->comp_addr_hi, dmae->comp_addr_lo,
462 dmae->comp_val);
463 else
464 DP(msglvl, "DMAE: opcode 0x%08x\n"
465 "src [%08x], len [%d*4], dst [%08x]\n"
466 "comp_addr [%x:%08x], comp_val 0x%08x\n",
467 dmae->opcode, dmae->src_addr_lo >> 2,
468 dmae->len, dmae->dst_addr_lo >> 2,
469 dmae->comp_addr_hi, dmae->comp_addr_lo,
470 dmae->comp_val);
471 break;
472 default:
473 if (src_type == DMAE_CMD_SRC_PCI)
474 DP(msglvl, "DMAE: opcode 0x%08x\n"
475 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
476 "dst_addr [none]\n"
477 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
478 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
479 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
480 dmae->comp_val);
481 else
482 DP(msglvl, "DMAE: opcode 0x%08x\n"
483 DP_LEVEL "src_addr [%08x] len [%d * 4] "
484 "dst_addr [none]\n"
485 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
486 dmae->opcode, dmae->src_addr_lo >> 2,
487 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
488 dmae->comp_val);
489 break;
490 }
491
492 }
493
494 const u32 dmae_reg_go_c[] = {
495 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
496 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
497 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
498 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
499 };
500
501 /* copy command into DMAE command memory and set DMAE command go */
502 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
503 {
504 u32 cmd_offset;
505 int i;
506
507 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
508 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
509 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
510
511 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
512 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
513 }
514 REG_WR(bp, dmae_reg_go_c[idx], 1);
515 }
516
517 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
518 {
519 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
520 DMAE_CMD_C_ENABLE);
521 }
522
523 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
524 {
525 return opcode & ~DMAE_CMD_SRC_RESET;
526 }
527
528 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
529 bool with_comp, u8 comp_type)
530 {
531 u32 opcode = 0;
532
533 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
534 (dst_type << DMAE_COMMAND_DST_SHIFT));
535
536 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
537
538 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
539 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
540 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
541 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
542
543 #ifdef __BIG_ENDIAN
544 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
545 #else
546 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
547 #endif
548 if (with_comp)
549 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
550 return opcode;
551 }
552
553 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
554 struct dmae_command *dmae,
555 u8 src_type, u8 dst_type)
556 {
557 memset(dmae, 0, sizeof(struct dmae_command));
558
559 /* set the opcode */
560 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
561 true, DMAE_COMP_PCI);
562
563 /* fill in the completion parameters */
564 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
565 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
566 dmae->comp_val = DMAE_COMP_VAL;
567 }
568
569 /* issue a dmae command over the init-channel and wailt for completion */
570 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
571 struct dmae_command *dmae)
572 {
573 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
574 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
575 int rc = 0;
576
577 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
578 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
579 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
580
581 /* lock the dmae channel */
582 spin_lock_bh(&bp->dmae_lock);
583
584 /* reset completion */
585 *wb_comp = 0;
586
587 /* post the command on the channel used for initializations */
588 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
589
590 /* wait for completion */
591 udelay(5);
592 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
593 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
594
595 if (!cnt) {
596 BNX2X_ERR("DMAE timeout!\n");
597 rc = DMAE_TIMEOUT;
598 goto unlock;
599 }
600 cnt--;
601 udelay(50);
602 }
603 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
604 BNX2X_ERR("DMAE PCI error!\n");
605 rc = DMAE_PCI_ERROR;
606 }
607
608 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
609 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
610 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
611
612 unlock:
613 spin_unlock_bh(&bp->dmae_lock);
614 return rc;
615 }
616
617 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
618 u32 len32)
619 {
620 struct dmae_command dmae;
621
622 if (!bp->dmae_ready) {
623 u32 *data = bnx2x_sp(bp, wb_data[0]);
624
625 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
626 " using indirect\n", dst_addr, len32);
627 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
628 return;
629 }
630
631 /* set opcode and fixed command fields */
632 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
633
634 /* fill in addresses and len */
635 dmae.src_addr_lo = U64_LO(dma_addr);
636 dmae.src_addr_hi = U64_HI(dma_addr);
637 dmae.dst_addr_lo = dst_addr >> 2;
638 dmae.dst_addr_hi = 0;
639 dmae.len = len32;
640
641 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
642
643 /* issue the command and wait for completion */
644 bnx2x_issue_dmae_with_comp(bp, &dmae);
645 }
646
647 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
648 {
649 struct dmae_command dmae;
650
651 if (!bp->dmae_ready) {
652 u32 *data = bnx2x_sp(bp, wb_data[0]);
653 int i;
654
655 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
656 " using indirect\n", src_addr, len32);
657 for (i = 0; i < len32; i++)
658 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
659 return;
660 }
661
662 /* set opcode and fixed command fields */
663 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
664
665 /* fill in addresses and len */
666 dmae.src_addr_lo = src_addr >> 2;
667 dmae.src_addr_hi = 0;
668 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
669 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
670 dmae.len = len32;
671
672 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
673
674 /* issue the command and wait for completion */
675 bnx2x_issue_dmae_with_comp(bp, &dmae);
676 }
677
678 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
679 u32 addr, u32 len)
680 {
681 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
682 int offset = 0;
683
684 while (len > dmae_wr_max) {
685 bnx2x_write_dmae(bp, phys_addr + offset,
686 addr + offset, dmae_wr_max);
687 offset += dmae_wr_max * 4;
688 len -= dmae_wr_max;
689 }
690
691 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
692 }
693
694 /* used only for slowpath so not inlined */
695 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
696 {
697 u32 wb_write[2];
698
699 wb_write[0] = val_hi;
700 wb_write[1] = val_lo;
701 REG_WR_DMAE(bp, reg, wb_write, 2);
702 }
703
704 #ifdef USE_WB_RD
705 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
706 {
707 u32 wb_data[2];
708
709 REG_RD_DMAE(bp, reg, wb_data, 2);
710
711 return HILO_U64(wb_data[0], wb_data[1]);
712 }
713 #endif
714
715 static int bnx2x_mc_assert(struct bnx2x *bp)
716 {
717 char last_idx;
718 int i, rc = 0;
719 u32 row0, row1, row2, row3;
720
721 /* XSTORM */
722 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
723 XSTORM_ASSERT_LIST_INDEX_OFFSET);
724 if (last_idx)
725 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
726
727 /* print the asserts */
728 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
729
730 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
731 XSTORM_ASSERT_LIST_OFFSET(i));
732 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
733 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
734 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
735 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
736 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
737 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
738
739 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
740 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
741 " 0x%08x 0x%08x 0x%08x\n",
742 i, row3, row2, row1, row0);
743 rc++;
744 } else {
745 break;
746 }
747 }
748
749 /* TSTORM */
750 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
751 TSTORM_ASSERT_LIST_INDEX_OFFSET);
752 if (last_idx)
753 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
754
755 /* print the asserts */
756 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
757
758 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
759 TSTORM_ASSERT_LIST_OFFSET(i));
760 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
761 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
762 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
763 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
764 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
765 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
766
767 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
768 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
769 " 0x%08x 0x%08x 0x%08x\n",
770 i, row3, row2, row1, row0);
771 rc++;
772 } else {
773 break;
774 }
775 }
776
777 /* CSTORM */
778 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
779 CSTORM_ASSERT_LIST_INDEX_OFFSET);
780 if (last_idx)
781 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
782
783 /* print the asserts */
784 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
785
786 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
787 CSTORM_ASSERT_LIST_OFFSET(i));
788 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
789 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
790 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
791 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
792 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
793 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
794
795 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
796 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
797 " 0x%08x 0x%08x 0x%08x\n",
798 i, row3, row2, row1, row0);
799 rc++;
800 } else {
801 break;
802 }
803 }
804
805 /* USTORM */
806 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
807 USTORM_ASSERT_LIST_INDEX_OFFSET);
808 if (last_idx)
809 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
810
811 /* print the asserts */
812 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
813
814 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
815 USTORM_ASSERT_LIST_OFFSET(i));
816 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
817 USTORM_ASSERT_LIST_OFFSET(i) + 4);
818 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
819 USTORM_ASSERT_LIST_OFFSET(i) + 8);
820 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
821 USTORM_ASSERT_LIST_OFFSET(i) + 12);
822
823 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
824 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
825 " 0x%08x 0x%08x 0x%08x\n",
826 i, row3, row2, row1, row0);
827 rc++;
828 } else {
829 break;
830 }
831 }
832
833 return rc;
834 }
835
836 static void bnx2x_fw_dump(struct bnx2x *bp)
837 {
838 u32 addr;
839 u32 mark, offset;
840 __be32 data[9];
841 int word;
842 u32 trace_shmem_base;
843 if (BP_NOMCP(bp)) {
844 BNX2X_ERR("NO MCP - can not dump\n");
845 return;
846 }
847
848 if (BP_PATH(bp) == 0)
849 trace_shmem_base = bp->common.shmem_base;
850 else
851 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
852 addr = trace_shmem_base - 0x0800 + 4;
853 mark = REG_RD(bp, addr);
854 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
855 + ((mark + 0x3) & ~0x3) - 0x08000000;
856 pr_err("begin fw dump (mark 0x%x)\n", mark);
857
858 pr_err("");
859 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
860 for (word = 0; word < 8; word++)
861 data[word] = htonl(REG_RD(bp, offset + 4*word));
862 data[8] = 0x0;
863 pr_cont("%s", (char *)data);
864 }
865 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
866 for (word = 0; word < 8; word++)
867 data[word] = htonl(REG_RD(bp, offset + 4*word));
868 data[8] = 0x0;
869 pr_cont("%s", (char *)data);
870 }
871 pr_err("end of fw dump\n");
872 }
873
874 void bnx2x_panic_dump(struct bnx2x *bp)
875 {
876 int i;
877 u16 j;
878 struct hc_sp_status_block_data sp_sb_data;
879 int func = BP_FUNC(bp);
880 #ifdef BNX2X_STOP_ON_ERROR
881 u16 start = 0, end = 0;
882 #endif
883
884 bp->stats_state = STATS_STATE_DISABLED;
885 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
886
887 BNX2X_ERR("begin crash dump -----------------\n");
888
889 /* Indices */
890 /* Common */
891 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
892 " spq_prod_idx(0x%x)\n",
893 bp->def_idx, bp->def_att_idx,
894 bp->attn_state, bp->spq_prod_idx);
895 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
896 bp->def_status_blk->atten_status_block.attn_bits,
897 bp->def_status_blk->atten_status_block.attn_bits_ack,
898 bp->def_status_blk->atten_status_block.status_block_id,
899 bp->def_status_blk->atten_status_block.attn_bits_index);
900 BNX2X_ERR(" def (");
901 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
902 pr_cont("0x%x%s",
903 bp->def_status_blk->sp_sb.index_values[i],
904 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
905
906 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
907 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
908 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
909 i*sizeof(u32));
910
911 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
912 "pf_id(0x%x) vnic_id(0x%x) "
913 "vf_id(0x%x) vf_valid (0x%x)\n",
914 sp_sb_data.igu_sb_id,
915 sp_sb_data.igu_seg_id,
916 sp_sb_data.p_func.pf_id,
917 sp_sb_data.p_func.vnic_id,
918 sp_sb_data.p_func.vf_id,
919 sp_sb_data.p_func.vf_valid);
920
921
922 for_each_eth_queue(bp, i) {
923 struct bnx2x_fastpath *fp = &bp->fp[i];
924 int loop;
925 struct hc_status_block_data_e2 sb_data_e2;
926 struct hc_status_block_data_e1x sb_data_e1x;
927 struct hc_status_block_sm *hc_sm_p =
928 CHIP_IS_E2(bp) ?
929 sb_data_e2.common.state_machine :
930 sb_data_e1x.common.state_machine;
931 struct hc_index_data *hc_index_p =
932 CHIP_IS_E2(bp) ?
933 sb_data_e2.index_data :
934 sb_data_e1x.index_data;
935 int data_size;
936 u32 *sb_data_p;
937
938 /* Rx */
939 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
940 " rx_comp_prod(0x%x)"
941 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
942 i, fp->rx_bd_prod, fp->rx_bd_cons,
943 fp->rx_comp_prod,
944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
946 " fp_hc_idx(0x%x)\n",
947 fp->rx_sge_prod, fp->last_max_sge,
948 le16_to_cpu(fp->fp_hc_idx));
949
950 /* Tx */
951 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
952 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
953 " *tx_cons_sb(0x%x)\n",
954 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
955 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
956
957 loop = CHIP_IS_E2(bp) ?
958 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
959
960 /* host sb data */
961
962 #ifdef BCM_CNIC
963 if (IS_FCOE_FP(fp))
964 continue;
965 #endif
966 BNX2X_ERR(" run indexes (");
967 for (j = 0; j < HC_SB_MAX_SM; j++)
968 pr_cont("0x%x%s",
969 fp->sb_running_index[j],
970 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
971
972 BNX2X_ERR(" indexes (");
973 for (j = 0; j < loop; j++)
974 pr_cont("0x%x%s",
975 fp->sb_index_values[j],
976 (j == loop - 1) ? ")" : " ");
977 /* fw sb data */
978 data_size = CHIP_IS_E2(bp) ?
979 sizeof(struct hc_status_block_data_e2) :
980 sizeof(struct hc_status_block_data_e1x);
981 data_size /= sizeof(u32);
982 sb_data_p = CHIP_IS_E2(bp) ?
983 (u32 *)&sb_data_e2 :
984 (u32 *)&sb_data_e1x;
985 /* copy sb data in here */
986 for (j = 0; j < data_size; j++)
987 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
988 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
989 j * sizeof(u32));
990
991 if (CHIP_IS_E2(bp)) {
992 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
993 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
994 sb_data_e2.common.p_func.pf_id,
995 sb_data_e2.common.p_func.vf_id,
996 sb_data_e2.common.p_func.vf_valid,
997 sb_data_e2.common.p_func.vnic_id,
998 sb_data_e2.common.same_igu_sb_1b);
999 } else {
1000 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1001 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1002 sb_data_e1x.common.p_func.pf_id,
1003 sb_data_e1x.common.p_func.vf_id,
1004 sb_data_e1x.common.p_func.vf_valid,
1005 sb_data_e1x.common.p_func.vnic_id,
1006 sb_data_e1x.common.same_igu_sb_1b);
1007 }
1008
1009 /* SB_SMs data */
1010 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011 pr_cont("SM[%d] __flags (0x%x) "
1012 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1013 "time_to_expire (0x%x) "
1014 "timer_value(0x%x)\n", j,
1015 hc_sm_p[j].__flags,
1016 hc_sm_p[j].igu_sb_id,
1017 hc_sm_p[j].igu_seg_id,
1018 hc_sm_p[j].time_to_expire,
1019 hc_sm_p[j].timer_value);
1020 }
1021
1022 /* Indecies data */
1023 for (j = 0; j < loop; j++) {
1024 pr_cont("INDEX[%d] flags (0x%x) "
1025 "timeout (0x%x)\n", j,
1026 hc_index_p[j].flags,
1027 hc_index_p[j].timeout);
1028 }
1029 }
1030
1031 #ifdef BNX2X_STOP_ON_ERROR
1032 /* Rings */
1033 /* Rx */
1034 for_each_rx_queue(bp, i) {
1035 struct bnx2x_fastpath *fp = &bp->fp[i];
1036
1037 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1038 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1039 for (j = start; j != end; j = RX_BD(j + 1)) {
1040 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1041 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1042
1043 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1044 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
1045 }
1046
1047 start = RX_SGE(fp->rx_sge_prod);
1048 end = RX_SGE(fp->last_max_sge);
1049 for (j = start; j != end; j = RX_SGE(j + 1)) {
1050 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1051 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1052
1053 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1054 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1055 }
1056
1057 start = RCQ_BD(fp->rx_comp_cons - 10);
1058 end = RCQ_BD(fp->rx_comp_cons + 503);
1059 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1060 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1061
1062 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1063 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1064 }
1065 }
1066
1067 /* Tx */
1068 for_each_tx_queue(bp, i) {
1069 struct bnx2x_fastpath *fp = &bp->fp[i];
1070
1071 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1072 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1073 for (j = start; j != end; j = TX_BD(j + 1)) {
1074 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1075
1076 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1077 i, j, sw_bd->skb, sw_bd->first_bd);
1078 }
1079
1080 start = TX_BD(fp->tx_bd_cons - 10);
1081 end = TX_BD(fp->tx_bd_cons + 254);
1082 for (j = start; j != end; j = TX_BD(j + 1)) {
1083 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1084
1085 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1086 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
1087 }
1088 }
1089 #endif
1090 bnx2x_fw_dump(bp);
1091 bnx2x_mc_assert(bp);
1092 BNX2X_ERR("end crash dump -----------------\n");
1093 }
1094
1095 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1096 {
1097 int port = BP_PORT(bp);
1098 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1099 u32 val = REG_RD(bp, addr);
1100 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1101 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1102
1103 if (msix) {
1104 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1105 HC_CONFIG_0_REG_INT_LINE_EN_0);
1106 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1107 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1108 } else if (msi) {
1109 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1110 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1111 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1112 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1113 } else {
1114 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1115 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1116 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1117 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1118
1119 if (!CHIP_IS_E1(bp)) {
1120 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1121 val, port, addr);
1122
1123 REG_WR(bp, addr, val);
1124
1125 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1126 }
1127 }
1128
1129 if (CHIP_IS_E1(bp))
1130 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1131
1132 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1133 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1134
1135 REG_WR(bp, addr, val);
1136 /*
1137 * Ensure that HC_CONFIG is written before leading/trailing edge config
1138 */
1139 mmiowb();
1140 barrier();
1141
1142 if (!CHIP_IS_E1(bp)) {
1143 /* init leading/trailing edge */
1144 if (IS_MF(bp)) {
1145 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1146 if (bp->port.pmf)
1147 /* enable nig and gpio3 attention */
1148 val |= 0x1100;
1149 } else
1150 val = 0xffff;
1151
1152 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1153 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1154 }
1155
1156 /* Make sure that interrupts are indeed enabled from here on */
1157 mmiowb();
1158 }
1159
1160 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1161 {
1162 u32 val;
1163 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1164 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1165
1166 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1167
1168 if (msix) {
1169 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1170 IGU_PF_CONF_SINGLE_ISR_EN);
1171 val |= (IGU_PF_CONF_FUNC_EN |
1172 IGU_PF_CONF_MSI_MSIX_EN |
1173 IGU_PF_CONF_ATTN_BIT_EN);
1174 } else if (msi) {
1175 val &= ~IGU_PF_CONF_INT_LINE_EN;
1176 val |= (IGU_PF_CONF_FUNC_EN |
1177 IGU_PF_CONF_MSI_MSIX_EN |
1178 IGU_PF_CONF_ATTN_BIT_EN |
1179 IGU_PF_CONF_SINGLE_ISR_EN);
1180 } else {
1181 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1182 val |= (IGU_PF_CONF_FUNC_EN |
1183 IGU_PF_CONF_INT_LINE_EN |
1184 IGU_PF_CONF_ATTN_BIT_EN |
1185 IGU_PF_CONF_SINGLE_ISR_EN);
1186 }
1187
1188 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1189 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1190
1191 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1192
1193 barrier();
1194
1195 /* init leading/trailing edge */
1196 if (IS_MF(bp)) {
1197 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1198 if (bp->port.pmf)
1199 /* enable nig and gpio3 attention */
1200 val |= 0x1100;
1201 } else
1202 val = 0xffff;
1203
1204 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1205 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1206
1207 /* Make sure that interrupts are indeed enabled from here on */
1208 mmiowb();
1209 }
1210
1211 void bnx2x_int_enable(struct bnx2x *bp)
1212 {
1213 if (bp->common.int_block == INT_BLOCK_HC)
1214 bnx2x_hc_int_enable(bp);
1215 else
1216 bnx2x_igu_int_enable(bp);
1217 }
1218
1219 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1220 {
1221 int port = BP_PORT(bp);
1222 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1223 u32 val = REG_RD(bp, addr);
1224
1225 /*
1226 * in E1 we must use only PCI configuration space to disable
1227 * MSI/MSIX capablility
1228 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1229 */
1230 if (CHIP_IS_E1(bp)) {
1231 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1232 * Use mask register to prevent from HC sending interrupts
1233 * after we exit the function
1234 */
1235 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1236
1237 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1238 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1239 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1240 } else
1241 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1242 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1243 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1244 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1245
1246 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1247 val, port, addr);
1248
1249 /* flush all outstanding writes */
1250 mmiowb();
1251
1252 REG_WR(bp, addr, val);
1253 if (REG_RD(bp, addr) != val)
1254 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1255 }
1256
1257 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1258 {
1259 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1260
1261 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1262 IGU_PF_CONF_INT_LINE_EN |
1263 IGU_PF_CONF_ATTN_BIT_EN);
1264
1265 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1266
1267 /* flush all outstanding writes */
1268 mmiowb();
1269
1270 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1271 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1272 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1273 }
1274
1275 static void bnx2x_int_disable(struct bnx2x *bp)
1276 {
1277 if (bp->common.int_block == INT_BLOCK_HC)
1278 bnx2x_hc_int_disable(bp);
1279 else
1280 bnx2x_igu_int_disable(bp);
1281 }
1282
1283 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1284 {
1285 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1286 int i, offset;
1287
1288 /* disable interrupt handling */
1289 atomic_inc(&bp->intr_sem);
1290 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1291
1292 if (disable_hw)
1293 /* prevent the HW from sending interrupts */
1294 bnx2x_int_disable(bp);
1295
1296 /* make sure all ISRs are done */
1297 if (msix) {
1298 synchronize_irq(bp->msix_table[0].vector);
1299 offset = 1;
1300 #ifdef BCM_CNIC
1301 offset++;
1302 #endif
1303 for_each_eth_queue(bp, i)
1304 synchronize_irq(bp->msix_table[i + offset].vector);
1305 } else
1306 synchronize_irq(bp->pdev->irq);
1307
1308 /* make sure sp_task is not running */
1309 cancel_delayed_work(&bp->sp_task);
1310 flush_workqueue(bnx2x_wq);
1311 }
1312
1313 /* fast path */
1314
1315 /*
1316 * General service functions
1317 */
1318
1319 /* Return true if succeeded to acquire the lock */
1320 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1321 {
1322 u32 lock_status;
1323 u32 resource_bit = (1 << resource);
1324 int func = BP_FUNC(bp);
1325 u32 hw_lock_control_reg;
1326
1327 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1328
1329 /* Validating that the resource is within range */
1330 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1331 DP(NETIF_MSG_HW,
1332 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1333 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1334 return false;
1335 }
1336
1337 if (func <= 5)
1338 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1339 else
1340 hw_lock_control_reg =
1341 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1342
1343 /* Try to acquire the lock */
1344 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1345 lock_status = REG_RD(bp, hw_lock_control_reg);
1346 if (lock_status & resource_bit)
1347 return true;
1348
1349 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1350 return false;
1351 }
1352
1353 #ifdef BCM_CNIC
1354 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1355 #endif
1356
1357 void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1358 union eth_rx_cqe *rr_cqe)
1359 {
1360 struct bnx2x *bp = fp->bp;
1361 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1362 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1363
1364 DP(BNX2X_MSG_SP,
1365 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1366 fp->index, cid, command, bp->state,
1367 rr_cqe->ramrod_cqe.ramrod_type);
1368
1369 switch (command | fp->state) {
1370 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1371 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1372 fp->state = BNX2X_FP_STATE_OPEN;
1373 break;
1374
1375 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1376 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1377 fp->state = BNX2X_FP_STATE_HALTED;
1378 break;
1379
1380 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1381 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1382 fp->state = BNX2X_FP_STATE_TERMINATED;
1383 break;
1384
1385 default:
1386 BNX2X_ERR("unexpected MC reply (%d) "
1387 "fp[%d] state is %x\n",
1388 command, fp->index, fp->state);
1389 break;
1390 }
1391
1392 smp_mb__before_atomic_inc();
1393 atomic_inc(&bp->cq_spq_left);
1394 /* push the change in fp->state and towards the memory */
1395 smp_wmb();
1396
1397 return;
1398 }
1399
1400 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1401 {
1402 struct bnx2x *bp = netdev_priv(dev_instance);
1403 u16 status = bnx2x_ack_int(bp);
1404 u16 mask;
1405 int i;
1406
1407 /* Return here if interrupt is shared and it's not for us */
1408 if (unlikely(status == 0)) {
1409 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1410 return IRQ_NONE;
1411 }
1412 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1413
1414 /* Return here if interrupt is disabled */
1415 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1416 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1417 return IRQ_HANDLED;
1418 }
1419
1420 #ifdef BNX2X_STOP_ON_ERROR
1421 if (unlikely(bp->panic))
1422 return IRQ_HANDLED;
1423 #endif
1424
1425 for_each_eth_queue(bp, i) {
1426 struct bnx2x_fastpath *fp = &bp->fp[i];
1427
1428 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1429 if (status & mask) {
1430 /* Handle Rx and Tx according to SB id */
1431 prefetch(fp->rx_cons_sb);
1432 prefetch(fp->tx_cons_sb);
1433 prefetch(&fp->sb_running_index[SM_RX_ID]);
1434 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1435 status &= ~mask;
1436 }
1437 }
1438
1439 #ifdef BCM_CNIC
1440 mask = 0x2;
1441 if (status & (mask | 0x1)) {
1442 struct cnic_ops *c_ops = NULL;
1443
1444 rcu_read_lock();
1445 c_ops = rcu_dereference(bp->cnic_ops);
1446 if (c_ops)
1447 c_ops->cnic_handler(bp->cnic_data, NULL);
1448 rcu_read_unlock();
1449
1450 status &= ~mask;
1451 }
1452 #endif
1453
1454 if (unlikely(status & 0x1)) {
1455 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1456
1457 status &= ~0x1;
1458 if (!status)
1459 return IRQ_HANDLED;
1460 }
1461
1462 if (unlikely(status))
1463 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1464 status);
1465
1466 return IRQ_HANDLED;
1467 }
1468
1469 /* end of fast path */
1470
1471
1472 /* Link */
1473
1474 /*
1475 * General service functions
1476 */
1477
1478 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1479 {
1480 u32 lock_status;
1481 u32 resource_bit = (1 << resource);
1482 int func = BP_FUNC(bp);
1483 u32 hw_lock_control_reg;
1484 int cnt;
1485
1486 /* Validating that the resource is within range */
1487 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1488 DP(NETIF_MSG_HW,
1489 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1490 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1491 return -EINVAL;
1492 }
1493
1494 if (func <= 5) {
1495 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1496 } else {
1497 hw_lock_control_reg =
1498 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1499 }
1500
1501 /* Validating that the resource is not already taken */
1502 lock_status = REG_RD(bp, hw_lock_control_reg);
1503 if (lock_status & resource_bit) {
1504 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1505 lock_status, resource_bit);
1506 return -EEXIST;
1507 }
1508
1509 /* Try for 5 second every 5ms */
1510 for (cnt = 0; cnt < 1000; cnt++) {
1511 /* Try to acquire the lock */
1512 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1513 lock_status = REG_RD(bp, hw_lock_control_reg);
1514 if (lock_status & resource_bit)
1515 return 0;
1516
1517 msleep(5);
1518 }
1519 DP(NETIF_MSG_HW, "Timeout\n");
1520 return -EAGAIN;
1521 }
1522
1523 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1524 {
1525 u32 lock_status;
1526 u32 resource_bit = (1 << resource);
1527 int func = BP_FUNC(bp);
1528 u32 hw_lock_control_reg;
1529
1530 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1531
1532 /* Validating that the resource is within range */
1533 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1534 DP(NETIF_MSG_HW,
1535 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1536 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1537 return -EINVAL;
1538 }
1539
1540 if (func <= 5) {
1541 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1542 } else {
1543 hw_lock_control_reg =
1544 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1545 }
1546
1547 /* Validating that the resource is currently taken */
1548 lock_status = REG_RD(bp, hw_lock_control_reg);
1549 if (!(lock_status & resource_bit)) {
1550 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1551 lock_status, resource_bit);
1552 return -EFAULT;
1553 }
1554
1555 REG_WR(bp, hw_lock_control_reg, resource_bit);
1556 return 0;
1557 }
1558
1559
1560 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1561 {
1562 /* The GPIO should be swapped if swap register is set and active */
1563 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1564 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1565 int gpio_shift = gpio_num +
1566 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1567 u32 gpio_mask = (1 << gpio_shift);
1568 u32 gpio_reg;
1569 int value;
1570
1571 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1572 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1573 return -EINVAL;
1574 }
1575
1576 /* read GPIO value */
1577 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1578
1579 /* get the requested pin value */
1580 if ((gpio_reg & gpio_mask) == gpio_mask)
1581 value = 1;
1582 else
1583 value = 0;
1584
1585 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1586
1587 return value;
1588 }
1589
1590 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1591 {
1592 /* The GPIO should be swapped if swap register is set and active */
1593 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1594 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1595 int gpio_shift = gpio_num +
1596 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1597 u32 gpio_mask = (1 << gpio_shift);
1598 u32 gpio_reg;
1599
1600 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1601 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1602 return -EINVAL;
1603 }
1604
1605 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1606 /* read GPIO and mask except the float bits */
1607 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1608
1609 switch (mode) {
1610 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1611 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1612 gpio_num, gpio_shift);
1613 /* clear FLOAT and set CLR */
1614 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1615 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1616 break;
1617
1618 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1619 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1620 gpio_num, gpio_shift);
1621 /* clear FLOAT and set SET */
1622 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1623 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1624 break;
1625
1626 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1627 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1628 gpio_num, gpio_shift);
1629 /* set FLOAT */
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1631 break;
1632
1633 default:
1634 break;
1635 }
1636
1637 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1638 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1639
1640 return 0;
1641 }
1642
1643 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1644 {
1645 /* The GPIO should be swapped if swap register is set and active */
1646 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1647 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1648 int gpio_shift = gpio_num +
1649 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1650 u32 gpio_mask = (1 << gpio_shift);
1651 u32 gpio_reg;
1652
1653 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1654 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1655 return -EINVAL;
1656 }
1657
1658 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1659 /* read GPIO int */
1660 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1661
1662 switch (mode) {
1663 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1664 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1665 "output low\n", gpio_num, gpio_shift);
1666 /* clear SET and set CLR */
1667 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1668 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1669 break;
1670
1671 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1672 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1673 "output high\n", gpio_num, gpio_shift);
1674 /* clear CLR and set SET */
1675 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1677 break;
1678
1679 default:
1680 break;
1681 }
1682
1683 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1684 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1685
1686 return 0;
1687 }
1688
1689 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1690 {
1691 u32 spio_mask = (1 << spio_num);
1692 u32 spio_reg;
1693
1694 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1695 (spio_num > MISC_REGISTERS_SPIO_7)) {
1696 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1697 return -EINVAL;
1698 }
1699
1700 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1701 /* read SPIO and mask except the float bits */
1702 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1703
1704 switch (mode) {
1705 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1706 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1707 /* clear FLOAT and set CLR */
1708 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1709 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1710 break;
1711
1712 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1714 /* clear FLOAT and set SET */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1717 break;
1718
1719 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1721 /* set FLOAT */
1722 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 break;
1724
1725 default:
1726 break;
1727 }
1728
1729 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1730 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1731
1732 return 0;
1733 }
1734
1735 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1736 {
1737 u32 sel_phy_idx = 0;
1738 if (bp->link_vars.link_up) {
1739 sel_phy_idx = EXT_PHY1;
1740 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1741 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1742 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1743 sel_phy_idx = EXT_PHY2;
1744 } else {
1745
1746 switch (bnx2x_phy_selection(&bp->link_params)) {
1747 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1748 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1749 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1750 sel_phy_idx = EXT_PHY1;
1751 break;
1752 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1753 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1754 sel_phy_idx = EXT_PHY2;
1755 break;
1756 }
1757 }
1758 /*
1759 * The selected actived PHY is always after swapping (in case PHY
1760 * swapping is enabled). So when swapping is enabled, we need to reverse
1761 * the configuration
1762 */
1763
1764 if (bp->link_params.multi_phy_config &
1765 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1766 if (sel_phy_idx == EXT_PHY1)
1767 sel_phy_idx = EXT_PHY2;
1768 else if (sel_phy_idx == EXT_PHY2)
1769 sel_phy_idx = EXT_PHY1;
1770 }
1771 return LINK_CONFIG_IDX(sel_phy_idx);
1772 }
1773
1774 void bnx2x_calc_fc_adv(struct bnx2x *bp)
1775 {
1776 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1777 switch (bp->link_vars.ieee_fc &
1778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1779 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1780 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1781 ADVERTISED_Pause);
1782 break;
1783
1784 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1785 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
1786 ADVERTISED_Pause);
1787 break;
1788
1789 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1790 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
1791 break;
1792
1793 default:
1794 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1795 ADVERTISED_Pause);
1796 break;
1797 }
1798 }
1799
1800 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1801 {
1802 if (!BP_NOMCP(bp)) {
1803 u8 rc;
1804 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1805 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1806 /* Initialize link parameters structure variables */
1807 /* It is recommended to turn off RX FC for jumbo frames
1808 for better performance */
1809 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
1810 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1811 else
1812 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1813
1814 bnx2x_acquire_phy_lock(bp);
1815
1816 if (load_mode == LOAD_DIAG) {
1817 bp->link_params.loopback_mode = LOOPBACK_XGXS;
1818 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1819 }
1820
1821 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1822
1823 bnx2x_release_phy_lock(bp);
1824
1825 bnx2x_calc_fc_adv(bp);
1826
1827 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1828 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1829 bnx2x_link_report(bp);
1830 }
1831 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
1832 return rc;
1833 }
1834 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
1835 return -EINVAL;
1836 }
1837
1838 void bnx2x_link_set(struct bnx2x *bp)
1839 {
1840 if (!BP_NOMCP(bp)) {
1841 bnx2x_acquire_phy_lock(bp);
1842 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1843 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1844 bnx2x_release_phy_lock(bp);
1845
1846 bnx2x_calc_fc_adv(bp);
1847 } else
1848 BNX2X_ERR("Bootcode is missing - can not set link\n");
1849 }
1850
1851 static void bnx2x__link_reset(struct bnx2x *bp)
1852 {
1853 if (!BP_NOMCP(bp)) {
1854 bnx2x_acquire_phy_lock(bp);
1855 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1856 bnx2x_release_phy_lock(bp);
1857 } else
1858 BNX2X_ERR("Bootcode is missing - can not reset link\n");
1859 }
1860
1861 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
1862 {
1863 u8 rc = 0;
1864
1865 if (!BP_NOMCP(bp)) {
1866 bnx2x_acquire_phy_lock(bp);
1867 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1868 is_serdes);
1869 bnx2x_release_phy_lock(bp);
1870 } else
1871 BNX2X_ERR("Bootcode is missing - can not test link\n");
1872
1873 return rc;
1874 }
1875
1876 static void bnx2x_init_port_minmax(struct bnx2x *bp)
1877 {
1878 u32 r_param = bp->link_vars.line_speed / 8;
1879 u32 fair_periodic_timeout_usec;
1880 u32 t_fair;
1881
1882 memset(&(bp->cmng.rs_vars), 0,
1883 sizeof(struct rate_shaping_vars_per_port));
1884 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
1885
1886 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1887 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
1888
1889 /* this is the threshold below which no timer arming will occur
1890 1.25 coefficient is for the threshold to be a little bigger
1891 than the real time, to compensate for timer in-accuracy */
1892 bp->cmng.rs_vars.rs_threshold =
1893 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1894
1895 /* resolution of fairness timer */
1896 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1897 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1898 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
1899
1900 /* this is the threshold below which we won't arm the timer anymore */
1901 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
1902
1903 /* we multiply by 1e3/8 to get bytes/msec.
1904 We don't want the credits to pass a credit
1905 of the t_fair*FAIR_MEM (algorithm resolution) */
1906 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1907 /* since each tick is 4 usec */
1908 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
1909 }
1910
1911 /* Calculates the sum of vn_min_rates.
1912 It's needed for further normalizing of the min_rates.
1913 Returns:
1914 sum of vn_min_rates.
1915 or
1916 0 - if all the min_rates are 0.
1917 In the later case fainess algorithm should be deactivated.
1918 If not all min_rates are zero then those that are zeroes will be set to 1.
1919 */
1920 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1921 {
1922 int all_zero = 1;
1923 int vn;
1924
1925 bp->vn_weight_sum = 0;
1926 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1927 u32 vn_cfg = bp->mf_config[vn];
1928 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1929 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1930
1931 /* Skip hidden vns */
1932 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1933 continue;
1934
1935 /* If min rate is zero - set it to 1 */
1936 if (!vn_min_rate)
1937 vn_min_rate = DEF_MIN_RATE;
1938 else
1939 all_zero = 0;
1940
1941 bp->vn_weight_sum += vn_min_rate;
1942 }
1943
1944 /* ... only if all min rates are zeros - disable fairness */
1945 if (all_zero) {
1946 bp->cmng.flags.cmng_enables &=
1947 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1948 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1949 " fairness will be disabled\n");
1950 } else
1951 bp->cmng.flags.cmng_enables |=
1952 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1953 }
1954
1955 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
1956 {
1957 struct rate_shaping_vars_per_vn m_rs_vn;
1958 struct fairness_vars_per_vn m_fair_vn;
1959 u32 vn_cfg = bp->mf_config[vn];
1960 int func = 2*vn + BP_PORT(bp);
1961 u16 vn_min_rate, vn_max_rate;
1962 int i;
1963
1964 /* If function is hidden - set min and max to zeroes */
1965 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1966 vn_min_rate = 0;
1967 vn_max_rate = 0;
1968
1969 } else {
1970 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
1971
1972 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1973 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1974 /* If fairness is enabled (not all min rates are zeroes) and
1975 if current min rate is zero - set it to 1.
1976 This is a requirement of the algorithm. */
1977 if (bp->vn_weight_sum && (vn_min_rate == 0))
1978 vn_min_rate = DEF_MIN_RATE;
1979
1980 if (IS_MF_SI(bp))
1981 /* maxCfg in percents of linkspeed */
1982 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
1983 else
1984 /* maxCfg is absolute in 100Mb units */
1985 vn_max_rate = maxCfg * 100;
1986 }
1987
1988 DP(NETIF_MSG_IFUP,
1989 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
1990 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
1991
1992 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1993 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1994
1995 /* global vn counter - maximal Mbps for this vn */
1996 m_rs_vn.vn_counter.rate = vn_max_rate;
1997
1998 /* quota - number of bytes transmitted in this period */
1999 m_rs_vn.vn_counter.quota =
2000 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2001
2002 if (bp->vn_weight_sum) {
2003 /* credit for each period of the fairness algorithm:
2004 number of bytes in T_FAIR (the vn share the port rate).
2005 vn_weight_sum should not be larger than 10000, thus
2006 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2007 than zero */
2008 m_fair_vn.vn_credit_delta =
2009 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2010 (8 * bp->vn_weight_sum))),
2011 (bp->cmng.fair_vars.fair_threshold +
2012 MIN_ABOVE_THRESH));
2013 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2014 m_fair_vn.vn_credit_delta);
2015 }
2016
2017 /* Store it to internal memory */
2018 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2019 REG_WR(bp, BAR_XSTRORM_INTMEM +
2020 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2021 ((u32 *)(&m_rs_vn))[i]);
2022
2023 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2024 REG_WR(bp, BAR_XSTRORM_INTMEM +
2025 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2026 ((u32 *)(&m_fair_vn))[i]);
2027 }
2028
2029 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2030 {
2031 if (CHIP_REV_IS_SLOW(bp))
2032 return CMNG_FNS_NONE;
2033 if (IS_MF(bp))
2034 return CMNG_FNS_MINMAX;
2035
2036 return CMNG_FNS_NONE;
2037 }
2038
2039 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2040 {
2041 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2042
2043 if (BP_NOMCP(bp))
2044 return; /* what should be the default bvalue in this case */
2045
2046 /* For 2 port configuration the absolute function number formula
2047 * is:
2048 * abs_func = 2 * vn + BP_PORT + BP_PATH
2049 *
2050 * and there are 4 functions per port
2051 *
2052 * For 4 port configuration it is
2053 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2054 *
2055 * and there are 2 functions per port
2056 */
2057 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2058 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2059
2060 if (func >= E1H_FUNC_MAX)
2061 break;
2062
2063 bp->mf_config[vn] =
2064 MF_CFG_RD(bp, func_mf_config[func].config);
2065 }
2066 }
2067
2068 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2069 {
2070
2071 if (cmng_type == CMNG_FNS_MINMAX) {
2072 int vn;
2073
2074 /* clear cmng_enables */
2075 bp->cmng.flags.cmng_enables = 0;
2076
2077 /* read mf conf from shmem */
2078 if (read_cfg)
2079 bnx2x_read_mf_cfg(bp);
2080
2081 /* Init rate shaping and fairness contexts */
2082 bnx2x_init_port_minmax(bp);
2083
2084 /* vn_weight_sum and enable fairness if not 0 */
2085 bnx2x_calc_vn_weight_sum(bp);
2086
2087 /* calculate and set min-max rate for each vn */
2088 if (bp->port.pmf)
2089 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2090 bnx2x_init_vn_minmax(bp, vn);
2091
2092 /* always enable rate shaping and fairness */
2093 bp->cmng.flags.cmng_enables |=
2094 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2095 if (!bp->vn_weight_sum)
2096 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2097 " fairness will be disabled\n");
2098 return;
2099 }
2100
2101 /* rate shaping and fairness are disabled */
2102 DP(NETIF_MSG_IFUP,
2103 "rate shaping and fairness are disabled\n");
2104 }
2105
2106 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2107 {
2108 int port = BP_PORT(bp);
2109 int func;
2110 int vn;
2111
2112 /* Set the attention towards other drivers on the same port */
2113 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2114 if (vn == BP_E1HVN(bp))
2115 continue;
2116
2117 func = ((vn << 1) | port);
2118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2119 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2120 }
2121 }
2122
2123 /* This function is called upon link interrupt */
2124 static void bnx2x_link_attn(struct bnx2x *bp)
2125 {
2126 /* Make sure that we are synced with the current statistics */
2127 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2128
2129 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2130
2131 if (bp->link_vars.link_up) {
2132
2133 /* dropless flow control */
2134 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2135 int port = BP_PORT(bp);
2136 u32 pause_enabled = 0;
2137
2138 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2139 pause_enabled = 1;
2140
2141 REG_WR(bp, BAR_USTRORM_INTMEM +
2142 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2143 pause_enabled);
2144 }
2145
2146 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2147 struct host_port_stats *pstats;
2148
2149 pstats = bnx2x_sp(bp, port_stats);
2150 /* reset old bmac stats */
2151 memset(&(pstats->mac_stx[0]), 0,
2152 sizeof(struct mac_stx));
2153 }
2154 if (bp->state == BNX2X_STATE_OPEN)
2155 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2156 }
2157
2158 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2159 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2160
2161 if (cmng_fns != CMNG_FNS_NONE) {
2162 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2163 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2164 } else
2165 /* rate shaping and fairness are disabled */
2166 DP(NETIF_MSG_IFUP,
2167 "single function mode without fairness\n");
2168 }
2169
2170 __bnx2x_link_report(bp);
2171
2172 if (IS_MF(bp))
2173 bnx2x_link_sync_notify(bp);
2174 }
2175
2176 void bnx2x__link_status_update(struct bnx2x *bp)
2177 {
2178 if (bp->state != BNX2X_STATE_OPEN)
2179 return;
2180
2181 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2182
2183 if (bp->link_vars.link_up)
2184 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2185 else
2186 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2187
2188 /* indicate link status */
2189 bnx2x_link_report(bp);
2190 }
2191
2192 static void bnx2x_pmf_update(struct bnx2x *bp)
2193 {
2194 int port = BP_PORT(bp);
2195 u32 val;
2196
2197 bp->port.pmf = 1;
2198 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2199
2200 /* enable nig attention */
2201 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2202 if (bp->common.int_block == INT_BLOCK_HC) {
2203 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2204 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2205 } else if (CHIP_IS_E2(bp)) {
2206 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2207 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2208 }
2209
2210 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2211 }
2212
2213 /* end of Link */
2214
2215 /* slow path */
2216
2217 /*
2218 * General service functions
2219 */
2220
2221 /* send the MCP a request, block until there is a reply */
2222 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2223 {
2224 int mb_idx = BP_FW_MB_IDX(bp);
2225 u32 seq;
2226 u32 rc = 0;
2227 u32 cnt = 1;
2228 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2229
2230 mutex_lock(&bp->fw_mb_mutex);
2231 seq = ++bp->fw_seq;
2232 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2233 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2234
2235 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2236
2237 do {
2238 /* let the FW do it's magic ... */
2239 msleep(delay);
2240
2241 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2242
2243 /* Give the FW up to 5 second (500*10ms) */
2244 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2245
2246 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2247 cnt*delay, rc, seq);
2248
2249 /* is this a reply to our command? */
2250 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2251 rc &= FW_MSG_CODE_MASK;
2252 else {
2253 /* FW BUG! */
2254 BNX2X_ERR("FW failed to respond!\n");
2255 bnx2x_fw_dump(bp);
2256 rc = 0;
2257 }
2258 mutex_unlock(&bp->fw_mb_mutex);
2259
2260 return rc;
2261 }
2262
2263 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2264 {
2265 #ifdef BCM_CNIC
2266 if (IS_FCOE_FP(fp) && IS_MF(bp))
2267 return false;
2268 #endif
2269 return true;
2270 }
2271
2272 /* must be called under rtnl_lock */
2273 static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2274 {
2275 u32 mask = (1 << cl_id);
2276
2277 /* initial seeting is BNX2X_ACCEPT_NONE */
2278 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2279 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2280 u8 unmatched_unicast = 0;
2281
2282 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2283 unmatched_unicast = 1;
2284
2285 if (filters & BNX2X_PROMISCUOUS_MODE) {
2286 /* promiscious - accept all, drop none */
2287 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2288 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
2289 if (IS_MF_SI(bp)) {
2290 /*
2291 * SI mode defines to accept in promiscuos mode
2292 * only unmatched packets
2293 */
2294 unmatched_unicast = 1;
2295 accp_all_ucast = 0;
2296 }
2297 }
2298 if (filters & BNX2X_ACCEPT_UNICAST) {
2299 /* accept matched ucast */
2300 drop_all_ucast = 0;
2301 }
2302 if (filters & BNX2X_ACCEPT_MULTICAST)
2303 /* accept matched mcast */
2304 drop_all_mcast = 0;
2305
2306 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2307 /* accept all mcast */
2308 drop_all_ucast = 0;
2309 accp_all_ucast = 1;
2310 }
2311 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2312 /* accept all mcast */
2313 drop_all_mcast = 0;
2314 accp_all_mcast = 1;
2315 }
2316 if (filters & BNX2X_ACCEPT_BROADCAST) {
2317 /* accept (all) bcast */
2318 drop_all_bcast = 0;
2319 accp_all_bcast = 1;
2320 }
2321
2322 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2323 bp->mac_filters.ucast_drop_all | mask :
2324 bp->mac_filters.ucast_drop_all & ~mask;
2325
2326 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2327 bp->mac_filters.mcast_drop_all | mask :
2328 bp->mac_filters.mcast_drop_all & ~mask;
2329
2330 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2331 bp->mac_filters.bcast_drop_all | mask :
2332 bp->mac_filters.bcast_drop_all & ~mask;
2333
2334 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2335 bp->mac_filters.ucast_accept_all | mask :
2336 bp->mac_filters.ucast_accept_all & ~mask;
2337
2338 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2339 bp->mac_filters.mcast_accept_all | mask :
2340 bp->mac_filters.mcast_accept_all & ~mask;
2341
2342 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2343 bp->mac_filters.bcast_accept_all | mask :
2344 bp->mac_filters.bcast_accept_all & ~mask;
2345
2346 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2347 bp->mac_filters.unmatched_unicast | mask :
2348 bp->mac_filters.unmatched_unicast & ~mask;
2349 }
2350
2351 static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2352 {
2353 struct tstorm_eth_function_common_config tcfg = {0};
2354 u16 rss_flgs;
2355
2356 /* tpa */
2357 if (p->func_flgs & FUNC_FLG_TPA)
2358 tcfg.config_flags |=
2359 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2360
2361 /* set rss flags */
2362 rss_flgs = (p->rss->mode <<
2363 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2364
2365 if (p->rss->cap & RSS_IPV4_CAP)
2366 rss_flgs |= RSS_IPV4_CAP_MASK;
2367 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2368 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2369 if (p->rss->cap & RSS_IPV6_CAP)
2370 rss_flgs |= RSS_IPV6_CAP_MASK;
2371 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2372 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2373
2374 tcfg.config_flags |= rss_flgs;
2375 tcfg.rss_result_mask = p->rss->result_mask;
2376
2377 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2378
2379 /* Enable the function in the FW */
2380 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2381 storm_memset_func_en(bp, p->func_id, 1);
2382
2383 /* statistics */
2384 if (p->func_flgs & FUNC_FLG_STATS) {
2385 struct stats_indication_flags stats_flags = {0};
2386 stats_flags.collect_eth = 1;
2387
2388 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2389 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2390
2391 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2392 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2393
2394 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2395 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2396
2397 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2398 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2399 }
2400
2401 /* spq */
2402 if (p->func_flgs & FUNC_FLG_SPQ) {
2403 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2404 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2405 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2406 }
2407 }
2408
2409 static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2410 struct bnx2x_fastpath *fp)
2411 {
2412 u16 flags = 0;
2413
2414 /* calculate queue flags */
2415 flags |= QUEUE_FLG_CACHE_ALIGN;
2416 flags |= QUEUE_FLG_HC;
2417 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
2418
2419 flags |= QUEUE_FLG_VLAN;
2420 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
2421
2422 if (!fp->disable_tpa)
2423 flags |= QUEUE_FLG_TPA;
2424
2425 flags = stat_counter_valid(bp, fp) ?
2426 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
2427
2428 return flags;
2429 }
2430
2431 static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2432 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2433 struct bnx2x_rxq_init_params *rxq_init)
2434 {
2435 u16 max_sge = 0;
2436 u16 sge_sz = 0;
2437 u16 tpa_agg_size = 0;
2438
2439 /* calculate queue flags */
2440 u16 flags = bnx2x_get_cl_flags(bp, fp);
2441
2442 if (!fp->disable_tpa) {
2443 pause->sge_th_hi = 250;
2444 pause->sge_th_lo = 150;
2445 tpa_agg_size = min_t(u32,
2446 (min_t(u32, 8, MAX_SKB_FRAGS) *
2447 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2448 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2449 SGE_PAGE_SHIFT;
2450 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2451 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2452 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2453 0xffff);
2454 }
2455
2456 /* pause - not for e1 */
2457 if (!CHIP_IS_E1(bp)) {
2458 pause->bd_th_hi = 350;
2459 pause->bd_th_lo = 250;
2460 pause->rcq_th_hi = 350;
2461 pause->rcq_th_lo = 250;
2462 pause->sge_th_hi = 0;
2463 pause->sge_th_lo = 0;
2464 pause->pri_map = 1;
2465 }
2466
2467 /* rxq setup */
2468 rxq_init->flags = flags;
2469 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2470 rxq_init->dscr_map = fp->rx_desc_mapping;
2471 rxq_init->sge_map = fp->rx_sge_mapping;
2472 rxq_init->rcq_map = fp->rx_comp_mapping;
2473 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2474
2475 /* Always use mini-jumbo MTU for FCoE L2 ring */
2476 if (IS_FCOE_FP(fp))
2477 rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2478 else
2479 rxq_init->mtu = bp->dev->mtu;
2480
2481 rxq_init->buf_sz = fp->rx_buf_size;
2482 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2483 rxq_init->cl_id = fp->cl_id;
2484 rxq_init->spcl_id = fp->cl_id;
2485 rxq_init->stat_id = fp->cl_id;
2486 rxq_init->tpa_agg_sz = tpa_agg_size;
2487 rxq_init->sge_buf_sz = sge_sz;
2488 rxq_init->max_sges_pkt = max_sge;
2489 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2490 rxq_init->fw_sb_id = fp->fw_sb_id;
2491
2492 if (IS_FCOE_FP(fp))
2493 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2494 else
2495 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2496
2497 rxq_init->cid = HW_CID(bp, fp->cid);
2498
2499 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2500 }
2501
2502 static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2503 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2504 {
2505 u16 flags = bnx2x_get_cl_flags(bp, fp);
2506
2507 txq_init->flags = flags;
2508 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2509 txq_init->dscr_map = fp->tx_desc_mapping;
2510 txq_init->stat_id = fp->cl_id;
2511 txq_init->cid = HW_CID(bp, fp->cid);
2512 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2513 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2514 txq_init->fw_sb_id = fp->fw_sb_id;
2515
2516 if (IS_FCOE_FP(fp)) {
2517 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2518 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2519 }
2520
2521 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2522 }
2523
2524 static void bnx2x_pf_init(struct bnx2x *bp)
2525 {
2526 struct bnx2x_func_init_params func_init = {0};
2527 struct bnx2x_rss_params rss = {0};
2528 struct event_ring_data eq_data = { {0} };
2529 u16 flags;
2530
2531 /* pf specific setups */
2532 if (!CHIP_IS_E1(bp))
2533 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
2534
2535 if (CHIP_IS_E2(bp)) {
2536 /* reset IGU PF statistics: MSIX + ATTN */
2537 /* PF */
2538 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2539 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2540 (CHIP_MODE_IS_4_PORT(bp) ?
2541 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2542 /* ATTN */
2543 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2544 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2545 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2546 (CHIP_MODE_IS_4_PORT(bp) ?
2547 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2548 }
2549
2550 /* function setup flags */
2551 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2552
2553 if (CHIP_IS_E1x(bp))
2554 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2555 else
2556 flags |= FUNC_FLG_TPA;
2557
2558 /* function setup */
2559
2560 /**
2561 * Although RSS is meaningless when there is a single HW queue we
2562 * still need it enabled in order to have HW Rx hash generated.
2563 */
2564 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2565 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2566 rss.mode = bp->multi_mode;
2567 rss.result_mask = MULTI_MASK;
2568 func_init.rss = &rss;
2569
2570 func_init.func_flgs = flags;
2571 func_init.pf_id = BP_FUNC(bp);
2572 func_init.func_id = BP_FUNC(bp);
2573 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2574 func_init.spq_map = bp->spq_mapping;
2575 func_init.spq_prod = bp->spq_prod_idx;
2576
2577 bnx2x_func_init(bp, &func_init);
2578
2579 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2580
2581 /*
2582 Congestion management values depend on the link rate
2583 There is no active link so initial link rate is set to 10 Gbps.
2584 When the link comes up The congestion management values are
2585 re-calculated according to the actual link rate.
2586 */
2587 bp->link_vars.line_speed = SPEED_10000;
2588 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2589
2590 /* Only the PMF sets the HW */
2591 if (bp->port.pmf)
2592 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2593
2594 /* no rx until link is up */
2595 bp->rx_mode = BNX2X_RX_MODE_NONE;
2596 bnx2x_set_storm_rx_mode(bp);
2597
2598 /* init Event Queue */
2599 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2600 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2601 eq_data.producer = bp->eq_prod;
2602 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2603 eq_data.sb_id = DEF_SB_ID;
2604 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2605 }
2606
2607
2608 static void bnx2x_e1h_disable(struct bnx2x *bp)
2609 {
2610 int port = BP_PORT(bp);
2611
2612 netif_tx_disable(bp->dev);
2613
2614 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2615
2616 netif_carrier_off(bp->dev);
2617 }
2618
2619 static void bnx2x_e1h_enable(struct bnx2x *bp)
2620 {
2621 int port = BP_PORT(bp);
2622
2623 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2624
2625 /* Tx queue should be only reenabled */
2626 netif_tx_wake_all_queues(bp->dev);
2627
2628 /*
2629 * Should not call netif_carrier_on since it will be called if the link
2630 * is up when checking for link state
2631 */
2632 }
2633
2634 /* called due to MCP event (on pmf):
2635 * reread new bandwidth configuration
2636 * configure FW
2637 * notify others function about the change
2638 */
2639 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2640 {
2641 if (bp->link_vars.link_up) {
2642 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2643 bnx2x_link_sync_notify(bp);
2644 }
2645 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2646 }
2647
2648 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2649 {
2650 bnx2x_config_mf_bw(bp);
2651 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2652 }
2653
2654 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2655 {
2656 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2657
2658 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2659
2660 /*
2661 * This is the only place besides the function initialization
2662 * where the bp->flags can change so it is done without any
2663 * locks
2664 */
2665 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2666 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2667 bp->flags |= MF_FUNC_DIS;
2668
2669 bnx2x_e1h_disable(bp);
2670 } else {
2671 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2672 bp->flags &= ~MF_FUNC_DIS;
2673
2674 bnx2x_e1h_enable(bp);
2675 }
2676 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2677 }
2678 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2679 bnx2x_config_mf_bw(bp);
2680 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2681 }
2682
2683 /* Report results to MCP */
2684 if (dcc_event)
2685 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2686 else
2687 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2688 }
2689
2690 /* must be called under the spq lock */
2691 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2692 {
2693 struct eth_spe *next_spe = bp->spq_prod_bd;
2694
2695 if (bp->spq_prod_bd == bp->spq_last_bd) {
2696 bp->spq_prod_bd = bp->spq;
2697 bp->spq_prod_idx = 0;
2698 DP(NETIF_MSG_TIMER, "end of spq\n");
2699 } else {
2700 bp->spq_prod_bd++;
2701 bp->spq_prod_idx++;
2702 }
2703 return next_spe;
2704 }
2705
2706 /* must be called under the spq lock */
2707 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2708 {
2709 int func = BP_FUNC(bp);
2710
2711 /* Make sure that BD data is updated before writing the producer */
2712 wmb();
2713
2714 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2715 bp->spq_prod_idx);
2716 mmiowb();
2717 }
2718
2719 /* the slow path queue is odd since completions arrive on the fastpath ring */
2720 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2721 u32 data_hi, u32 data_lo, int common)
2722 {
2723 struct eth_spe *spe;
2724 u16 type;
2725
2726 #ifdef BNX2X_STOP_ON_ERROR
2727 if (unlikely(bp->panic))
2728 return -EIO;
2729 #endif
2730
2731 spin_lock_bh(&bp->spq_lock);
2732
2733 if (common) {
2734 if (!atomic_read(&bp->eq_spq_left)) {
2735 BNX2X_ERR("BUG! EQ ring full!\n");
2736 spin_unlock_bh(&bp->spq_lock);
2737 bnx2x_panic();
2738 return -EBUSY;
2739 }
2740 } else if (!atomic_read(&bp->cq_spq_left)) {
2741 BNX2X_ERR("BUG! SPQ ring full!\n");
2742 spin_unlock_bh(&bp->spq_lock);
2743 bnx2x_panic();
2744 return -EBUSY;
2745 }
2746
2747 spe = bnx2x_sp_get_next(bp);
2748
2749 /* CID needs port number to be encoded int it */
2750 spe->hdr.conn_and_cmd_data =
2751 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2752 HW_CID(bp, cid));
2753
2754 if (common)
2755 /* Common ramrods:
2756 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2757 * TRAFFIC_STOP, TRAFFIC_START
2758 */
2759 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2760 & SPE_HDR_CONN_TYPE;
2761 else
2762 /* ETH ramrods: SETUP, HALT */
2763 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2764 & SPE_HDR_CONN_TYPE;
2765
2766 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2767 SPE_HDR_FUNCTION_ID);
2768
2769 spe->hdr.type = cpu_to_le16(type);
2770
2771 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2772 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2773
2774 /* stats ramrod has it's own slot on the spq */
2775 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
2776 /* It's ok if the actual decrement is issued towards the memory
2777 * somewhere between the spin_lock and spin_unlock. Thus no
2778 * more explict memory barrier is needed.
2779 */
2780 if (common)
2781 atomic_dec(&bp->eq_spq_left);
2782 else
2783 atomic_dec(&bp->cq_spq_left);
2784 }
2785
2786
2787 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2788 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2789 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
2790 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2791 (u32)(U64_LO(bp->spq_mapping) +
2792 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2793 HW_CID(bp, cid), data_hi, data_lo, type,
2794 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
2795
2796 bnx2x_sp_prod_update(bp);
2797 spin_unlock_bh(&bp->spq_lock);
2798 return 0;
2799 }
2800
2801 /* acquire split MCP access lock register */
2802 static int bnx2x_acquire_alr(struct bnx2x *bp)
2803 {
2804 u32 j, val;
2805 int rc = 0;
2806
2807 might_sleep();
2808 for (j = 0; j < 1000; j++) {
2809 val = (1UL << 31);
2810 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2811 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2812 if (val & (1L << 31))
2813 break;
2814
2815 msleep(5);
2816 }
2817 if (!(val & (1L << 31))) {
2818 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2819 rc = -EBUSY;
2820 }
2821
2822 return rc;
2823 }
2824
2825 /* release split MCP access lock register */
2826 static void bnx2x_release_alr(struct bnx2x *bp)
2827 {
2828 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
2829 }
2830
2831 #define BNX2X_DEF_SB_ATT_IDX 0x0001
2832 #define BNX2X_DEF_SB_IDX 0x0002
2833
2834 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2835 {
2836 struct host_sp_status_block *def_sb = bp->def_status_blk;
2837 u16 rc = 0;
2838
2839 barrier(); /* status block is written to by the chip */
2840 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2841 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2842 rc |= BNX2X_DEF_SB_ATT_IDX;
2843 }
2844
2845 if (bp->def_idx != def_sb->sp_sb.running_index) {
2846 bp->def_idx = def_sb->sp_sb.running_index;
2847 rc |= BNX2X_DEF_SB_IDX;
2848 }
2849
2850 /* Do not reorder: indecies reading should complete before handling */
2851 barrier();
2852 return rc;
2853 }
2854
2855 /*
2856 * slow path service functions
2857 */
2858
2859 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2860 {
2861 int port = BP_PORT(bp);
2862 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2863 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2864 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2865 NIG_REG_MASK_INTERRUPT_PORT0;
2866 u32 aeu_mask;
2867 u32 nig_mask = 0;
2868 u32 reg_addr;
2869
2870 if (bp->attn_state & asserted)
2871 BNX2X_ERR("IGU ERROR\n");
2872
2873 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2874 aeu_mask = REG_RD(bp, aeu_addr);
2875
2876 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2877 aeu_mask, asserted);
2878 aeu_mask &= ~(asserted & 0x3ff);
2879 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2880
2881 REG_WR(bp, aeu_addr, aeu_mask);
2882 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2883
2884 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2885 bp->attn_state |= asserted;
2886 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2887
2888 if (asserted & ATTN_HARD_WIRED_MASK) {
2889 if (asserted & ATTN_NIG_FOR_FUNC) {
2890
2891 bnx2x_acquire_phy_lock(bp);
2892
2893 /* save nig interrupt mask */
2894 nig_mask = REG_RD(bp, nig_int_mask_addr);
2895 REG_WR(bp, nig_int_mask_addr, 0);
2896
2897 bnx2x_link_attn(bp);
2898
2899 /* handle unicore attn? */
2900 }
2901 if (asserted & ATTN_SW_TIMER_4_FUNC)
2902 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2903
2904 if (asserted & GPIO_2_FUNC)
2905 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2906
2907 if (asserted & GPIO_3_FUNC)
2908 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2909
2910 if (asserted & GPIO_4_FUNC)
2911 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2912
2913 if (port == 0) {
2914 if (asserted & ATTN_GENERAL_ATTN_1) {
2915 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2916 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2917 }
2918 if (asserted & ATTN_GENERAL_ATTN_2) {
2919 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2920 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2921 }
2922 if (asserted & ATTN_GENERAL_ATTN_3) {
2923 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2924 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2925 }
2926 } else {
2927 if (asserted & ATTN_GENERAL_ATTN_4) {
2928 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2929 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2930 }
2931 if (asserted & ATTN_GENERAL_ATTN_5) {
2932 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2933 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2934 }
2935 if (asserted & ATTN_GENERAL_ATTN_6) {
2936 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2937 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2938 }
2939 }
2940
2941 } /* if hardwired */
2942
2943 if (bp->common.int_block == INT_BLOCK_HC)
2944 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2945 COMMAND_REG_ATTN_BITS_SET);
2946 else
2947 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2948
2949 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2950 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2951 REG_WR(bp, reg_addr, asserted);
2952
2953 /* now set back the mask */
2954 if (asserted & ATTN_NIG_FOR_FUNC) {
2955 REG_WR(bp, nig_int_mask_addr, nig_mask);
2956 bnx2x_release_phy_lock(bp);
2957 }
2958 }
2959
2960 static inline void bnx2x_fan_failure(struct bnx2x *bp)
2961 {
2962 int port = BP_PORT(bp);
2963 u32 ext_phy_config;
2964 /* mark the failure */
2965 ext_phy_config =
2966 SHMEM_RD(bp,
2967 dev_info.port_hw_config[port].external_phy_config);
2968
2969 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2970 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2971 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2972 ext_phy_config);
2973
2974 /* log the failure */
2975 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2976 " the driver to shutdown the card to prevent permanent"
2977 " damage. Please contact OEM Support for assistance\n");
2978 }
2979
2980 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2981 {
2982 int port = BP_PORT(bp);
2983 int reg_offset;
2984 u32 val;
2985
2986 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2987 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2988
2989 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2990
2991 val = REG_RD(bp, reg_offset);
2992 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2993 REG_WR(bp, reg_offset, val);
2994
2995 BNX2X_ERR("SPIO5 hw attention\n");
2996
2997 /* Fan failure attention */
2998 bnx2x_hw_reset_phy(&bp->link_params);
2999 bnx2x_fan_failure(bp);
3000 }
3001
3002 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3003 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3004 bnx2x_acquire_phy_lock(bp);
3005 bnx2x_handle_module_detect_int(&bp->link_params);
3006 bnx2x_release_phy_lock(bp);
3007 }
3008
3009 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3010
3011 val = REG_RD(bp, reg_offset);
3012 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3013 REG_WR(bp, reg_offset, val);
3014
3015 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3016 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3017 bnx2x_panic();
3018 }
3019 }
3020
3021 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3022 {
3023 u32 val;
3024
3025 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3026
3027 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3028 BNX2X_ERR("DB hw attention 0x%x\n", val);
3029 /* DORQ discard attention */
3030 if (val & 0x2)
3031 BNX2X_ERR("FATAL error from DORQ\n");
3032 }
3033
3034 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3035
3036 int port = BP_PORT(bp);
3037 int reg_offset;
3038
3039 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3040 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3041
3042 val = REG_RD(bp, reg_offset);
3043 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3044 REG_WR(bp, reg_offset, val);
3045
3046 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3047 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3048 bnx2x_panic();
3049 }
3050 }
3051
3052 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3053 {
3054 u32 val;
3055
3056 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3057
3058 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3059 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3060 /* CFC error attention */
3061 if (val & 0x2)
3062 BNX2X_ERR("FATAL error from CFC\n");
3063 }
3064
3065 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3066
3067 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3068 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3069 /* RQ_USDMDP_FIFO_OVERFLOW */
3070 if (val & 0x18000)
3071 BNX2X_ERR("FATAL error from PXP\n");
3072 if (CHIP_IS_E2(bp)) {
3073 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3074 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3075 }
3076 }
3077
3078 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3079
3080 int port = BP_PORT(bp);
3081 int reg_offset;
3082
3083 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3084 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3085
3086 val = REG_RD(bp, reg_offset);
3087 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3088 REG_WR(bp, reg_offset, val);
3089
3090 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3091 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3092 bnx2x_panic();
3093 }
3094 }
3095
3096 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3097 {
3098 u32 val;
3099
3100 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3101
3102 if (attn & BNX2X_PMF_LINK_ASSERT) {
3103 int func = BP_FUNC(bp);
3104
3105 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3106 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3107 func_mf_config[BP_ABS_FUNC(bp)].config);
3108 val = SHMEM_RD(bp,
3109 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3110 if (val & DRV_STATUS_DCC_EVENT_MASK)
3111 bnx2x_dcc_event(bp,
3112 (val & DRV_STATUS_DCC_EVENT_MASK));
3113
3114 if (val & DRV_STATUS_SET_MF_BW)
3115 bnx2x_set_mf_bw(bp);
3116
3117 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3118 bnx2x_pmf_update(bp);
3119
3120 /* Always call it here: bnx2x_link_report() will
3121 * prevent the link indication duplication.
3122 */
3123 bnx2x__link_status_update(bp);
3124
3125 if (bp->port.pmf &&
3126 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3127 bp->dcbx_enabled > 0)
3128 /* start dcbx state machine */
3129 bnx2x_dcbx_set_params(bp,
3130 BNX2X_DCBX_STATE_NEG_RECEIVED);
3131 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3132
3133 BNX2X_ERR("MC assert!\n");
3134 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3135 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3136 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3137 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3138 bnx2x_panic();
3139
3140 } else if (attn & BNX2X_MCP_ASSERT) {
3141
3142 BNX2X_ERR("MCP assert!\n");
3143 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3144 bnx2x_fw_dump(bp);
3145
3146 } else
3147 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3148 }
3149
3150 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3151 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3152 if (attn & BNX2X_GRC_TIMEOUT) {
3153 val = CHIP_IS_E1(bp) ? 0 :
3154 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3155 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3156 }
3157 if (attn & BNX2X_GRC_RSV) {
3158 val = CHIP_IS_E1(bp) ? 0 :
3159 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3160 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3161 }
3162 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3163 }
3164 }
3165
3166 #define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3167 #define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3168 #define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3169 #define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3170 #define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
3171
3172 /*
3173 * should be run under rtnl lock
3174 */
3175 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3176 {
3177 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3178 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3179 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3180 barrier();
3181 mmiowb();
3182 }
3183
3184 /*
3185 * should be run under rtnl lock
3186 */
3187 static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3188 {
3189 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3190 val |= (1 << 16);
3191 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3192 barrier();
3193 mmiowb();
3194 }
3195
3196 /*
3197 * should be run under rtnl lock
3198 */
3199 bool bnx2x_reset_is_done(struct bnx2x *bp)
3200 {
3201 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3202 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3203 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3204 }
3205
3206 /*
3207 * should be run under rtnl lock
3208 */
3209 inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
3210 {
3211 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3212
3213 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3214
3215 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3216 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3217 barrier();
3218 mmiowb();
3219 }
3220
3221 /*
3222 * should be run under rtnl lock
3223 */
3224 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3225 {
3226 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3227
3228 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3229
3230 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3231 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3232 barrier();
3233 mmiowb();
3234
3235 return val1;
3236 }
3237
3238 /*
3239 * should be run under rtnl lock
3240 */
3241 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3242 {
3243 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3244 }
3245
3246 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3247 {
3248 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3249 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3250 }
3251
3252 static inline void _print_next_block(int idx, const char *blk)
3253 {
3254 if (idx)
3255 pr_cont(", ");
3256 pr_cont("%s", blk);
3257 }
3258
3259 static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3260 {
3261 int i = 0;
3262 u32 cur_bit = 0;
3263 for (i = 0; sig; i++) {
3264 cur_bit = ((u32)0x1 << i);
3265 if (sig & cur_bit) {
3266 switch (cur_bit) {
3267 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3268 _print_next_block(par_num++, "BRB");
3269 break;
3270 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3271 _print_next_block(par_num++, "PARSER");
3272 break;
3273 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3274 _print_next_block(par_num++, "TSDM");
3275 break;
3276 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3277 _print_next_block(par_num++, "SEARCHER");
3278 break;
3279 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3280 _print_next_block(par_num++, "TSEMI");
3281 break;
3282 }
3283
3284 /* Clear the bit */
3285 sig &= ~cur_bit;
3286 }
3287 }
3288
3289 return par_num;
3290 }
3291
3292 static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3293 {
3294 int i = 0;
3295 u32 cur_bit = 0;
3296 for (i = 0; sig; i++) {
3297 cur_bit = ((u32)0x1 << i);
3298 if (sig & cur_bit) {
3299 switch (cur_bit) {
3300 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3301 _print_next_block(par_num++, "PBCLIENT");
3302 break;
3303 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3304 _print_next_block(par_num++, "QM");
3305 break;
3306 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3307 _print_next_block(par_num++, "XSDM");
3308 break;
3309 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3310 _print_next_block(par_num++, "XSEMI");
3311 break;
3312 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3313 _print_next_block(par_num++, "DOORBELLQ");
3314 break;
3315 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3316 _print_next_block(par_num++, "VAUX PCI CORE");
3317 break;
3318 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3319 _print_next_block(par_num++, "DEBUG");
3320 break;
3321 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3322 _print_next_block(par_num++, "USDM");
3323 break;
3324 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3325 _print_next_block(par_num++, "USEMI");
3326 break;
3327 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3328 _print_next_block(par_num++, "UPB");
3329 break;
3330 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3331 _print_next_block(par_num++, "CSDM");
3332 break;
3333 }
3334
3335 /* Clear the bit */
3336 sig &= ~cur_bit;
3337 }
3338 }
3339
3340 return par_num;
3341 }
3342
3343 static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3344 {
3345 int i = 0;
3346 u32 cur_bit = 0;
3347 for (i = 0; sig; i++) {
3348 cur_bit = ((u32)0x1 << i);
3349 if (sig & cur_bit) {
3350 switch (cur_bit) {
3351 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3352 _print_next_block(par_num++, "CSEMI");
3353 break;
3354 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3355 _print_next_block(par_num++, "PXP");
3356 break;
3357 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3358 _print_next_block(par_num++,
3359 "PXPPCICLOCKCLIENT");
3360 break;
3361 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3362 _print_next_block(par_num++, "CFC");
3363 break;
3364 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3365 _print_next_block(par_num++, "CDU");
3366 break;
3367 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3368 _print_next_block(par_num++, "IGU");
3369 break;
3370 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3371 _print_next_block(par_num++, "MISC");
3372 break;
3373 }
3374
3375 /* Clear the bit */
3376 sig &= ~cur_bit;
3377 }
3378 }
3379
3380 return par_num;
3381 }
3382
3383 static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3384 {
3385 int i = 0;
3386 u32 cur_bit = 0;
3387 for (i = 0; sig; i++) {
3388 cur_bit = ((u32)0x1 << i);
3389 if (sig & cur_bit) {
3390 switch (cur_bit) {
3391 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3392 _print_next_block(par_num++, "MCP ROM");
3393 break;
3394 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3395 _print_next_block(par_num++, "MCP UMP RX");
3396 break;
3397 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3398 _print_next_block(par_num++, "MCP UMP TX");
3399 break;
3400 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3401 _print_next_block(par_num++, "MCP SCPAD");
3402 break;
3403 }
3404
3405 /* Clear the bit */
3406 sig &= ~cur_bit;
3407 }
3408 }
3409
3410 return par_num;
3411 }
3412
3413 static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3414 u32 sig2, u32 sig3)
3415 {
3416 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3417 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3418 int par_num = 0;
3419 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3420 "[0]:0x%08x [1]:0x%08x "
3421 "[2]:0x%08x [3]:0x%08x\n",
3422 sig0 & HW_PRTY_ASSERT_SET_0,
3423 sig1 & HW_PRTY_ASSERT_SET_1,
3424 sig2 & HW_PRTY_ASSERT_SET_2,
3425 sig3 & HW_PRTY_ASSERT_SET_3);
3426 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3427 bp->dev->name);
3428 par_num = bnx2x_print_blocks_with_parity0(
3429 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3430 par_num = bnx2x_print_blocks_with_parity1(
3431 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3432 par_num = bnx2x_print_blocks_with_parity2(
3433 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3434 par_num = bnx2x_print_blocks_with_parity3(
3435 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3436 printk("\n");
3437 return true;
3438 } else
3439 return false;
3440 }
3441
3442 bool bnx2x_chk_parity_attn(struct bnx2x *bp)
3443 {
3444 struct attn_route attn;
3445 int port = BP_PORT(bp);
3446
3447 attn.sig[0] = REG_RD(bp,
3448 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3449 port*4);
3450 attn.sig[1] = REG_RD(bp,
3451 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3452 port*4);
3453 attn.sig[2] = REG_RD(bp,
3454 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3455 port*4);
3456 attn.sig[3] = REG_RD(bp,
3457 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3458 port*4);
3459
3460 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3461 attn.sig[3]);
3462 }
3463
3464
3465 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3466 {
3467 u32 val;
3468 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3469
3470 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3471 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3472 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3473 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3474 "ADDRESS_ERROR\n");
3475 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3476 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3477 "INCORRECT_RCV_BEHAVIOR\n");
3478 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3479 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3480 "WAS_ERROR_ATTN\n");
3481 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3482 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3483 "VF_LENGTH_VIOLATION_ATTN\n");
3484 if (val &
3485 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3486 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3487 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3488 if (val &
3489 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3490 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3491 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3492 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3493 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3494 "TCPL_ERROR_ATTN\n");
3495 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3496 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3497 "TCPL_IN_TWO_RCBS_ATTN\n");
3498 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3499 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3500 "CSSNOOP_FIFO_OVERFLOW\n");
3501 }
3502 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3503 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3504 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3505 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3506 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3507 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3508 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3509 "_ATC_TCPL_TO_NOT_PEND\n");
3510 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3511 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3512 "ATC_GPA_MULTIPLE_HITS\n");
3513 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3514 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3515 "ATC_RCPL_TO_EMPTY_CNT\n");
3516 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3517 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3518 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3519 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3520 "ATC_IREQ_LESS_THAN_STU\n");
3521 }
3522
3523 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3524 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3525 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3526 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3527 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3528 }
3529
3530 }
3531
3532 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3533 {
3534 struct attn_route attn, *group_mask;
3535 int port = BP_PORT(bp);
3536 int index;
3537 u32 reg_addr;
3538 u32 val;
3539 u32 aeu_mask;
3540
3541 /* need to take HW lock because MCP or other port might also
3542 try to handle this event */
3543 bnx2x_acquire_alr(bp);
3544
3545 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
3546 bp->recovery_state = BNX2X_RECOVERY_INIT;
3547 bnx2x_set_reset_in_progress(bp);
3548 schedule_delayed_work(&bp->reset_task, 0);
3549 /* Disable HW interrupts */
3550 bnx2x_int_disable(bp);
3551 bnx2x_release_alr(bp);
3552 /* In case of parity errors don't handle attentions so that
3553 * other function would "see" parity errors.
3554 */
3555 return;
3556 }
3557
3558 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3559 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3560 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3561 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3562 if (CHIP_IS_E2(bp))
3563 attn.sig[4] =
3564 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3565 else
3566 attn.sig[4] = 0;
3567
3568 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3569 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
3570
3571 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3572 if (deasserted & (1 << index)) {
3573 group_mask = &bp->attn_group[index];
3574
3575 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3576 "%08x %08x %08x\n",
3577 index,
3578 group_mask->sig[0], group_mask->sig[1],
3579 group_mask->sig[2], group_mask->sig[3],
3580 group_mask->sig[4]);
3581
3582 bnx2x_attn_int_deasserted4(bp,
3583 attn.sig[4] & group_mask->sig[4]);
3584 bnx2x_attn_int_deasserted3(bp,
3585 attn.sig[3] & group_mask->sig[3]);
3586 bnx2x_attn_int_deasserted1(bp,
3587 attn.sig[1] & group_mask->sig[1]);
3588 bnx2x_attn_int_deasserted2(bp,
3589 attn.sig[2] & group_mask->sig[2]);
3590 bnx2x_attn_int_deasserted0(bp,
3591 attn.sig[0] & group_mask->sig[0]);
3592 }
3593 }
3594
3595 bnx2x_release_alr(bp);
3596
3597 if (bp->common.int_block == INT_BLOCK_HC)
3598 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3599 COMMAND_REG_ATTN_BITS_CLR);
3600 else
3601 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
3602
3603 val = ~deasserted;
3604 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3605 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3606 REG_WR(bp, reg_addr, val);
3607
3608 if (~bp->attn_state & deasserted)
3609 BNX2X_ERR("IGU ERROR\n");
3610
3611 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3612 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3613
3614 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3615 aeu_mask = REG_RD(bp, reg_addr);
3616
3617 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3618 aeu_mask, deasserted);
3619 aeu_mask |= (deasserted & 0x3ff);
3620 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3621
3622 REG_WR(bp, reg_addr, aeu_mask);
3623 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3624
3625 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3626 bp->attn_state &= ~deasserted;
3627 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3628 }
3629
3630 static void bnx2x_attn_int(struct bnx2x *bp)
3631 {
3632 /* read local copy of bits */
3633 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3634 attn_bits);
3635 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3636 attn_bits_ack);
3637 u32 attn_state = bp->attn_state;
3638
3639 /* look for changed bits */
3640 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3641 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3642
3643 DP(NETIF_MSG_HW,
3644 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3645 attn_bits, attn_ack, asserted, deasserted);
3646
3647 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
3648 BNX2X_ERR("BAD attention state\n");
3649
3650 /* handle bits that were raised */
3651 if (asserted)
3652 bnx2x_attn_int_asserted(bp, asserted);
3653
3654 if (deasserted)
3655 bnx2x_attn_int_deasserted(bp, deasserted);
3656 }
3657
3658 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3659 {
3660 /* No memory barriers */
3661 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3662 mmiowb(); /* keep prod updates ordered */
3663 }
3664
3665 #ifdef BCM_CNIC
3666 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3667 union event_ring_elem *elem)
3668 {
3669 if (!bp->cnic_eth_dev.starting_cid ||
3670 (cid < bp->cnic_eth_dev.starting_cid &&
3671 cid != bp->cnic_eth_dev.iscsi_l2_cid))
3672 return 1;
3673
3674 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3675
3676 if (unlikely(elem->message.data.cfc_del_event.error)) {
3677 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3678 cid);
3679 bnx2x_panic_dump(bp);
3680 }
3681 bnx2x_cnic_cfc_comp(bp, cid);
3682 return 0;
3683 }
3684 #endif
3685
3686 static void bnx2x_eq_int(struct bnx2x *bp)
3687 {
3688 u16 hw_cons, sw_cons, sw_prod;
3689 union event_ring_elem *elem;
3690 u32 cid;
3691 u8 opcode;
3692 int spqe_cnt = 0;
3693
3694 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3695
3696 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3697 * when we get the the next-page we nned to adjust so the loop
3698 * condition below will be met. The next element is the size of a
3699 * regular element and hence incrementing by 1
3700 */
3701 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3702 hw_cons++;
3703
3704 /* This function may never run in parallel with itself for a
3705 * specific bp, thus there is no need in "paired" read memory
3706 * barrier here.
3707 */
3708 sw_cons = bp->eq_cons;
3709 sw_prod = bp->eq_prod;
3710
3711 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
3712 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
3713
3714 for (; sw_cons != hw_cons;
3715 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3716
3717
3718 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3719
3720 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3721 opcode = elem->message.opcode;
3722
3723
3724 /* handle eq element */
3725 switch (opcode) {
3726 case EVENT_RING_OPCODE_STAT_QUERY:
3727 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3728 /* nothing to do with stats comp */
3729 continue;
3730
3731 case EVENT_RING_OPCODE_CFC_DEL:
3732 /* handle according to cid range */
3733 /*
3734 * we may want to verify here that the bp state is
3735 * HALTING
3736 */
3737 DP(NETIF_MSG_IFDOWN,
3738 "got delete ramrod for MULTI[%d]\n", cid);
3739 #ifdef BCM_CNIC
3740 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3741 goto next_spqe;
3742 if (cid == BNX2X_FCOE_ETH_CID)
3743 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3744 else
3745 #endif
3746 bnx2x_fp(bp, cid, state) =
3747 BNX2X_FP_STATE_CLOSED;
3748
3749 goto next_spqe;
3750
3751 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3752 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3753 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3754 goto next_spqe;
3755 case EVENT_RING_OPCODE_START_TRAFFIC:
3756 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3757 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3758 goto next_spqe;
3759 }
3760
3761 switch (opcode | bp->state) {
3762 case (EVENT_RING_OPCODE_FUNCTION_START |
3763 BNX2X_STATE_OPENING_WAIT4_PORT):
3764 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3765 bp->state = BNX2X_STATE_FUNC_STARTED;
3766 break;
3767
3768 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3769 BNX2X_STATE_CLOSING_WAIT4_HALT):
3770 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3771 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3772 break;
3773
3774 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3775 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3776 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3777 if (elem->message.data.set_mac_event.echo)
3778 bp->set_mac_pending = 0;
3779 break;
3780
3781 case (EVENT_RING_OPCODE_SET_MAC |
3782 BNX2X_STATE_CLOSING_WAIT4_HALT):
3783 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3784 if (elem->message.data.set_mac_event.echo)
3785 bp->set_mac_pending = 0;
3786 break;
3787 default:
3788 /* unknown event log error and continue */
3789 BNX2X_ERR("Unknown EQ event %d\n",
3790 elem->message.opcode);
3791 }
3792 next_spqe:
3793 spqe_cnt++;
3794 } /* for */
3795
3796 smp_mb__before_atomic_inc();
3797 atomic_add(spqe_cnt, &bp->eq_spq_left);
3798
3799 bp->eq_cons = sw_cons;
3800 bp->eq_prod = sw_prod;
3801 /* Make sure that above mem writes were issued towards the memory */
3802 smp_wmb();
3803
3804 /* update producer */
3805 bnx2x_update_eq_prod(bp, bp->eq_prod);
3806 }
3807
3808 static void bnx2x_sp_task(struct work_struct *work)
3809 {
3810 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
3811 u16 status;
3812
3813 /* Return here if interrupt is disabled */
3814 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3815 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3816 return;
3817 }
3818
3819 status = bnx2x_update_dsb_idx(bp);
3820 /* if (status == 0) */
3821 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
3822
3823 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
3824
3825 /* HW attentions */
3826 if (status & BNX2X_DEF_SB_ATT_IDX) {
3827 bnx2x_attn_int(bp);
3828 status &= ~BNX2X_DEF_SB_ATT_IDX;
3829 }
3830
3831 /* SP events: STAT_QUERY and others */
3832 if (status & BNX2X_DEF_SB_IDX) {
3833 #ifdef BCM_CNIC
3834 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
3835
3836 if ((!NO_FCOE(bp)) &&
3837 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3838 napi_schedule(&bnx2x_fcoe(bp, napi));
3839 #endif
3840 /* Handle EQ completions */
3841 bnx2x_eq_int(bp);
3842
3843 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3844 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3845
3846 status &= ~BNX2X_DEF_SB_IDX;
3847 }
3848
3849 if (unlikely(status))
3850 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3851 status);
3852
3853 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3854 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
3855 }
3856
3857 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3858 {
3859 struct net_device *dev = dev_instance;
3860 struct bnx2x *bp = netdev_priv(dev);
3861
3862 /* Return here if interrupt is disabled */
3863 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3864 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3865 return IRQ_HANDLED;
3866 }
3867
3868 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3869 IGU_INT_DISABLE, 0);
3870
3871 #ifdef BNX2X_STOP_ON_ERROR
3872 if (unlikely(bp->panic))
3873 return IRQ_HANDLED;
3874 #endif
3875
3876 #ifdef BCM_CNIC
3877 {
3878 struct cnic_ops *c_ops;
3879
3880 rcu_read_lock();
3881 c_ops = rcu_dereference(bp->cnic_ops);
3882 if (c_ops)
3883 c_ops->cnic_handler(bp->cnic_data, NULL);
3884 rcu_read_unlock();
3885 }
3886 #endif
3887 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
3888
3889 return IRQ_HANDLED;
3890 }
3891
3892 /* end of slow path */
3893
3894 static void bnx2x_timer(unsigned long data)
3895 {
3896 struct bnx2x *bp = (struct bnx2x *) data;
3897
3898 if (!netif_running(bp->dev))
3899 return;
3900
3901 if (atomic_read(&bp->intr_sem) != 0)
3902 goto timer_restart;
3903
3904 if (poll) {
3905 struct bnx2x_fastpath *fp = &bp->fp[0];
3906
3907 bnx2x_tx_int(fp);
3908 bnx2x_rx_int(fp, 1000);
3909 }
3910
3911 if (!BP_NOMCP(bp)) {
3912 int mb_idx = BP_FW_MB_IDX(bp);
3913 u32 drv_pulse;
3914 u32 mcp_pulse;
3915
3916 ++bp->fw_drv_pulse_wr_seq;
3917 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3918 /* TBD - add SYSTEM_TIME */
3919 drv_pulse = bp->fw_drv_pulse_wr_seq;
3920 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
3921
3922 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
3923 MCP_PULSE_SEQ_MASK);
3924 /* The delta between driver pulse and mcp response
3925 * should be 1 (before mcp response) or 0 (after mcp response)
3926 */
3927 if ((drv_pulse != mcp_pulse) &&
3928 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3929 /* someone lost a heartbeat... */
3930 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3931 drv_pulse, mcp_pulse);
3932 }
3933 }
3934
3935 if (bp->state == BNX2X_STATE_OPEN)
3936 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3937
3938 timer_restart:
3939 mod_timer(&bp->timer, jiffies + bp->current_interval);
3940 }
3941
3942 /* end of Statistics */
3943
3944 /* nic init */
3945
3946 /*
3947 * nic init service functions
3948 */
3949
3950 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
3951 {
3952 u32 i;
3953 if (!(len%4) && !(addr%4))
3954 for (i = 0; i < len; i += 4)
3955 REG_WR(bp, addr + i, fill);
3956 else
3957 for (i = 0; i < len; i++)
3958 REG_WR8(bp, addr + i, fill);
3959
3960 }
3961
3962 /* helper: writes FP SP data to FW - data_size in dwords */
3963 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3964 int fw_sb_id,
3965 u32 *sb_data_p,
3966 u32 data_size)
3967 {
3968 int index;
3969 for (index = 0; index < data_size; index++)
3970 REG_WR(bp, BAR_CSTRORM_INTMEM +
3971 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3972 sizeof(u32)*index,
3973 *(sb_data_p + index));
3974 }
3975
3976 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3977 {
3978 u32 *sb_data_p;
3979 u32 data_size = 0;
3980 struct hc_status_block_data_e2 sb_data_e2;
3981 struct hc_status_block_data_e1x sb_data_e1x;
3982
3983 /* disable the function first */
3984 if (CHIP_IS_E2(bp)) {
3985 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3986 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3987 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3988 sb_data_e2.common.p_func.vf_valid = false;
3989 sb_data_p = (u32 *)&sb_data_e2;
3990 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3991 } else {
3992 memset(&sb_data_e1x, 0,
3993 sizeof(struct hc_status_block_data_e1x));
3994 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3995 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3996 sb_data_e1x.common.p_func.vf_valid = false;
3997 sb_data_p = (u32 *)&sb_data_e1x;
3998 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3999 }
4000 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4001
4002 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4003 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4004 CSTORM_STATUS_BLOCK_SIZE);
4005 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4006 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4007 CSTORM_SYNC_BLOCK_SIZE);
4008 }
4009
4010 /* helper: writes SP SB data to FW */
4011 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4012 struct hc_sp_status_block_data *sp_sb_data)
4013 {
4014 int func = BP_FUNC(bp);
4015 int i;
4016 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4017 REG_WR(bp, BAR_CSTRORM_INTMEM +
4018 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4019 i*sizeof(u32),
4020 *((u32 *)sp_sb_data + i));
4021 }
4022
4023 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4024 {
4025 int func = BP_FUNC(bp);
4026 struct hc_sp_status_block_data sp_sb_data;
4027 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4028
4029 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4030 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4031 sp_sb_data.p_func.vf_valid = false;
4032
4033 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4034
4035 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4036 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4037 CSTORM_SP_STATUS_BLOCK_SIZE);
4038 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4039 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4040 CSTORM_SP_SYNC_BLOCK_SIZE);
4041
4042 }
4043
4044
4045 static inline
4046 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4047 int igu_sb_id, int igu_seg_id)
4048 {
4049 hc_sm->igu_sb_id = igu_sb_id;
4050 hc_sm->igu_seg_id = igu_seg_id;
4051 hc_sm->timer_value = 0xFF;
4052 hc_sm->time_to_expire = 0xFFFFFFFF;
4053 }
4054
4055 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4056 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4057 {
4058 int igu_seg_id;
4059
4060 struct hc_status_block_data_e2 sb_data_e2;
4061 struct hc_status_block_data_e1x sb_data_e1x;
4062 struct hc_status_block_sm *hc_sm_p;
4063 int data_size;
4064 u32 *sb_data_p;
4065
4066 if (CHIP_INT_MODE_IS_BC(bp))
4067 igu_seg_id = HC_SEG_ACCESS_NORM;
4068 else
4069 igu_seg_id = IGU_SEG_ACCESS_NORM;
4070
4071 bnx2x_zero_fp_sb(bp, fw_sb_id);
4072
4073 if (CHIP_IS_E2(bp)) {
4074 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4075 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4076 sb_data_e2.common.p_func.vf_id = vfid;
4077 sb_data_e2.common.p_func.vf_valid = vf_valid;
4078 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4079 sb_data_e2.common.same_igu_sb_1b = true;
4080 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4081 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4082 hc_sm_p = sb_data_e2.common.state_machine;
4083 sb_data_p = (u32 *)&sb_data_e2;
4084 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4085 } else {
4086 memset(&sb_data_e1x, 0,
4087 sizeof(struct hc_status_block_data_e1x));
4088 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4089 sb_data_e1x.common.p_func.vf_id = 0xff;
4090 sb_data_e1x.common.p_func.vf_valid = false;
4091 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4092 sb_data_e1x.common.same_igu_sb_1b = true;
4093 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4094 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4095 hc_sm_p = sb_data_e1x.common.state_machine;
4096 sb_data_p = (u32 *)&sb_data_e1x;
4097 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4098 }
4099
4100 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4101 igu_sb_id, igu_seg_id);
4102 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4103 igu_sb_id, igu_seg_id);
4104
4105 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4106
4107 /* write indecies to HW */
4108 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4109 }
4110
4111 static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4112 u8 sb_index, u8 disable, u16 usec)
4113 {
4114 int port = BP_PORT(bp);
4115 u8 ticks = usec / BNX2X_BTR;
4116
4117 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4118
4119 disable = disable ? 1 : (usec ? 0 : 1);
4120 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4121 }
4122
4123 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4124 u16 tx_usec, u16 rx_usec)
4125 {
4126 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4127 false, rx_usec);
4128 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4129 false, tx_usec);
4130 }
4131
4132 static void bnx2x_init_def_sb(struct bnx2x *bp)
4133 {
4134 struct host_sp_status_block *def_sb = bp->def_status_blk;
4135 dma_addr_t mapping = bp->def_status_blk_mapping;
4136 int igu_sp_sb_index;
4137 int igu_seg_id;
4138 int port = BP_PORT(bp);
4139 int func = BP_FUNC(bp);
4140 int reg_offset;
4141 u64 section;
4142 int index;
4143 struct hc_sp_status_block_data sp_sb_data;
4144 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4145
4146 if (CHIP_INT_MODE_IS_BC(bp)) {
4147 igu_sp_sb_index = DEF_SB_IGU_ID;
4148 igu_seg_id = HC_SEG_ACCESS_DEF;
4149 } else {
4150 igu_sp_sb_index = bp->igu_dsb_id;
4151 igu_seg_id = IGU_SEG_ACCESS_DEF;
4152 }
4153
4154 /* ATTN */
4155 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4156 atten_status_block);
4157 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4158
4159 bp->attn_state = 0;
4160
4161 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4162 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4163 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4164 int sindex;
4165 /* take care of sig[0]..sig[4] */
4166 for (sindex = 0; sindex < 4; sindex++)
4167 bp->attn_group[index].sig[sindex] =
4168 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4169
4170 if (CHIP_IS_E2(bp))
4171 /*
4172 * enable5 is separate from the rest of the registers,
4173 * and therefore the address skip is 4
4174 * and not 16 between the different groups
4175 */
4176 bp->attn_group[index].sig[4] = REG_RD(bp,
4177 reg_offset + 0x10 + 0x4*index);
4178 else
4179 bp->attn_group[index].sig[4] = 0;
4180 }
4181
4182 if (bp->common.int_block == INT_BLOCK_HC) {
4183 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4184 HC_REG_ATTN_MSG0_ADDR_L);
4185
4186 REG_WR(bp, reg_offset, U64_LO(section));
4187 REG_WR(bp, reg_offset + 4, U64_HI(section));
4188 } else if (CHIP_IS_E2(bp)) {
4189 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4190 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4191 }
4192
4193 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4194 sp_sb);
4195
4196 bnx2x_zero_sp_sb(bp);
4197
4198 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4199 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4200 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4201 sp_sb_data.igu_seg_id = igu_seg_id;
4202 sp_sb_data.p_func.pf_id = func;
4203 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4204 sp_sb_data.p_func.vf_id = 0xff;
4205
4206 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4207
4208 bp->stats_pending = 0;
4209 bp->set_mac_pending = 0;
4210
4211 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4212 }
4213
4214 void bnx2x_update_coalesce(struct bnx2x *bp)
4215 {
4216 int i;
4217
4218 for_each_eth_queue(bp, i)
4219 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4220 bp->tx_ticks, bp->rx_ticks);
4221 }
4222
4223 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4224 {
4225 spin_lock_init(&bp->spq_lock);
4226 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4227
4228 bp->spq_prod_idx = 0;
4229 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4230 bp->spq_prod_bd = bp->spq;
4231 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4232 }
4233
4234 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4235 {
4236 int i;
4237 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4238 union event_ring_elem *elem =
4239 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4240
4241 elem->next_page.addr.hi =
4242 cpu_to_le32(U64_HI(bp->eq_mapping +
4243 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4244 elem->next_page.addr.lo =
4245 cpu_to_le32(U64_LO(bp->eq_mapping +
4246 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4247 }
4248 bp->eq_cons = 0;
4249 bp->eq_prod = NUM_EQ_DESC;
4250 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4251 /* we want a warning message before it gets rought... */
4252 atomic_set(&bp->eq_spq_left,
4253 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
4254 }
4255
4256 void bnx2x_push_indir_table(struct bnx2x *bp)
4257 {
4258 int func = BP_FUNC(bp);
4259 int i;
4260
4261 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4262 return;
4263
4264 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4265 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4266 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4267 bp->fp->cl_id + bp->rx_indir_table[i]);
4268 }
4269
4270 static void bnx2x_init_ind_table(struct bnx2x *bp)
4271 {
4272 int i;
4273
4274 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4275 bp->rx_indir_table[i] = i % BNX2X_NUM_ETH_QUEUES(bp);
4276
4277 bnx2x_push_indir_table(bp);
4278 }
4279
4280 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4281 {
4282 int mode = bp->rx_mode;
4283 int port = BP_PORT(bp);
4284 u16 cl_id;
4285 u32 def_q_filters = 0;
4286
4287 /* All but management unicast packets should pass to the host as well */
4288 u32 llh_mask =
4289 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4290 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4291 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4292 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
4293
4294 switch (mode) {
4295 case BNX2X_RX_MODE_NONE: /* no Rx */
4296 def_q_filters = BNX2X_ACCEPT_NONE;
4297 #ifdef BCM_CNIC
4298 if (!NO_FCOE(bp)) {
4299 cl_id = bnx2x_fcoe(bp, cl_id);
4300 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4301 }
4302 #endif
4303 break;
4304
4305 case BNX2X_RX_MODE_NORMAL:
4306 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4307 BNX2X_ACCEPT_MULTICAST;
4308 #ifdef BCM_CNIC
4309 if (!NO_FCOE(bp)) {
4310 cl_id = bnx2x_fcoe(bp, cl_id);
4311 bnx2x_rxq_set_mac_filters(bp, cl_id,
4312 BNX2X_ACCEPT_UNICAST |
4313 BNX2X_ACCEPT_MULTICAST);
4314 }
4315 #endif
4316 break;
4317
4318 case BNX2X_RX_MODE_ALLMULTI:
4319 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4320 BNX2X_ACCEPT_ALL_MULTICAST;
4321 #ifdef BCM_CNIC
4322 /*
4323 * Prevent duplication of multicast packets by configuring FCoE
4324 * L2 Client to receive only matched unicast frames.
4325 */
4326 if (!NO_FCOE(bp)) {
4327 cl_id = bnx2x_fcoe(bp, cl_id);
4328 bnx2x_rxq_set_mac_filters(bp, cl_id,
4329 BNX2X_ACCEPT_UNICAST);
4330 }
4331 #endif
4332 break;
4333
4334 case BNX2X_RX_MODE_PROMISC:
4335 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4336 #ifdef BCM_CNIC
4337 /*
4338 * Prevent packets duplication by configuring DROP_ALL for FCoE
4339 * L2 Client.
4340 */
4341 if (!NO_FCOE(bp)) {
4342 cl_id = bnx2x_fcoe(bp, cl_id);
4343 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4344 }
4345 #endif
4346 /* pass management unicast packets as well */
4347 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
4348 break;
4349
4350 default:
4351 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4352 break;
4353 }
4354
4355 cl_id = BP_L_ID(bp);
4356 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4357
4358 REG_WR(bp,
4359 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4360 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
4361
4362 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4363 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
4364 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4365 "unmatched_ucast 0x%x\n", mode,
4366 bp->mac_filters.ucast_drop_all,
4367 bp->mac_filters.mcast_drop_all,
4368 bp->mac_filters.bcast_drop_all,
4369 bp->mac_filters.ucast_accept_all,
4370 bp->mac_filters.mcast_accept_all,
4371 bp->mac_filters.bcast_accept_all,
4372 bp->mac_filters.unmatched_unicast
4373 );
4374
4375 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
4376 }
4377
4378 static void bnx2x_init_internal_common(struct bnx2x *bp)
4379 {
4380 int i;
4381
4382 if (!CHIP_IS_E1(bp)) {
4383
4384 /* xstorm needs to know whether to add ovlan to packets or not,
4385 * in switch-independent we'll write 0 to here... */
4386 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4387 bp->mf_mode);
4388 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4389 bp->mf_mode);
4390 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4391 bp->mf_mode);
4392 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4393 bp->mf_mode);
4394 }
4395
4396 if (IS_MF_SI(bp))
4397 /*
4398 * In switch independent mode, the TSTORM needs to accept
4399 * packets that failed classification, since approximate match
4400 * mac addresses aren't written to NIG LLH
4401 */
4402 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4403 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4404
4405 /* Zero this manually as its initialization is
4406 currently missing in the initTool */
4407 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4408 REG_WR(bp, BAR_USTRORM_INTMEM +
4409 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4410 if (CHIP_IS_E2(bp)) {
4411 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4412 CHIP_INT_MODE_IS_BC(bp) ?
4413 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4414 }
4415 }
4416
4417 static void bnx2x_init_internal_port(struct bnx2x *bp)
4418 {
4419 /* port */
4420 bnx2x_dcb_init_intmem_pfc(bp);
4421 }
4422
4423 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4424 {
4425 switch (load_code) {
4426 case FW_MSG_CODE_DRV_LOAD_COMMON:
4427 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4428 bnx2x_init_internal_common(bp);
4429 /* no break */
4430
4431 case FW_MSG_CODE_DRV_LOAD_PORT:
4432 bnx2x_init_internal_port(bp);
4433 /* no break */
4434
4435 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4436 /* internal memory per function is
4437 initialized inside bnx2x_pf_init */
4438 break;
4439
4440 default:
4441 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4442 break;
4443 }
4444 }
4445
4446 static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4447 {
4448 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4449
4450 fp->state = BNX2X_FP_STATE_CLOSED;
4451
4452 fp->cid = fp_idx;
4453 fp->cl_id = BP_L_ID(bp) + fp_idx;
4454 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4455 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4456 /* qZone id equals to FW (per path) client id */
4457 fp->cl_qzone_id = fp->cl_id +
4458 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4459 ETH_MAX_RX_CLIENTS_E1H);
4460 /* init shortcut */
4461 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4462 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
4463 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4464 /* Setup SB indicies */
4465 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4466 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4467
4468 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4469 "cl_id %d fw_sb %d igu_sb %d\n",
4470 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4471 fp->igu_sb_id);
4472 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4473 fp->fw_sb_id, fp->igu_sb_id);
4474
4475 bnx2x_update_fpsb_idx(fp);
4476 }
4477
4478 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4479 {
4480 int i;
4481
4482 for_each_eth_queue(bp, i)
4483 bnx2x_init_fp_sb(bp, i);
4484 #ifdef BCM_CNIC
4485 if (!NO_FCOE(bp))
4486 bnx2x_init_fcoe_fp(bp);
4487
4488 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4489 BNX2X_VF_ID_INVALID, false,
4490 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4491
4492 #endif
4493
4494 /* ensure status block indices were read */
4495 rmb();
4496
4497 bnx2x_init_def_sb(bp);
4498 bnx2x_update_dsb_idx(bp);
4499 bnx2x_init_rx_rings(bp);
4500 bnx2x_init_tx_rings(bp);
4501 bnx2x_init_sp_ring(bp);
4502 bnx2x_init_eq_ring(bp);
4503 bnx2x_init_internal(bp, load_code);
4504 bnx2x_pf_init(bp);
4505 bnx2x_init_ind_table(bp);
4506 bnx2x_stats_init(bp);
4507
4508 /* At this point, we are ready for interrupts */
4509 atomic_set(&bp->intr_sem, 0);
4510
4511 /* flush all before enabling interrupts */
4512 mb();
4513 mmiowb();
4514
4515 bnx2x_int_enable(bp);
4516
4517 /* Check for SPIO5 */
4518 bnx2x_attn_int_deasserted0(bp,
4519 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4520 AEU_INPUTS_ATTN_BITS_SPIO5);
4521 }
4522
4523 /* end of nic init */
4524
4525 /*
4526 * gzip service functions
4527 */
4528
4529 static int bnx2x_gunzip_init(struct bnx2x *bp)
4530 {
4531 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4532 &bp->gunzip_mapping, GFP_KERNEL);
4533 if (bp->gunzip_buf == NULL)
4534 goto gunzip_nomem1;
4535
4536 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4537 if (bp->strm == NULL)
4538 goto gunzip_nomem2;
4539
4540 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4541 GFP_KERNEL);
4542 if (bp->strm->workspace == NULL)
4543 goto gunzip_nomem3;
4544
4545 return 0;
4546
4547 gunzip_nomem3:
4548 kfree(bp->strm);
4549 bp->strm = NULL;
4550
4551 gunzip_nomem2:
4552 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4553 bp->gunzip_mapping);
4554 bp->gunzip_buf = NULL;
4555
4556 gunzip_nomem1:
4557 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4558 " un-compression\n");
4559 return -ENOMEM;
4560 }
4561
4562 static void bnx2x_gunzip_end(struct bnx2x *bp)
4563 {
4564 if (bp->strm) {
4565 kfree(bp->strm->workspace);
4566 kfree(bp->strm);
4567 bp->strm = NULL;
4568 }
4569
4570 if (bp->gunzip_buf) {
4571 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4572 bp->gunzip_mapping);
4573 bp->gunzip_buf = NULL;
4574 }
4575 }
4576
4577 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
4578 {
4579 int n, rc;
4580
4581 /* check gzip header */
4582 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4583 BNX2X_ERR("Bad gzip header\n");
4584 return -EINVAL;
4585 }
4586
4587 n = 10;
4588
4589 #define FNAME 0x8
4590
4591 if (zbuf[3] & FNAME)
4592 while ((zbuf[n++] != 0) && (n < len));
4593
4594 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
4595 bp->strm->avail_in = len - n;
4596 bp->strm->next_out = bp->gunzip_buf;
4597 bp->strm->avail_out = FW_BUF_SIZE;
4598
4599 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4600 if (rc != Z_OK)
4601 return rc;
4602
4603 rc = zlib_inflate(bp->strm, Z_FINISH);
4604 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4605 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4606 bp->strm->msg);
4607
4608 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4609 if (bp->gunzip_outlen & 0x3)
4610 netdev_err(bp->dev, "Firmware decompression error:"
4611 " gunzip_outlen (%d) not aligned\n",
4612 bp->gunzip_outlen);
4613 bp->gunzip_outlen >>= 2;
4614
4615 zlib_inflateEnd(bp->strm);
4616
4617 if (rc == Z_STREAM_END)
4618 return 0;
4619
4620 return rc;
4621 }
4622
4623 /* nic load/unload */
4624
4625 /*
4626 * General service functions
4627 */
4628
4629 /* send a NIG loopback debug packet */
4630 static void bnx2x_lb_pckt(struct bnx2x *bp)
4631 {
4632 u32 wb_write[3];
4633
4634 /* Ethernet source and destination addresses */
4635 wb_write[0] = 0x55555555;
4636 wb_write[1] = 0x55555555;
4637 wb_write[2] = 0x20; /* SOP */
4638 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4639
4640 /* NON-IP protocol */
4641 wb_write[0] = 0x09000000;
4642 wb_write[1] = 0x55555555;
4643 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4644 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4645 }
4646
4647 /* some of the internal memories
4648 * are not directly readable from the driver
4649 * to test them we send debug packets
4650 */
4651 static int bnx2x_int_mem_test(struct bnx2x *bp)
4652 {
4653 int factor;
4654 int count, i;
4655 u32 val = 0;
4656
4657 if (CHIP_REV_IS_FPGA(bp))
4658 factor = 120;
4659 else if (CHIP_REV_IS_EMUL(bp))
4660 factor = 200;
4661 else
4662 factor = 1;
4663
4664 /* Disable inputs of parser neighbor blocks */
4665 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4666 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4667 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4668 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4669
4670 /* Write 0 to parser credits for CFC search request */
4671 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4672
4673 /* send Ethernet packet */
4674 bnx2x_lb_pckt(bp);
4675
4676 /* TODO do i reset NIG statistic? */
4677 /* Wait until NIG register shows 1 packet of size 0x10 */
4678 count = 1000 * factor;
4679 while (count) {
4680
4681 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4682 val = *bnx2x_sp(bp, wb_data[0]);
4683 if (val == 0x10)
4684 break;
4685
4686 msleep(10);
4687 count--;
4688 }
4689 if (val != 0x10) {
4690 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4691 return -1;
4692 }
4693
4694 /* Wait until PRS register shows 1 packet */
4695 count = 1000 * factor;
4696 while (count) {
4697 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4698 if (val == 1)
4699 break;
4700
4701 msleep(10);
4702 count--;
4703 }
4704 if (val != 0x1) {
4705 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4706 return -2;
4707 }
4708
4709 /* Reset and init BRB, PRS */
4710 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4711 msleep(50);
4712 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4713 msleep(50);
4714 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4715 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4716
4717 DP(NETIF_MSG_HW, "part2\n");
4718
4719 /* Disable inputs of parser neighbor blocks */
4720 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4721 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4722 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4723 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4724
4725 /* Write 0 to parser credits for CFC search request */
4726 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4727
4728 /* send 10 Ethernet packets */
4729 for (i = 0; i < 10; i++)
4730 bnx2x_lb_pckt(bp);
4731
4732 /* Wait until NIG register shows 10 + 1
4733 packets of size 11*0x10 = 0xb0 */
4734 count = 1000 * factor;
4735 while (count) {
4736
4737 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4738 val = *bnx2x_sp(bp, wb_data[0]);
4739 if (val == 0xb0)
4740 break;
4741
4742 msleep(10);
4743 count--;
4744 }
4745 if (val != 0xb0) {
4746 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4747 return -3;
4748 }
4749
4750 /* Wait until PRS register shows 2 packets */
4751 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4752 if (val != 2)
4753 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4754
4755 /* Write 1 to parser credits for CFC search request */
4756 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4757
4758 /* Wait until PRS register shows 3 packets */
4759 msleep(10 * factor);
4760 /* Wait until NIG register shows 1 packet of size 0x10 */
4761 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4762 if (val != 3)
4763 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4764
4765 /* clear NIG EOP FIFO */
4766 for (i = 0; i < 11; i++)
4767 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4768 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4769 if (val != 1) {
4770 BNX2X_ERR("clear of NIG failed\n");
4771 return -4;
4772 }
4773
4774 /* Reset and init BRB, PRS, NIG */
4775 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4776 msleep(50);
4777 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4778 msleep(50);
4779 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4780 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4781 #ifndef BCM_CNIC
4782 /* set NIC mode */
4783 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4784 #endif
4785
4786 /* Enable inputs of parser neighbor blocks */
4787 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4788 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4789 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
4790 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
4791
4792 DP(NETIF_MSG_HW, "done\n");
4793
4794 return 0; /* OK */
4795 }
4796
4797 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
4798 {
4799 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4800 if (CHIP_IS_E2(bp))
4801 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4802 else
4803 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
4804 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4805 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
4806 /*
4807 * mask read length error interrupts in brb for parser
4808 * (parsing unit and 'checksum and crc' unit)
4809 * these errors are legal (PU reads fixed length and CAC can cause
4810 * read length error on truncated packets)
4811 */
4812 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
4813 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4814 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4815 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4816 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4817 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
4818 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4819 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
4820 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4821 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4822 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
4823 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4824 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
4825 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4826 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4827 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4828 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
4829 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4830 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
4831
4832 if (CHIP_REV_IS_FPGA(bp))
4833 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
4834 else if (CHIP_IS_E2(bp))
4835 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4836 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4837 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4838 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4839 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4840 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
4841 else
4842 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
4843 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4844 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4845 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
4846 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4847 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
4848 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4849 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
4850 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4851 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
4852 }
4853
4854 static void bnx2x_reset_common(struct bnx2x *bp)
4855 {
4856 /* reset_common */
4857 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4858 0xd3ffff7f);
4859 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4860 }
4861
4862 static void bnx2x_init_pxp(struct bnx2x *bp)
4863 {
4864 u16 devctl;
4865 int r_order, w_order;
4866
4867 pci_read_config_word(bp->pdev,
4868 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4869 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4870 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4871 if (bp->mrrs == -1)
4872 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4873 else {
4874 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4875 r_order = bp->mrrs;
4876 }
4877
4878 bnx2x_init_pxp_arb(bp, r_order, w_order);
4879 }
4880
4881 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4882 {
4883 int is_required;
4884 u32 val;
4885 int port;
4886
4887 if (BP_NOMCP(bp))
4888 return;
4889
4890 is_required = 0;
4891 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4892 SHARED_HW_CFG_FAN_FAILURE_MASK;
4893
4894 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4895 is_required = 1;
4896
4897 /*
4898 * The fan failure mechanism is usually related to the PHY type since
4899 * the power consumption of the board is affected by the PHY. Currently,
4900 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4901 */
4902 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4903 for (port = PORT_0; port < PORT_MAX; port++) {
4904 is_required |=
4905 bnx2x_fan_failure_det_req(
4906 bp,
4907 bp->common.shmem_base,
4908 bp->common.shmem2_base,
4909 port);
4910 }
4911
4912 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4913
4914 if (is_required == 0)
4915 return;
4916
4917 /* Fan failure is indicated by SPIO 5 */
4918 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4919 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4920
4921 /* set to active low mode */
4922 val = REG_RD(bp, MISC_REG_SPIO_INT);
4923 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
4924 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
4925 REG_WR(bp, MISC_REG_SPIO_INT, val);
4926
4927 /* enable interrupt to signal the IGU */
4928 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4929 val |= (1 << MISC_REGISTERS_SPIO_5);
4930 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4931 }
4932
4933 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4934 {
4935 u32 offset = 0;
4936
4937 if (CHIP_IS_E1(bp))
4938 return;
4939 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4940 return;
4941
4942 switch (BP_ABS_FUNC(bp)) {
4943 case 0:
4944 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4945 break;
4946 case 1:
4947 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4948 break;
4949 case 2:
4950 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4951 break;
4952 case 3:
4953 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4954 break;
4955 case 4:
4956 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4957 break;
4958 case 5:
4959 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4960 break;
4961 case 6:
4962 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4963 break;
4964 case 7:
4965 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4966 break;
4967 default:
4968 return;
4969 }
4970
4971 REG_WR(bp, offset, pretend_func_num);
4972 REG_RD(bp, offset);
4973 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4974 }
4975
4976 static void bnx2x_pf_disable(struct bnx2x *bp)
4977 {
4978 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4979 val &= ~IGU_PF_CONF_FUNC_EN;
4980
4981 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4982 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4983 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4984 }
4985
4986 static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
4987 {
4988 u32 val, i;
4989
4990 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
4991
4992 bnx2x_reset_common(bp);
4993 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4994 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
4995
4996 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
4997 if (!CHIP_IS_E1(bp))
4998 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
4999
5000 if (CHIP_IS_E2(bp)) {
5001 u8 fid;
5002
5003 /**
5004 * 4-port mode or 2-port mode we need to turn of master-enable
5005 * for everyone, after that, turn it back on for self.
5006 * so, we disregard multi-function or not, and always disable
5007 * for all functions on the given path, this means 0,2,4,6 for
5008 * path 0 and 1,3,5,7 for path 1
5009 */
5010 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
5011 if (fid == BP_ABS_FUNC(bp)) {
5012 REG_WR(bp,
5013 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5014 1);
5015 continue;
5016 }
5017
5018 bnx2x_pretend_func(bp, fid);
5019 /* clear pf enable */
5020 bnx2x_pf_disable(bp);
5021 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5022 }
5023 }
5024
5025 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
5026 if (CHIP_IS_E1(bp)) {
5027 /* enable HW interrupt from PXP on USDM overflow
5028 bit 16 on INT_MASK_0 */
5029 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5030 }
5031
5032 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
5033 bnx2x_init_pxp(bp);
5034
5035 #ifdef __BIG_ENDIAN
5036 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5037 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5038 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5039 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5040 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5041 /* make sure this value is 0 */
5042 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5043
5044 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5045 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5046 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5047 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5048 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5049 #endif
5050
5051 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5052
5053 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5054 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5055
5056 /* let the HW do it's magic ... */
5057 msleep(100);
5058 /* finish PXP init */
5059 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5060 if (val != 1) {
5061 BNX2X_ERR("PXP2 CFG failed\n");
5062 return -EBUSY;
5063 }
5064 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5065 if (val != 1) {
5066 BNX2X_ERR("PXP2 RD_INIT failed\n");
5067 return -EBUSY;
5068 }
5069
5070 /* Timers bug workaround E2 only. We need to set the entire ILT to
5071 * have entries with value "0" and valid bit on.
5072 * This needs to be done by the first PF that is loaded in a path
5073 * (i.e. common phase)
5074 */
5075 if (CHIP_IS_E2(bp)) {
5076 struct ilt_client_info ilt_cli;
5077 struct bnx2x_ilt ilt;
5078 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5079 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5080
5081 /* initialize dummy TM client */
5082 ilt_cli.start = 0;
5083 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5084 ilt_cli.client_num = ILT_CLIENT_TM;
5085
5086 /* Step 1: set zeroes to all ilt page entries with valid bit on
5087 * Step 2: set the timers first/last ilt entry to point
5088 * to the entire range to prevent ILT range error for 3rd/4th
5089 * vnic (this code assumes existence of the vnic)
5090 *
5091 * both steps performed by call to bnx2x_ilt_client_init_op()
5092 * with dummy TM client
5093 *
5094 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5095 * and his brother are split registers
5096 */
5097 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5098 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5099 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5100
5101 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5102 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5103 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5104 }
5105
5106
5107 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5108 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5109
5110 if (CHIP_IS_E2(bp)) {
5111 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5112 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5113 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5114
5115 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5116
5117 /* let the HW do it's magic ... */
5118 do {
5119 msleep(200);
5120 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5121 } while (factor-- && (val != 1));
5122
5123 if (val != 1) {
5124 BNX2X_ERR("ATC_INIT failed\n");
5125 return -EBUSY;
5126 }
5127 }
5128
5129 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5130
5131 /* clean the DMAE memory */
5132 bp->dmae_ready = 1;
5133 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5134
5135 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5136 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5137 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5138 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
5139
5140 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5141 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5142 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5143 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5144
5145 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
5146
5147 if (CHIP_MODE_IS_4_PORT(bp))
5148 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
5149
5150 /* QM queues pointers table */
5151 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5152
5153 /* soft reset pulse */
5154 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5155 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5156
5157 #ifdef BCM_CNIC
5158 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5159 #endif
5160
5161 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
5162 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5163
5164 if (!CHIP_REV_IS_SLOW(bp)) {
5165 /* enable hw interrupt from doorbell Q */
5166 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5167 }
5168
5169 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5170 if (CHIP_MODE_IS_4_PORT(bp)) {
5171 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5172 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5173 }
5174
5175 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5176 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5177 #ifndef BCM_CNIC
5178 /* set NIC mode */
5179 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5180 #endif
5181 if (!CHIP_IS_E1(bp))
5182 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
5183
5184 if (CHIP_IS_E2(bp)) {
5185 /* Bit-map indicating which L2 hdrs may appear after the
5186 basic Ethernet header */
5187 int has_ovlan = IS_MF_SD(bp);
5188 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5189 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5190 }
5191
5192 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5193 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5194 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5195 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5196
5197 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5198 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5199 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5200 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5201
5202 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5203 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5204 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5205 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
5206
5207 if (CHIP_MODE_IS_4_PORT(bp))
5208 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5209
5210 /* sync semi rtc */
5211 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5212 0x80000000);
5213 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5214 0x80000000);
5215
5216 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5217 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5218 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
5219
5220 if (CHIP_IS_E2(bp)) {
5221 int has_ovlan = IS_MF_SD(bp);
5222 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5223 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5224 }
5225
5226 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5227 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5228 REG_WR(bp, i, random32());
5229
5230 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5231 #ifdef BCM_CNIC
5232 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5233 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5234 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5235 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5236 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5237 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5238 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5239 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5240 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5241 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5242 #endif
5243 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5244
5245 if (sizeof(union cdu_context) != 1024)
5246 /* we currently assume that a context is 1024 bytes */
5247 dev_alert(&bp->pdev->dev, "please adjust the size "
5248 "of cdu_context(%ld)\n",
5249 (long)sizeof(union cdu_context));
5250
5251 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5252 val = (4 << 24) + (0 << 12) + 1024;
5253 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5254
5255 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5256 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5257 /* enable context validation interrupt from CFC */
5258 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5259
5260 /* set the thresholds to prevent CFC/CDU race */
5261 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5262
5263 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5264
5265 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5266 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5267
5268 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
5269 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
5270
5271 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
5272 /* Reset PCIE errors for debug */
5273 REG_WR(bp, 0x2814, 0xffffffff);
5274 REG_WR(bp, 0x3820, 0xffffffff);
5275
5276 if (CHIP_IS_E2(bp)) {
5277 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5278 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5279 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5280 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5281 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5282 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5283 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5284 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5285 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5286 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5287 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5288 }
5289
5290 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
5291 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
5292 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
5293 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
5294
5295 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
5296 if (!CHIP_IS_E1(bp)) {
5297 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5298 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5299 }
5300 if (CHIP_IS_E2(bp)) {
5301 /* Bit-map indicating which L2 hdrs may appear after the
5302 basic Ethernet header */
5303 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
5304 }
5305
5306 if (CHIP_REV_IS_SLOW(bp))
5307 msleep(200);
5308
5309 /* finish CFC init */
5310 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5311 if (val != 1) {
5312 BNX2X_ERR("CFC LL_INIT failed\n");
5313 return -EBUSY;
5314 }
5315 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5316 if (val != 1) {
5317 BNX2X_ERR("CFC AC_INIT failed\n");
5318 return -EBUSY;
5319 }
5320 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5321 if (val != 1) {
5322 BNX2X_ERR("CFC CAM_INIT failed\n");
5323 return -EBUSY;
5324 }
5325 REG_WR(bp, CFC_REG_DEBUG0, 0);
5326
5327 if (CHIP_IS_E1(bp)) {
5328 /* read NIG statistic
5329 to see if this is our first up since powerup */
5330 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5331 val = *bnx2x_sp(bp, wb_data[0]);
5332
5333 /* do internal memory self test */
5334 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5335 BNX2X_ERR("internal mem self test failed\n");
5336 return -EBUSY;
5337 }
5338 }
5339
5340 bnx2x_setup_fan_failure_detection(bp);
5341
5342 /* clear PXP2 attentions */
5343 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5344
5345 bnx2x_enable_blocks_attention(bp);
5346 if (CHIP_PARITY_ENABLED(bp))
5347 bnx2x_enable_blocks_parity(bp);
5348
5349 if (!BP_NOMCP(bp)) {
5350 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5351 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5352 CHIP_IS_E1x(bp)) {
5353 u32 shmem_base[2], shmem2_base[2];
5354 shmem_base[0] = bp->common.shmem_base;
5355 shmem2_base[0] = bp->common.shmem2_base;
5356 if (CHIP_IS_E2(bp)) {
5357 shmem_base[1] =
5358 SHMEM2_RD(bp, other_shmem_base_addr);
5359 shmem2_base[1] =
5360 SHMEM2_RD(bp, other_shmem2_base_addr);
5361 }
5362 bnx2x_acquire_phy_lock(bp);
5363 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5364 bp->common.chip_id);
5365 bnx2x_release_phy_lock(bp);
5366 }
5367 } else
5368 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5369
5370 return 0;
5371 }
5372
5373 static int bnx2x_init_hw_port(struct bnx2x *bp)
5374 {
5375 int port = BP_PORT(bp);
5376 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
5377 u32 low, high;
5378 u32 val;
5379
5380 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
5381
5382 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5383
5384 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
5385 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
5386
5387 /* Timers bug workaround: disables the pf_master bit in pglue at
5388 * common phase, we need to enable it here before any dmae access are
5389 * attempted. Therefore we manually added the enable-master to the
5390 * port phase (it also happens in the function phase)
5391 */
5392 if (CHIP_IS_E2(bp))
5393 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5394
5395 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5396 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5397 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
5398 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
5399
5400 /* QM cid (connection) count */
5401 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
5402
5403 #ifdef BCM_CNIC
5404 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
5405 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5406 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
5407 #endif
5408
5409 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
5410
5411 if (CHIP_MODE_IS_4_PORT(bp))
5412 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5413
5414 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5415 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5416 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5417 /* no pause for emulation and FPGA */
5418 low = 0;
5419 high = 513;
5420 } else {
5421 if (IS_MF(bp))
5422 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5423 else if (bp->dev->mtu > 4096) {
5424 if (bp->flags & ONE_PORT_FLAG)
5425 low = 160;
5426 else {
5427 val = bp->dev->mtu;
5428 /* (24*1024 + val*4)/256 */
5429 low = 96 + (val/64) +
5430 ((val % 64) ? 1 : 0);
5431 }
5432 } else
5433 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5434 high = low + 56; /* 14*1024/256 */
5435 }
5436 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5437 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5438 }
5439
5440 if (CHIP_MODE_IS_4_PORT(bp)) {
5441 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5442 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5443 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5444 BRB1_REG_MAC_GUARANTIED_0), 40);
5445 }
5446
5447 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
5448
5449 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
5450 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
5451 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
5452 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
5453
5454 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5455 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5456 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5457 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5458 if (CHIP_MODE_IS_4_PORT(bp))
5459 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
5460
5461 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
5462 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
5463
5464 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
5465
5466 if (!CHIP_IS_E2(bp)) {
5467 /* configure PBF to work without PAUSE mtu 9000 */
5468 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5469
5470 /* update threshold */
5471 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5472 /* update init credit */
5473 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5474
5475 /* probe changes */
5476 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5477 udelay(50);
5478 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5479 }
5480
5481 #ifdef BCM_CNIC
5482 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
5483 #endif
5484 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
5485 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
5486
5487 if (CHIP_IS_E1(bp)) {
5488 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5489 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5490 }
5491 bnx2x_init_block(bp, HC_BLOCK, init_stage);
5492
5493 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5494
5495 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
5496 /* init aeu_mask_attn_func_0/1:
5497 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5498 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5499 * bits 4-7 are used for "per vn group attention" */
5500 val = IS_MF(bp) ? 0xF7 : 0x7;
5501 /* Enable DCBX attention for all but E1 */
5502 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5503 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
5504
5505 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5506 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
5507 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
5508 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
5509 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
5510
5511 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
5512
5513 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5514
5515 if (!CHIP_IS_E1(bp)) {
5516 /* 0x2 disable mf_ov, 0x1 enable */
5517 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5518 (IS_MF_SD(bp) ? 0x1 : 0x2));
5519
5520 if (CHIP_IS_E2(bp)) {
5521 val = 0;
5522 switch (bp->mf_mode) {
5523 case MULTI_FUNCTION_SD:
5524 val = 1;
5525 break;
5526 case MULTI_FUNCTION_SI:
5527 val = 2;
5528 break;
5529 }
5530
5531 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5532 NIG_REG_LLH0_CLS_TYPE), val);
5533 }
5534 {
5535 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5536 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5537 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5538 }
5539 }
5540
5541 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
5542 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
5543 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
5544 bp->common.shmem2_base, port)) {
5545 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5546 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5547 val = REG_RD(bp, reg_addr);
5548 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5549 REG_WR(bp, reg_addr, val);
5550 }
5551 bnx2x__link_reset(bp);
5552
5553 return 0;
5554 }
5555
5556 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5557 {
5558 int reg;
5559
5560 if (CHIP_IS_E1(bp))
5561 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5562 else
5563 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5564
5565 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5566 }
5567
5568 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5569 {
5570 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5571 }
5572
5573 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5574 {
5575 u32 i, base = FUNC_ILT_BASE(func);
5576 for (i = base; i < base + ILT_PER_FUNC; i++)
5577 bnx2x_ilt_wr(bp, i, 0);
5578 }
5579
5580 static int bnx2x_init_hw_func(struct bnx2x *bp)
5581 {
5582 int port = BP_PORT(bp);
5583 int func = BP_FUNC(bp);
5584 struct bnx2x_ilt *ilt = BP_ILT(bp);
5585 u16 cdu_ilt_start;
5586 u32 addr, val;
5587 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5588 int i, main_mem_width;
5589
5590 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
5591
5592 /* set MSI reconfigure capability */
5593 if (bp->common.int_block == INT_BLOCK_HC) {
5594 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5595 val = REG_RD(bp, addr);
5596 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5597 REG_WR(bp, addr, val);
5598 }
5599
5600 ilt = BP_ILT(bp);
5601 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
5602
5603 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5604 ilt->lines[cdu_ilt_start + i].page =
5605 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5606 ilt->lines[cdu_ilt_start + i].page_mapping =
5607 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5608 /* cdu ilt pages are allocated manually so there's no need to
5609 set the size */
5610 }
5611 bnx2x_ilt_init_op(bp, INITOP_SET);
5612
5613 #ifdef BCM_CNIC
5614 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
5615
5616 /* T1 hash bits value determines the T1 number of entries */
5617 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5618 #endif
5619
5620 #ifndef BCM_CNIC
5621 /* set NIC mode */
5622 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5623 #endif /* BCM_CNIC */
5624
5625 if (CHIP_IS_E2(bp)) {
5626 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5627
5628 /* Turn on a single ISR mode in IGU if driver is going to use
5629 * INT#x or MSI
5630 */
5631 if (!(bp->flags & USING_MSIX_FLAG))
5632 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5633 /*
5634 * Timers workaround bug: function init part.
5635 * Need to wait 20msec after initializing ILT,
5636 * needed to make sure there are no requests in
5637 * one of the PXP internal queues with "old" ILT addresses
5638 */
5639 msleep(20);
5640 /*
5641 * Master enable - Due to WB DMAE writes performed before this
5642 * register is re-initialized as part of the regular function
5643 * init
5644 */
5645 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5646 /* Enable the function in IGU */
5647 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5648 }
5649
5650 bp->dmae_ready = 1;
5651
5652 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5653
5654 if (CHIP_IS_E2(bp))
5655 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5656
5657 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5658 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5659 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5660 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5661 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5662 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5663 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5664 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5665 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5666
5667 if (CHIP_IS_E2(bp)) {
5668 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5669 BP_PATH(bp));
5670 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5671 BP_PATH(bp));
5672 }
5673
5674 if (CHIP_MODE_IS_4_PORT(bp))
5675 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5676
5677 if (CHIP_IS_E2(bp))
5678 REG_WR(bp, QM_REG_PF_EN, 1);
5679
5680 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
5681
5682 if (CHIP_MODE_IS_4_PORT(bp))
5683 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5684
5685 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5686 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5687 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5688 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5689 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5690 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5691 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5692 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5693 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5694 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5695 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
5696 if (CHIP_IS_E2(bp))
5697 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5698
5699 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5700
5701 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
5702
5703 if (CHIP_IS_E2(bp))
5704 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5705
5706 if (IS_MF(bp)) {
5707 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5708 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
5709 }
5710
5711 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5712
5713 /* HC init per function */
5714 if (bp->common.int_block == INT_BLOCK_HC) {
5715 if (CHIP_IS_E1H(bp)) {
5716 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5717
5718 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5719 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5720 }
5721 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5722
5723 } else {
5724 int num_segs, sb_idx, prod_offset;
5725
5726 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5727
5728 if (CHIP_IS_E2(bp)) {
5729 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5730 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5731 }
5732
5733 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5734
5735 if (CHIP_IS_E2(bp)) {
5736 int dsb_idx = 0;
5737 /**
5738 * Producer memory:
5739 * E2 mode: address 0-135 match to the mapping memory;
5740 * 136 - PF0 default prod; 137 - PF1 default prod;
5741 * 138 - PF2 default prod; 139 - PF3 default prod;
5742 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5743 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5744 * 144-147 reserved.
5745 *
5746 * E1.5 mode - In backward compatible mode;
5747 * for non default SB; each even line in the memory
5748 * holds the U producer and each odd line hold
5749 * the C producer. The first 128 producers are for
5750 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5751 * producers are for the DSB for each PF.
5752 * Each PF has five segments: (the order inside each
5753 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5754 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5755 * 144-147 attn prods;
5756 */
5757 /* non-default-status-blocks */
5758 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5759 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5760 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5761 prod_offset = (bp->igu_base_sb + sb_idx) *
5762 num_segs;
5763
5764 for (i = 0; i < num_segs; i++) {
5765 addr = IGU_REG_PROD_CONS_MEMORY +
5766 (prod_offset + i) * 4;
5767 REG_WR(bp, addr, 0);
5768 }
5769 /* send consumer update with value 0 */
5770 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5771 USTORM_ID, 0, IGU_INT_NOP, 1);
5772 bnx2x_igu_clear_sb(bp,
5773 bp->igu_base_sb + sb_idx);
5774 }
5775
5776 /* default-status-blocks */
5777 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5778 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5779
5780 if (CHIP_MODE_IS_4_PORT(bp))
5781 dsb_idx = BP_FUNC(bp);
5782 else
5783 dsb_idx = BP_E1HVN(bp);
5784
5785 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5786 IGU_BC_BASE_DSB_PROD + dsb_idx :
5787 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5788
5789 for (i = 0; i < (num_segs * E1HVN_MAX);
5790 i += E1HVN_MAX) {
5791 addr = IGU_REG_PROD_CONS_MEMORY +
5792 (prod_offset + i)*4;
5793 REG_WR(bp, addr, 0);
5794 }
5795 /* send consumer update with 0 */
5796 if (CHIP_INT_MODE_IS_BC(bp)) {
5797 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5798 USTORM_ID, 0, IGU_INT_NOP, 1);
5799 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5800 CSTORM_ID, 0, IGU_INT_NOP, 1);
5801 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5802 XSTORM_ID, 0, IGU_INT_NOP, 1);
5803 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5804 TSTORM_ID, 0, IGU_INT_NOP, 1);
5805 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5806 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5807 } else {
5808 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5809 USTORM_ID, 0, IGU_INT_NOP, 1);
5810 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5811 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5812 }
5813 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5814
5815 /* !!! these should become driver const once
5816 rf-tool supports split-68 const */
5817 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5818 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5819 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5820 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5821 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5822 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5823 }
5824 }
5825
5826 /* Reset PCIE errors for debug */
5827 REG_WR(bp, 0x2114, 0xffffffff);
5828 REG_WR(bp, 0x2120, 0xffffffff);
5829
5830 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5831 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5832 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5833 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5834 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5835 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5836
5837 if (CHIP_IS_E1x(bp)) {
5838 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5839 main_mem_base = HC_REG_MAIN_MEMORY +
5840 BP_PORT(bp) * (main_mem_size * 4);
5841 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5842 main_mem_width = 8;
5843
5844 val = REG_RD(bp, main_mem_prty_clr);
5845 if (val)
5846 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5847 "block during "
5848 "function init (0x%x)!\n", val);
5849
5850 /* Clear "false" parity errors in MSI-X table */
5851 for (i = main_mem_base;
5852 i < main_mem_base + main_mem_size * 4;
5853 i += main_mem_width) {
5854 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5855 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5856 i, main_mem_width / 4);
5857 }
5858 /* Clear HC parity attention */
5859 REG_RD(bp, main_mem_prty_clr);
5860 }
5861
5862 bnx2x_phy_probe(&bp->link_params);
5863
5864 return 0;
5865 }
5866
5867 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5868 {
5869 int rc = 0;
5870
5871 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5872 BP_ABS_FUNC(bp), load_code);
5873
5874 bp->dmae_ready = 0;
5875 spin_lock_init(&bp->dmae_lock);
5876
5877 switch (load_code) {
5878 case FW_MSG_CODE_DRV_LOAD_COMMON:
5879 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5880 rc = bnx2x_init_hw_common(bp, load_code);
5881 if (rc)
5882 goto init_hw_err;
5883 /* no break */
5884
5885 case FW_MSG_CODE_DRV_LOAD_PORT:
5886 rc = bnx2x_init_hw_port(bp);
5887 if (rc)
5888 goto init_hw_err;
5889 /* no break */
5890
5891 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5892 rc = bnx2x_init_hw_func(bp);
5893 if (rc)
5894 goto init_hw_err;
5895 break;
5896
5897 default:
5898 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5899 break;
5900 }
5901
5902 if (!BP_NOMCP(bp)) {
5903 int mb_idx = BP_FW_MB_IDX(bp);
5904
5905 bp->fw_drv_pulse_wr_seq =
5906 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
5907 DRV_PULSE_SEQ_MASK);
5908 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5909 }
5910
5911 init_hw_err:
5912 bnx2x_gunzip_end(bp);
5913
5914 return rc;
5915 }
5916
5917 void bnx2x_free_mem(struct bnx2x *bp)
5918 {
5919 bnx2x_gunzip_end(bp);
5920
5921 /* fastpath */
5922 bnx2x_free_fp_mem(bp);
5923 /* end of fastpath */
5924
5925 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
5926 sizeof(struct host_sp_status_block));
5927
5928 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
5929 sizeof(struct bnx2x_slowpath));
5930
5931 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5932 bp->context.size);
5933
5934 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5935
5936 BNX2X_FREE(bp->ilt->lines);
5937
5938 #ifdef BCM_CNIC
5939 if (CHIP_IS_E2(bp))
5940 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5941 sizeof(struct host_hc_status_block_e2));
5942 else
5943 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5944 sizeof(struct host_hc_status_block_e1x));
5945
5946 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
5947 #endif
5948
5949 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
5950
5951 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5952 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5953
5954 BNX2X_FREE(bp->rx_indir_table);
5955 }
5956
5957
5958 int bnx2x_alloc_mem(struct bnx2x *bp)
5959 {
5960 if (bnx2x_gunzip_init(bp))
5961 return -ENOMEM;
5962
5963 #ifdef BCM_CNIC
5964 if (CHIP_IS_E2(bp))
5965 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
5966 sizeof(struct host_hc_status_block_e2));
5967 else
5968 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
5969 sizeof(struct host_hc_status_block_e1x));
5970
5971 /* allocate searcher T2 table */
5972 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
5973 #endif
5974
5975
5976 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5977 sizeof(struct host_sp_status_block));
5978
5979 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5980 sizeof(struct bnx2x_slowpath));
5981
5982 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
5983
5984 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
5985 bp->context.size);
5986
5987 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
5988
5989 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
5990 goto alloc_mem_err;
5991
5992 /* Slow path ring */
5993 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
5994
5995 /* EQ */
5996 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
5997 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5998
5999 BNX2X_ALLOC(bp->rx_indir_table, sizeof(bp->rx_indir_table[0]) *
6000 TSTORM_INDIRECTION_TABLE_SIZE);
6001
6002 /* fastpath */
6003 /* need to be done at the end, since it's self adjusting to amount
6004 * of memory available for RSS queues
6005 */
6006 if (bnx2x_alloc_fp_mem(bp))
6007 goto alloc_mem_err;
6008 return 0;
6009
6010 alloc_mem_err:
6011 bnx2x_free_mem(bp);
6012 return -ENOMEM;
6013 }
6014
6015 /*
6016 * Init service functions
6017 */
6018 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6019 int *state_p, int flags);
6020
6021 int bnx2x_func_start(struct bnx2x *bp)
6022 {
6023 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
6024
6025 /* Wait for completion */
6026 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6027 WAIT_RAMROD_COMMON);
6028 }
6029
6030 static int bnx2x_func_stop(struct bnx2x *bp)
6031 {
6032 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
6033
6034 /* Wait for completion */
6035 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6036 0, &(bp->state), WAIT_RAMROD_COMMON);
6037 }
6038
6039 /**
6040 * bnx2x_set_mac_addr_gen - set a MAC in a CAM for a few L2 Clients for E1x chips
6041 *
6042 * @bp: driver handle
6043 * @set: set or clear an entry (1 or 0)
6044 * @mac: pointer to a buffer containing a MAC
6045 * @cl_bit_vec: bit vector of clients to register a MAC for
6046 * @cam_offset: offset in a CAM to use
6047 * @is_bcast: is the set MAC a broadcast address (for E1 only)
6048 */
6049 static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
6050 u32 cl_bit_vec, u8 cam_offset,
6051 u8 is_bcast)
6052 {
6053 struct mac_configuration_cmd *config =
6054 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6055 int ramrod_flags = WAIT_RAMROD_COMMON;
6056
6057 bp->set_mac_pending = 1;
6058
6059 config->hdr.length = 1;
6060 config->hdr.offset = cam_offset;
6061 config->hdr.client_id = 0xff;
6062 /* Mark the single MAC configuration ramrod as opposed to a
6063 * UC/MC list configuration).
6064 */
6065 config->hdr.echo = 1;
6066
6067 /* primary MAC */
6068 config->config_table[0].msb_mac_addr =
6069 swab16(*(u16 *)&mac[0]);
6070 config->config_table[0].middle_mac_addr =
6071 swab16(*(u16 *)&mac[2]);
6072 config->config_table[0].lsb_mac_addr =
6073 swab16(*(u16 *)&mac[4]);
6074 config->config_table[0].clients_bit_vector =
6075 cpu_to_le32(cl_bit_vec);
6076 config->config_table[0].vlan_id = 0;
6077 config->config_table[0].pf_id = BP_FUNC(bp);
6078 if (set)
6079 SET_FLAG(config->config_table[0].flags,
6080 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6081 T_ETH_MAC_COMMAND_SET);
6082 else
6083 SET_FLAG(config->config_table[0].flags,
6084 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6085 T_ETH_MAC_COMMAND_INVALIDATE);
6086
6087 if (is_bcast)
6088 SET_FLAG(config->config_table[0].flags,
6089 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6090
6091 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
6092 (set ? "setting" : "clearing"),
6093 config->config_table[0].msb_mac_addr,
6094 config->config_table[0].middle_mac_addr,
6095 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
6096
6097 mb();
6098
6099 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6100 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6101 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6102
6103 /* Wait for a completion */
6104 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
6105 }
6106
6107 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6108 int *state_p, int flags)
6109 {
6110 /* can take a while if any port is running */
6111 int cnt = 5000;
6112 u8 poll = flags & WAIT_RAMROD_POLL;
6113 u8 common = flags & WAIT_RAMROD_COMMON;
6114
6115 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6116 poll ? "polling" : "waiting", state, idx);
6117
6118 might_sleep();
6119 while (cnt--) {
6120 if (poll) {
6121 if (common)
6122 bnx2x_eq_int(bp);
6123 else {
6124 bnx2x_rx_int(bp->fp, 10);
6125 /* if index is different from 0
6126 * the reply for some commands will
6127 * be on the non default queue
6128 */
6129 if (idx)
6130 bnx2x_rx_int(&bp->fp[idx], 10);
6131 }
6132 }
6133
6134 mb(); /* state is changed by bnx2x_sp_event() */
6135 if (*state_p == state) {
6136 #ifdef BNX2X_STOP_ON_ERROR
6137 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6138 #endif
6139 return 0;
6140 }
6141
6142 msleep(1);
6143
6144 if (bp->panic)
6145 return -EIO;
6146 }
6147
6148 /* timeout! */
6149 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6150 poll ? "polling" : "waiting", state, idx);
6151 #ifdef BNX2X_STOP_ON_ERROR
6152 bnx2x_panic();
6153 #endif
6154
6155 return -EBUSY;
6156 }
6157
6158 static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
6159 {
6160 if (CHIP_IS_E1H(bp))
6161 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6162 else if (CHIP_MODE_IS_4_PORT(bp))
6163 return E2_FUNC_MAX * rel_offset + BP_FUNC(bp);
6164 else
6165 return E2_FUNC_MAX * rel_offset + BP_VN(bp);
6166 }
6167
6168 /**
6169 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6170 * relevant. In addition, current implementation is tuned for a
6171 * single ETH MAC.
6172 */
6173 enum {
6174 LLH_CAM_ISCSI_ETH_LINE = 0,
6175 LLH_CAM_ETH_LINE,
6176 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6177 };
6178
6179 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6180 int set,
6181 unsigned char *dev_addr,
6182 int index)
6183 {
6184 u32 wb_data[2];
6185 u32 mem_offset, ena_offset, mem_index;
6186 /**
6187 * indexes mapping:
6188 * 0..7 - goes to MEM
6189 * 8..15 - goes to MEM2
6190 */
6191
6192 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6193 return;
6194
6195 /* calculate memory start offset according to the mapping
6196 * and index in the memory */
6197 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6198 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6199 NIG_REG_LLH0_FUNC_MEM;
6200 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6201 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6202 mem_index = index;
6203 } else {
6204 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6205 NIG_REG_P0_LLH_FUNC_MEM2;
6206 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6207 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6208 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6209 }
6210
6211 if (set) {
6212 /* LLH_FUNC_MEM is a u64 WB register */
6213 mem_offset += 8*mem_index;
6214
6215 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6216 (dev_addr[4] << 8) | dev_addr[5]);
6217 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6218
6219 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6220 }
6221
6222 /* enable/disable the entry */
6223 REG_WR(bp, ena_offset + 4*mem_index, set);
6224
6225 }
6226
6227 void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6228 {
6229 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6230 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
6231
6232 /* networking MAC */
6233 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6234 (1 << bp->fp->cl_id), cam_offset , 0);
6235
6236 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6237
6238 if (CHIP_IS_E1(bp)) {
6239 /* broadcast MAC */
6240 static const u8 bcast[ETH_ALEN] = {
6241 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6242 };
6243 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6244 }
6245 }
6246
6247 static inline u8 bnx2x_e1_cam_mc_offset(struct bnx2x *bp)
6248 {
6249 return CHIP_REV_IS_SLOW(bp) ?
6250 (BNX2X_MAX_EMUL_MULTI * (1 + BP_PORT(bp))) :
6251 (BNX2X_MAX_MULTICAST * (1 + BP_PORT(bp)));
6252 }
6253
6254 /* set mc list, do not wait as wait implies sleep and
6255 * set_rx_mode can be invoked from non-sleepable context.
6256 *
6257 * Instead we use the same ramrod data buffer each time we need
6258 * to configure a list of addresses, and use the fact that the
6259 * list of MACs is changed in an incremental way and that the
6260 * function is called under the netif_addr_lock. A temporary
6261 * inconsistent CAM configuration (possible in case of a very fast
6262 * sequence of add/del/add on the host side) will shortly be
6263 * restored by the handler of the last ramrod.
6264 */
6265 static int bnx2x_set_e1_mc_list(struct bnx2x *bp)
6266 {
6267 int i = 0, old;
6268 struct net_device *dev = bp->dev;
6269 u8 offset = bnx2x_e1_cam_mc_offset(bp);
6270 struct netdev_hw_addr *ha;
6271 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6272 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6273
6274 if (netdev_mc_count(dev) > BNX2X_MAX_MULTICAST)
6275 return -EINVAL;
6276
6277 netdev_for_each_mc_addr(ha, dev) {
6278 /* copy mac */
6279 config_cmd->config_table[i].msb_mac_addr =
6280 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6281 config_cmd->config_table[i].middle_mac_addr =
6282 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6283 config_cmd->config_table[i].lsb_mac_addr =
6284 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
6285
6286 config_cmd->config_table[i].vlan_id = 0;
6287 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6288 config_cmd->config_table[i].clients_bit_vector =
6289 cpu_to_le32(1 << BP_L_ID(bp));
6290
6291 SET_FLAG(config_cmd->config_table[i].flags,
6292 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6293 T_ETH_MAC_COMMAND_SET);
6294
6295 DP(NETIF_MSG_IFUP,
6296 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6297 config_cmd->config_table[i].msb_mac_addr,
6298 config_cmd->config_table[i].middle_mac_addr,
6299 config_cmd->config_table[i].lsb_mac_addr);
6300 i++;
6301 }
6302 old = config_cmd->hdr.length;
6303 if (old > i) {
6304 for (; i < old; i++) {
6305 if (CAM_IS_INVALID(config_cmd->
6306 config_table[i])) {
6307 /* already invalidated */
6308 break;
6309 }
6310 /* invalidate */
6311 SET_FLAG(config_cmd->config_table[i].flags,
6312 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6313 T_ETH_MAC_COMMAND_INVALIDATE);
6314 }
6315 }
6316
6317 wmb();
6318
6319 config_cmd->hdr.length = i;
6320 config_cmd->hdr.offset = offset;
6321 config_cmd->hdr.client_id = 0xff;
6322 /* Mark that this ramrod doesn't use bp->set_mac_pending for
6323 * synchronization.
6324 */
6325 config_cmd->hdr.echo = 0;
6326
6327 mb();
6328
6329 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6330 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6331 }
6332
6333 void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp)
6334 {
6335 int i;
6336 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6337 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6338 int ramrod_flags = WAIT_RAMROD_COMMON;
6339 u8 offset = bnx2x_e1_cam_mc_offset(bp);
6340
6341 for (i = 0; i < BNX2X_MAX_MULTICAST; i++)
6342 SET_FLAG(config_cmd->config_table[i].flags,
6343 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6344 T_ETH_MAC_COMMAND_INVALIDATE);
6345
6346 wmb();
6347
6348 config_cmd->hdr.length = BNX2X_MAX_MULTICAST;
6349 config_cmd->hdr.offset = offset;
6350 config_cmd->hdr.client_id = 0xff;
6351 /* We'll wait for a completion this time... */
6352 config_cmd->hdr.echo = 1;
6353
6354 bp->set_mac_pending = 1;
6355
6356 mb();
6357
6358 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6359 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6360
6361 /* Wait for a completion */
6362 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6363 ramrod_flags);
6364
6365 }
6366
6367 /* Accept one or more multicasts */
6368 static int bnx2x_set_e1h_mc_list(struct bnx2x *bp)
6369 {
6370 struct net_device *dev = bp->dev;
6371 struct netdev_hw_addr *ha;
6372 u32 mc_filter[MC_HASH_SIZE];
6373 u32 crc, bit, regidx;
6374 int i;
6375
6376 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
6377
6378 netdev_for_each_mc_addr(ha, dev) {
6379 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
6380 bnx2x_mc_addr(ha));
6381
6382 crc = crc32c_le(0, bnx2x_mc_addr(ha),
6383 ETH_ALEN);
6384 bit = (crc >> 24) & 0xff;
6385 regidx = bit >> 5;
6386 bit &= 0x1f;
6387 mc_filter[regidx] |= (1 << bit);
6388 }
6389
6390 for (i = 0; i < MC_HASH_SIZE; i++)
6391 REG_WR(bp, MC_HASH_OFFSET(bp, i),
6392 mc_filter[i]);
6393
6394 return 0;
6395 }
6396
6397 void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp)
6398 {
6399 int i;
6400
6401 for (i = 0; i < MC_HASH_SIZE; i++)
6402 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6403 }
6404
6405 #ifdef BCM_CNIC
6406 /**
6407 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
6408 *
6409 * @bp: driver handle
6410 * @set: set or clear the CAM entry
6411 *
6412 * This function will wait until the ramdord completion returns.
6413 * Return 0 if success, -ENODEV if ramrod doesn't return.
6414 */
6415 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
6416 {
6417 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6418 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
6419 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6420 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
6421 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
6422 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
6423
6424 /* Send a SET_MAC ramrod */
6425 bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,
6426 cam_offset, 0);
6427
6428 bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
6429
6430 return 0;
6431 }
6432
6433 /**
6434 * bnx2x_set_fip_eth_mac_addr - set FCoE L2 MAC(s)
6435 *
6436 * @bp: driver handle
6437 * @set: set or clear the CAM entry
6438 *
6439 * This function will wait until the ramrod completion returns.
6440 * Returns 0 if success, -ENODEV if ramrod doesn't return.
6441 */
6442 int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6443 {
6444 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6445 /**
6446 * CAM allocation for E1H
6447 * eth unicasts: by func number
6448 * iscsi: by func number
6449 * fip unicast: by func number
6450 * fip multicast: by func number
6451 */
6452 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6453 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6454
6455 return 0;
6456 }
6457
6458 int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6459 {
6460 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6461
6462 /**
6463 * CAM allocation for E1H
6464 * eth unicasts: by func number
6465 * iscsi: by func number
6466 * fip unicast: by func number
6467 * fip multicast: by func number
6468 */
6469 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6470 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6471
6472 return 0;
6473 }
6474 #endif
6475
6476 static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6477 struct bnx2x_client_init_params *params,
6478 u8 activate,
6479 struct client_init_ramrod_data *data)
6480 {
6481 /* Clear the buffer */
6482 memset(data, 0, sizeof(*data));
6483
6484 /* general */
6485 data->general.client_id = params->rxq_params.cl_id;
6486 data->general.statistics_counter_id = params->rxq_params.stat_id;
6487 data->general.statistics_en_flg =
6488 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
6489 data->general.is_fcoe_flg =
6490 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
6491 data->general.activate_flg = activate;
6492 data->general.sp_client_id = params->rxq_params.spcl_id;
6493
6494 /* Rx data */
6495 data->rx.tpa_en_flg =
6496 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6497 data->rx.vmqueue_mode_en_flg = 0;
6498 data->rx.cache_line_alignment_log_size =
6499 params->rxq_params.cache_line_log;
6500 data->rx.enable_dynamic_hc =
6501 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6502 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6503 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6504 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6505
6506 /* We don't set drop flags */
6507 data->rx.drop_ip_cs_err_flg = 0;
6508 data->rx.drop_tcp_cs_err_flg = 0;
6509 data->rx.drop_ttl0_flg = 0;
6510 data->rx.drop_udp_cs_err_flg = 0;
6511
6512 data->rx.inner_vlan_removal_enable_flg =
6513 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6514 data->rx.outer_vlan_removal_enable_flg =
6515 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6516 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6517 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6518 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6519 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6520 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6521 data->rx.bd_page_base.lo =
6522 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6523 data->rx.bd_page_base.hi =
6524 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6525 data->rx.sge_page_base.lo =
6526 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6527 data->rx.sge_page_base.hi =
6528 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6529 data->rx.cqe_page_base.lo =
6530 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6531 data->rx.cqe_page_base.hi =
6532 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6533 data->rx.is_leading_rss =
6534 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6535 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6536
6537 /* Tx data */
6538 data->tx.enforce_security_flg = 0; /* VF specific */
6539 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6540 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6541 data->tx.mtu = 0; /* VF specific */
6542 data->tx.tx_bd_page_base.lo =
6543 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6544 data->tx.tx_bd_page_base.hi =
6545 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6546
6547 /* flow control data */
6548 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6549 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6550 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6551 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6552 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6553 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6554 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6555
6556 data->fc.safc_group_num = params->txq_params.cos;
6557 data->fc.safc_group_en_flg =
6558 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
6559 data->fc.traffic_type =
6560 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6561 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
6562 }
6563
6564 static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6565 {
6566 /* ustorm cxt validation */
6567 cxt->ustorm_ag_context.cdu_usage =
6568 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6569 ETH_CONNECTION_TYPE);
6570 /* xcontext validation */
6571 cxt->xstorm_ag_context.cdu_reserved =
6572 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6573 ETH_CONNECTION_TYPE);
6574 }
6575
6576 static int bnx2x_setup_fw_client(struct bnx2x *bp,
6577 struct bnx2x_client_init_params *params,
6578 u8 activate,
6579 struct client_init_ramrod_data *data,
6580 dma_addr_t data_mapping)
6581 {
6582 u16 hc_usec;
6583 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6584 int ramrod_flags = 0, rc;
6585
6586 /* HC and context validation values */
6587 hc_usec = params->txq_params.hc_rate ?
6588 1000000 / params->txq_params.hc_rate : 0;
6589 bnx2x_update_coalesce_sb_index(bp,
6590 params->txq_params.fw_sb_id,
6591 params->txq_params.sb_cq_index,
6592 !(params->txq_params.flags & QUEUE_FLG_HC),
6593 hc_usec);
6594
6595 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6596
6597 hc_usec = params->rxq_params.hc_rate ?
6598 1000000 / params->rxq_params.hc_rate : 0;
6599 bnx2x_update_coalesce_sb_index(bp,
6600 params->rxq_params.fw_sb_id,
6601 params->rxq_params.sb_cq_index,
6602 !(params->rxq_params.flags & QUEUE_FLG_HC),
6603 hc_usec);
6604
6605 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6606 params->rxq_params.cid);
6607
6608 /* zero stats */
6609 if (params->txq_params.flags & QUEUE_FLG_STATS)
6610 storm_memset_xstats_zero(bp, BP_PORT(bp),
6611 params->txq_params.stat_id);
6612
6613 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6614 storm_memset_ustats_zero(bp, BP_PORT(bp),
6615 params->rxq_params.stat_id);
6616 storm_memset_tstats_zero(bp, BP_PORT(bp),
6617 params->rxq_params.stat_id);
6618 }
6619
6620 /* Fill the ramrod data */
6621 bnx2x_fill_cl_init_data(bp, params, activate, data);
6622
6623 /* SETUP ramrod.
6624 *
6625 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6626 * barrier except from mmiowb() is needed to impose a
6627 * proper ordering of memory operations.
6628 */
6629 mmiowb();
6630
6631
6632 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6633 U64_HI(data_mapping), U64_LO(data_mapping), 0);
6634
6635 /* Wait for completion */
6636 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6637 params->ramrod_params.index,
6638 params->ramrod_params.pstate,
6639 ramrod_flags);
6640 return rc;
6641 }
6642
6643 /**
6644 * bnx2x_set_int_mode - configure interrupt mode
6645 *
6646 * @bp: driver handle
6647 *
6648 * In case of MSI-X it will also try to enable MSI-X.
6649 */
6650 static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6651 {
6652 int rc = 0;
6653
6654 switch (bp->int_mode) {
6655 case INT_MODE_MSI:
6656 bnx2x_enable_msi(bp);
6657 /* falling through... */
6658 case INT_MODE_INTx:
6659 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6660 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6661 break;
6662 default:
6663 /* Set number of queues according to bp->multi_mode value */
6664 bnx2x_set_num_queues(bp);
6665
6666 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6667 bp->num_queues);
6668
6669 /* if we can't use MSI-X we only need one fp,
6670 * so try to enable MSI-X with the requested number of fp's
6671 * and fallback to MSI or legacy INTx with one fp
6672 */
6673 rc = bnx2x_enable_msix(bp);
6674 if (rc) {
6675 /* failed to enable MSI-X */
6676 if (bp->multi_mode)
6677 DP(NETIF_MSG_IFUP,
6678 "Multi requested but failed to "
6679 "enable MSI-X (%d), "
6680 "set number of queues to %d\n",
6681 bp->num_queues,
6682 1 + NONE_ETH_CONTEXT_USE);
6683 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6684
6685 if (!(bp->flags & DISABLE_MSI_FLAG))
6686 bnx2x_enable_msi(bp);
6687 }
6688
6689 break;
6690 }
6691
6692 return rc;
6693 }
6694
6695 /* must be called prioir to any HW initializations */
6696 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6697 {
6698 return L2_ILT_LINES(bp);
6699 }
6700
6701 void bnx2x_ilt_set_info(struct bnx2x *bp)
6702 {
6703 struct ilt_client_info *ilt_client;
6704 struct bnx2x_ilt *ilt = BP_ILT(bp);
6705 u16 line = 0;
6706
6707 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6708 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6709
6710 /* CDU */
6711 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6712 ilt_client->client_num = ILT_CLIENT_CDU;
6713 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6714 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6715 ilt_client->start = line;
6716 line += L2_ILT_LINES(bp);
6717 #ifdef BCM_CNIC
6718 line += CNIC_ILT_LINES;
6719 #endif
6720 ilt_client->end = line - 1;
6721
6722 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6723 "flags 0x%x, hw psz %d\n",
6724 ilt_client->start,
6725 ilt_client->end,
6726 ilt_client->page_size,
6727 ilt_client->flags,
6728 ilog2(ilt_client->page_size >> 12));
6729
6730 /* QM */
6731 if (QM_INIT(bp->qm_cid_count)) {
6732 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6733 ilt_client->client_num = ILT_CLIENT_QM;
6734 ilt_client->page_size = QM_ILT_PAGE_SZ;
6735 ilt_client->flags = 0;
6736 ilt_client->start = line;
6737
6738 /* 4 bytes for each cid */
6739 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6740 QM_ILT_PAGE_SZ);
6741
6742 ilt_client->end = line - 1;
6743
6744 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6745 "flags 0x%x, hw psz %d\n",
6746 ilt_client->start,
6747 ilt_client->end,
6748 ilt_client->page_size,
6749 ilt_client->flags,
6750 ilog2(ilt_client->page_size >> 12));
6751
6752 }
6753 /* SRC */
6754 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6755 #ifdef BCM_CNIC
6756 ilt_client->client_num = ILT_CLIENT_SRC;
6757 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6758 ilt_client->flags = 0;
6759 ilt_client->start = line;
6760 line += SRC_ILT_LINES;
6761 ilt_client->end = line - 1;
6762
6763 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6764 "flags 0x%x, hw psz %d\n",
6765 ilt_client->start,
6766 ilt_client->end,
6767 ilt_client->page_size,
6768 ilt_client->flags,
6769 ilog2(ilt_client->page_size >> 12));
6770
6771 #else
6772 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6773 #endif
6774
6775 /* TM */
6776 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6777 #ifdef BCM_CNIC
6778 ilt_client->client_num = ILT_CLIENT_TM;
6779 ilt_client->page_size = TM_ILT_PAGE_SZ;
6780 ilt_client->flags = 0;
6781 ilt_client->start = line;
6782 line += TM_ILT_LINES;
6783 ilt_client->end = line - 1;
6784
6785 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6786 "flags 0x%x, hw psz %d\n",
6787 ilt_client->start,
6788 ilt_client->end,
6789 ilt_client->page_size,
6790 ilt_client->flags,
6791 ilog2(ilt_client->page_size >> 12));
6792
6793 #else
6794 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6795 #endif
6796 }
6797
6798 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6799 int is_leading)
6800 {
6801 struct bnx2x_client_init_params params = { {0} };
6802 int rc;
6803
6804 /* reset IGU state skip FCoE L2 queue */
6805 if (!IS_FCOE_FP(fp))
6806 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6807 IGU_INT_ENABLE, 0);
6808
6809 params.ramrod_params.pstate = &fp->state;
6810 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6811 params.ramrod_params.index = fp->index;
6812 params.ramrod_params.cid = fp->cid;
6813
6814 #ifdef BCM_CNIC
6815 if (IS_FCOE_FP(fp))
6816 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6817
6818 #endif
6819
6820 if (is_leading)
6821 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
6822
6823 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6824
6825 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6826
6827 rc = bnx2x_setup_fw_client(bp, &params, 1,
6828 bnx2x_sp(bp, client_init_data),
6829 bnx2x_sp_mapping(bp, client_init_data));
6830 return rc;
6831 }
6832
6833 static int bnx2x_stop_fw_client(struct bnx2x *bp,
6834 struct bnx2x_client_ramrod_params *p)
6835 {
6836 int rc;
6837
6838 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
6839
6840 /* halt the connection */
6841 *p->pstate = BNX2X_FP_STATE_HALTING;
6842 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6843 p->cl_id, 0);
6844
6845 /* Wait for completion */
6846 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6847 p->pstate, poll_flag);
6848 if (rc) /* timeout */
6849 return rc;
6850
6851 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6852 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6853 p->cl_id, 0);
6854 /* Wait for completion */
6855 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6856 p->pstate, poll_flag);
6857 if (rc) /* timeout */
6858 return rc;
6859
6860
6861 /* delete cfc entry */
6862 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
6863
6864 /* Wait for completion */
6865 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6866 p->pstate, WAIT_RAMROD_COMMON);
6867 return rc;
6868 }
6869
6870 static int bnx2x_stop_client(struct bnx2x *bp, int index)
6871 {
6872 struct bnx2x_client_ramrod_params client_stop = {0};
6873 struct bnx2x_fastpath *fp = &bp->fp[index];
6874
6875 client_stop.index = index;
6876 client_stop.cid = fp->cid;
6877 client_stop.cl_id = fp->cl_id;
6878 client_stop.pstate = &(fp->state);
6879 client_stop.poll = 0;
6880
6881 return bnx2x_stop_fw_client(bp, &client_stop);
6882 }
6883
6884
6885 static void bnx2x_reset_func(struct bnx2x *bp)
6886 {
6887 int port = BP_PORT(bp);
6888 int func = BP_FUNC(bp);
6889 int i;
6890 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
6891 (CHIP_IS_E2(bp) ?
6892 offsetof(struct hc_status_block_data_e2, common) :
6893 offsetof(struct hc_status_block_data_e1x, common));
6894 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6895 int pfid_offset = offsetof(struct pci_entity, pf_id);
6896
6897 /* Disable the function in the FW */
6898 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6899 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6900 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6901 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6902
6903 /* FP SBs */
6904 for_each_eth_queue(bp, i) {
6905 struct bnx2x_fastpath *fp = &bp->fp[i];
6906 REG_WR8(bp,
6907 BAR_CSTRORM_INTMEM +
6908 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6909 + pfunc_offset_fp + pfid_offset,
6910 HC_FUNCTION_DISABLED);
6911 }
6912
6913 /* SP SB */
6914 REG_WR8(bp,
6915 BAR_CSTRORM_INTMEM +
6916 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6917 pfunc_offset_sp + pfid_offset,
6918 HC_FUNCTION_DISABLED);
6919
6920
6921 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6922 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6923 0);
6924
6925 /* Configure IGU */
6926 if (bp->common.int_block == INT_BLOCK_HC) {
6927 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6928 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6929 } else {
6930 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6931 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6932 }
6933
6934 #ifdef BCM_CNIC
6935 /* Disable Timer scan */
6936 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6937 /*
6938 * Wait for at least 10ms and up to 2 second for the timers scan to
6939 * complete
6940 */
6941 for (i = 0; i < 200; i++) {
6942 msleep(10);
6943 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6944 break;
6945 }
6946 #endif
6947 /* Clear ILT */
6948 bnx2x_clear_func_ilt(bp, func);
6949
6950 /* Timers workaround bug for E2: if this is vnic-3,
6951 * we need to set the entire ilt range for this timers.
6952 */
6953 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6954 struct ilt_client_info ilt_cli;
6955 /* use dummy TM client */
6956 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6957 ilt_cli.start = 0;
6958 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6959 ilt_cli.client_num = ILT_CLIENT_TM;
6960
6961 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
6962 }
6963
6964 /* this assumes that reset_port() called before reset_func()*/
6965 if (CHIP_IS_E2(bp))
6966 bnx2x_pf_disable(bp);
6967
6968 bp->dmae_ready = 0;
6969 }
6970
6971 static void bnx2x_reset_port(struct bnx2x *bp)
6972 {
6973 int port = BP_PORT(bp);
6974 u32 val;
6975
6976 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6977
6978 /* Do not rcv packets to BRB */
6979 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6980 /* Do not direct rcv packets that are not for MCP to the BRB */
6981 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6982 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6983
6984 /* Configure AEU */
6985 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6986
6987 msleep(100);
6988 /* Check for BRB port occupancy */
6989 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6990 if (val)
6991 DP(NETIF_MSG_IFDOWN,
6992 "BRB1 is not empty %d blocks are occupied\n", val);
6993
6994 /* TODO: Close Doorbell port? */
6995 }
6996
6997 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6998 {
6999 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
7000 BP_ABS_FUNC(bp), reset_code);
7001
7002 switch (reset_code) {
7003 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7004 bnx2x_reset_port(bp);
7005 bnx2x_reset_func(bp);
7006 bnx2x_reset_common(bp);
7007 break;
7008
7009 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7010 bnx2x_reset_port(bp);
7011 bnx2x_reset_func(bp);
7012 break;
7013
7014 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7015 bnx2x_reset_func(bp);
7016 break;
7017
7018 default:
7019 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7020 break;
7021 }
7022 }
7023
7024 #ifdef BCM_CNIC
7025 static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7026 {
7027 if (bp->flags & FCOE_MACS_SET) {
7028 if (!IS_MF_SD(bp))
7029 bnx2x_set_fip_eth_mac_addr(bp, 0);
7030
7031 bnx2x_set_all_enode_macs(bp, 0);
7032
7033 bp->flags &= ~FCOE_MACS_SET;
7034 }
7035 }
7036 #endif
7037
7038 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7039 {
7040 int port = BP_PORT(bp);
7041 u32 reset_code = 0;
7042 int i, cnt, rc;
7043
7044 /* Wait until tx fastpath tasks complete */
7045 for_each_tx_queue(bp, i) {
7046 struct bnx2x_fastpath *fp = &bp->fp[i];
7047
7048 cnt = 1000;
7049 while (bnx2x_has_tx_work_unload(fp)) {
7050
7051 if (!cnt) {
7052 BNX2X_ERR("timeout waiting for queue[%d]\n",
7053 i);
7054 #ifdef BNX2X_STOP_ON_ERROR
7055 bnx2x_panic();
7056 return -EBUSY;
7057 #else
7058 break;
7059 #endif
7060 }
7061 cnt--;
7062 msleep(1);
7063 }
7064 }
7065 /* Give HW time to discard old tx messages */
7066 msleep(1);
7067
7068 bnx2x_set_eth_mac(bp, 0);
7069
7070 bnx2x_invalidate_uc_list(bp);
7071
7072 if (CHIP_IS_E1(bp))
7073 bnx2x_invalidate_e1_mc_list(bp);
7074 else {
7075 bnx2x_invalidate_e1h_mc_list(bp);
7076 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7077 }
7078
7079 #ifdef BCM_CNIC
7080 bnx2x_del_fcoe_eth_macs(bp);
7081 #endif
7082
7083 if (unload_mode == UNLOAD_NORMAL)
7084 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7085
7086 else if (bp->flags & NO_WOL_FLAG)
7087 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7088
7089 else if (bp->wol) {
7090 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7091 u8 *mac_addr = bp->dev->dev_addr;
7092 u32 val;
7093 /* The mac address is written to entries 1-4 to
7094 preserve entry 0 which is used by the PMF */
7095 u8 entry = (BP_E1HVN(bp) + 1)*8;
7096
7097 val = (mac_addr[0] << 8) | mac_addr[1];
7098 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7099
7100 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7101 (mac_addr[4] << 8) | mac_addr[5];
7102 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7103
7104 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7105
7106 } else
7107 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7108
7109 /* Close multi and leading connections
7110 Completions for ramrods are collected in a synchronous way */
7111 for_each_queue(bp, i)
7112
7113 if (bnx2x_stop_client(bp, i))
7114 #ifdef BNX2X_STOP_ON_ERROR
7115 return;
7116 #else
7117 goto unload_error;
7118 #endif
7119
7120 rc = bnx2x_func_stop(bp);
7121 if (rc) {
7122 BNX2X_ERR("Function stop failed!\n");
7123 #ifdef BNX2X_STOP_ON_ERROR
7124 return;
7125 #else
7126 goto unload_error;
7127 #endif
7128 }
7129 #ifndef BNX2X_STOP_ON_ERROR
7130 unload_error:
7131 #endif
7132 if (!BP_NOMCP(bp))
7133 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7134 else {
7135 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7136 "%d, %d, %d\n", BP_PATH(bp),
7137 load_count[BP_PATH(bp)][0],
7138 load_count[BP_PATH(bp)][1],
7139 load_count[BP_PATH(bp)][2]);
7140 load_count[BP_PATH(bp)][0]--;
7141 load_count[BP_PATH(bp)][1 + port]--;
7142 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7143 "%d, %d, %d\n", BP_PATH(bp),
7144 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7145 load_count[BP_PATH(bp)][2]);
7146 if (load_count[BP_PATH(bp)][0] == 0)
7147 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7148 else if (load_count[BP_PATH(bp)][1 + port] == 0)
7149 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7150 else
7151 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7152 }
7153
7154 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7155 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7156 bnx2x__link_reset(bp);
7157
7158 /* Disable HW interrupts, NAPI */
7159 bnx2x_netif_stop(bp, 1);
7160
7161 /* Release IRQs */
7162 bnx2x_free_irq(bp);
7163
7164 /* Reset the chip */
7165 bnx2x_reset_chip(bp, reset_code);
7166
7167 /* Report UNLOAD_DONE to MCP */
7168 if (!BP_NOMCP(bp))
7169 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7170
7171 }
7172
7173 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7174 {
7175 u32 val;
7176
7177 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7178
7179 if (CHIP_IS_E1(bp)) {
7180 int port = BP_PORT(bp);
7181 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7182 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7183
7184 val = REG_RD(bp, addr);
7185 val &= ~(0x300);
7186 REG_WR(bp, addr, val);
7187 } else if (CHIP_IS_E1H(bp)) {
7188 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7189 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7190 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7191 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7192 }
7193 }
7194
7195 /* Close gates #2, #3 and #4: */
7196 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7197 {
7198 u32 val, addr;
7199
7200 /* Gates #2 and #4a are closed/opened for "not E1" only */
7201 if (!CHIP_IS_E1(bp)) {
7202 /* #4 */
7203 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7204 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7205 close ? (val | 0x1) : (val & (~(u32)1)));
7206 /* #2 */
7207 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7208 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7209 close ? (val | 0x1) : (val & (~(u32)1)));
7210 }
7211
7212 /* #3 */
7213 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7214 val = REG_RD(bp, addr);
7215 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7216
7217 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7218 close ? "closing" : "opening");
7219 mmiowb();
7220 }
7221
7222 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7223
7224 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7225 {
7226 /* Do some magic... */
7227 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7228 *magic_val = val & SHARED_MF_CLP_MAGIC;
7229 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7230 }
7231
7232 /**
7233 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7234 *
7235 * @bp: driver handle
7236 * @magic_val: old value of the `magic' bit.
7237 */
7238 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7239 {
7240 /* Restore the `magic' bit value... */
7241 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7242 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7243 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7244 }
7245
7246 /**
7247 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7248 *
7249 * @bp: driver handle
7250 * @magic_val: old value of 'magic' bit.
7251 *
7252 * Takes care of CLP configurations.
7253 */
7254 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7255 {
7256 u32 shmem;
7257 u32 validity_offset;
7258
7259 DP(NETIF_MSG_HW, "Starting\n");
7260
7261 /* Set `magic' bit in order to save MF config */
7262 if (!CHIP_IS_E1(bp))
7263 bnx2x_clp_reset_prep(bp, magic_val);
7264
7265 /* Get shmem offset */
7266 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7267 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7268
7269 /* Clear validity map flags */
7270 if (shmem > 0)
7271 REG_WR(bp, shmem + validity_offset, 0);
7272 }
7273
7274 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7275 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7276
7277 /**
7278 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7279 *
7280 * @bp: driver handle
7281 */
7282 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7283 {
7284 /* special handling for emulation and FPGA,
7285 wait 10 times longer */
7286 if (CHIP_REV_IS_SLOW(bp))
7287 msleep(MCP_ONE_TIMEOUT*10);
7288 else
7289 msleep(MCP_ONE_TIMEOUT);
7290 }
7291
7292 /*
7293 * initializes bp->common.shmem_base and waits for validity signature to appear
7294 */
7295 static int bnx2x_init_shmem(struct bnx2x *bp)
7296 {
7297 int cnt = 0;
7298 u32 val = 0;
7299
7300 do {
7301 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7302 if (bp->common.shmem_base) {
7303 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7304 if (val & SHR_MEM_VALIDITY_MB)
7305 return 0;
7306 }
7307
7308 bnx2x_mcp_wait_one(bp);
7309
7310 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7311
7312 BNX2X_ERR("BAD MCP validity signature\n");
7313
7314 return -ENODEV;
7315 }
7316
7317 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7318 {
7319 int rc = bnx2x_init_shmem(bp);
7320
7321 /* Restore the `magic' bit value */
7322 if (!CHIP_IS_E1(bp))
7323 bnx2x_clp_reset_done(bp, magic_val);
7324
7325 return rc;
7326 }
7327
7328 static void bnx2x_pxp_prep(struct bnx2x *bp)
7329 {
7330 if (!CHIP_IS_E1(bp)) {
7331 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7332 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7333 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7334 mmiowb();
7335 }
7336 }
7337
7338 /*
7339 * Reset the whole chip except for:
7340 * - PCIE core
7341 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7342 * one reset bit)
7343 * - IGU
7344 * - MISC (including AEU)
7345 * - GRC
7346 * - RBCN, RBCP
7347 */
7348 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7349 {
7350 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7351
7352 not_reset_mask1 =
7353 MISC_REGISTERS_RESET_REG_1_RST_HC |
7354 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7355 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7356
7357 not_reset_mask2 =
7358 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7359 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7360 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7361 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7362 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7363 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7364 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7365 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7366
7367 reset_mask1 = 0xffffffff;
7368
7369 if (CHIP_IS_E1(bp))
7370 reset_mask2 = 0xffff;
7371 else
7372 reset_mask2 = 0x1ffff;
7373
7374 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7375 reset_mask1 & (~not_reset_mask1));
7376 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7377 reset_mask2 & (~not_reset_mask2));
7378
7379 barrier();
7380 mmiowb();
7381
7382 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7383 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7384 mmiowb();
7385 }
7386
7387 static int bnx2x_process_kill(struct bnx2x *bp)
7388 {
7389 int cnt = 1000;
7390 u32 val = 0;
7391 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7392
7393
7394 /* Empty the Tetris buffer, wait for 1s */
7395 do {
7396 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7397 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7398 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7399 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7400 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7401 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7402 ((port_is_idle_0 & 0x1) == 0x1) &&
7403 ((port_is_idle_1 & 0x1) == 0x1) &&
7404 (pgl_exp_rom2 == 0xffffffff))
7405 break;
7406 msleep(1);
7407 } while (cnt-- > 0);
7408
7409 if (cnt <= 0) {
7410 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7411 " are still"
7412 " outstanding read requests after 1s!\n");
7413 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7414 " port_is_idle_0=0x%08x,"
7415 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7416 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7417 pgl_exp_rom2);
7418 return -EAGAIN;
7419 }
7420
7421 barrier();
7422
7423 /* Close gates #2, #3 and #4 */
7424 bnx2x_set_234_gates(bp, true);
7425
7426 /* TBD: Indicate that "process kill" is in progress to MCP */
7427
7428 /* Clear "unprepared" bit */
7429 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7430 barrier();
7431
7432 /* Make sure all is written to the chip before the reset */
7433 mmiowb();
7434
7435 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7436 * PSWHST, GRC and PSWRD Tetris buffer.
7437 */
7438 msleep(1);
7439
7440 /* Prepare to chip reset: */
7441 /* MCP */
7442 bnx2x_reset_mcp_prep(bp, &val);
7443
7444 /* PXP */
7445 bnx2x_pxp_prep(bp);
7446 barrier();
7447
7448 /* reset the chip */
7449 bnx2x_process_kill_chip_reset(bp);
7450 barrier();
7451
7452 /* Recover after reset: */
7453 /* MCP */
7454 if (bnx2x_reset_mcp_comp(bp, val))
7455 return -EAGAIN;
7456
7457 /* PXP */
7458 bnx2x_pxp_prep(bp);
7459
7460 /* Open the gates #2, #3 and #4 */
7461 bnx2x_set_234_gates(bp, false);
7462
7463 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7464 * reset state, re-enable attentions. */
7465
7466 return 0;
7467 }
7468
7469 static int bnx2x_leader_reset(struct bnx2x *bp)
7470 {
7471 int rc = 0;
7472 /* Try to recover after the failure */
7473 if (bnx2x_process_kill(bp)) {
7474 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7475 bp->dev->name);
7476 rc = -EAGAIN;
7477 goto exit_leader_reset;
7478 }
7479
7480 /* Clear "reset is in progress" bit and update the driver state */
7481 bnx2x_set_reset_done(bp);
7482 bp->recovery_state = BNX2X_RECOVERY_DONE;
7483
7484 exit_leader_reset:
7485 bp->is_leader = 0;
7486 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7487 smp_wmb();
7488 return rc;
7489 }
7490
7491 /* Assumption: runs under rtnl lock. This together with the fact
7492 * that it's called only from bnx2x_reset_task() ensure that it
7493 * will never be called when netif_running(bp->dev) is false.
7494 */
7495 static void bnx2x_parity_recover(struct bnx2x *bp)
7496 {
7497 DP(NETIF_MSG_HW, "Handling parity\n");
7498 while (1) {
7499 switch (bp->recovery_state) {
7500 case BNX2X_RECOVERY_INIT:
7501 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7502 /* Try to get a LEADER_LOCK HW lock */
7503 if (bnx2x_trylock_hw_lock(bp,
7504 HW_LOCK_RESOURCE_RESERVED_08))
7505 bp->is_leader = 1;
7506
7507 /* Stop the driver */
7508 /* If interface has been removed - break */
7509 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7510 return;
7511
7512 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7513 /* Ensure "is_leader" and "recovery_state"
7514 * update values are seen on other CPUs
7515 */
7516 smp_wmb();
7517 break;
7518
7519 case BNX2X_RECOVERY_WAIT:
7520 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7521 if (bp->is_leader) {
7522 u32 load_counter = bnx2x_get_load_cnt(bp);
7523 if (load_counter) {
7524 /* Wait until all other functions get
7525 * down.
7526 */
7527 schedule_delayed_work(&bp->reset_task,
7528 HZ/10);
7529 return;
7530 } else {
7531 /* If all other functions got down -
7532 * try to bring the chip back to
7533 * normal. In any case it's an exit
7534 * point for a leader.
7535 */
7536 if (bnx2x_leader_reset(bp) ||
7537 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7538 printk(KERN_ERR"%s: Recovery "
7539 "has failed. Power cycle is "
7540 "needed.\n", bp->dev->name);
7541 /* Disconnect this device */
7542 netif_device_detach(bp->dev);
7543 /* Block ifup for all function
7544 * of this ASIC until
7545 * "process kill" or power
7546 * cycle.
7547 */
7548 bnx2x_set_reset_in_progress(bp);
7549 /* Shut down the power */
7550 bnx2x_set_power_state(bp,
7551 PCI_D3hot);
7552 return;
7553 }
7554
7555 return;
7556 }
7557 } else { /* non-leader */
7558 if (!bnx2x_reset_is_done(bp)) {
7559 /* Try to get a LEADER_LOCK HW lock as
7560 * long as a former leader may have
7561 * been unloaded by the user or
7562 * released a leadership by another
7563 * reason.
7564 */
7565 if (bnx2x_trylock_hw_lock(bp,
7566 HW_LOCK_RESOURCE_RESERVED_08)) {
7567 /* I'm a leader now! Restart a
7568 * switch case.
7569 */
7570 bp->is_leader = 1;
7571 break;
7572 }
7573
7574 schedule_delayed_work(&bp->reset_task,
7575 HZ/10);
7576 return;
7577
7578 } else { /* A leader has completed
7579 * the "process kill". It's an exit
7580 * point for a non-leader.
7581 */
7582 bnx2x_nic_load(bp, LOAD_NORMAL);
7583 bp->recovery_state =
7584 BNX2X_RECOVERY_DONE;
7585 smp_wmb();
7586 return;
7587 }
7588 }
7589 default:
7590 return;
7591 }
7592 }
7593 }
7594
7595 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7596 * scheduled on a general queue in order to prevent a dead lock.
7597 */
7598 static void bnx2x_reset_task(struct work_struct *work)
7599 {
7600 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
7601
7602 #ifdef BNX2X_STOP_ON_ERROR
7603 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7604 " so reset not done to allow debug dump,\n"
7605 KERN_ERR " you will need to reboot when done\n");
7606 return;
7607 #endif
7608
7609 rtnl_lock();
7610
7611 if (!netif_running(bp->dev))
7612 goto reset_task_exit;
7613
7614 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7615 bnx2x_parity_recover(bp);
7616 else {
7617 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7618 bnx2x_nic_load(bp, LOAD_NORMAL);
7619 }
7620
7621 reset_task_exit:
7622 rtnl_unlock();
7623 }
7624
7625 /* end of nic load/unload */
7626
7627 /*
7628 * Init service functions
7629 */
7630
7631 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
7632 {
7633 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7634 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7635 return base + (BP_ABS_FUNC(bp)) * stride;
7636 }
7637
7638 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
7639 {
7640 u32 reg = bnx2x_get_pretend_reg(bp);
7641
7642 /* Flush all outstanding writes */
7643 mmiowb();
7644
7645 /* Pretend to be function 0 */
7646 REG_WR(bp, reg, 0);
7647 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
7648
7649 /* From now we are in the "like-E1" mode */
7650 bnx2x_int_disable(bp);
7651
7652 /* Flush all outstanding writes */
7653 mmiowb();
7654
7655 /* Restore the original function */
7656 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7657 REG_RD(bp, reg);
7658 }
7659
7660 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
7661 {
7662 if (CHIP_IS_E1(bp))
7663 bnx2x_int_disable(bp);
7664 else
7665 bnx2x_undi_int_disable_e1h(bp);
7666 }
7667
7668 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7669 {
7670 u32 val;
7671
7672 /* Check if there is any driver already loaded */
7673 val = REG_RD(bp, MISC_REG_UNPREPARED);
7674 if (val == 0x1) {
7675 /* Check if it is the UNDI driver
7676 * UNDI driver initializes CID offset for normal bell to 0x7
7677 */
7678 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7679 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7680 if (val == 0x7) {
7681 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7682 /* save our pf_num */
7683 int orig_pf_num = bp->pf_num;
7684 u32 swap_en;
7685 u32 swap_val;
7686
7687 /* clear the UNDI indication */
7688 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7689
7690 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7691
7692 /* try unload UNDI on port 0 */
7693 bp->pf_num = 0;
7694 bp->fw_seq =
7695 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7696 DRV_MSG_SEQ_NUMBER_MASK);
7697 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7698
7699 /* if UNDI is loaded on the other port */
7700 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7701
7702 /* send "DONE" for previous unload */
7703 bnx2x_fw_command(bp,
7704 DRV_MSG_CODE_UNLOAD_DONE, 0);
7705
7706 /* unload UNDI on port 1 */
7707 bp->pf_num = 1;
7708 bp->fw_seq =
7709 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7710 DRV_MSG_SEQ_NUMBER_MASK);
7711 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7712
7713 bnx2x_fw_command(bp, reset_code, 0);
7714 }
7715
7716 /* now it's safe to release the lock */
7717 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7718
7719 bnx2x_undi_int_disable(bp);
7720
7721 /* close input traffic and wait for it */
7722 /* Do not rcv packets to BRB */
7723 REG_WR(bp,
7724 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7725 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7726 /* Do not direct rcv packets that are not for MCP to
7727 * the BRB */
7728 REG_WR(bp,
7729 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7730 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7731 /* clear AEU */
7732 REG_WR(bp,
7733 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7734 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7735 msleep(10);
7736
7737 /* save NIG port swap info */
7738 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7739 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7740 /* reset device */
7741 REG_WR(bp,
7742 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7743 0xd3ffffff);
7744 REG_WR(bp,
7745 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7746 0x1403);
7747 /* take the NIG out of reset and restore swap values */
7748 REG_WR(bp,
7749 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7750 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7751 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7752 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7753
7754 /* send unload done to the MCP */
7755 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7756
7757 /* restore our func and fw_seq */
7758 bp->pf_num = orig_pf_num;
7759 bp->fw_seq =
7760 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7761 DRV_MSG_SEQ_NUMBER_MASK);
7762 } else
7763 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7764 }
7765 }
7766
7767 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7768 {
7769 u32 val, val2, val3, val4, id;
7770 u16 pmc;
7771
7772 /* Get the chip revision id and number. */
7773 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7774 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7775 id = ((val & 0xffff) << 16);
7776 val = REG_RD(bp, MISC_REG_CHIP_REV);
7777 id |= ((val & 0xf) << 12);
7778 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7779 id |= ((val & 0xff) << 4);
7780 val = REG_RD(bp, MISC_REG_BOND_ID);
7781 id |= (val & 0xf);
7782 bp->common.chip_id = id;
7783
7784 /* Set doorbell size */
7785 bp->db_size = (1 << BNX2X_DB_SHIFT);
7786
7787 if (CHIP_IS_E2(bp)) {
7788 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7789 if ((val & 1) == 0)
7790 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7791 else
7792 val = (val >> 1) & 1;
7793 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7794 "2_PORT_MODE");
7795 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7796 CHIP_2_PORT_MODE;
7797
7798 if (CHIP_MODE_IS_4_PORT(bp))
7799 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7800 else
7801 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7802 } else {
7803 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7804 bp->pfid = bp->pf_num; /* 0..7 */
7805 }
7806
7807 /*
7808 * set base FW non-default (fast path) status block id, this value is
7809 * used to initialize the fw_sb_id saved on the fp/queue structure to
7810 * determine the id used by the FW.
7811 */
7812 if (CHIP_IS_E1x(bp))
7813 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7814 else /* E2 */
7815 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7816
7817 bp->link_params.chip_id = bp->common.chip_id;
7818 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
7819
7820 val = (REG_RD(bp, 0x2874) & 0x55);
7821 if ((bp->common.chip_id & 0x1) ||
7822 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7823 bp->flags |= ONE_PORT_FLAG;
7824 BNX2X_DEV_INFO("single port device\n");
7825 }
7826
7827 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7828 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7829 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7830 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7831 bp->common.flash_size, bp->common.flash_size);
7832
7833 bnx2x_init_shmem(bp);
7834
7835 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7836 MISC_REG_GENERIC_CR_1 :
7837 MISC_REG_GENERIC_CR_0));
7838
7839 bp->link_params.shmem_base = bp->common.shmem_base;
7840 bp->link_params.shmem2_base = bp->common.shmem2_base;
7841 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7842 bp->common.shmem_base, bp->common.shmem2_base);
7843
7844 if (!bp->common.shmem_base) {
7845 BNX2X_DEV_INFO("MCP not active\n");
7846 bp->flags |= NO_MCP_FLAG;
7847 return;
7848 }
7849
7850 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7851 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
7852
7853 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7854 SHARED_HW_CFG_LED_MODE_MASK) >>
7855 SHARED_HW_CFG_LED_MODE_SHIFT);
7856
7857 bp->link_params.feature_config_flags = 0;
7858 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7859 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7860 bp->link_params.feature_config_flags |=
7861 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7862 else
7863 bp->link_params.feature_config_flags &=
7864 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7865
7866 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7867 bp->common.bc_ver = val;
7868 BNX2X_DEV_INFO("bc_ver %X\n", val);
7869 if (val < BNX2X_BC_VER) {
7870 /* for now only warn
7871 * later we might need to enforce this */
7872 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7873 "please upgrade BC\n", BNX2X_BC_VER, val);
7874 }
7875 bp->link_params.feature_config_flags |=
7876 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
7877 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7878
7879 bp->link_params.feature_config_flags |=
7880 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7881 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
7882
7883 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7884 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7885
7886 BNX2X_DEV_INFO("%sWoL capable\n",
7887 (bp->flags & NO_WOL_FLAG) ? "not " : "");
7888
7889 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7890 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7891 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7892 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7893
7894 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7895 val, val2, val3, val4);
7896 }
7897
7898 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7899 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7900
7901 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7902 {
7903 int pfid = BP_FUNC(bp);
7904 int vn = BP_E1HVN(bp);
7905 int igu_sb_id;
7906 u32 val;
7907 u8 fid;
7908
7909 bp->igu_base_sb = 0xff;
7910 bp->igu_sb_cnt = 0;
7911 if (CHIP_INT_MODE_IS_BC(bp)) {
7912 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
7913 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7914
7915 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7916 FP_SB_MAX_E1x;
7917
7918 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7919 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7920
7921 return;
7922 }
7923
7924 /* IGU in normal mode - read CAM */
7925 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7926 igu_sb_id++) {
7927 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7928 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7929 continue;
7930 fid = IGU_FID(val);
7931 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7932 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7933 continue;
7934 if (IGU_VEC(val) == 0)
7935 /* default status block */
7936 bp->igu_dsb_id = igu_sb_id;
7937 else {
7938 if (bp->igu_base_sb == 0xff)
7939 bp->igu_base_sb = igu_sb_id;
7940 bp->igu_sb_cnt++;
7941 }
7942 }
7943 }
7944 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
7945 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7946 if (bp->igu_sb_cnt == 0)
7947 BNX2X_ERR("CAM configuration error\n");
7948 }
7949
7950 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
7951 u32 switch_cfg)
7952 {
7953 int cfg_size = 0, idx, port = BP_PORT(bp);
7954
7955 /* Aggregation of supported attributes of all external phys */
7956 bp->port.supported[0] = 0;
7957 bp->port.supported[1] = 0;
7958 switch (bp->link_params.num_phys) {
7959 case 1:
7960 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
7961 cfg_size = 1;
7962 break;
7963 case 2:
7964 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
7965 cfg_size = 1;
7966 break;
7967 case 3:
7968 if (bp->link_params.multi_phy_config &
7969 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
7970 bp->port.supported[1] =
7971 bp->link_params.phy[EXT_PHY1].supported;
7972 bp->port.supported[0] =
7973 bp->link_params.phy[EXT_PHY2].supported;
7974 } else {
7975 bp->port.supported[0] =
7976 bp->link_params.phy[EXT_PHY1].supported;
7977 bp->port.supported[1] =
7978 bp->link_params.phy[EXT_PHY2].supported;
7979 }
7980 cfg_size = 2;
7981 break;
7982 }
7983
7984 if (!(bp->port.supported[0] || bp->port.supported[1])) {
7985 BNX2X_ERR("NVRAM config error. BAD phy config."
7986 "PHY1 config 0x%x, PHY2 config 0x%x\n",
7987 SHMEM_RD(bp,
7988 dev_info.port_hw_config[port].external_phy_config),
7989 SHMEM_RD(bp,
7990 dev_info.port_hw_config[port].external_phy_config2));
7991 return;
7992 }
7993
7994 switch (switch_cfg) {
7995 case SWITCH_CFG_1G:
7996 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
7997 port*0x10);
7998 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7999 break;
8000
8001 case SWITCH_CFG_10G:
8002 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8003 port*0x18);
8004 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8005 break;
8006
8007 default:
8008 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8009 bp->port.link_config[0]);
8010 return;
8011 }
8012 /* mask what we support according to speed_cap_mask per configuration */
8013 for (idx = 0; idx < cfg_size; idx++) {
8014 if (!(bp->link_params.speed_cap_mask[idx] &
8015 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8016 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8017
8018 if (!(bp->link_params.speed_cap_mask[idx] &
8019 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8020 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8021
8022 if (!(bp->link_params.speed_cap_mask[idx] &
8023 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8024 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8025
8026 if (!(bp->link_params.speed_cap_mask[idx] &
8027 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8028 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8029
8030 if (!(bp->link_params.speed_cap_mask[idx] &
8031 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8032 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8033 SUPPORTED_1000baseT_Full);
8034
8035 if (!(bp->link_params.speed_cap_mask[idx] &
8036 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8037 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8038
8039 if (!(bp->link_params.speed_cap_mask[idx] &
8040 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8041 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8042
8043 }
8044
8045 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8046 bp->port.supported[1]);
8047 }
8048
8049 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8050 {
8051 u32 link_config, idx, cfg_size = 0;
8052 bp->port.advertising[0] = 0;
8053 bp->port.advertising[1] = 0;
8054 switch (bp->link_params.num_phys) {
8055 case 1:
8056 case 2:
8057 cfg_size = 1;
8058 break;
8059 case 3:
8060 cfg_size = 2;
8061 break;
8062 }
8063 for (idx = 0; idx < cfg_size; idx++) {
8064 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8065 link_config = bp->port.link_config[idx];
8066 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8067 case PORT_FEATURE_LINK_SPEED_AUTO:
8068 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8069 bp->link_params.req_line_speed[idx] =
8070 SPEED_AUTO_NEG;
8071 bp->port.advertising[idx] |=
8072 bp->port.supported[idx];
8073 } else {
8074 /* force 10G, no AN */
8075 bp->link_params.req_line_speed[idx] =
8076 SPEED_10000;
8077 bp->port.advertising[idx] |=
8078 (ADVERTISED_10000baseT_Full |
8079 ADVERTISED_FIBRE);
8080 continue;
8081 }
8082 break;
8083
8084 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8085 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8086 bp->link_params.req_line_speed[idx] =
8087 SPEED_10;
8088 bp->port.advertising[idx] |=
8089 (ADVERTISED_10baseT_Full |
8090 ADVERTISED_TP);
8091 } else {
8092 BNX2X_ERROR("NVRAM config error. "
8093 "Invalid link_config 0x%x"
8094 " speed_cap_mask 0x%x\n",
8095 link_config,
8096 bp->link_params.speed_cap_mask[idx]);
8097 return;
8098 }
8099 break;
8100
8101 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8102 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8103 bp->link_params.req_line_speed[idx] =
8104 SPEED_10;
8105 bp->link_params.req_duplex[idx] =
8106 DUPLEX_HALF;
8107 bp->port.advertising[idx] |=
8108 (ADVERTISED_10baseT_Half |
8109 ADVERTISED_TP);
8110 } else {
8111 BNX2X_ERROR("NVRAM config error. "
8112 "Invalid link_config 0x%x"
8113 " speed_cap_mask 0x%x\n",
8114 link_config,
8115 bp->link_params.speed_cap_mask[idx]);
8116 return;
8117 }
8118 break;
8119
8120 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8121 if (bp->port.supported[idx] &
8122 SUPPORTED_100baseT_Full) {
8123 bp->link_params.req_line_speed[idx] =
8124 SPEED_100;
8125 bp->port.advertising[idx] |=
8126 (ADVERTISED_100baseT_Full |
8127 ADVERTISED_TP);
8128 } else {
8129 BNX2X_ERROR("NVRAM config error. "
8130 "Invalid link_config 0x%x"
8131 " speed_cap_mask 0x%x\n",
8132 link_config,
8133 bp->link_params.speed_cap_mask[idx]);
8134 return;
8135 }
8136 break;
8137
8138 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8139 if (bp->port.supported[idx] &
8140 SUPPORTED_100baseT_Half) {
8141 bp->link_params.req_line_speed[idx] =
8142 SPEED_100;
8143 bp->link_params.req_duplex[idx] =
8144 DUPLEX_HALF;
8145 bp->port.advertising[idx] |=
8146 (ADVERTISED_100baseT_Half |
8147 ADVERTISED_TP);
8148 } else {
8149 BNX2X_ERROR("NVRAM config error. "
8150 "Invalid link_config 0x%x"
8151 " speed_cap_mask 0x%x\n",
8152 link_config,
8153 bp->link_params.speed_cap_mask[idx]);
8154 return;
8155 }
8156 break;
8157
8158 case PORT_FEATURE_LINK_SPEED_1G:
8159 if (bp->port.supported[idx] &
8160 SUPPORTED_1000baseT_Full) {
8161 bp->link_params.req_line_speed[idx] =
8162 SPEED_1000;
8163 bp->port.advertising[idx] |=
8164 (ADVERTISED_1000baseT_Full |
8165 ADVERTISED_TP);
8166 } else {
8167 BNX2X_ERROR("NVRAM config error. "
8168 "Invalid link_config 0x%x"
8169 " speed_cap_mask 0x%x\n",
8170 link_config,
8171 bp->link_params.speed_cap_mask[idx]);
8172 return;
8173 }
8174 break;
8175
8176 case PORT_FEATURE_LINK_SPEED_2_5G:
8177 if (bp->port.supported[idx] &
8178 SUPPORTED_2500baseX_Full) {
8179 bp->link_params.req_line_speed[idx] =
8180 SPEED_2500;
8181 bp->port.advertising[idx] |=
8182 (ADVERTISED_2500baseX_Full |
8183 ADVERTISED_TP);
8184 } else {
8185 BNX2X_ERROR("NVRAM config error. "
8186 "Invalid link_config 0x%x"
8187 " speed_cap_mask 0x%x\n",
8188 link_config,
8189 bp->link_params.speed_cap_mask[idx]);
8190 return;
8191 }
8192 break;
8193
8194 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8195 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8196 case PORT_FEATURE_LINK_SPEED_10G_KR:
8197 if (bp->port.supported[idx] &
8198 SUPPORTED_10000baseT_Full) {
8199 bp->link_params.req_line_speed[idx] =
8200 SPEED_10000;
8201 bp->port.advertising[idx] |=
8202 (ADVERTISED_10000baseT_Full |
8203 ADVERTISED_FIBRE);
8204 } else {
8205 BNX2X_ERROR("NVRAM config error. "
8206 "Invalid link_config 0x%x"
8207 " speed_cap_mask 0x%x\n",
8208 link_config,
8209 bp->link_params.speed_cap_mask[idx]);
8210 return;
8211 }
8212 break;
8213
8214 default:
8215 BNX2X_ERROR("NVRAM config error. "
8216 "BAD link speed link_config 0x%x\n",
8217 link_config);
8218 bp->link_params.req_line_speed[idx] =
8219 SPEED_AUTO_NEG;
8220 bp->port.advertising[idx] =
8221 bp->port.supported[idx];
8222 break;
8223 }
8224
8225 bp->link_params.req_flow_ctrl[idx] = (link_config &
8226 PORT_FEATURE_FLOW_CONTROL_MASK);
8227 if ((bp->link_params.req_flow_ctrl[idx] ==
8228 BNX2X_FLOW_CTRL_AUTO) &&
8229 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8230 bp->link_params.req_flow_ctrl[idx] =
8231 BNX2X_FLOW_CTRL_NONE;
8232 }
8233
8234 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8235 " 0x%x advertising 0x%x\n",
8236 bp->link_params.req_line_speed[idx],
8237 bp->link_params.req_duplex[idx],
8238 bp->link_params.req_flow_ctrl[idx],
8239 bp->port.advertising[idx]);
8240 }
8241 }
8242
8243 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8244 {
8245 mac_hi = cpu_to_be16(mac_hi);
8246 mac_lo = cpu_to_be32(mac_lo);
8247 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8248 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8249 }
8250
8251 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8252 {
8253 int port = BP_PORT(bp);
8254 u32 config;
8255 u32 ext_phy_type, ext_phy_config;
8256
8257 bp->link_params.bp = bp;
8258 bp->link_params.port = port;
8259
8260 bp->link_params.lane_config =
8261 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8262
8263 bp->link_params.speed_cap_mask[0] =
8264 SHMEM_RD(bp,
8265 dev_info.port_hw_config[port].speed_capability_mask);
8266 bp->link_params.speed_cap_mask[1] =
8267 SHMEM_RD(bp,
8268 dev_info.port_hw_config[port].speed_capability_mask2);
8269 bp->port.link_config[0] =
8270 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8271
8272 bp->port.link_config[1] =
8273 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8274
8275 bp->link_params.multi_phy_config =
8276 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8277 /* If the device is capable of WoL, set the default state according
8278 * to the HW
8279 */
8280 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8281 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8282 (config & PORT_FEATURE_WOL_ENABLED));
8283
8284 BNX2X_DEV_INFO("lane_config 0x%08x "
8285 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
8286 bp->link_params.lane_config,
8287 bp->link_params.speed_cap_mask[0],
8288 bp->port.link_config[0]);
8289
8290 bp->link_params.switch_cfg = (bp->port.link_config[0] &
8291 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8292 bnx2x_phy_probe(&bp->link_params);
8293 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8294
8295 bnx2x_link_settings_requested(bp);
8296
8297 /*
8298 * If connected directly, work with the internal PHY, otherwise, work
8299 * with the external PHY
8300 */
8301 ext_phy_config =
8302 SHMEM_RD(bp,
8303 dev_info.port_hw_config[port].external_phy_config);
8304 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8305 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8306 bp->mdio.prtad = bp->port.phy_addr;
8307
8308 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8309 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8310 bp->mdio.prtad =
8311 XGXS_EXT_PHY_ADDR(ext_phy_config);
8312
8313 /*
8314 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8315 * In MF mode, it is set to cover self test cases
8316 */
8317 if (IS_MF(bp))
8318 bp->port.need_hw_lock = 1;
8319 else
8320 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8321 bp->common.shmem_base,
8322 bp->common.shmem2_base);
8323 }
8324
8325 #ifdef BCM_CNIC
8326 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8327 {
8328 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8329 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8330 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8331 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8332
8333 /* Get the number of maximum allowed iSCSI and FCoE connections */
8334 bp->cnic_eth_dev.max_iscsi_conn =
8335 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8336 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8337
8338 bp->cnic_eth_dev.max_fcoe_conn =
8339 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8340 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8341
8342 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8343 bp->cnic_eth_dev.max_iscsi_conn,
8344 bp->cnic_eth_dev.max_fcoe_conn);
8345
8346 /* If mamimum allowed number of connections is zero -
8347 * disable the feature.
8348 */
8349 if (!bp->cnic_eth_dev.max_iscsi_conn)
8350 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8351
8352 if (!bp->cnic_eth_dev.max_fcoe_conn)
8353 bp->flags |= NO_FCOE_FLAG;
8354 }
8355 #endif
8356
8357 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8358 {
8359 u32 val, val2;
8360 int func = BP_ABS_FUNC(bp);
8361 int port = BP_PORT(bp);
8362 #ifdef BCM_CNIC
8363 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8364 u8 *fip_mac = bp->fip_mac;
8365 #endif
8366
8367 if (BP_NOMCP(bp)) {
8368 BNX2X_ERROR("warning: random MAC workaround active\n");
8369 random_ether_addr(bp->dev->dev_addr);
8370 } else if (IS_MF(bp)) {
8371 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8372 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8373 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8374 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8375 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8376
8377 #ifdef BCM_CNIC
8378 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8379 * FCoE MAC then the appropriate feature should be disabled.
8380 */
8381 if (IS_MF_SI(bp)) {
8382 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8383 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8384 val2 = MF_CFG_RD(bp, func_ext_config[func].
8385 iscsi_mac_addr_upper);
8386 val = MF_CFG_RD(bp, func_ext_config[func].
8387 iscsi_mac_addr_lower);
8388 BNX2X_DEV_INFO("Read iSCSI MAC: "
8389 "0x%x:0x%04x\n", val2, val);
8390 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8391 } else
8392 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8393
8394 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8395 val2 = MF_CFG_RD(bp, func_ext_config[func].
8396 fcoe_mac_addr_upper);
8397 val = MF_CFG_RD(bp, func_ext_config[func].
8398 fcoe_mac_addr_lower);
8399 BNX2X_DEV_INFO("Read FCoE MAC to "
8400 "0x%x:0x%04x\n", val2, val);
8401 bnx2x_set_mac_buf(fip_mac, val, val2);
8402
8403 } else
8404 bp->flags |= NO_FCOE_FLAG;
8405 }
8406 #endif
8407 } else {
8408 /* in SF read MACs from port configuration */
8409 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8410 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8411 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8412
8413 #ifdef BCM_CNIC
8414 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8415 iscsi_mac_upper);
8416 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8417 iscsi_mac_lower);
8418 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8419 #endif
8420 }
8421
8422 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8423 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8424
8425 #ifdef BCM_CNIC
8426 /* Set the FCoE MAC in modes other then MF_SI */
8427 if (!CHIP_IS_E1x(bp)) {
8428 if (IS_MF_SD(bp))
8429 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8430 else if (!IS_MF(bp))
8431 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
8432 }
8433
8434 /* Disable iSCSI if MAC configuration is
8435 * invalid.
8436 */
8437 if (!is_valid_ether_addr(iscsi_mac)) {
8438 bp->flags |= NO_ISCSI_FLAG;
8439 memset(iscsi_mac, 0, ETH_ALEN);
8440 }
8441
8442 /* Disable FCoE if MAC configuration is
8443 * invalid.
8444 */
8445 if (!is_valid_ether_addr(fip_mac)) {
8446 bp->flags |= NO_FCOE_FLAG;
8447 memset(bp->fip_mac, 0, ETH_ALEN);
8448 }
8449 #endif
8450 }
8451
8452 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8453 {
8454 int /*abs*/func = BP_ABS_FUNC(bp);
8455 int vn;
8456 u32 val = 0;
8457 int rc = 0;
8458
8459 bnx2x_get_common_hwinfo(bp);
8460
8461 if (CHIP_IS_E1x(bp)) {
8462 bp->common.int_block = INT_BLOCK_HC;
8463
8464 bp->igu_dsb_id = DEF_SB_IGU_ID;
8465 bp->igu_base_sb = 0;
8466 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8467 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8468 } else {
8469 bp->common.int_block = INT_BLOCK_IGU;
8470 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8471 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8472 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8473 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8474 } else
8475 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
8476
8477 bnx2x_get_igu_cam_info(bp);
8478
8479 }
8480 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8481 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8482
8483 /*
8484 * Initialize MF configuration
8485 */
8486
8487 bp->mf_ov = 0;
8488 bp->mf_mode = 0;
8489 vn = BP_E1HVN(bp);
8490
8491 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8492 DP(NETIF_MSG_PROBE,
8493 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8494 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8495 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8496 if (SHMEM2_HAS(bp, mf_cfg_addr))
8497 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8498 else
8499 bp->common.mf_cfg_base = bp->common.shmem_base +
8500 offsetof(struct shmem_region, func_mb) +
8501 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8502 /*
8503 * get mf configuration:
8504 * 1. existence of MF configuration
8505 * 2. MAC address must be legal (check only upper bytes)
8506 * for Switch-Independent mode;
8507 * OVLAN must be legal for Switch-Dependent mode
8508 * 3. SF_MODE configures specific MF mode
8509 */
8510 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8511 /* get mf configuration */
8512 val = SHMEM_RD(bp,
8513 dev_info.shared_feature_config.config);
8514 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8515
8516 switch (val) {
8517 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8518 val = MF_CFG_RD(bp, func_mf_config[func].
8519 mac_upper);
8520 /* check for legal mac (upper bytes)*/
8521 if (val != 0xffff) {
8522 bp->mf_mode = MULTI_FUNCTION_SI;
8523 bp->mf_config[vn] = MF_CFG_RD(bp,
8524 func_mf_config[func].config);
8525 } else
8526 DP(NETIF_MSG_PROBE, "illegal MAC "
8527 "address for SI\n");
8528 break;
8529 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8530 /* get OV configuration */
8531 val = MF_CFG_RD(bp,
8532 func_mf_config[FUNC_0].e1hov_tag);
8533 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8534
8535 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8536 bp->mf_mode = MULTI_FUNCTION_SD;
8537 bp->mf_config[vn] = MF_CFG_RD(bp,
8538 func_mf_config[func].config);
8539 } else
8540 DP(NETIF_MSG_PROBE, "illegal OV for "
8541 "SD\n");
8542 break;
8543 default:
8544 /* Unknown configuration: reset mf_config */
8545 bp->mf_config[vn] = 0;
8546 DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
8547 val);
8548 }
8549 }
8550
8551 BNX2X_DEV_INFO("%s function mode\n",
8552 IS_MF(bp) ? "multi" : "single");
8553
8554 switch (bp->mf_mode) {
8555 case MULTI_FUNCTION_SD:
8556 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8557 FUNC_MF_CFG_E1HOV_TAG_MASK;
8558 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8559 bp->mf_ov = val;
8560 BNX2X_DEV_INFO("MF OV for func %d is %d"
8561 " (0x%04x)\n", func,
8562 bp->mf_ov, bp->mf_ov);
8563 } else {
8564 BNX2X_ERR("No valid MF OV for func %d,"
8565 " aborting\n", func);
8566 rc = -EPERM;
8567 }
8568 break;
8569 case MULTI_FUNCTION_SI:
8570 BNX2X_DEV_INFO("func %d is in MF "
8571 "switch-independent mode\n", func);
8572 break;
8573 default:
8574 if (vn) {
8575 BNX2X_ERR("VN %d in single function mode,"
8576 " aborting\n", vn);
8577 rc = -EPERM;
8578 }
8579 break;
8580 }
8581
8582 }
8583
8584 /* adjust igu_sb_cnt to MF for E1x */
8585 if (CHIP_IS_E1x(bp) && IS_MF(bp))
8586 bp->igu_sb_cnt /= E1HVN_MAX;
8587
8588 /*
8589 * adjust E2 sb count: to be removed when FW will support
8590 * more then 16 L2 clients
8591 */
8592 #define MAX_L2_CLIENTS 16
8593 if (CHIP_IS_E2(bp))
8594 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8595 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8596
8597 if (!BP_NOMCP(bp)) {
8598 bnx2x_get_port_hwinfo(bp);
8599
8600 bp->fw_seq =
8601 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8602 DRV_MSG_SEQ_NUMBER_MASK);
8603 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8604 }
8605
8606 /* Get MAC addresses */
8607 bnx2x_get_mac_hwinfo(bp);
8608
8609 #ifdef BCM_CNIC
8610 bnx2x_get_cnic_info(bp);
8611 #endif
8612
8613 return rc;
8614 }
8615
8616 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8617 {
8618 int cnt, i, block_end, rodi;
8619 char vpd_data[BNX2X_VPD_LEN+1];
8620 char str_id_reg[VENDOR_ID_LEN+1];
8621 char str_id_cap[VENDOR_ID_LEN+1];
8622 u8 len;
8623
8624 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8625 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8626
8627 if (cnt < BNX2X_VPD_LEN)
8628 goto out_not_found;
8629
8630 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8631 PCI_VPD_LRDT_RO_DATA);
8632 if (i < 0)
8633 goto out_not_found;
8634
8635
8636 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8637 pci_vpd_lrdt_size(&vpd_data[i]);
8638
8639 i += PCI_VPD_LRDT_TAG_SIZE;
8640
8641 if (block_end > BNX2X_VPD_LEN)
8642 goto out_not_found;
8643
8644 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8645 PCI_VPD_RO_KEYWORD_MFR_ID);
8646 if (rodi < 0)
8647 goto out_not_found;
8648
8649 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8650
8651 if (len != VENDOR_ID_LEN)
8652 goto out_not_found;
8653
8654 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8655
8656 /* vendor specific info */
8657 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8658 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8659 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8660 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8661
8662 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8663 PCI_VPD_RO_KEYWORD_VENDOR0);
8664 if (rodi >= 0) {
8665 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8666
8667 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8668
8669 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8670 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8671 bp->fw_ver[len] = ' ';
8672 }
8673 }
8674 return;
8675 }
8676 out_not_found:
8677 return;
8678 }
8679
8680 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8681 {
8682 int func;
8683 int timer_interval;
8684 int rc;
8685
8686 /* Disable interrupt handling until HW is initialized */
8687 atomic_set(&bp->intr_sem, 1);
8688 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
8689
8690 mutex_init(&bp->port.phy_mutex);
8691 mutex_init(&bp->fw_mb_mutex);
8692 spin_lock_init(&bp->stats_lock);
8693 #ifdef BCM_CNIC
8694 mutex_init(&bp->cnic_mutex);
8695 #endif
8696
8697 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
8698 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
8699
8700 rc = bnx2x_get_hwinfo(bp);
8701
8702 if (!rc)
8703 rc = bnx2x_alloc_mem_bp(bp);
8704
8705 bnx2x_read_fwinfo(bp);
8706
8707 func = BP_FUNC(bp);
8708
8709 /* need to reset chip if undi was active */
8710 if (!BP_NOMCP(bp))
8711 bnx2x_undi_unload(bp);
8712
8713 if (CHIP_REV_IS_FPGA(bp))
8714 dev_err(&bp->pdev->dev, "FPGA detected\n");
8715
8716 if (BP_NOMCP(bp) && (func == 0))
8717 dev_err(&bp->pdev->dev, "MCP disabled, "
8718 "must load devices in order!\n");
8719
8720 bp->multi_mode = multi_mode;
8721 bp->int_mode = int_mode;
8722
8723 /* Set TPA flags */
8724 if (disable_tpa) {
8725 bp->flags &= ~TPA_ENABLE_FLAG;
8726 bp->dev->features &= ~NETIF_F_LRO;
8727 } else {
8728 bp->flags |= TPA_ENABLE_FLAG;
8729 bp->dev->features |= NETIF_F_LRO;
8730 }
8731 bp->disable_tpa = disable_tpa;
8732
8733 if (CHIP_IS_E1(bp))
8734 bp->dropless_fc = 0;
8735 else
8736 bp->dropless_fc = dropless_fc;
8737
8738 bp->mrrs = mrrs;
8739
8740 bp->tx_ring_size = MAX_TX_AVAIL;
8741
8742 /* make sure that the numbers are in the right granularity */
8743 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8744 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
8745
8746 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8747 bp->current_interval = (poll ? poll : timer_interval);
8748
8749 init_timer(&bp->timer);
8750 bp->timer.expires = jiffies + bp->current_interval;
8751 bp->timer.data = (unsigned long) bp;
8752 bp->timer.function = bnx2x_timer;
8753
8754 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
8755 bnx2x_dcbx_init_params(bp);
8756
8757 return rc;
8758 }
8759
8760
8761 /****************************************************************************
8762 * General service functions
8763 ****************************************************************************/
8764
8765 /* called with rtnl_lock */
8766 static int bnx2x_open(struct net_device *dev)
8767 {
8768 struct bnx2x *bp = netdev_priv(dev);
8769
8770 netif_carrier_off(dev);
8771
8772 bnx2x_set_power_state(bp, PCI_D0);
8773
8774 if (!bnx2x_reset_is_done(bp)) {
8775 do {
8776 /* Reset MCP mail box sequence if there is on going
8777 * recovery
8778 */
8779 bp->fw_seq = 0;
8780
8781 /* If it's the first function to load and reset done
8782 * is still not cleared it may mean that. We don't
8783 * check the attention state here because it may have
8784 * already been cleared by a "common" reset but we
8785 * shell proceed with "process kill" anyway.
8786 */
8787 if ((bnx2x_get_load_cnt(bp) == 0) &&
8788 bnx2x_trylock_hw_lock(bp,
8789 HW_LOCK_RESOURCE_RESERVED_08) &&
8790 (!bnx2x_leader_reset(bp))) {
8791 DP(NETIF_MSG_HW, "Recovered in open\n");
8792 break;
8793 }
8794
8795 bnx2x_set_power_state(bp, PCI_D3hot);
8796
8797 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8798 " completed yet. Try again later. If u still see this"
8799 " message after a few retries then power cycle is"
8800 " required.\n", bp->dev->name);
8801
8802 return -EAGAIN;
8803 } while (0);
8804 }
8805
8806 bp->recovery_state = BNX2X_RECOVERY_DONE;
8807
8808 return bnx2x_nic_load(bp, LOAD_OPEN);
8809 }
8810
8811 /* called with rtnl_lock */
8812 static int bnx2x_close(struct net_device *dev)
8813 {
8814 struct bnx2x *bp = netdev_priv(dev);
8815
8816 /* Unload the driver, release IRQs */
8817 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
8818 bnx2x_set_power_state(bp, PCI_D3hot);
8819
8820 return 0;
8821 }
8822
8823 #define E1_MAX_UC_LIST 29
8824 #define E1H_MAX_UC_LIST 30
8825 #define E2_MAX_UC_LIST 14
8826 static inline u8 bnx2x_max_uc_list(struct bnx2x *bp)
8827 {
8828 if (CHIP_IS_E1(bp))
8829 return E1_MAX_UC_LIST;
8830 else if (CHIP_IS_E1H(bp))
8831 return E1H_MAX_UC_LIST;
8832 else
8833 return E2_MAX_UC_LIST;
8834 }
8835
8836
8837 static inline u8 bnx2x_uc_list_cam_offset(struct bnx2x *bp)
8838 {
8839 if (CHIP_IS_E1(bp))
8840 /* CAM Entries for Port0:
8841 * 0 - prim ETH MAC
8842 * 1 - BCAST MAC
8843 * 2 - iSCSI L2 ring ETH MAC
8844 * 3-31 - UC MACs
8845 *
8846 * Port1 entries are allocated the same way starting from
8847 * entry 32.
8848 */
8849 return 3 + 32 * BP_PORT(bp);
8850 else if (CHIP_IS_E1H(bp)) {
8851 /* CAM Entries:
8852 * 0-7 - prim ETH MAC for each function
8853 * 8-15 - iSCSI L2 ring ETH MAC for each function
8854 * 16 till 255 UC MAC lists for each function
8855 *
8856 * Remark: There is no FCoE support for E1H, thus FCoE related
8857 * MACs are not considered.
8858 */
8859 return E1H_FUNC_MAX * (CAM_ISCSI_ETH_LINE + 1) +
8860 bnx2x_max_uc_list(bp) * BP_FUNC(bp);
8861 } else {
8862 /* CAM Entries (there is a separate CAM per engine):
8863 * 0-4 - prim ETH MAC for each function
8864 * 4-7 - iSCSI L2 ring ETH MAC for each function
8865 * 8-11 - FIP ucast L2 MAC for each function
8866 * 12-15 - ALL_ENODE_MACS mcast MAC for each function
8867 * 16 till 71 UC MAC lists for each function
8868 */
8869 u8 func_idx =
8870 (CHIP_MODE_IS_4_PORT(bp) ? BP_FUNC(bp) : BP_VN(bp));
8871
8872 return E2_FUNC_MAX * (CAM_MAX_PF_LINE + 1) +
8873 bnx2x_max_uc_list(bp) * func_idx;
8874 }
8875 }
8876
8877 /* set uc list, do not wait as wait implies sleep and
8878 * set_rx_mode can be invoked from non-sleepable context.
8879 *
8880 * Instead we use the same ramrod data buffer each time we need
8881 * to configure a list of addresses, and use the fact that the
8882 * list of MACs is changed in an incremental way and that the
8883 * function is called under the netif_addr_lock. A temporary
8884 * inconsistent CAM configuration (possible in case of very fast
8885 * sequence of add/del/add on the host side) will shortly be
8886 * restored by the handler of the last ramrod.
8887 */
8888 static int bnx2x_set_uc_list(struct bnx2x *bp)
8889 {
8890 int i = 0, old;
8891 struct net_device *dev = bp->dev;
8892 u8 offset = bnx2x_uc_list_cam_offset(bp);
8893 struct netdev_hw_addr *ha;
8894 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8895 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8896
8897 if (netdev_uc_count(dev) > bnx2x_max_uc_list(bp))
8898 return -EINVAL;
8899
8900 netdev_for_each_uc_addr(ha, dev) {
8901 /* copy mac */
8902 config_cmd->config_table[i].msb_mac_addr =
8903 swab16(*(u16 *)&bnx2x_uc_addr(ha)[0]);
8904 config_cmd->config_table[i].middle_mac_addr =
8905 swab16(*(u16 *)&bnx2x_uc_addr(ha)[2]);
8906 config_cmd->config_table[i].lsb_mac_addr =
8907 swab16(*(u16 *)&bnx2x_uc_addr(ha)[4]);
8908
8909 config_cmd->config_table[i].vlan_id = 0;
8910 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
8911 config_cmd->config_table[i].clients_bit_vector =
8912 cpu_to_le32(1 << BP_L_ID(bp));
8913
8914 SET_FLAG(config_cmd->config_table[i].flags,
8915 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8916 T_ETH_MAC_COMMAND_SET);
8917
8918 DP(NETIF_MSG_IFUP,
8919 "setting UCAST[%d] (%04x:%04x:%04x)\n", i,
8920 config_cmd->config_table[i].msb_mac_addr,
8921 config_cmd->config_table[i].middle_mac_addr,
8922 config_cmd->config_table[i].lsb_mac_addr);
8923
8924 i++;
8925
8926 /* Set uc MAC in NIG */
8927 bnx2x_set_mac_in_nig(bp, 1, bnx2x_uc_addr(ha),
8928 LLH_CAM_ETH_LINE + i);
8929 }
8930 old = config_cmd->hdr.length;
8931 if (old > i) {
8932 for (; i < old; i++) {
8933 if (CAM_IS_INVALID(config_cmd->
8934 config_table[i])) {
8935 /* already invalidated */
8936 break;
8937 }
8938 /* invalidate */
8939 SET_FLAG(config_cmd->config_table[i].flags,
8940 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8941 T_ETH_MAC_COMMAND_INVALIDATE);
8942 }
8943 }
8944
8945 wmb();
8946
8947 config_cmd->hdr.length = i;
8948 config_cmd->hdr.offset = offset;
8949 config_cmd->hdr.client_id = 0xff;
8950 /* Mark that this ramrod doesn't use bp->set_mac_pending for
8951 * synchronization.
8952 */
8953 config_cmd->hdr.echo = 0;
8954
8955 mb();
8956
8957 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8958 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8959
8960 }
8961
8962 void bnx2x_invalidate_uc_list(struct bnx2x *bp)
8963 {
8964 int i;
8965 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8966 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8967 int ramrod_flags = WAIT_RAMROD_COMMON;
8968 u8 offset = bnx2x_uc_list_cam_offset(bp);
8969 u8 max_list_size = bnx2x_max_uc_list(bp);
8970
8971 for (i = 0; i < max_list_size; i++) {
8972 SET_FLAG(config_cmd->config_table[i].flags,
8973 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8974 T_ETH_MAC_COMMAND_INVALIDATE);
8975 bnx2x_set_mac_in_nig(bp, 0, NULL, LLH_CAM_ETH_LINE + 1 + i);
8976 }
8977
8978 wmb();
8979
8980 config_cmd->hdr.length = max_list_size;
8981 config_cmd->hdr.offset = offset;
8982 config_cmd->hdr.client_id = 0xff;
8983 /* We'll wait for a completion this time... */
8984 config_cmd->hdr.echo = 1;
8985
8986 bp->set_mac_pending = 1;
8987
8988 mb();
8989
8990 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8991 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8992
8993 /* Wait for a completion */
8994 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
8995 ramrod_flags);
8996
8997 }
8998
8999 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9000 {
9001 /* some multicasts */
9002 if (CHIP_IS_E1(bp)) {
9003 return bnx2x_set_e1_mc_list(bp);
9004 } else { /* E1H and newer */
9005 return bnx2x_set_e1h_mc_list(bp);
9006 }
9007 }
9008
9009 /* called with netif_tx_lock from dev_mcast.c */
9010 void bnx2x_set_rx_mode(struct net_device *dev)
9011 {
9012 struct bnx2x *bp = netdev_priv(dev);
9013 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9014
9015 if (bp->state != BNX2X_STATE_OPEN) {
9016 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9017 return;
9018 }
9019
9020 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
9021
9022 if (dev->flags & IFF_PROMISC)
9023 rx_mode = BNX2X_RX_MODE_PROMISC;
9024 else if (dev->flags & IFF_ALLMULTI)
9025 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9026 else {
9027 /* some multicasts */
9028 if (bnx2x_set_mc_list(bp))
9029 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9030
9031 /* some unicasts */
9032 if (bnx2x_set_uc_list(bp))
9033 rx_mode = BNX2X_RX_MODE_PROMISC;
9034 }
9035
9036 bp->rx_mode = rx_mode;
9037 bnx2x_set_storm_rx_mode(bp);
9038 }
9039
9040 /* called with rtnl_lock */
9041 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9042 int devad, u16 addr)
9043 {
9044 struct bnx2x *bp = netdev_priv(netdev);
9045 u16 value;
9046 int rc;
9047
9048 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9049 prtad, devad, addr);
9050
9051 /* The HW expects different devad if CL22 is used */
9052 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9053
9054 bnx2x_acquire_phy_lock(bp);
9055 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
9056 bnx2x_release_phy_lock(bp);
9057 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
9058
9059 if (!rc)
9060 rc = value;
9061 return rc;
9062 }
9063
9064 /* called with rtnl_lock */
9065 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9066 u16 addr, u16 value)
9067 {
9068 struct bnx2x *bp = netdev_priv(netdev);
9069 int rc;
9070
9071 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9072 " value 0x%x\n", prtad, devad, addr, value);
9073
9074 /* The HW expects different devad if CL22 is used */
9075 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9076
9077 bnx2x_acquire_phy_lock(bp);
9078 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
9079 bnx2x_release_phy_lock(bp);
9080 return rc;
9081 }
9082
9083 /* called with rtnl_lock */
9084 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9085 {
9086 struct bnx2x *bp = netdev_priv(dev);
9087 struct mii_ioctl_data *mdio = if_mii(ifr);
9088
9089 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9090 mdio->phy_id, mdio->reg_num, mdio->val_in);
9091
9092 if (!netif_running(dev))
9093 return -EAGAIN;
9094
9095 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
9096 }
9097
9098 #ifdef CONFIG_NET_POLL_CONTROLLER
9099 static void poll_bnx2x(struct net_device *dev)
9100 {
9101 struct bnx2x *bp = netdev_priv(dev);
9102
9103 disable_irq(bp->pdev->irq);
9104 bnx2x_interrupt(bp->pdev->irq, dev);
9105 enable_irq(bp->pdev->irq);
9106 }
9107 #endif
9108
9109 static const struct net_device_ops bnx2x_netdev_ops = {
9110 .ndo_open = bnx2x_open,
9111 .ndo_stop = bnx2x_close,
9112 .ndo_start_xmit = bnx2x_start_xmit,
9113 .ndo_select_queue = bnx2x_select_queue,
9114 .ndo_set_rx_mode = bnx2x_set_rx_mode,
9115 .ndo_set_mac_address = bnx2x_change_mac_addr,
9116 .ndo_validate_addr = eth_validate_addr,
9117 .ndo_do_ioctl = bnx2x_ioctl,
9118 .ndo_change_mtu = bnx2x_change_mtu,
9119 .ndo_fix_features = bnx2x_fix_features,
9120 .ndo_set_features = bnx2x_set_features,
9121 .ndo_tx_timeout = bnx2x_tx_timeout,
9122 #ifdef CONFIG_NET_POLL_CONTROLLER
9123 .ndo_poll_controller = poll_bnx2x,
9124 #endif
9125 };
9126
9127 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9128 struct net_device *dev)
9129 {
9130 struct bnx2x *bp;
9131 int rc;
9132
9133 SET_NETDEV_DEV(dev, &pdev->dev);
9134 bp = netdev_priv(dev);
9135
9136 bp->dev = dev;
9137 bp->pdev = pdev;
9138 bp->flags = 0;
9139 bp->pf_num = PCI_FUNC(pdev->devfn);
9140
9141 rc = pci_enable_device(pdev);
9142 if (rc) {
9143 dev_err(&bp->pdev->dev,
9144 "Cannot enable PCI device, aborting\n");
9145 goto err_out;
9146 }
9147
9148 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9149 dev_err(&bp->pdev->dev,
9150 "Cannot find PCI device base address, aborting\n");
9151 rc = -ENODEV;
9152 goto err_out_disable;
9153 }
9154
9155 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9156 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9157 " base address, aborting\n");
9158 rc = -ENODEV;
9159 goto err_out_disable;
9160 }
9161
9162 if (atomic_read(&pdev->enable_cnt) == 1) {
9163 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9164 if (rc) {
9165 dev_err(&bp->pdev->dev,
9166 "Cannot obtain PCI resources, aborting\n");
9167 goto err_out_disable;
9168 }
9169
9170 pci_set_master(pdev);
9171 pci_save_state(pdev);
9172 }
9173
9174 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9175 if (bp->pm_cap == 0) {
9176 dev_err(&bp->pdev->dev,
9177 "Cannot find power management capability, aborting\n");
9178 rc = -EIO;
9179 goto err_out_release;
9180 }
9181
9182 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9183 if (bp->pcie_cap == 0) {
9184 dev_err(&bp->pdev->dev,
9185 "Cannot find PCI Express capability, aborting\n");
9186 rc = -EIO;
9187 goto err_out_release;
9188 }
9189
9190 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
9191 bp->flags |= USING_DAC_FLAG;
9192 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
9193 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9194 " failed, aborting\n");
9195 rc = -EIO;
9196 goto err_out_release;
9197 }
9198
9199 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9200 dev_err(&bp->pdev->dev,
9201 "System does not support DMA, aborting\n");
9202 rc = -EIO;
9203 goto err_out_release;
9204 }
9205
9206 dev->mem_start = pci_resource_start(pdev, 0);
9207 dev->base_addr = dev->mem_start;
9208 dev->mem_end = pci_resource_end(pdev, 0);
9209
9210 dev->irq = pdev->irq;
9211
9212 bp->regview = pci_ioremap_bar(pdev, 0);
9213 if (!bp->regview) {
9214 dev_err(&bp->pdev->dev,
9215 "Cannot map register space, aborting\n");
9216 rc = -ENOMEM;
9217 goto err_out_release;
9218 }
9219
9220 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9221 min_t(u64, BNX2X_DB_SIZE(bp),
9222 pci_resource_len(pdev, 2)));
9223 if (!bp->doorbells) {
9224 dev_err(&bp->pdev->dev,
9225 "Cannot map doorbell space, aborting\n");
9226 rc = -ENOMEM;
9227 goto err_out_unmap;
9228 }
9229
9230 bnx2x_set_power_state(bp, PCI_D0);
9231
9232 /* clean indirect addresses */
9233 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9234 PCICFG_VENDOR_ID_OFFSET);
9235 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9236 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9237 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9238 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9239
9240 /* Reset the load counter */
9241 bnx2x_clear_load_cnt(bp);
9242
9243 dev->watchdog_timeo = TX_TIMEOUT;
9244
9245 dev->netdev_ops = &bnx2x_netdev_ops;
9246 bnx2x_set_ethtool_ops(dev);
9247
9248 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9249 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9250 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9251
9252 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9253 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9254
9255 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
9256 if (bp->flags & USING_DAC_FLAG)
9257 dev->features |= NETIF_F_HIGHDMA;
9258
9259 /* Add Loopback capability to the device */
9260 dev->hw_features |= NETIF_F_LOOPBACK;
9261
9262 #ifdef BCM_DCBNL
9263 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9264 #endif
9265
9266 /* get_port_hwinfo() will set prtad and mmds properly */
9267 bp->mdio.prtad = MDIO_PRTAD_NONE;
9268 bp->mdio.mmds = 0;
9269 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9270 bp->mdio.dev = dev;
9271 bp->mdio.mdio_read = bnx2x_mdio_read;
9272 bp->mdio.mdio_write = bnx2x_mdio_write;
9273
9274 return 0;
9275
9276 err_out_unmap:
9277 if (bp->regview) {
9278 iounmap(bp->regview);
9279 bp->regview = NULL;
9280 }
9281 if (bp->doorbells) {
9282 iounmap(bp->doorbells);
9283 bp->doorbells = NULL;
9284 }
9285
9286 err_out_release:
9287 if (atomic_read(&pdev->enable_cnt) == 1)
9288 pci_release_regions(pdev);
9289
9290 err_out_disable:
9291 pci_disable_device(pdev);
9292 pci_set_drvdata(pdev, NULL);
9293
9294 err_out:
9295 return rc;
9296 }
9297
9298 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9299 int *width, int *speed)
9300 {
9301 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9302
9303 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9304
9305 /* return value of 1=2.5GHz 2=5GHz */
9306 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9307 }
9308
9309 static int bnx2x_check_firmware(struct bnx2x *bp)
9310 {
9311 const struct firmware *firmware = bp->firmware;
9312 struct bnx2x_fw_file_hdr *fw_hdr;
9313 struct bnx2x_fw_file_section *sections;
9314 u32 offset, len, num_ops;
9315 u16 *ops_offsets;
9316 int i;
9317 const u8 *fw_ver;
9318
9319 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9320 return -EINVAL;
9321
9322 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9323 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9324
9325 /* Make sure none of the offsets and sizes make us read beyond
9326 * the end of the firmware data */
9327 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9328 offset = be32_to_cpu(sections[i].offset);
9329 len = be32_to_cpu(sections[i].len);
9330 if (offset + len > firmware->size) {
9331 dev_err(&bp->pdev->dev,
9332 "Section %d length is out of bounds\n", i);
9333 return -EINVAL;
9334 }
9335 }
9336
9337 /* Likewise for the init_ops offsets */
9338 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9339 ops_offsets = (u16 *)(firmware->data + offset);
9340 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9341
9342 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9343 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9344 dev_err(&bp->pdev->dev,
9345 "Section offset %d is out of bounds\n", i);
9346 return -EINVAL;
9347 }
9348 }
9349
9350 /* Check FW version */
9351 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9352 fw_ver = firmware->data + offset;
9353 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9354 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9355 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9356 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9357 dev_err(&bp->pdev->dev,
9358 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9359 fw_ver[0], fw_ver[1], fw_ver[2],
9360 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9361 BCM_5710_FW_MINOR_VERSION,
9362 BCM_5710_FW_REVISION_VERSION,
9363 BCM_5710_FW_ENGINEERING_VERSION);
9364 return -EINVAL;
9365 }
9366
9367 return 0;
9368 }
9369
9370 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9371 {
9372 const __be32 *source = (const __be32 *)_source;
9373 u32 *target = (u32 *)_target;
9374 u32 i;
9375
9376 for (i = 0; i < n/4; i++)
9377 target[i] = be32_to_cpu(source[i]);
9378 }
9379
9380 /*
9381 Ops array is stored in the following format:
9382 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9383 */
9384 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9385 {
9386 const __be32 *source = (const __be32 *)_source;
9387 struct raw_op *target = (struct raw_op *)_target;
9388 u32 i, j, tmp;
9389
9390 for (i = 0, j = 0; i < n/8; i++, j += 2) {
9391 tmp = be32_to_cpu(source[j]);
9392 target[i].op = (tmp >> 24) & 0xff;
9393 target[i].offset = tmp & 0xffffff;
9394 target[i].raw_data = be32_to_cpu(source[j + 1]);
9395 }
9396 }
9397
9398 /**
9399 * IRO array is stored in the following format:
9400 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9401 */
9402 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9403 {
9404 const __be32 *source = (const __be32 *)_source;
9405 struct iro *target = (struct iro *)_target;
9406 u32 i, j, tmp;
9407
9408 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9409 target[i].base = be32_to_cpu(source[j]);
9410 j++;
9411 tmp = be32_to_cpu(source[j]);
9412 target[i].m1 = (tmp >> 16) & 0xffff;
9413 target[i].m2 = tmp & 0xffff;
9414 j++;
9415 tmp = be32_to_cpu(source[j]);
9416 target[i].m3 = (tmp >> 16) & 0xffff;
9417 target[i].size = tmp & 0xffff;
9418 j++;
9419 }
9420 }
9421
9422 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9423 {
9424 const __be16 *source = (const __be16 *)_source;
9425 u16 *target = (u16 *)_target;
9426 u32 i;
9427
9428 for (i = 0; i < n/2; i++)
9429 target[i] = be16_to_cpu(source[i]);
9430 }
9431
9432 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9433 do { \
9434 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9435 bp->arr = kmalloc(len, GFP_KERNEL); \
9436 if (!bp->arr) { \
9437 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9438 goto lbl; \
9439 } \
9440 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9441 (u8 *)bp->arr, len); \
9442 } while (0)
9443
9444 int bnx2x_init_firmware(struct bnx2x *bp)
9445 {
9446 const char *fw_file_name;
9447 struct bnx2x_fw_file_hdr *fw_hdr;
9448 int rc;
9449
9450 if (CHIP_IS_E1(bp))
9451 fw_file_name = FW_FILE_NAME_E1;
9452 else if (CHIP_IS_E1H(bp))
9453 fw_file_name = FW_FILE_NAME_E1H;
9454 else if (CHIP_IS_E2(bp))
9455 fw_file_name = FW_FILE_NAME_E2;
9456 else {
9457 BNX2X_ERR("Unsupported chip revision\n");
9458 return -EINVAL;
9459 }
9460
9461 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9462
9463 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9464 if (rc) {
9465 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9466 goto request_firmware_exit;
9467 }
9468
9469 rc = bnx2x_check_firmware(bp);
9470 if (rc) {
9471 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9472 goto request_firmware_exit;
9473 }
9474
9475 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9476
9477 /* Initialize the pointers to the init arrays */
9478 /* Blob */
9479 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9480
9481 /* Opcodes */
9482 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9483
9484 /* Offsets */
9485 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9486 be16_to_cpu_n);
9487
9488 /* STORMs firmware */
9489 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9490 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9491 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9492 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9493 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9494 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9495 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9496 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9497 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9498 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9499 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9500 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9501 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9502 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9503 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9504 be32_to_cpu(fw_hdr->csem_pram_data.offset);
9505 /* IRO */
9506 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
9507
9508 return 0;
9509
9510 iro_alloc_err:
9511 kfree(bp->init_ops_offsets);
9512 init_offsets_alloc_err:
9513 kfree(bp->init_ops);
9514 init_ops_alloc_err:
9515 kfree(bp->init_data);
9516 request_firmware_exit:
9517 release_firmware(bp->firmware);
9518
9519 return rc;
9520 }
9521
9522 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9523 {
9524 int cid_count = L2_FP_COUNT(l2_cid_count);
9525
9526 #ifdef BCM_CNIC
9527 cid_count += CNIC_CID_MAX;
9528 #endif
9529 return roundup(cid_count, QM_CID_ROUND);
9530 }
9531
9532 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9533 const struct pci_device_id *ent)
9534 {
9535 struct net_device *dev = NULL;
9536 struct bnx2x *bp;
9537 int pcie_width, pcie_speed;
9538 int rc, cid_count;
9539
9540 switch (ent->driver_data) {
9541 case BCM57710:
9542 case BCM57711:
9543 case BCM57711E:
9544 cid_count = FP_SB_MAX_E1x;
9545 break;
9546
9547 case BCM57712:
9548 case BCM57712E:
9549 cid_count = FP_SB_MAX_E2;
9550 break;
9551
9552 default:
9553 pr_err("Unknown board_type (%ld), aborting\n",
9554 ent->driver_data);
9555 return -ENODEV;
9556 }
9557
9558 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
9559
9560 /* dev zeroed in init_etherdev */
9561 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
9562 if (!dev) {
9563 dev_err(&pdev->dev, "Cannot allocate net device\n");
9564 return -ENOMEM;
9565 }
9566
9567 bp = netdev_priv(dev);
9568 bp->msg_enable = debug;
9569
9570 pci_set_drvdata(pdev, dev);
9571
9572 bp->l2_cid_count = cid_count;
9573
9574 rc = bnx2x_init_dev(pdev, dev);
9575 if (rc < 0) {
9576 free_netdev(dev);
9577 return rc;
9578 }
9579
9580 rc = bnx2x_init_bp(bp);
9581 if (rc)
9582 goto init_one_exit;
9583
9584 /* calc qm_cid_count */
9585 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9586
9587 #ifdef BCM_CNIC
9588 /* disable FCOE L2 queue for E1x*/
9589 if (CHIP_IS_E1x(bp))
9590 bp->flags |= NO_FCOE_FLAG;
9591
9592 #endif
9593
9594 /* Configure interrupt mode: try to enable MSI-X/MSI if
9595 * needed, set bp->num_queues appropriately.
9596 */
9597 bnx2x_set_int_mode(bp);
9598
9599 /* Add all NAPI objects */
9600 bnx2x_add_all_napi(bp);
9601
9602 rc = register_netdev(dev);
9603 if (rc) {
9604 dev_err(&pdev->dev, "Cannot register net device\n");
9605 goto init_one_exit;
9606 }
9607
9608 #ifdef BCM_CNIC
9609 if (!NO_FCOE(bp)) {
9610 /* Add storage MAC address */
9611 rtnl_lock();
9612 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9613 rtnl_unlock();
9614 }
9615 #endif
9616
9617 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
9618
9619 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9620 " IRQ %d, ", board_info[ent->driver_data].name,
9621 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
9622 pcie_width,
9623 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9624 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9625 "5GHz (Gen2)" : "2.5GHz",
9626 dev->base_addr, bp->pdev->irq);
9627 pr_cont("node addr %pM\n", dev->dev_addr);
9628
9629 return 0;
9630
9631 init_one_exit:
9632 if (bp->regview)
9633 iounmap(bp->regview);
9634
9635 if (bp->doorbells)
9636 iounmap(bp->doorbells);
9637
9638 free_netdev(dev);
9639
9640 if (atomic_read(&pdev->enable_cnt) == 1)
9641 pci_release_regions(pdev);
9642
9643 pci_disable_device(pdev);
9644 pci_set_drvdata(pdev, NULL);
9645
9646 return rc;
9647 }
9648
9649 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9650 {
9651 struct net_device *dev = pci_get_drvdata(pdev);
9652 struct bnx2x *bp;
9653
9654 if (!dev) {
9655 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
9656 return;
9657 }
9658 bp = netdev_priv(dev);
9659
9660 #ifdef BCM_CNIC
9661 /* Delete storage MAC address */
9662 if (!NO_FCOE(bp)) {
9663 rtnl_lock();
9664 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9665 rtnl_unlock();
9666 }
9667 #endif
9668
9669 #ifdef BCM_DCBNL
9670 /* Delete app tlvs from dcbnl */
9671 bnx2x_dcbnl_update_applist(bp, true);
9672 #endif
9673
9674 unregister_netdev(dev);
9675
9676 /* Delete all NAPI objects */
9677 bnx2x_del_all_napi(bp);
9678
9679 /* Power on: we can't let PCI layer write to us while we are in D3 */
9680 bnx2x_set_power_state(bp, PCI_D0);
9681
9682 /* Disable MSI/MSI-X */
9683 bnx2x_disable_msi(bp);
9684
9685 /* Power off */
9686 bnx2x_set_power_state(bp, PCI_D3hot);
9687
9688 /* Make sure RESET task is not scheduled before continuing */
9689 cancel_delayed_work_sync(&bp->reset_task);
9690
9691 if (bp->regview)
9692 iounmap(bp->regview);
9693
9694 if (bp->doorbells)
9695 iounmap(bp->doorbells);
9696
9697 bnx2x_free_mem_bp(bp);
9698
9699 free_netdev(dev);
9700
9701 if (atomic_read(&pdev->enable_cnt) == 1)
9702 pci_release_regions(pdev);
9703
9704 pci_disable_device(pdev);
9705 pci_set_drvdata(pdev, NULL);
9706 }
9707
9708 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9709 {
9710 int i;
9711
9712 bp->state = BNX2X_STATE_ERROR;
9713
9714 bp->rx_mode = BNX2X_RX_MODE_NONE;
9715
9716 bnx2x_netif_stop(bp, 0);
9717 netif_carrier_off(bp->dev);
9718
9719 del_timer_sync(&bp->timer);
9720 bp->stats_state = STATS_STATE_DISABLED;
9721 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9722
9723 /* Release IRQs */
9724 bnx2x_free_irq(bp);
9725
9726 /* Free SKBs, SGEs, TPA pool and driver internals */
9727 bnx2x_free_skbs(bp);
9728
9729 for_each_rx_queue(bp, i)
9730 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
9731
9732 bnx2x_free_mem(bp);
9733
9734 bp->state = BNX2X_STATE_CLOSED;
9735
9736 return 0;
9737 }
9738
9739 static void bnx2x_eeh_recover(struct bnx2x *bp)
9740 {
9741 u32 val;
9742
9743 mutex_init(&bp->port.phy_mutex);
9744
9745 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9746 bp->link_params.shmem_base = bp->common.shmem_base;
9747 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9748
9749 if (!bp->common.shmem_base ||
9750 (bp->common.shmem_base < 0xA0000) ||
9751 (bp->common.shmem_base >= 0xC0000)) {
9752 BNX2X_DEV_INFO("MCP not active\n");
9753 bp->flags |= NO_MCP_FLAG;
9754 return;
9755 }
9756
9757 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9758 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9759 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9760 BNX2X_ERR("BAD MCP validity signature\n");
9761
9762 if (!BP_NOMCP(bp)) {
9763 bp->fw_seq =
9764 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9765 DRV_MSG_SEQ_NUMBER_MASK);
9766 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9767 }
9768 }
9769
9770 /**
9771 * bnx2x_io_error_detected - called when PCI error is detected
9772 * @pdev: Pointer to PCI device
9773 * @state: The current pci connection state
9774 *
9775 * This function is called after a PCI bus error affecting
9776 * this device has been detected.
9777 */
9778 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9779 pci_channel_state_t state)
9780 {
9781 struct net_device *dev = pci_get_drvdata(pdev);
9782 struct bnx2x *bp = netdev_priv(dev);
9783
9784 rtnl_lock();
9785
9786 netif_device_detach(dev);
9787
9788 if (state == pci_channel_io_perm_failure) {
9789 rtnl_unlock();
9790 return PCI_ERS_RESULT_DISCONNECT;
9791 }
9792
9793 if (netif_running(dev))
9794 bnx2x_eeh_nic_unload(bp);
9795
9796 pci_disable_device(pdev);
9797
9798 rtnl_unlock();
9799
9800 /* Request a slot reset */
9801 return PCI_ERS_RESULT_NEED_RESET;
9802 }
9803
9804 /**
9805 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9806 * @pdev: Pointer to PCI device
9807 *
9808 * Restart the card from scratch, as if from a cold-boot.
9809 */
9810 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9811 {
9812 struct net_device *dev = pci_get_drvdata(pdev);
9813 struct bnx2x *bp = netdev_priv(dev);
9814
9815 rtnl_lock();
9816
9817 if (pci_enable_device(pdev)) {
9818 dev_err(&pdev->dev,
9819 "Cannot re-enable PCI device after reset\n");
9820 rtnl_unlock();
9821 return PCI_ERS_RESULT_DISCONNECT;
9822 }
9823
9824 pci_set_master(pdev);
9825 pci_restore_state(pdev);
9826
9827 if (netif_running(dev))
9828 bnx2x_set_power_state(bp, PCI_D0);
9829
9830 rtnl_unlock();
9831
9832 return PCI_ERS_RESULT_RECOVERED;
9833 }
9834
9835 /**
9836 * bnx2x_io_resume - called when traffic can start flowing again
9837 * @pdev: Pointer to PCI device
9838 *
9839 * This callback is called when the error recovery driver tells us that
9840 * its OK to resume normal operation.
9841 */
9842 static void bnx2x_io_resume(struct pci_dev *pdev)
9843 {
9844 struct net_device *dev = pci_get_drvdata(pdev);
9845 struct bnx2x *bp = netdev_priv(dev);
9846
9847 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9848 printk(KERN_ERR "Handling parity error recovery. "
9849 "Try again later\n");
9850 return;
9851 }
9852
9853 rtnl_lock();
9854
9855 bnx2x_eeh_recover(bp);
9856
9857 if (netif_running(dev))
9858 bnx2x_nic_load(bp, LOAD_NORMAL);
9859
9860 netif_device_attach(dev);
9861
9862 rtnl_unlock();
9863 }
9864
9865 static struct pci_error_handlers bnx2x_err_handler = {
9866 .error_detected = bnx2x_io_error_detected,
9867 .slot_reset = bnx2x_io_slot_reset,
9868 .resume = bnx2x_io_resume,
9869 };
9870
9871 static struct pci_driver bnx2x_pci_driver = {
9872 .name = DRV_MODULE_NAME,
9873 .id_table = bnx2x_pci_tbl,
9874 .probe = bnx2x_init_one,
9875 .remove = __devexit_p(bnx2x_remove_one),
9876 .suspend = bnx2x_suspend,
9877 .resume = bnx2x_resume,
9878 .err_handler = &bnx2x_err_handler,
9879 };
9880
9881 static int __init bnx2x_init(void)
9882 {
9883 int ret;
9884
9885 pr_info("%s", version);
9886
9887 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9888 if (bnx2x_wq == NULL) {
9889 pr_err("Cannot create workqueue\n");
9890 return -ENOMEM;
9891 }
9892
9893 ret = pci_register_driver(&bnx2x_pci_driver);
9894 if (ret) {
9895 pr_err("Cannot register driver\n");
9896 destroy_workqueue(bnx2x_wq);
9897 }
9898 return ret;
9899 }
9900
9901 static void __exit bnx2x_cleanup(void)
9902 {
9903 pci_unregister_driver(&bnx2x_pci_driver);
9904
9905 destroy_workqueue(bnx2x_wq);
9906 }
9907
9908 module_init(bnx2x_init);
9909 module_exit(bnx2x_cleanup);
9910
9911 #ifdef BCM_CNIC
9912
9913 /* count denotes the number of new completions we have seen */
9914 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9915 {
9916 struct eth_spe *spe;
9917
9918 #ifdef BNX2X_STOP_ON_ERROR
9919 if (unlikely(bp->panic))
9920 return;
9921 #endif
9922
9923 spin_lock_bh(&bp->spq_lock);
9924 BUG_ON(bp->cnic_spq_pending < count);
9925 bp->cnic_spq_pending -= count;
9926
9927
9928 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9929 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9930 & SPE_HDR_CONN_TYPE) >>
9931 SPE_HDR_CONN_TYPE_SHIFT;
9932
9933 /* Set validation for iSCSI L2 client before sending SETUP
9934 * ramrod
9935 */
9936 if (type == ETH_CONNECTION_TYPE) {
9937 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9938 hdr.conn_and_cmd_data) >>
9939 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9940
9941 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9942 bnx2x_set_ctx_validation(&bp->context.
9943 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9944 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9945 }
9946
9947 /* There may be not more than 8 L2 and not more than 8 L5 SPEs
9948 * We also check that the number of outstanding
9949 * COMMON ramrods is not more than the EQ and SPQ can
9950 * accommodate.
9951 */
9952 if (type == ETH_CONNECTION_TYPE) {
9953 if (!atomic_read(&bp->cq_spq_left))
9954 break;
9955 else
9956 atomic_dec(&bp->cq_spq_left);
9957 } else if (type == NONE_CONNECTION_TYPE) {
9958 if (!atomic_read(&bp->eq_spq_left))
9959 break;
9960 else
9961 atomic_dec(&bp->eq_spq_left);
9962 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9963 (type == FCOE_CONNECTION_TYPE)) {
9964 if (bp->cnic_spq_pending >=
9965 bp->cnic_eth_dev.max_kwqe_pending)
9966 break;
9967 else
9968 bp->cnic_spq_pending++;
9969 } else {
9970 BNX2X_ERR("Unknown SPE type: %d\n", type);
9971 bnx2x_panic();
9972 break;
9973 }
9974
9975 spe = bnx2x_sp_get_next(bp);
9976 *spe = *bp->cnic_kwq_cons;
9977
9978 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9979 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9980
9981 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9982 bp->cnic_kwq_cons = bp->cnic_kwq;
9983 else
9984 bp->cnic_kwq_cons++;
9985 }
9986 bnx2x_sp_prod_update(bp);
9987 spin_unlock_bh(&bp->spq_lock);
9988 }
9989
9990 static int bnx2x_cnic_sp_queue(struct net_device *dev,
9991 struct kwqe_16 *kwqes[], u32 count)
9992 {
9993 struct bnx2x *bp = netdev_priv(dev);
9994 int i;
9995
9996 #ifdef BNX2X_STOP_ON_ERROR
9997 if (unlikely(bp->panic))
9998 return -EIO;
9999 #endif
10000
10001 spin_lock_bh(&bp->spq_lock);
10002
10003 for (i = 0; i < count; i++) {
10004 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10005
10006 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10007 break;
10008
10009 *bp->cnic_kwq_prod = *spe;
10010
10011 bp->cnic_kwq_pending++;
10012
10013 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10014 spe->hdr.conn_and_cmd_data, spe->hdr.type,
10015 spe->data.update_data_addr.hi,
10016 spe->data.update_data_addr.lo,
10017 bp->cnic_kwq_pending);
10018
10019 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10020 bp->cnic_kwq_prod = bp->cnic_kwq;
10021 else
10022 bp->cnic_kwq_prod++;
10023 }
10024
10025 spin_unlock_bh(&bp->spq_lock);
10026
10027 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10028 bnx2x_cnic_sp_post(bp, 0);
10029
10030 return i;
10031 }
10032
10033 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10034 {
10035 struct cnic_ops *c_ops;
10036 int rc = 0;
10037
10038 mutex_lock(&bp->cnic_mutex);
10039 c_ops = rcu_dereference_protected(bp->cnic_ops,
10040 lockdep_is_held(&bp->cnic_mutex));
10041 if (c_ops)
10042 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10043 mutex_unlock(&bp->cnic_mutex);
10044
10045 return rc;
10046 }
10047
10048 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10049 {
10050 struct cnic_ops *c_ops;
10051 int rc = 0;
10052
10053 rcu_read_lock();
10054 c_ops = rcu_dereference(bp->cnic_ops);
10055 if (c_ops)
10056 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10057 rcu_read_unlock();
10058
10059 return rc;
10060 }
10061
10062 /*
10063 * for commands that have no data
10064 */
10065 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
10066 {
10067 struct cnic_ctl_info ctl = {0};
10068
10069 ctl.cmd = cmd;
10070
10071 return bnx2x_cnic_ctl_send(bp, &ctl);
10072 }
10073
10074 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
10075 {
10076 struct cnic_ctl_info ctl;
10077
10078 /* first we tell CNIC and only then we count this as a completion */
10079 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10080 ctl.data.comp.cid = cid;
10081
10082 bnx2x_cnic_ctl_send_bh(bp, &ctl);
10083 bnx2x_cnic_sp_post(bp, 0);
10084 }
10085
10086 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10087 {
10088 struct bnx2x *bp = netdev_priv(dev);
10089 int rc = 0;
10090
10091 switch (ctl->cmd) {
10092 case DRV_CTL_CTXTBL_WR_CMD: {
10093 u32 index = ctl->data.io.offset;
10094 dma_addr_t addr = ctl->data.io.dma_addr;
10095
10096 bnx2x_ilt_wr(bp, index, addr);
10097 break;
10098 }
10099
10100 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10101 int count = ctl->data.credit.credit_count;
10102
10103 bnx2x_cnic_sp_post(bp, count);
10104 break;
10105 }
10106
10107 /* rtnl_lock is held. */
10108 case DRV_CTL_START_L2_CMD: {
10109 u32 cli = ctl->data.ring.client_id;
10110
10111 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
10112 bnx2x_del_fcoe_eth_macs(bp);
10113
10114 /* Set iSCSI MAC address */
10115 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
10116
10117 mmiowb();
10118 barrier();
10119
10120 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10121 * because it's the only way for UIO Client to accept
10122 * multicasts (in non-promiscuous mode only one Client per
10123 * function will receive multicast packets (leading in our
10124 * case).
10125 */
10126 bnx2x_rxq_set_mac_filters(bp, cli,
10127 BNX2X_ACCEPT_UNICAST |
10128 BNX2X_ACCEPT_BROADCAST |
10129 BNX2X_ACCEPT_ALL_MULTICAST);
10130 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10131
10132 break;
10133 }
10134
10135 /* rtnl_lock is held. */
10136 case DRV_CTL_STOP_L2_CMD: {
10137 u32 cli = ctl->data.ring.client_id;
10138
10139 /* Stop accepting on iSCSI L2 ring */
10140 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10141 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10142
10143 mmiowb();
10144 barrier();
10145
10146 /* Unset iSCSI L2 MAC */
10147 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
10148 break;
10149 }
10150 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10151 int count = ctl->data.credit.credit_count;
10152
10153 smp_mb__before_atomic_inc();
10154 atomic_add(count, &bp->cq_spq_left);
10155 smp_mb__after_atomic_inc();
10156 break;
10157 }
10158
10159 case DRV_CTL_ISCSI_STOPPED_CMD: {
10160 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_ISCSI_STOPPED);
10161 break;
10162 }
10163
10164 default:
10165 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10166 rc = -EINVAL;
10167 }
10168
10169 return rc;
10170 }
10171
10172 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
10173 {
10174 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10175
10176 if (bp->flags & USING_MSIX_FLAG) {
10177 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10178 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10179 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10180 } else {
10181 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10182 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10183 }
10184 if (CHIP_IS_E2(bp))
10185 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10186 else
10187 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10188
10189 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
10190 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
10191 cp->irq_arr[1].status_blk = bp->def_status_blk;
10192 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10193 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10194
10195 cp->num_irq = 2;
10196 }
10197
10198 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10199 void *data)
10200 {
10201 struct bnx2x *bp = netdev_priv(dev);
10202 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10203
10204 if (ops == NULL)
10205 return -EINVAL;
10206
10207 if (atomic_read(&bp->intr_sem) != 0)
10208 return -EBUSY;
10209
10210 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10211 if (!bp->cnic_kwq)
10212 return -ENOMEM;
10213
10214 bp->cnic_kwq_cons = bp->cnic_kwq;
10215 bp->cnic_kwq_prod = bp->cnic_kwq;
10216 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10217
10218 bp->cnic_spq_pending = 0;
10219 bp->cnic_kwq_pending = 0;
10220
10221 bp->cnic_data = data;
10222
10223 cp->num_irq = 0;
10224 cp->drv_state = CNIC_DRV_STATE_REGD;
10225 cp->iro_arr = bp->iro_arr;
10226
10227 bnx2x_setup_cnic_irq_info(bp);
10228
10229 rcu_assign_pointer(bp->cnic_ops, ops);
10230
10231 return 0;
10232 }
10233
10234 static int bnx2x_unregister_cnic(struct net_device *dev)
10235 {
10236 struct bnx2x *bp = netdev_priv(dev);
10237 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10238
10239 mutex_lock(&bp->cnic_mutex);
10240 cp->drv_state = 0;
10241 rcu_assign_pointer(bp->cnic_ops, NULL);
10242 mutex_unlock(&bp->cnic_mutex);
10243 synchronize_rcu();
10244 kfree(bp->cnic_kwq);
10245 bp->cnic_kwq = NULL;
10246
10247 return 0;
10248 }
10249
10250 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10251 {
10252 struct bnx2x *bp = netdev_priv(dev);
10253 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10254
10255 /* If both iSCSI and FCoE are disabled - return NULL in
10256 * order to indicate CNIC that it should not try to work
10257 * with this device.
10258 */
10259 if (NO_ISCSI(bp) && NO_FCOE(bp))
10260 return NULL;
10261
10262 cp->drv_owner = THIS_MODULE;
10263 cp->chip_id = CHIP_ID(bp);
10264 cp->pdev = bp->pdev;
10265 cp->io_base = bp->regview;
10266 cp->io_base2 = bp->doorbells;
10267 cp->max_kwqe_pending = 8;
10268 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10269 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10270 bnx2x_cid_ilt_lines(bp);
10271 cp->ctx_tbl_len = CNIC_ILT_LINES;
10272 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10273 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10274 cp->drv_ctl = bnx2x_drv_ctl;
10275 cp->drv_register_cnic = bnx2x_register_cnic;
10276 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10277 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10278 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10279 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
10280 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10281
10282 if (NO_ISCSI_OOO(bp))
10283 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10284
10285 if (NO_ISCSI(bp))
10286 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10287
10288 if (NO_FCOE(bp))
10289 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10290
10291 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10292 "starting cid %d\n",
10293 cp->ctx_blk_size,
10294 cp->ctx_tbl_offset,
10295 cp->ctx_tbl_len,
10296 cp->starting_cid);
10297 return cp;
10298 }
10299 EXPORT_SYMBOL(bnx2x_cnic_probe);
10300
10301 #endif /* BCM_CNIC */
10302
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