1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
15 /****************************************************************************
16 * Shared HW configuration *
17 ****************************************************************************/
18 struct shared_hw_cfg
{ /* NVRAM Offset */
19 /* Up to 16 bytes of NULL-terminated string */
20 u8 part_num
[16]; /* 0x104 */
22 u32 config
; /* 0x114 */
23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
29 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
31 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
33 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
35 /* Whatever MFW found in NVM
36 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
39 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
40 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
41 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
44 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
47 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
51 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
52 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
53 #define SHARED_HW_CFG_LED_MAC1 0x00000000
54 #define SHARED_HW_CFG_LED_PHY1 0x00010000
55 #define SHARED_HW_CFG_LED_PHY2 0x00020000
56 #define SHARED_HW_CFG_LED_PHY3 0x00030000
57 #define SHARED_HW_CFG_LED_MAC2 0x00040000
58 #define SHARED_HW_CFG_LED_PHY4 0x00050000
59 #define SHARED_HW_CFG_LED_PHY5 0x00060000
60 #define SHARED_HW_CFG_LED_PHY6 0x00070000
61 #define SHARED_HW_CFG_LED_MAC3 0x00080000
62 #define SHARED_HW_CFG_LED_PHY7 0x00090000
63 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
64 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
65 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
66 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
68 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
70 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
71 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
72 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
77 u32 config2
; /* 0x118 */
78 /* one time auto detect grace period (in sec) */
79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
84 /* The default value for the core clock is 250MHz and it is
85 achieved by setting the clock change to 4 */
86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
92 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
94 u32 power_dissipated
; /* 0x11c */
95 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
96 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
98 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
99 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
100 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
101 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
102 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
103 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
105 u32 ump_nc_si_config
; /* 0x120 */
106 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
107 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
108 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
109 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
110 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
111 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
113 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
114 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
116 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
117 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
118 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
119 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
121 u32 board
; /* 0x124 */
122 #define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff
123 #define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0
124 #define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000
125 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001
126 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002
127 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003
128 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004
129 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005
130 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
131 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
132 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
133 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
134 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
135 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b
136 #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c
137 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d
138 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e
139 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f
140 #define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010
142 #define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
143 #define SHARED_HW_CFG_BOARD_VER_SHIFT 16
144 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000
145 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28
146 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000
147 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24
148 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
149 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
151 u32 reserved
; /* 0x128 */
156 /****************************************************************************
157 * Port HW configuration *
158 ****************************************************************************/
159 struct port_hw_cfg
{ /* port 0: 0x12c port 1: 0x2bc */
162 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
163 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
166 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
167 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
169 u32 power_dissipated
;
170 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
171 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
172 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
173 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
174 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
175 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
176 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
177 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
180 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
181 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
182 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
183 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
184 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
185 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
186 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
187 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
190 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
191 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
194 u32 iscsi_mac_upper
; /* Upper 16 bits are always zeroes */
197 u32 rdma_mac_upper
; /* Upper 16 bits are always zeroes */
201 /* for external PHY, or forced mode or during AN */
202 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
203 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
205 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
206 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
208 u16 serdes_tx_driver_pre_emphasis
[16];
209 u16 serdes_rx_driver_equalizer
[16];
211 u32 xgxs_config_lane0
;
212 u32 xgxs_config_lane1
;
213 u32 xgxs_config_lane2
;
214 u32 xgxs_config_lane3
;
215 /* for external PHY, or forced mode or during AN */
216 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
217 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
219 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
220 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
222 u16 xgxs_tx_driver_pre_emphasis_lane0
[16];
223 u16 xgxs_tx_driver_pre_emphasis_lane1
[16];
224 u16 xgxs_tx_driver_pre_emphasis_lane2
[16];
225 u16 xgxs_tx_driver_pre_emphasis_lane3
[16];
227 u16 xgxs_rx_driver_equalizer_lane0
[16];
228 u16 xgxs_rx_driver_equalizer_lane1
[16];
229 u16 xgxs_rx_driver_equalizer_lane2
[16];
230 u16 xgxs_rx_driver_equalizer_lane3
[16];
233 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
234 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
235 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
236 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
237 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
238 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
239 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
240 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
242 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
244 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
246 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
248 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
250 u32 external_phy_config
;
251 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
252 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
253 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
254 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
255 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
257 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
258 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
260 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
261 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
262 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
263 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
264 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
265 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
266 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
267 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
268 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
269 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
270 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
271 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
272 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
274 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
275 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
277 u32 speed_capability_mask
;
278 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
279 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
280 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
281 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
282 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
283 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
284 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
285 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
286 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
287 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
288 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
289 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
290 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
291 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
292 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
294 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
295 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
296 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
297 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
298 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
299 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
300 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
301 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
302 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
303 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
304 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
305 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
306 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
307 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
308 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
315 /****************************************************************************
316 * Shared Feature configuration *
317 ****************************************************************************/
318 struct shared_feat_cfg
{ /* NVRAM Offset */
320 u32 config
; /* 0x450 */
321 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
322 #define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
327 /****************************************************************************
328 * Port Feature configuration *
329 ****************************************************************************/
330 struct port_feat_cfg
{ /* port 0: 0x454 port 1: 0x4c8 */
333 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
334 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
335 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
336 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
337 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
338 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
339 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
340 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
341 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
342 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
343 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
344 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
345 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
346 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
347 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
348 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
349 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
350 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
351 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
352 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
353 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
354 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
355 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
356 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
357 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
358 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
359 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
360 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
361 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
362 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
363 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
364 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
365 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
366 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
367 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
368 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
369 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
370 #define PORT_FEATURE_EN_SIZE_SHIFT 24
371 #define PORT_FEATURE_WOL_ENABLED 0x01000000
372 #define PORT_FEATURE_MBA_ENABLED 0x02000000
373 #define PORT_FEATURE_MFW_ENABLED 0x04000000
376 /* Default is used when driver sets to "auto" mode */
377 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
378 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
379 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
380 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
381 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
382 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
383 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
384 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
385 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
388 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
389 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
390 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
391 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
392 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
393 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
394 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
395 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
396 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
397 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
398 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
399 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
400 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
401 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
402 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
403 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
404 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
405 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
406 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
407 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
408 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
409 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
410 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
411 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
412 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
413 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
414 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
415 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
416 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
417 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
418 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
419 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
420 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
421 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
422 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
423 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
424 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
425 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
426 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
427 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
428 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
429 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
430 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
431 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
432 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
433 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
434 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
435 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
436 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
437 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
438 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
439 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
440 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
441 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
444 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
445 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
448 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
449 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
450 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
453 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
454 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
455 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
456 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
457 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
461 #define PORT_FEATURE_SMBUS_EN 0x00000001
462 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
463 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
467 u32 link_config
; /* Used as HW defaults for the driver */
468 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
469 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
470 /* (forced) low speed switch (< 10G) */
471 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
472 /* (forced) high speed switch (>= 10G) */
473 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
474 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
475 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
477 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
478 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
479 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
480 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
481 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
482 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
483 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
484 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
485 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
486 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
487 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
488 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
489 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
490 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
491 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
492 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
493 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
495 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
496 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
497 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
498 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
499 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
500 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
501 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
503 /* The default for MCP link configuration,
504 uses the same defines as link_config */
505 u32 mfw_wol_link_cfg
;
512 /****************************************************************************
513 * Device Information *
514 ****************************************************************************/
515 struct dev_info
{ /* size */
517 u32 bc_rev
; /* 8 bits each: major, minor, build */ /* 4 */
519 struct shared_hw_cfg shared_hw_config
; /* 40 */
521 struct port_hw_cfg port_hw_config
[PORT_MAX
]; /* 400*2=800 */
523 struct shared_feat_cfg shared_feature_config
; /* 4 */
525 struct port_feat_cfg port_feature_config
[PORT_MAX
];/* 116*2=232 */
538 #define E1_FUNC_MAX 2
539 #define E1H_FUNC_MAX 8
549 /* This value (in milliseconds) determines the frequency of the driver
550 * issuing the PULSE message code. The firmware monitors this periodic
551 * pulse to determine when to switch to an OS-absent mode. */
552 #define DRV_PULSE_PERIOD_MS 250
554 /* This value (in milliseconds) determines how long the driver should
555 * wait for an acknowledgement from the firmware before timing out. Once
556 * the firmware has timed out, the driver will assume there is no firmware
557 * running and there won't be any firmware-driver synchronization during a
559 #define FW_ACK_TIME_OUT_MS 5000
561 #define FW_ACK_POLL_TIME_MS 1
563 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
565 /* LED Blink rate that will achieve ~15.9Hz */
566 #define LED_BLINK_RATE_VAL 480
568 /****************************************************************************
569 * Driver <-> FW Mailbox *
570 ****************************************************************************/
574 /* Driver should update this field on any link change event */
576 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
577 #define LINK_STATUS_LINK_UP 0x00000001
578 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
579 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
580 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
581 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
582 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
583 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
584 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
585 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
586 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
587 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
588 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
589 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
590 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
591 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
592 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
593 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
594 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
595 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
596 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
597 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
598 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
599 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
600 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
601 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
602 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
604 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
605 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
607 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
608 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
609 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
611 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
612 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
613 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
614 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
615 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
616 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
617 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
619 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
620 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
622 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
623 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
625 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
626 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
627 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
628 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
629 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
631 #define LINK_STATUS_SERDES_LINK 0x00100000
633 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
634 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
635 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
636 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
637 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
638 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
639 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
640 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
653 #define DRV_MSG_CODE_MASK 0xffff0000
654 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
655 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
656 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
657 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
658 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
659 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
660 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
661 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
662 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
663 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
664 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
665 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
666 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
668 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
669 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
670 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
671 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
673 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
678 #define FW_MSG_CODE_MASK 0xffff0000
679 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
680 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
681 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
682 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
683 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
684 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
685 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
686 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
687 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
688 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
689 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
690 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
691 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
692 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
693 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
694 #define FW_MSG_CODE_NO_KEY 0x80f00000
695 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
696 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
697 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
698 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
699 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
700 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
702 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
703 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
704 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
705 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
707 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
712 #define DRV_PULSE_SEQ_MASK 0x00007fff
713 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
714 /* The system time is in the format of
715 * (year-2001)*12*32 + month*32 + day. */
716 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
717 /* Indicate to the firmware not to go into the
718 * OS-absent when it is not getting driver pulse.
719 * This is used for debugging as well for PXE(MBA). */
722 #define MCP_PULSE_SEQ_MASK 0x00007fff
723 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
724 /* Indicates to the driver not to assert due to lack
726 #define MCP_EVENT_MASK 0xffff0000
727 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
729 u32 iscsi_boot_signature
;
730 u32 iscsi_boot_block_offset
;
733 #define DRV_STATUS_PMF 0x00000001
736 #define VIRT_MAC_SIGN_MASK 0xffff0000
737 #define VIRT_MAC_SIGNATURE 0x564d0000
743 /****************************************************************************
744 * Management firmware state *
745 ****************************************************************************/
746 /* Allocate 440 bytes for management firmware */
747 #define MGMTFW_STATE_WORD_SIZE 110
749 struct mgmtfw_state
{
750 u32 opaque
[MGMTFW_STATE_WORD_SIZE
];
754 /****************************************************************************
755 * Multi-Function configuration *
756 ****************************************************************************/
757 struct shared_mf_cfg
{
760 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
762 #define SHARED_MF_CLP_EXIT 0x00000001
764 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
770 u32 dynamic_cfg
; /* device control channel */
771 #define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
772 #define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
773 #define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
774 #define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
784 /* function 0 of each port cannot be hidden */
785 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
787 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
788 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
789 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
790 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
791 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
792 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
794 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
797 /* 0 - low priority, 3 - high priority */
798 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
799 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
800 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
803 /* value range - 0..100, increments in 100Mbps */
804 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
805 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
806 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
807 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
808 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
809 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
811 u32 mac_upper
; /* MAC */
812 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
813 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
814 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
816 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
818 u32 e1hov_tag
; /* VNI */
819 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
820 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
821 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
829 struct shared_mf_cfg shared_mf_config
;
830 struct port_mf_cfg port_mf_config
[PORT_MAX
];
832 struct func_mf_cfg func_mf_config
[E1_FUNC_MAX
];
834 struct func_mf_cfg func_mf_config
[E1H_FUNC_MAX
];
840 /****************************************************************************
841 * Shared Memory Region *
842 ****************************************************************************/
843 struct shmem_region
{ /* SharedMem Offset (size) */
845 u32 validity_map
[PORT_MAX
]; /* 0x0 (4*2 = 0x8) */
846 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
847 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
849 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
850 #define SHR_MEM_VALIDITY_MB 0x00200000
851 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
852 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
853 /* One licensing bit should be set */
854 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
855 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
856 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
857 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
859 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
860 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
861 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
862 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
863 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
864 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
866 struct dev_info dev_info
; /* 0x8 (0x438) */
868 u8 reserved
[52*PORT_MAX
];
870 /* FW information (for internal FW use) */
871 u32 fw_info_fio_offset
; /* 0x4a8 (0x4) */
872 struct mgmtfw_state mgmtfw_state
; /* 0x4ac (0x1b8) */
874 struct drv_port_mb port_mb
[PORT_MAX
]; /* 0x664 (16*2=0x20) */
875 struct drv_func_mb func_mb
[E1H_FUNC_MAX
];
877 struct mf_cfg mf_cfg
;
883 u32 rx_stat_ifhcinoctets
;
884 u32 rx_stat_ifhcinbadoctets
;
885 u32 rx_stat_etherstatsfragments
;
886 u32 rx_stat_ifhcinucastpkts
;
887 u32 rx_stat_ifhcinmulticastpkts
;
888 u32 rx_stat_ifhcinbroadcastpkts
;
889 u32 rx_stat_dot3statsfcserrors
;
890 u32 rx_stat_dot3statsalignmenterrors
;
891 u32 rx_stat_dot3statscarriersenseerrors
;
892 u32 rx_stat_xonpauseframesreceived
;
893 u32 rx_stat_xoffpauseframesreceived
;
894 u32 rx_stat_maccontrolframesreceived
;
895 u32 rx_stat_xoffstateentered
;
896 u32 rx_stat_dot3statsframestoolong
;
897 u32 rx_stat_etherstatsjabbers
;
898 u32 rx_stat_etherstatsundersizepkts
;
899 u32 rx_stat_etherstatspkts64octets
;
900 u32 rx_stat_etherstatspkts65octetsto127octets
;
901 u32 rx_stat_etherstatspkts128octetsto255octets
;
902 u32 rx_stat_etherstatspkts256octetsto511octets
;
903 u32 rx_stat_etherstatspkts512octetsto1023octets
;
904 u32 rx_stat_etherstatspkts1024octetsto1522octets
;
905 u32 rx_stat_etherstatspktsover1522octets
;
907 u32 rx_stat_falsecarriererrors
;
909 u32 tx_stat_ifhcoutoctets
;
910 u32 tx_stat_ifhcoutbadoctets
;
911 u32 tx_stat_etherstatscollisions
;
912 u32 tx_stat_outxonsent
;
913 u32 tx_stat_outxoffsent
;
914 u32 tx_stat_flowcontroldone
;
915 u32 tx_stat_dot3statssinglecollisionframes
;
916 u32 tx_stat_dot3statsmultiplecollisionframes
;
917 u32 tx_stat_dot3statsdeferredtransmissions
;
918 u32 tx_stat_dot3statsexcessivecollisions
;
919 u32 tx_stat_dot3statslatecollisions
;
920 u32 tx_stat_ifhcoutucastpkts
;
921 u32 tx_stat_ifhcoutmulticastpkts
;
922 u32 tx_stat_ifhcoutbroadcastpkts
;
923 u32 tx_stat_etherstatspkts64octets
;
924 u32 tx_stat_etherstatspkts65octetsto127octets
;
925 u32 tx_stat_etherstatspkts128octetsto255octets
;
926 u32 tx_stat_etherstatspkts256octetsto511octets
;
927 u32 tx_stat_etherstatspkts512octetsto1023octets
;
928 u32 tx_stat_etherstatspkts1024octetsto1522octets
;
929 u32 tx_stat_etherstatspktsover1522octets
;
930 u32 tx_stat_dot3statsinternalmactransmiterrors
;
935 u32 tx_stat_gtpkt_lo
;
936 u32 tx_stat_gtpkt_hi
;
937 u32 tx_stat_gtxpf_lo
;
938 u32 tx_stat_gtxpf_hi
;
939 u32 tx_stat_gtfcs_lo
;
940 u32 tx_stat_gtfcs_hi
;
941 u32 tx_stat_gtmca_lo
;
942 u32 tx_stat_gtmca_hi
;
943 u32 tx_stat_gtbca_lo
;
944 u32 tx_stat_gtbca_hi
;
945 u32 tx_stat_gtfrg_lo
;
946 u32 tx_stat_gtfrg_hi
;
947 u32 tx_stat_gtovr_lo
;
948 u32 tx_stat_gtovr_hi
;
951 u32 tx_stat_gt127_lo
;
952 u32 tx_stat_gt127_hi
;
953 u32 tx_stat_gt255_lo
;
954 u32 tx_stat_gt255_hi
;
955 u32 tx_stat_gt511_lo
;
956 u32 tx_stat_gt511_hi
;
957 u32 tx_stat_gt1023_lo
;
958 u32 tx_stat_gt1023_hi
;
959 u32 tx_stat_gt1518_lo
;
960 u32 tx_stat_gt1518_hi
;
961 u32 tx_stat_gt2047_lo
;
962 u32 tx_stat_gt2047_hi
;
963 u32 tx_stat_gt4095_lo
;
964 u32 tx_stat_gt4095_hi
;
965 u32 tx_stat_gt9216_lo
;
966 u32 tx_stat_gt9216_hi
;
967 u32 tx_stat_gt16383_lo
;
968 u32 tx_stat_gt16383_hi
;
969 u32 tx_stat_gtmax_lo
;
970 u32 tx_stat_gtmax_hi
;
971 u32 tx_stat_gtufl_lo
;
972 u32 tx_stat_gtufl_hi
;
973 u32 tx_stat_gterr_lo
;
974 u32 tx_stat_gterr_hi
;
975 u32 tx_stat_gtbyt_lo
;
976 u32 tx_stat_gtbyt_hi
;
980 u32 rx_stat_gr127_lo
;
981 u32 rx_stat_gr127_hi
;
982 u32 rx_stat_gr255_lo
;
983 u32 rx_stat_gr255_hi
;
984 u32 rx_stat_gr511_lo
;
985 u32 rx_stat_gr511_hi
;
986 u32 rx_stat_gr1023_lo
;
987 u32 rx_stat_gr1023_hi
;
988 u32 rx_stat_gr1518_lo
;
989 u32 rx_stat_gr1518_hi
;
990 u32 rx_stat_gr2047_lo
;
991 u32 rx_stat_gr2047_hi
;
992 u32 rx_stat_gr4095_lo
;
993 u32 rx_stat_gr4095_hi
;
994 u32 rx_stat_gr9216_lo
;
995 u32 rx_stat_gr9216_hi
;
996 u32 rx_stat_gr16383_lo
;
997 u32 rx_stat_gr16383_hi
;
998 u32 rx_stat_grmax_lo
;
999 u32 rx_stat_grmax_hi
;
1000 u32 rx_stat_grpkt_lo
;
1001 u32 rx_stat_grpkt_hi
;
1002 u32 rx_stat_grfcs_lo
;
1003 u32 rx_stat_grfcs_hi
;
1004 u32 rx_stat_grmca_lo
;
1005 u32 rx_stat_grmca_hi
;
1006 u32 rx_stat_grbca_lo
;
1007 u32 rx_stat_grbca_hi
;
1008 u32 rx_stat_grxcf_lo
;
1009 u32 rx_stat_grxcf_hi
;
1010 u32 rx_stat_grxpf_lo
;
1011 u32 rx_stat_grxpf_hi
;
1012 u32 rx_stat_grxuo_lo
;
1013 u32 rx_stat_grxuo_hi
;
1014 u32 rx_stat_grjbr_lo
;
1015 u32 rx_stat_grjbr_hi
;
1016 u32 rx_stat_grovr_lo
;
1017 u32 rx_stat_grovr_hi
;
1018 u32 rx_stat_grflr_lo
;
1019 u32 rx_stat_grflr_hi
;
1020 u32 rx_stat_grmeg_lo
;
1021 u32 rx_stat_grmeg_hi
;
1022 u32 rx_stat_grmeb_lo
;
1023 u32 rx_stat_grmeb_hi
;
1024 u32 rx_stat_grbyt_lo
;
1025 u32 rx_stat_grbyt_hi
;
1026 u32 rx_stat_grund_lo
;
1027 u32 rx_stat_grund_hi
;
1028 u32 rx_stat_grfrg_lo
;
1029 u32 rx_stat_grfrg_hi
;
1030 u32 rx_stat_grerb_lo
;
1031 u32 rx_stat_grerb_hi
;
1032 u32 rx_stat_grfre_lo
;
1033 u32 rx_stat_grfre_hi
;
1034 u32 rx_stat_gripj_lo
;
1035 u32 rx_stat_gripj_hi
;
1040 struct emac_stats emac_stats
;
1041 struct bmac_stats bmac_stats
;
1047 u32 rx_stat_ifhcinbadoctets_hi
;
1048 u32 rx_stat_ifhcinbadoctets_lo
;
1050 /* out_bad_octets */
1051 u32 tx_stat_ifhcoutbadoctets_hi
;
1052 u32 tx_stat_ifhcoutbadoctets_lo
;
1054 /* crc_receive_errors */
1055 u32 rx_stat_dot3statsfcserrors_hi
;
1056 u32 rx_stat_dot3statsfcserrors_lo
;
1057 /* alignment_errors */
1058 u32 rx_stat_dot3statsalignmenterrors_hi
;
1059 u32 rx_stat_dot3statsalignmenterrors_lo
;
1060 /* carrier_sense_errors */
1061 u32 rx_stat_dot3statscarriersenseerrors_hi
;
1062 u32 rx_stat_dot3statscarriersenseerrors_lo
;
1063 /* false_carrier_detections */
1064 u32 rx_stat_falsecarriererrors_hi
;
1065 u32 rx_stat_falsecarriererrors_lo
;
1067 /* runt_packets_received */
1068 u32 rx_stat_etherstatsundersizepkts_hi
;
1069 u32 rx_stat_etherstatsundersizepkts_lo
;
1070 /* jabber_packets_received */
1071 u32 rx_stat_dot3statsframestoolong_hi
;
1072 u32 rx_stat_dot3statsframestoolong_lo
;
1074 /* error_runt_packets_received */
1075 u32 rx_stat_etherstatsfragments_hi
;
1076 u32 rx_stat_etherstatsfragments_lo
;
1077 /* error_jabber_packets_received */
1078 u32 rx_stat_etherstatsjabbers_hi
;
1079 u32 rx_stat_etherstatsjabbers_lo
;
1081 /* control_frames_received */
1082 u32 rx_stat_maccontrolframesreceived_hi
;
1083 u32 rx_stat_maccontrolframesreceived_lo
;
1084 u32 rx_stat_bmac_xpf_hi
;
1085 u32 rx_stat_bmac_xpf_lo
;
1086 u32 rx_stat_bmac_xcf_hi
;
1087 u32 rx_stat_bmac_xcf_lo
;
1089 /* xoff_state_entered */
1090 u32 rx_stat_xoffstateentered_hi
;
1091 u32 rx_stat_xoffstateentered_lo
;
1092 /* pause_xon_frames_received */
1093 u32 rx_stat_xonpauseframesreceived_hi
;
1094 u32 rx_stat_xonpauseframesreceived_lo
;
1095 /* pause_xoff_frames_received */
1096 u32 rx_stat_xoffpauseframesreceived_hi
;
1097 u32 rx_stat_xoffpauseframesreceived_lo
;
1098 /* pause_xon_frames_transmitted */
1099 u32 tx_stat_outxonsent_hi
;
1100 u32 tx_stat_outxonsent_lo
;
1101 /* pause_xoff_frames_transmitted */
1102 u32 tx_stat_outxoffsent_hi
;
1103 u32 tx_stat_outxoffsent_lo
;
1104 /* flow_control_done */
1105 u32 tx_stat_flowcontroldone_hi
;
1106 u32 tx_stat_flowcontroldone_lo
;
1108 /* ether_stats_collisions */
1109 u32 tx_stat_etherstatscollisions_hi
;
1110 u32 tx_stat_etherstatscollisions_lo
;
1111 /* single_collision_transmit_frames */
1112 u32 tx_stat_dot3statssinglecollisionframes_hi
;
1113 u32 tx_stat_dot3statssinglecollisionframes_lo
;
1114 /* multiple_collision_transmit_frames */
1115 u32 tx_stat_dot3statsmultiplecollisionframes_hi
;
1116 u32 tx_stat_dot3statsmultiplecollisionframes_lo
;
1117 /* deferred_transmissions */
1118 u32 tx_stat_dot3statsdeferredtransmissions_hi
;
1119 u32 tx_stat_dot3statsdeferredtransmissions_lo
;
1120 /* excessive_collision_frames */
1121 u32 tx_stat_dot3statsexcessivecollisions_hi
;
1122 u32 tx_stat_dot3statsexcessivecollisions_lo
;
1123 /* late_collision_frames */
1124 u32 tx_stat_dot3statslatecollisions_hi
;
1125 u32 tx_stat_dot3statslatecollisions_lo
;
1127 /* frames_transmitted_64_bytes */
1128 u32 tx_stat_etherstatspkts64octets_hi
;
1129 u32 tx_stat_etherstatspkts64octets_lo
;
1130 /* frames_transmitted_65_127_bytes */
1131 u32 tx_stat_etherstatspkts65octetsto127octets_hi
;
1132 u32 tx_stat_etherstatspkts65octetsto127octets_lo
;
1133 /* frames_transmitted_128_255_bytes */
1134 u32 tx_stat_etherstatspkts128octetsto255octets_hi
;
1135 u32 tx_stat_etherstatspkts128octetsto255octets_lo
;
1136 /* frames_transmitted_256_511_bytes */
1137 u32 tx_stat_etherstatspkts256octetsto511octets_hi
;
1138 u32 tx_stat_etherstatspkts256octetsto511octets_lo
;
1139 /* frames_transmitted_512_1023_bytes */
1140 u32 tx_stat_etherstatspkts512octetsto1023octets_hi
;
1141 u32 tx_stat_etherstatspkts512octetsto1023octets_lo
;
1142 /* frames_transmitted_1024_1522_bytes */
1143 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi
;
1144 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo
;
1145 /* frames_transmitted_1523_9022_bytes */
1146 u32 tx_stat_etherstatspktsover1522octets_hi
;
1147 u32 tx_stat_etherstatspktsover1522octets_lo
;
1148 u32 tx_stat_bmac_2047_hi
;
1149 u32 tx_stat_bmac_2047_lo
;
1150 u32 tx_stat_bmac_4095_hi
;
1151 u32 tx_stat_bmac_4095_lo
;
1152 u32 tx_stat_bmac_9216_hi
;
1153 u32 tx_stat_bmac_9216_lo
;
1154 u32 tx_stat_bmac_16383_hi
;
1155 u32 tx_stat_bmac_16383_lo
;
1157 /* internal_mac_transmit_errors */
1158 u32 tx_stat_dot3statsinternalmactransmiterrors_hi
;
1159 u32 tx_stat_dot3statsinternalmactransmiterrors_lo
;
1161 /* if_out_discards */
1162 u32 tx_stat_bmac_ufl_hi
;
1163 u32 tx_stat_bmac_ufl_lo
;
1167 #define MAC_STX_IDX_MAX 2
1169 struct host_port_stats
{
1170 u32 host_port_stats_start
;
1172 struct mac_stx mac_stx
[MAC_STX_IDX_MAX
];
1177 u32 host_port_stats_end
;
1181 struct host_func_stats
{
1182 u32 host_func_stats_start
;
1184 u32 total_bytes_received_hi
;
1185 u32 total_bytes_received_lo
;
1187 u32 total_bytes_transmitted_hi
;
1188 u32 total_bytes_transmitted_lo
;
1190 u32 total_unicast_packets_received_hi
;
1191 u32 total_unicast_packets_received_lo
;
1193 u32 total_multicast_packets_received_hi
;
1194 u32 total_multicast_packets_received_lo
;
1196 u32 total_broadcast_packets_received_hi
;
1197 u32 total_broadcast_packets_received_lo
;
1199 u32 total_unicast_packets_transmitted_hi
;
1200 u32 total_unicast_packets_transmitted_lo
;
1202 u32 total_multicast_packets_transmitted_hi
;
1203 u32 total_multicast_packets_transmitted_lo
;
1205 u32 total_broadcast_packets_transmitted_hi
;
1206 u32 total_broadcast_packets_transmitted_lo
;
1208 u32 valid_bytes_received_hi
;
1209 u32 valid_bytes_received_lo
;
1211 u32 host_func_stats_end
;
1215 #define BCM_5710_FW_MAJOR_VERSION 4
1216 #define BCM_5710_FW_MINOR_VERSION 8
1217 #define BCM_5710_FW_REVISION_VERSION 53
1218 #define BCM_5710_FW_ENGINEERING_VERSION 0
1219 #define BCM_5710_FW_COMPILE_FLAGS 1
1225 struct atten_def_status_block
{
1230 u16 attn_bits_index
;
1236 * common data for all protocols
1238 struct doorbell_hdr
{
1240 #define DOORBELL_HDR_RX (0x1<<0)
1241 #define DOORBELL_HDR_RX_SHIFT 0
1242 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1243 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1244 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1245 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1246 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1247 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1251 * doorbell message sent to the chip
1254 #if defined(__BIG_ENDIAN)
1257 struct doorbell_hdr header
;
1258 #elif defined(__LITTLE_ENDIAN)
1259 struct doorbell_hdr header
;
1267 * IGU driver acknowledgement register
1269 struct igu_ack_register
{
1270 #if defined(__BIG_ENDIAN)
1271 u16 sb_id_and_flags
;
1272 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1273 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1274 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1275 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1276 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1277 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1278 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1279 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1280 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1281 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1282 u16 status_block_index
;
1283 #elif defined(__LITTLE_ENDIAN)
1284 u16 status_block_index
;
1285 u16 sb_id_and_flags
;
1286 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1287 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1288 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1289 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1290 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1291 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1292 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1293 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1294 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1295 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1301 * Parser parsing flags field
1303 struct parsing_flags
{
1305 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1306 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1307 #define PARSING_FLAGS_VLAN (0x1<<1)
1308 #define PARSING_FLAGS_VLAN_SHIFT 1
1309 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1310 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1311 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1312 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1313 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1314 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1315 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1316 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1317 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1318 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1319 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1320 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1321 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1322 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1323 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1324 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1325 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1326 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1327 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1328 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1329 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1330 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1341 * dmae command structure
1343 struct dmae_command
{
1345 #define DMAE_COMMAND_SRC (0x1<<0)
1346 #define DMAE_COMMAND_SRC_SHIFT 0
1347 #define DMAE_COMMAND_DST (0x3<<1)
1348 #define DMAE_COMMAND_DST_SHIFT 1
1349 #define DMAE_COMMAND_C_DST (0x1<<3)
1350 #define DMAE_COMMAND_C_DST_SHIFT 3
1351 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1352 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1353 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1354 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1355 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1356 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1357 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1358 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1359 #define DMAE_COMMAND_PORT (0x1<<11)
1360 #define DMAE_COMMAND_PORT_SHIFT 11
1361 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1362 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1363 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1364 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1365 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1366 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1367 #define DMAE_COMMAND_E1HVN (0x3<<15)
1368 #define DMAE_COMMAND_E1HVN_SHIFT 15
1369 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1370 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1375 #if defined(__BIG_ENDIAN)
1378 #elif defined(__LITTLE_ENDIAN)
1387 #if defined(__BIG_ENDIAN)
1390 #elif defined(__LITTLE_ENDIAN)
1394 #if defined(__BIG_ENDIAN)
1397 #elif defined(__LITTLE_ENDIAN)
1401 #if defined(__BIG_ENDIAN)
1404 #elif defined(__LITTLE_ENDIAN)
1411 struct double_regpair
{
1420 * The eth storm context of Ustorm (configuration part)
1422 struct ustorm_eth_st_context_config
{
1423 #if defined(__BIG_ENDIAN)
1425 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1426 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1427 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1428 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1429 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1430 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1431 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1432 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1433 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1434 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1435 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1436 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1439 u8 sb_index_numbers
;
1440 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1441 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1442 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1443 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1444 #elif defined(__LITTLE_ENDIAN)
1445 u8 sb_index_numbers
;
1446 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1447 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1448 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1449 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1453 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1454 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1455 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1456 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1457 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1458 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1459 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1460 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1461 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1462 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1463 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1464 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1466 #if defined(__BIG_ENDIAN)
1468 u8 statistics_counter_id
;
1469 u8 mc_alignment_log_size
;
1470 #elif defined(__LITTLE_ENDIAN)
1471 u8 mc_alignment_log_size
;
1472 u8 statistics_counter_id
;
1475 #if defined(__BIG_ENDIAN)
1476 u8 __local_sge_prod
;
1479 #elif defined(__LITTLE_ENDIAN)
1482 u8 __local_sge_prod
;
1485 u32 bd_page_base_lo
;
1486 u32 bd_page_base_hi
;
1487 u32 sge_page_base_lo
;
1488 u32 sge_page_base_hi
;
1492 * The eth Rx Buffer Descriptor
1500 * The eth Rx SGE Descriptor
1508 * Local BDs and SGEs rings (in ETH)
1510 struct eth_local_rx_rings
{
1511 struct eth_rx_bd __local_bd_ring
[16];
1512 struct eth_rx_sge __local_sge_ring
[12];
1516 * The eth storm context of Ustorm
1518 struct ustorm_eth_st_context
{
1519 struct ustorm_eth_st_context_config common
;
1520 struct eth_local_rx_rings __rings
;
1524 * The eth storm context of Tstorm
1526 struct tstorm_eth_st_context
{
1527 u32 __reserved0
[28];
1531 * The eth aggregative context section of Xstorm
1533 struct xstorm_eth_extra_ag_context_section
{
1534 #if defined(__BIG_ENDIAN)
1538 #elif defined(__LITTLE_ENDIAN)
1547 #if defined(__BIG_ENDIAN)
1550 u16 __tcp_agg_vars2
;
1551 #elif defined(__LITTLE_ENDIAN)
1552 u16 __tcp_agg_vars2
;
1560 #if defined(__BIG_ENDIAN)
1563 #elif defined(__LITTLE_ENDIAN)
1567 #if defined(__BIG_ENDIAN)
1572 #elif defined(__LITTLE_ENDIAN)
1578 u32 __tcp_agg_vars6
;
1579 #if defined(__BIG_ENDIAN)
1581 u16 __tcp_agg_vars7
;
1582 #elif defined(__LITTLE_ENDIAN)
1583 u16 __tcp_agg_vars7
;
1588 #if defined(__BIG_ENDIAN)
1592 #elif defined(__LITTLE_ENDIAN)
1600 * The eth aggregative context of Xstorm
1602 struct xstorm_eth_ag_context
{
1603 #if defined(__BIG_ENDIAN)
1607 #elif defined(__LITTLE_ENDIAN)
1612 #if defined(__BIG_ENDIAN)
1617 #elif defined(__LITTLE_ENDIAN)
1623 u32 __more_packets_to_send
;
1624 #if defined(__BIG_ENDIAN)
1627 #elif defined(__LITTLE_ENDIAN)
1631 struct xstorm_eth_extra_ag_context_section __extra_section
;
1632 #if defined(__BIG_ENDIAN)
1636 #elif defined(__LITTLE_ENDIAN)
1641 #if defined(__BIG_ENDIAN)
1644 #elif defined(__LITTLE_ENDIAN)
1648 #if defined(__BIG_ENDIAN)
1652 #elif defined(__LITTLE_ENDIAN)
1657 #if defined(__BIG_ENDIAN)
1660 #elif defined(__LITTLE_ENDIAN)
1665 #if defined(__BIG_ENDIAN)
1668 #elif defined(__LITTLE_ENDIAN)
1672 #if defined(__BIG_ENDIAN)
1677 #elif defined(__LITTLE_ENDIAN)
1683 #if defined(__BIG_ENDIAN)
1685 u16 __bd_ind_max_val
;
1686 #elif defined(__LITTLE_ENDIAN)
1687 u16 __bd_ind_max_val
;
1696 * The eth aggregative context section of Tstorm
1698 struct tstorm_eth_extra_ag_context_section
{
1700 #if defined(__BIG_ENDIAN)
1704 #elif defined(__LITTLE_ENDIAN)
1709 #if defined(__BIG_ENDIAN)
1713 #elif defined(__LITTLE_ENDIAN)
1723 u32 __tcp_agg_vars1
;
1730 * The eth aggregative context of Tstorm
1732 struct tstorm_eth_ag_context
{
1733 #if defined(__BIG_ENDIAN)
1737 #elif defined(__LITTLE_ENDIAN)
1742 #if defined(__BIG_ENDIAN)
1745 #elif defined(__LITTLE_ENDIAN)
1749 struct tstorm_eth_extra_ag_context_section __extra_section
;
1753 * The eth aggregative context of Cstorm
1755 struct cstorm_eth_ag_context
{
1757 #if defined(__BIG_ENDIAN)
1761 #elif defined(__LITTLE_ENDIAN)
1766 u32 __num_of_treated_packet
;
1767 u32 __last_packet_treated
;
1768 #if defined(__BIG_ENDIAN)
1771 #elif defined(__LITTLE_ENDIAN)
1775 #if defined(__BIG_ENDIAN)
1780 #elif defined(__LITTLE_ENDIAN)
1786 #if defined(__BIG_ENDIAN)
1789 #elif defined(__LITTLE_ENDIAN)
1794 #if defined(__BIG_ENDIAN)
1797 #elif defined(__LITTLE_ENDIAN)
1801 #if defined(__BIG_ENDIAN)
1802 u16 __packet_index_th
;
1804 #elif defined(__LITTLE_ENDIAN)
1806 u16 __packet_index_th
;
1811 * The eth aggregative context of Ustorm
1813 struct ustorm_eth_ag_context
{
1814 #if defined(__BIG_ENDIAN)
1815 u8 __aux_counter_flags
;
1819 #elif defined(__LITTLE_ENDIAN)
1823 u8 __aux_counter_flags
;
1825 #if defined(__BIG_ENDIAN)
1829 #elif defined(__LITTLE_ENDIAN)
1835 #if defined(__BIG_ENDIAN)
1839 #elif defined(__LITTLE_ENDIAN)
1846 #if defined(__BIG_ENDIAN)
1849 #elif defined(__LITTLE_ENDIAN)
1853 #if defined(__BIG_ENDIAN)
1855 u8 __decision_rules
;
1856 u8 __decision_rule_enable_bits
;
1857 #elif defined(__LITTLE_ENDIAN)
1858 u8 __decision_rule_enable_bits
;
1859 u8 __decision_rules
;
1865 * Timers connection context
1867 struct timers_block_context
{
1872 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1873 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1874 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1875 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1876 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1877 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1881 * structure for easy accessibility to assembler
1883 struct eth_tx_bd_flags
{
1885 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1886 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1887 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1888 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1889 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1890 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1891 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1892 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1893 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1894 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1895 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1896 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1897 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1898 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1899 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1900 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1904 * The eth Tx Buffer Descriptor
1912 struct eth_tx_bd_flags bd_flags
;
1914 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1915 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1916 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1917 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1921 * Tx parsing BD structure for ETH,Relevant in START
1923 struct eth_tx_parse_bd
{
1925 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1926 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1927 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1928 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1929 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1930 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1931 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1932 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1933 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1934 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1936 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1937 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1938 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1939 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1940 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1941 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1942 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1943 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1944 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1945 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1946 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1947 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1948 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1949 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1950 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1951 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1956 u16 tcp_pseudo_csum
;
1962 * The last BD in the BD memory will hold a pointer to the next BD memory
1964 struct eth_tx_next_bd
{
1971 * union for 3 Bd types
1973 union eth_tx_bd_types
{
1974 struct eth_tx_bd reg_bd
;
1975 struct eth_tx_parse_bd parse_bd
;
1976 struct eth_tx_next_bd next_bd
;
1980 * The eth storm context of Xstorm
1982 struct xstorm_eth_st_context
{
1983 u32 tx_bd_page_base_lo
;
1984 u32 tx_bd_page_base_hi
;
1985 #if defined(__BIG_ENDIAN)
1988 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1989 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1990 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1991 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1992 u8 __local_tx_bd_prod
;
1993 #elif defined(__LITTLE_ENDIAN)
1994 u8 __local_tx_bd_prod
;
1996 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1997 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1998 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1999 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2002 u32 db_data_addr_lo
;
2003 u32 db_data_addr_hi
;
2007 union eth_tx_bd_types __bds
[13];
2011 * The eth storm context of Cstorm
2013 struct cstorm_eth_st_context
{
2014 #if defined(__BIG_ENDIAN)
2018 #elif defined(__LITTLE_ENDIAN)
2027 * Ethernet connection context
2029 struct eth_context
{
2030 struct ustorm_eth_st_context ustorm_st_context
;
2031 struct tstorm_eth_st_context tstorm_st_context
;
2032 struct xstorm_eth_ag_context xstorm_ag_context
;
2033 struct tstorm_eth_ag_context tstorm_ag_context
;
2034 struct cstorm_eth_ag_context cstorm_ag_context
;
2035 struct ustorm_eth_ag_context ustorm_ag_context
;
2036 struct timers_block_context timers_context
;
2037 struct xstorm_eth_st_context xstorm_st_context
;
2038 struct cstorm_eth_st_context cstorm_st_context
;
2045 struct eth_tx_doorbell
{
2046 #if defined(__BIG_ENDIAN)
2049 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2050 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2051 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2052 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2053 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2054 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2055 struct doorbell_hdr hdr
;
2056 #elif defined(__LITTLE_ENDIAN)
2057 struct doorbell_hdr hdr
;
2059 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2060 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2061 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2062 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2063 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2064 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2071 * ustorm status block
2073 struct ustorm_def_status_block
{
2074 u16 index_values
[HC_USTORM_DEF_SB_NUM_INDICES
];
2075 u16 status_block_index
;
2082 * cstorm status block
2084 struct cstorm_def_status_block
{
2085 u16 index_values
[HC_CSTORM_DEF_SB_NUM_INDICES
];
2086 u16 status_block_index
;
2093 * xstorm status block
2095 struct xstorm_def_status_block
{
2096 u16 index_values
[HC_XSTORM_DEF_SB_NUM_INDICES
];
2097 u16 status_block_index
;
2104 * tstorm status block
2106 struct tstorm_def_status_block
{
2107 u16 index_values
[HC_TSTORM_DEF_SB_NUM_INDICES
];
2108 u16 status_block_index
;
2117 struct host_def_status_block
{
2118 struct atten_def_status_block atten_status_block
;
2119 struct ustorm_def_status_block u_def_status_block
;
2120 struct cstorm_def_status_block c_def_status_block
;
2121 struct xstorm_def_status_block x_def_status_block
;
2122 struct tstorm_def_status_block t_def_status_block
;
2127 * ustorm status block
2129 struct ustorm_status_block
{
2130 u16 index_values
[HC_USTORM_SB_NUM_INDICES
];
2131 u16 status_block_index
;
2138 * cstorm status block
2140 struct cstorm_status_block
{
2141 u16 index_values
[HC_CSTORM_SB_NUM_INDICES
];
2142 u16 status_block_index
;
2151 struct host_status_block
{
2152 struct ustorm_status_block u_status_block
;
2153 struct cstorm_status_block c_status_block
;
2158 * The data for RSS setup ramrod
2160 struct eth_client_setup_ramrod_data
{
2169 * L2 dynamic host coalescing init parameters
2171 struct eth_dynamic_hc_config
{
2178 * regular eth FP CQE parameters struct
2180 struct eth_fast_path_rx_cqe
{
2181 u8 type_error_flags
;
2182 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2183 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2184 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2185 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2186 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2187 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2188 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2189 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2190 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2191 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2192 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2193 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2194 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2195 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2197 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2198 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2199 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2200 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2201 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2202 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2203 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2204 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2205 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2206 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2207 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2208 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2209 u8 placement_offset
;
2211 u32 rss_hash_result
;
2215 struct parsing_flags pars_flags
;
2221 * The data for RSS setup ramrod
2223 struct eth_halt_ramrod_data
{
2230 * The data for statistics query ramrod
2232 struct eth_query_ramrod_data
{
2233 #if defined(__BIG_ENDIAN)
2237 #elif defined(__LITTLE_ENDIAN)
2247 * Place holder for ramrods protocol specific data
2249 struct ramrod_data
{
2255 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2257 union eth_ramrod_data
{
2258 struct ramrod_data general
;
2263 * Rx Last BD in page (in ETH)
2265 struct eth_rx_bd_next_page
{
2273 * Eth Rx Cqe structure- general structure for ramrods
2275 struct common_ramrod_eth_rx_cqe
{
2277 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2278 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2279 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2280 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
2283 u32 conn_and_cmd_data
;
2284 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2285 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2286 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2287 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2288 struct ramrod_data protocol_data
;
2293 * Rx Last CQE in page (in ETH)
2295 struct eth_rx_cqe_next_page
{
2302 * union for all eth rx cqe types (fix their sizes)
2305 struct eth_fast_path_rx_cqe fast_path_cqe
;
2306 struct common_ramrod_eth_rx_cqe ramrod_cqe
;
2307 struct eth_rx_cqe_next_page next_page_cqe
;
2312 * common data for all protocols
2315 u32 conn_and_cmd_data
;
2316 #define SPE_HDR_CID (0xFFFFFF<<0)
2317 #define SPE_HDR_CID_SHIFT 0
2318 #define SPE_HDR_CMD_ID (0xFF<<24)
2319 #define SPE_HDR_CMD_ID_SHIFT 24
2321 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2322 #define SPE_HDR_CONN_TYPE_SHIFT 0
2323 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2324 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2329 * Ethernet slow path element
2331 union eth_specific_data
{
2332 u8 protocol_data
[8];
2333 struct regpair mac_config_addr
;
2334 struct eth_client_setup_ramrod_data client_setup_ramrod_data
;
2335 struct eth_halt_ramrod_data halt_ramrod_data
;
2336 struct regpair leading_cqe_addr
;
2337 struct regpair update_data_addr
;
2338 struct eth_query_ramrod_data query_ramrod_data
;
2342 * Ethernet slow path element
2346 union eth_specific_data data
;
2351 * doorbell data in host memory
2353 struct eth_tx_db_data
{
2361 * Common configuration parameters per function in Tstorm
2363 struct tstorm_eth_function_common_config
{
2364 #if defined(__BIG_ENDIAN)
2365 u8 leading_client_id
;
2368 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2369 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2370 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2371 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2372 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2373 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2374 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2375 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2376 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2377 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2378 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2379 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2380 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2381 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2382 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2383 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2384 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2385 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2386 #elif defined(__LITTLE_ENDIAN)
2388 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2389 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2390 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2391 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2392 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2393 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2394 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2395 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2396 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2397 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2398 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2399 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2400 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2401 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2402 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2403 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2404 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2405 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2407 u8 leading_client_id
;
2413 * parameters for eth update ramrod
2415 struct eth_update_ramrod_data
{
2416 struct tstorm_eth_function_common_config func_config
;
2417 u8 indirectionTable
[128];
2422 * MAC filtering configuration command header
2424 struct mac_configuration_hdr
{
2432 * MAC address in list for ramrod
2434 struct tstorm_cam_entry
{
2436 u16 middle_mac_addr
;
2439 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2440 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2441 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2442 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2443 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2444 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2448 * MAC filtering: CAM target table entry
2450 struct tstorm_cam_target_table_entry
{
2452 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2453 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2454 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2455 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2456 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2457 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2458 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2459 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2460 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2461 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2467 * MAC address in list for ramrod
2469 struct mac_configuration_entry
{
2470 struct tstorm_cam_entry cam_entry
;
2471 struct tstorm_cam_target_table_entry target_table_entry
;
2475 * MAC filtering configuration command
2477 struct mac_configuration_cmd
{
2478 struct mac_configuration_hdr hdr
;
2479 struct mac_configuration_entry config_table
[64];
2484 * MAC address in list for ramrod
2486 struct mac_configuration_entry_e1h
{
2488 u16 middle_mac_addr
;
2494 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2495 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2496 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2497 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2498 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2499 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2500 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2501 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2505 * MAC filtering configuration command
2507 struct mac_configuration_cmd_e1h
{
2508 struct mac_configuration_hdr hdr
;
2509 struct mac_configuration_entry_e1h config_table
[32];
2514 * approximate-match multicast filtering for E1H per function in Tstorm
2516 struct tstorm_eth_approximate_match_multicast_filtering
{
2517 u32 mcast_add_hash_bit_array
[8];
2522 * Configuration parameters per client in Tstorm
2524 struct tstorm_eth_client_config
{
2525 #if defined(__BIG_ENDIAN)
2526 u8 max_sges_for_packet
;
2527 u8 statistics_counter_id
;
2529 #elif defined(__LITTLE_ENDIAN)
2531 u8 statistics_counter_id
;
2532 u8 max_sges_for_packet
;
2534 #if defined(__BIG_ENDIAN)
2536 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2537 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2538 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2539 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2540 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2541 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2542 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2543 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2544 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2545 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2547 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2548 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2549 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2550 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2551 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2552 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2553 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2554 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2555 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2556 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2557 #elif defined(__LITTLE_ENDIAN)
2559 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2560 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2561 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2562 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2563 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2564 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2565 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2566 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2567 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2568 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2570 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2571 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2572 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2573 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2574 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2575 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2576 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2577 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2578 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2579 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2585 * MAC filtering configuration parameters per port in Tstorm
2587 struct tstorm_eth_mac_filter_config
{
2589 u32 ucast_accept_all
;
2591 u32 mcast_accept_all
;
2593 u32 bcast_accept_all
;
2601 * common flag to indicate existance of TPA.
2603 struct tstorm_eth_tpa_exist
{
2604 #if defined(__BIG_ENDIAN)
2608 #elif defined(__LITTLE_ENDIAN)
2618 * Three RX producers for ETH
2620 struct ustorm_eth_rx_producers
{
2621 #if defined(__BIG_ENDIAN)
2624 #elif defined(__LITTLE_ENDIAN)
2628 #if defined(__BIG_ENDIAN)
2631 #elif defined(__LITTLE_ENDIAN)
2639 * per-port SAFC demo variables
2641 struct cmng_flags_per_port
{
2642 u8 con_number
[NUM_OF_PROTOCOLS
];
2644 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2645 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2646 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2647 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2648 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2649 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2650 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2651 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2652 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2653 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2654 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
2655 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2660 * per-port rate shaping variables
2662 struct rate_shaping_vars_per_port
{
2663 u32 rs_periodic_timeout
;
2669 * per-port fairness variables
2671 struct fairness_vars_per_port
{
2674 u32 fairness_timeout
;
2679 * per-port SAFC variables
2681 struct safc_struct_per_port
{
2682 #if defined(__BIG_ENDIAN)
2685 u8 safc_timeout_usec
;
2686 #elif defined(__LITTLE_ENDIAN)
2687 u8 safc_timeout_usec
;
2691 u16 cos_to_pause_mask
[NUM_OF_SAFC_BITS
];
2696 * Per-port congestion management variables
2698 struct cmng_struct_per_port
{
2699 struct rate_shaping_vars_per_port rs_vars
;
2700 struct fairness_vars_per_port fair_vars
;
2701 struct safc_struct_per_port safc_vars
;
2702 struct cmng_flags_per_port flags
;
2707 * Protocol-common statistics collected by the Xstorm (per client)
2709 struct xstorm_per_client_stats
{
2710 struct regpair total_sent_bytes
;
2711 u32 total_sent_pkts
;
2712 u32 unicast_pkts_sent
;
2713 struct regpair unicast_bytes_sent
;
2714 struct regpair multicast_bytes_sent
;
2715 u32 multicast_pkts_sent
;
2716 u32 broadcast_pkts_sent
;
2717 struct regpair broadcast_bytes_sent
;
2725 * Common statistics collected by the Xstorm (per port)
2727 struct xstorm_common_stats
{
2728 struct xstorm_per_client_stats client_statistics
[MAX_X_STAT_COUNTER_ID
];
2733 * Protocol-common statistics collected by the Tstorm (per port)
2735 struct tstorm_per_port_stats
{
2736 u32 mac_filter_discard
;
2737 u32 xxoverflow_discard
;
2738 u32 brb_truncate_discard
;
2744 * Protocol-common statistics collected by the Tstorm (per client)
2746 struct tstorm_per_client_stats
{
2747 struct regpair total_rcv_bytes
;
2748 struct regpair rcv_unicast_bytes
;
2749 struct regpair rcv_broadcast_bytes
;
2750 struct regpair rcv_multicast_bytes
;
2751 struct regpair rcv_error_bytes
;
2752 u32 checksum_discard
;
2753 u32 packets_too_big_discard
;
2755 u32 rcv_unicast_pkts
;
2756 u32 rcv_broadcast_pkts
;
2757 u32 rcv_multicast_pkts
;
2758 u32 no_buff_discard
;
2766 * Protocol-common statistics collected by the Tstorm
2768 struct tstorm_common_stats
{
2769 struct tstorm_per_port_stats port_statistics
;
2770 struct tstorm_per_client_stats client_statistics
[MAX_T_STAT_COUNTER_ID
];
2774 * Protocol-common statistics collected by the Ustorm (per client)
2776 struct ustorm_per_client_stats
{
2777 struct regpair ucast_no_buff_bytes
;
2778 struct regpair mcast_no_buff_bytes
;
2779 struct regpair bcast_no_buff_bytes
;
2780 __le32 ucast_no_buff_pkts
;
2781 __le32 mcast_no_buff_pkts
;
2782 __le32 bcast_no_buff_pkts
;
2783 __le16 stats_counter
;
2788 * Protocol-common statistics collected by the Ustorm
2790 struct ustorm_common_stats
{
2791 struct ustorm_per_client_stats client_statistics
[MAX_U_STAT_COUNTER_ID
];
2795 * Eth statistics query structure for the eth_stats_query ramrod
2797 struct eth_stats_query
{
2798 struct xstorm_common_stats xstorm_common
;
2799 struct tstorm_common_stats tstorm_common
;
2800 struct ustorm_common_stats ustorm_common
;
2805 * per-vnic fairness variables
2807 struct fairness_vars_per_vn
{
2808 u32 cos_credit_delta
[MAX_COS_NUMBER
];
2809 u32 protocol_credit_delta
[NUM_OF_PROTOCOLS
];
2810 u32 vn_credit_delta
;
2816 * FW version stored in the Xstorm RAM
2819 #if defined(__BIG_ENDIAN)
2824 #elif defined(__LITTLE_ENDIAN)
2831 #define FW_VERSION_OPTIMIZED (0x1<<0)
2832 #define FW_VERSION_OPTIMIZED_SHIFT 0
2833 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2834 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2835 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2836 #define FW_VERSION_CHIP_VERSION_SHIFT 2
2837 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2838 #define __FW_VERSION_RESERVED_SHIFT 4
2843 * FW version stored in first line of pram
2845 struct pram_fw_version
{
2851 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2852 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2853 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2854 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2855 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2856 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2857 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2858 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2859 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2860 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2865 * a single rate shaping counter. can be used as protocol or vnic counter
2867 struct rate_shaping_counter
{
2869 #if defined(__BIG_ENDIAN)
2872 #elif defined(__LITTLE_ENDIAN)
2880 * per-vnic rate shaping variables
2882 struct rate_shaping_vars_per_vn
{
2883 struct rate_shaping_counter protocol_counters
[NUM_OF_PROTOCOLS
];
2884 struct rate_shaping_counter vn_counter
;
2889 * The send queue element
2891 struct slow_path_element
{
2893 u8 protocol_data
[8];
2898 * eth/toe flags that indicate if to query
2900 struct stats_indication_flags
{