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can: Unify MTU settings for CAN interfaces
[mirror_ubuntu-bionic-kernel.git] / drivers / net / can / c_can / c_can.c
1 /*
2 * CAN bus driver for Bosch C_CAN controller
3 *
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
6 *
7 * Borrowed heavily from the C_CAN driver originally written by:
8 * Copyright (C) 2007
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11 *
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
13 * written by:
14 * Copyright
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
17 *
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
22 *
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
26 */
27
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
36 #include <linux/io.h>
37 #include <linux/pm_runtime.h>
38
39 #include <linux/can.h>
40 #include <linux/can/dev.h>
41 #include <linux/can/error.h>
42 #include <linux/can/led.h>
43
44 #include "c_can.h"
45
46 /* Number of interface registers */
47 #define IF_ENUM_REG_LEN 11
48 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
49
50 /* control extension register D_CAN specific */
51 #define CONTROL_EX_PDR BIT(8)
52
53 /* control register */
54 #define CONTROL_TEST BIT(7)
55 #define CONTROL_CCE BIT(6)
56 #define CONTROL_DISABLE_AR BIT(5)
57 #define CONTROL_ENABLE_AR (0 << 5)
58 #define CONTROL_EIE BIT(3)
59 #define CONTROL_SIE BIT(2)
60 #define CONTROL_IE BIT(1)
61 #define CONTROL_INIT BIT(0)
62
63 /* test register */
64 #define TEST_RX BIT(7)
65 #define TEST_TX1 BIT(6)
66 #define TEST_TX2 BIT(5)
67 #define TEST_LBACK BIT(4)
68 #define TEST_SILENT BIT(3)
69 #define TEST_BASIC BIT(2)
70
71 /* status register */
72 #define STATUS_PDA BIT(10)
73 #define STATUS_BOFF BIT(7)
74 #define STATUS_EWARN BIT(6)
75 #define STATUS_EPASS BIT(5)
76 #define STATUS_RXOK BIT(4)
77 #define STATUS_TXOK BIT(3)
78
79 /* error counter register */
80 #define ERR_CNT_TEC_MASK 0xff
81 #define ERR_CNT_TEC_SHIFT 0
82 #define ERR_CNT_REC_SHIFT 8
83 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
84 #define ERR_CNT_RP_SHIFT 15
85 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
86
87 /* bit-timing register */
88 #define BTR_BRP_MASK 0x3f
89 #define BTR_BRP_SHIFT 0
90 #define BTR_SJW_SHIFT 6
91 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
92 #define BTR_TSEG1_SHIFT 8
93 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
94 #define BTR_TSEG2_SHIFT 12
95 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
96
97 /* brp extension register */
98 #define BRP_EXT_BRPE_MASK 0x0f
99 #define BRP_EXT_BRPE_SHIFT 0
100
101 /* IFx command request */
102 #define IF_COMR_BUSY BIT(15)
103
104 /* IFx command mask */
105 #define IF_COMM_WR BIT(7)
106 #define IF_COMM_MASK BIT(6)
107 #define IF_COMM_ARB BIT(5)
108 #define IF_COMM_CONTROL BIT(4)
109 #define IF_COMM_CLR_INT_PND BIT(3)
110 #define IF_COMM_TXRQST BIT(2)
111 #define IF_COMM_DATAA BIT(1)
112 #define IF_COMM_DATAB BIT(0)
113 #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
114 IF_COMM_CONTROL | IF_COMM_TXRQST | \
115 IF_COMM_DATAA | IF_COMM_DATAB)
116
117 /* IFx arbitration */
118 #define IF_ARB_MSGVAL BIT(15)
119 #define IF_ARB_MSGXTD BIT(14)
120 #define IF_ARB_TRANSMIT BIT(13)
121
122 /* IFx message control */
123 #define IF_MCONT_NEWDAT BIT(15)
124 #define IF_MCONT_MSGLST BIT(14)
125 #define IF_MCONT_CLR_MSGLST (0 << 14)
126 #define IF_MCONT_INTPND BIT(13)
127 #define IF_MCONT_UMASK BIT(12)
128 #define IF_MCONT_TXIE BIT(11)
129 #define IF_MCONT_RXIE BIT(10)
130 #define IF_MCONT_RMTEN BIT(9)
131 #define IF_MCONT_TXRQST BIT(8)
132 #define IF_MCONT_EOB BIT(7)
133 #define IF_MCONT_DLC_MASK 0xf
134
135 /*
136 * IFx register masks:
137 * allow easy operation on 16-bit registers when the
138 * argument is 32-bit instead
139 */
140 #define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
141 #define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
142
143 /* message object split */
144 #define C_CAN_NO_OF_OBJECTS 32
145 #define C_CAN_MSG_OBJ_RX_NUM 16
146 #define C_CAN_MSG_OBJ_TX_NUM 16
147
148 #define C_CAN_MSG_OBJ_RX_FIRST 1
149 #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
150 C_CAN_MSG_OBJ_RX_NUM - 1)
151
152 #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
153 #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
154 C_CAN_MSG_OBJ_TX_NUM - 1)
155
156 #define C_CAN_MSG_OBJ_RX_SPLIT 9
157 #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
158
159 #define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
160 #define RECEIVE_OBJECT_BITS 0x0000ffff
161
162 /* status interrupt */
163 #define STATUS_INTERRUPT 0x8000
164
165 /* global interrupt masks */
166 #define ENABLE_ALL_INTERRUPTS 1
167 #define DISABLE_ALL_INTERRUPTS 0
168
169 /* minimum timeout for checking BUSY status */
170 #define MIN_TIMEOUT_VALUE 6
171
172 /* Wait for ~1 sec for INIT bit */
173 #define INIT_WAIT_MS 1000
174
175 /* napi related */
176 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
177
178 /* c_can lec values */
179 enum c_can_lec_type {
180 LEC_NO_ERROR = 0,
181 LEC_STUFF_ERROR,
182 LEC_FORM_ERROR,
183 LEC_ACK_ERROR,
184 LEC_BIT1_ERROR,
185 LEC_BIT0_ERROR,
186 LEC_CRC_ERROR,
187 LEC_UNUSED,
188 };
189
190 /*
191 * c_can error types:
192 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
193 */
194 enum c_can_bus_error_types {
195 C_CAN_NO_ERROR = 0,
196 C_CAN_BUS_OFF,
197 C_CAN_ERROR_WARNING,
198 C_CAN_ERROR_PASSIVE,
199 };
200
201 static const struct can_bittiming_const c_can_bittiming_const = {
202 .name = KBUILD_MODNAME,
203 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
204 .tseg1_max = 16,
205 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
206 .tseg2_max = 8,
207 .sjw_max = 4,
208 .brp_min = 1,
209 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
210 .brp_inc = 1,
211 };
212
213 static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
214 {
215 if (priv->device)
216 pm_runtime_enable(priv->device);
217 }
218
219 static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
220 {
221 if (priv->device)
222 pm_runtime_disable(priv->device);
223 }
224
225 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
226 {
227 if (priv->device)
228 pm_runtime_get_sync(priv->device);
229 }
230
231 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
232 {
233 if (priv->device)
234 pm_runtime_put_sync(priv->device);
235 }
236
237 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
238 {
239 if (priv->raminit)
240 priv->raminit(priv, enable);
241 }
242
243 static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
244 {
245 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
246 C_CAN_MSG_OBJ_TX_FIRST;
247 }
248
249 static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
250 {
251 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
252 C_CAN_MSG_OBJ_TX_FIRST;
253 }
254
255 static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index)
256 {
257 u32 val = priv->read_reg(priv, index);
258 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
259 return val;
260 }
261
262 static void c_can_enable_all_interrupts(struct c_can_priv *priv,
263 int enable)
264 {
265 unsigned int cntrl_save = priv->read_reg(priv,
266 C_CAN_CTRL_REG);
267
268 if (enable)
269 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
270 else
271 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
272
273 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save);
274 }
275
276 static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
277 {
278 int count = MIN_TIMEOUT_VALUE;
279
280 while (count && priv->read_reg(priv,
281 C_CAN_IFACE(COMREQ_REG, iface)) &
282 IF_COMR_BUSY) {
283 count--;
284 udelay(1);
285 }
286
287 if (!count)
288 return 1;
289
290 return 0;
291 }
292
293 static inline void c_can_object_get(struct net_device *dev,
294 int iface, int objno, int mask)
295 {
296 struct c_can_priv *priv = netdev_priv(dev);
297
298 /*
299 * As per specs, after writting the message object number in the
300 * IF command request register the transfer b/w interface
301 * register and message RAM must be complete in 6 CAN-CLK
302 * period.
303 */
304 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
305 IFX_WRITE_LOW_16BIT(mask));
306 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
307 IFX_WRITE_LOW_16BIT(objno));
308
309 if (c_can_msg_obj_is_busy(priv, iface))
310 netdev_err(dev, "timed out in object get\n");
311 }
312
313 static inline void c_can_object_put(struct net_device *dev,
314 int iface, int objno, int mask)
315 {
316 struct c_can_priv *priv = netdev_priv(dev);
317
318 /*
319 * As per specs, after writting the message object number in the
320 * IF command request register the transfer b/w interface
321 * register and message RAM must be complete in 6 CAN-CLK
322 * period.
323 */
324 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
325 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
326 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
327 IFX_WRITE_LOW_16BIT(objno));
328
329 if (c_can_msg_obj_is_busy(priv, iface))
330 netdev_err(dev, "timed out in object put\n");
331 }
332
333 static void c_can_write_msg_object(struct net_device *dev,
334 int iface, struct can_frame *frame, int objno)
335 {
336 int i;
337 u16 flags = 0;
338 unsigned int id;
339 struct c_can_priv *priv = netdev_priv(dev);
340
341 if (!(frame->can_id & CAN_RTR_FLAG))
342 flags |= IF_ARB_TRANSMIT;
343
344 if (frame->can_id & CAN_EFF_FLAG) {
345 id = frame->can_id & CAN_EFF_MASK;
346 flags |= IF_ARB_MSGXTD;
347 } else
348 id = ((frame->can_id & CAN_SFF_MASK) << 18);
349
350 flags |= IF_ARB_MSGVAL;
351
352 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
353 IFX_WRITE_LOW_16BIT(id));
354 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags |
355 IFX_WRITE_HIGH_16BIT(id));
356
357 for (i = 0; i < frame->can_dlc; i += 2) {
358 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
359 frame->data[i] | (frame->data[i + 1] << 8));
360 }
361
362 /* enable interrupt for this message object */
363 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
364 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
365 frame->can_dlc);
366 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
367 }
368
369 static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
370 int iface, int ctrl_mask,
371 int obj)
372 {
373 struct c_can_priv *priv = netdev_priv(dev);
374
375 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
376 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
377 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
378
379 }
380
381 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
382 int iface,
383 int ctrl_mask)
384 {
385 int i;
386 struct c_can_priv *priv = netdev_priv(dev);
387
388 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
389 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
390 ctrl_mask & ~(IF_MCONT_MSGLST |
391 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
392 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
393 }
394 }
395
396 static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
397 int iface, int ctrl_mask,
398 int obj)
399 {
400 struct c_can_priv *priv = netdev_priv(dev);
401
402 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
403 ctrl_mask & ~(IF_MCONT_MSGLST |
404 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
405 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
406 }
407
408 static void c_can_handle_lost_msg_obj(struct net_device *dev,
409 int iface, int objno)
410 {
411 struct c_can_priv *priv = netdev_priv(dev);
412 struct net_device_stats *stats = &dev->stats;
413 struct sk_buff *skb;
414 struct can_frame *frame;
415
416 netdev_err(dev, "msg lost in buffer %d\n", objno);
417
418 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
419
420 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
421 IF_MCONT_CLR_MSGLST);
422
423 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL);
424
425 /* create an error msg */
426 skb = alloc_can_err_skb(dev, &frame);
427 if (unlikely(!skb))
428 return;
429
430 frame->can_id |= CAN_ERR_CRTL;
431 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
432 stats->rx_errors++;
433 stats->rx_over_errors++;
434
435 netif_receive_skb(skb);
436 }
437
438 static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
439 {
440 u16 flags, data;
441 int i;
442 unsigned int val;
443 struct c_can_priv *priv = netdev_priv(dev);
444 struct net_device_stats *stats = &dev->stats;
445 struct sk_buff *skb;
446 struct can_frame *frame;
447
448 skb = alloc_can_skb(dev, &frame);
449 if (!skb) {
450 stats->rx_dropped++;
451 return -ENOMEM;
452 }
453
454 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
455
456 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface));
457 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) |
458 (flags << 16);
459
460 if (flags & IF_ARB_MSGXTD)
461 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
462 else
463 frame->can_id = (val >> 18) & CAN_SFF_MASK;
464
465 if (flags & IF_ARB_TRANSMIT)
466 frame->can_id |= CAN_RTR_FLAG;
467 else {
468 for (i = 0; i < frame->can_dlc; i += 2) {
469 data = priv->read_reg(priv,
470 C_CAN_IFACE(DATA1_REG, iface) + i / 2);
471 frame->data[i] = data;
472 frame->data[i + 1] = data >> 8;
473 }
474 }
475
476 netif_receive_skb(skb);
477
478 stats->rx_packets++;
479 stats->rx_bytes += frame->can_dlc;
480
481 can_led_event(dev, CAN_LED_EVENT_RX);
482
483 return 0;
484 }
485
486 static void c_can_setup_receive_object(struct net_device *dev, int iface,
487 int objno, unsigned int mask,
488 unsigned int id, unsigned int mcont)
489 {
490 struct c_can_priv *priv = netdev_priv(dev);
491
492 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface),
493 IFX_WRITE_LOW_16BIT(mask));
494
495 /* According to C_CAN documentation, the reserved bit
496 * in IFx_MASK2 register is fixed 1
497 */
498 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface),
499 IFX_WRITE_HIGH_16BIT(mask) | BIT(13));
500
501 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
502 IFX_WRITE_LOW_16BIT(id));
503 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface),
504 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
505
506 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
507 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
508
509 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
510 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
511 }
512
513 static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
514 {
515 struct c_can_priv *priv = netdev_priv(dev);
516
517 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
518 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
519 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
520
521 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
522
523 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
524 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
525 }
526
527 static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
528 {
529 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
530
531 /*
532 * as transmission request register's bit n-1 corresponds to
533 * message object n, we need to handle the same properly.
534 */
535 if (val & (1 << (objno - 1)))
536 return 1;
537
538 return 0;
539 }
540
541 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
542 struct net_device *dev)
543 {
544 u32 msg_obj_no;
545 struct c_can_priv *priv = netdev_priv(dev);
546 struct can_frame *frame = (struct can_frame *)skb->data;
547
548 if (can_dropped_invalid_skb(dev, skb))
549 return NETDEV_TX_OK;
550
551 msg_obj_no = get_tx_next_msg_obj(priv);
552
553 /* prepare message object for transmission */
554 c_can_write_msg_object(dev, 0, frame, msg_obj_no);
555 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
556
557 /*
558 * we have to stop the queue in case of a wrap around or
559 * if the next TX message object is still in use
560 */
561 priv->tx_next++;
562 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
563 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
564 netif_stop_queue(dev);
565
566 return NETDEV_TX_OK;
567 }
568
569 static int c_can_set_bittiming(struct net_device *dev)
570 {
571 unsigned int reg_btr, reg_brpe, ctrl_save;
572 u8 brp, brpe, sjw, tseg1, tseg2;
573 u32 ten_bit_brp;
574 struct c_can_priv *priv = netdev_priv(dev);
575 const struct can_bittiming *bt = &priv->can.bittiming;
576
577 /* c_can provides a 6-bit brp and 4-bit brpe fields */
578 ten_bit_brp = bt->brp - 1;
579 brp = ten_bit_brp & BTR_BRP_MASK;
580 brpe = ten_bit_brp >> 6;
581
582 sjw = bt->sjw - 1;
583 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
584 tseg2 = bt->phase_seg2 - 1;
585 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
586 (tseg2 << BTR_TSEG2_SHIFT);
587 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
588
589 netdev_info(dev,
590 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
591
592 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
593 priv->write_reg(priv, C_CAN_CTRL_REG,
594 ctrl_save | CONTROL_CCE | CONTROL_INIT);
595 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
596 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
597 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
598
599 return 0;
600 }
601
602 /*
603 * Configure C_CAN message objects for Tx and Rx purposes:
604 * C_CAN provides a total of 32 message objects that can be configured
605 * either for Tx or Rx purposes. Here the first 16 message objects are used as
606 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
607 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
608 * See user guide document for further details on configuring message
609 * objects.
610 */
611 static void c_can_configure_msg_objects(struct net_device *dev)
612 {
613 int i;
614
615 /* first invalidate all message objects */
616 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
617 c_can_inval_msg_object(dev, 0, i);
618
619 /* setup receive message objects */
620 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
621 c_can_setup_receive_object(dev, 0, i, 0, 0,
622 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
623
624 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
625 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
626 }
627
628 /*
629 * Configure C_CAN chip:
630 * - enable/disable auto-retransmission
631 * - set operating mode
632 * - configure message objects
633 */
634 static void c_can_chip_config(struct net_device *dev)
635 {
636 struct c_can_priv *priv = netdev_priv(dev);
637
638 /* enable automatic retransmission */
639 priv->write_reg(priv, C_CAN_CTRL_REG,
640 CONTROL_ENABLE_AR);
641
642 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
643 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
644 /* loopback + silent mode : useful for hot self-test */
645 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
646 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
647 priv->write_reg(priv, C_CAN_TEST_REG,
648 TEST_LBACK | TEST_SILENT);
649 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
650 /* loopback mode : useful for self-test function */
651 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
652 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
653 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
654 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
655 /* silent mode : bus-monitoring mode */
656 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
657 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
658 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
659 } else
660 /* normal mode*/
661 priv->write_reg(priv, C_CAN_CTRL_REG,
662 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
663
664 /* configure message objects */
665 c_can_configure_msg_objects(dev);
666
667 /* set a `lec` value so that we can check for updates later */
668 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
669
670 /* set bittiming params */
671 c_can_set_bittiming(dev);
672 }
673
674 static void c_can_start(struct net_device *dev)
675 {
676 struct c_can_priv *priv = netdev_priv(dev);
677
678 /* basic c_can configuration */
679 c_can_chip_config(dev);
680
681 priv->can.state = CAN_STATE_ERROR_ACTIVE;
682
683 /* reset tx helper pointers */
684 priv->tx_next = priv->tx_echo = 0;
685
686 /* enable status change, error and module interrupts */
687 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
688 }
689
690 static void c_can_stop(struct net_device *dev)
691 {
692 struct c_can_priv *priv = netdev_priv(dev);
693
694 /* disable all interrupts */
695 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
696
697 /* set the state as STOPPED */
698 priv->can.state = CAN_STATE_STOPPED;
699 }
700
701 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
702 {
703 switch (mode) {
704 case CAN_MODE_START:
705 c_can_start(dev);
706 netif_wake_queue(dev);
707 break;
708 default:
709 return -EOPNOTSUPP;
710 }
711
712 return 0;
713 }
714
715 static int __c_can_get_berr_counter(const struct net_device *dev,
716 struct can_berr_counter *bec)
717 {
718 unsigned int reg_err_counter;
719 struct c_can_priv *priv = netdev_priv(dev);
720
721 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
722 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
723 ERR_CNT_REC_SHIFT;
724 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
725
726 return 0;
727 }
728
729 static int c_can_get_berr_counter(const struct net_device *dev,
730 struct can_berr_counter *bec)
731 {
732 struct c_can_priv *priv = netdev_priv(dev);
733 int err;
734
735 c_can_pm_runtime_get_sync(priv);
736 err = __c_can_get_berr_counter(dev, bec);
737 c_can_pm_runtime_put_sync(priv);
738
739 return err;
740 }
741
742 /*
743 * theory of operation:
744 *
745 * priv->tx_echo holds the number of the oldest can_frame put for
746 * transmission into the hardware, but not yet ACKed by the CAN tx
747 * complete IRQ.
748 *
749 * We iterate from priv->tx_echo to priv->tx_next and check if the
750 * packet has been transmitted, echo it back to the CAN framework.
751 * If we discover a not yet transmitted packet, stop looking for more.
752 */
753 static void c_can_do_tx(struct net_device *dev)
754 {
755 u32 val;
756 u32 msg_obj_no;
757 struct c_can_priv *priv = netdev_priv(dev);
758 struct net_device_stats *stats = &dev->stats;
759
760 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
761 msg_obj_no = get_tx_echo_msg_obj(priv);
762 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
763 if (!(val & (1 << (msg_obj_no - 1)))) {
764 can_get_echo_skb(dev,
765 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
766 c_can_object_get(dev, 0, msg_obj_no, IF_COMM_ALL);
767 stats->tx_bytes += priv->read_reg(priv,
768 C_CAN_IFACE(MSGCTRL_REG, 0))
769 & IF_MCONT_DLC_MASK;
770 stats->tx_packets++;
771 can_led_event(dev, CAN_LED_EVENT_TX);
772 c_can_inval_msg_object(dev, 0, msg_obj_no);
773 } else {
774 break;
775 }
776 }
777
778 /* restart queue if wrap-up or if queue stalled on last pkt */
779 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
780 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
781 netif_wake_queue(dev);
782 }
783
784 /*
785 * theory of operation:
786 *
787 * c_can core saves a received CAN message into the first free message
788 * object it finds free (starting with the lowest). Bits NEWDAT and
789 * INTPND are set for this message object indicating that a new message
790 * has arrived. To work-around this issue, we keep two groups of message
791 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
792 *
793 * To ensure in-order frame reception we use the following
794 * approach while re-activating a message object to receive further
795 * frames:
796 * - if the current message object number is lower than
797 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
798 * the INTPND bit.
799 * - if the current message object number is equal to
800 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
801 * receive message objects.
802 * - if the current message object number is greater than
803 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
804 * only this message object.
805 */
806 static int c_can_do_rx_poll(struct net_device *dev, int quota)
807 {
808 u32 num_rx_pkts = 0;
809 unsigned int msg_obj, msg_ctrl_save;
810 struct c_can_priv *priv = netdev_priv(dev);
811 u16 val;
812
813 /*
814 * It is faster to read only one 16bit register. This is only possible
815 * for a maximum number of 16 objects.
816 */
817 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16,
818 "Implementation does not support more message objects than 16");
819
820 while (quota > 0 && (val = priv->read_reg(priv, C_CAN_INTPND1_REG))) {
821 while ((msg_obj = ffs(val)) && quota > 0) {
822 val &= ~BIT(msg_obj - 1);
823
824 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL &
825 ~IF_COMM_TXRQST);
826 msg_ctrl_save = priv->read_reg(priv,
827 C_CAN_IFACE(MSGCTRL_REG, 0));
828
829 if (msg_ctrl_save & IF_MCONT_MSGLST) {
830 c_can_handle_lost_msg_obj(dev, 0, msg_obj);
831 num_rx_pkts++;
832 quota--;
833 continue;
834 }
835
836 if (msg_ctrl_save & IF_MCONT_EOB)
837 return num_rx_pkts;
838
839 if (!(msg_ctrl_save & IF_MCONT_NEWDAT))
840 continue;
841
842 /* read the data from the message object */
843 c_can_read_msg_object(dev, 0, msg_ctrl_save);
844
845 if (msg_obj < C_CAN_MSG_RX_LOW_LAST)
846 c_can_mark_rx_msg_obj(dev, 0,
847 msg_ctrl_save, msg_obj);
848 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST)
849 /* activate this msg obj */
850 c_can_activate_rx_msg_obj(dev, 0,
851 msg_ctrl_save, msg_obj);
852 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST)
853 /* activate all lower message objects */
854 c_can_activate_all_lower_rx_msg_obj(dev,
855 0, msg_ctrl_save);
856
857 num_rx_pkts++;
858 quota--;
859 }
860 }
861
862 return num_rx_pkts;
863 }
864
865 static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
866 {
867 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
868 (priv->current_status & LEC_UNUSED);
869 }
870
871 static int c_can_handle_state_change(struct net_device *dev,
872 enum c_can_bus_error_types error_type)
873 {
874 unsigned int reg_err_counter;
875 unsigned int rx_err_passive;
876 struct c_can_priv *priv = netdev_priv(dev);
877 struct net_device_stats *stats = &dev->stats;
878 struct can_frame *cf;
879 struct sk_buff *skb;
880 struct can_berr_counter bec;
881
882 /* propagate the error condition to the CAN stack */
883 skb = alloc_can_err_skb(dev, &cf);
884 if (unlikely(!skb))
885 return 0;
886
887 __c_can_get_berr_counter(dev, &bec);
888 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
889 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
890 ERR_CNT_RP_SHIFT;
891
892 switch (error_type) {
893 case C_CAN_ERROR_WARNING:
894 /* error warning state */
895 priv->can.can_stats.error_warning++;
896 priv->can.state = CAN_STATE_ERROR_WARNING;
897 cf->can_id |= CAN_ERR_CRTL;
898 cf->data[1] = (bec.txerr > bec.rxerr) ?
899 CAN_ERR_CRTL_TX_WARNING :
900 CAN_ERR_CRTL_RX_WARNING;
901 cf->data[6] = bec.txerr;
902 cf->data[7] = bec.rxerr;
903
904 break;
905 case C_CAN_ERROR_PASSIVE:
906 /* error passive state */
907 priv->can.can_stats.error_passive++;
908 priv->can.state = CAN_STATE_ERROR_PASSIVE;
909 cf->can_id |= CAN_ERR_CRTL;
910 if (rx_err_passive)
911 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
912 if (bec.txerr > 127)
913 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
914
915 cf->data[6] = bec.txerr;
916 cf->data[7] = bec.rxerr;
917 break;
918 case C_CAN_BUS_OFF:
919 /* bus-off state */
920 priv->can.state = CAN_STATE_BUS_OFF;
921 cf->can_id |= CAN_ERR_BUSOFF;
922 /*
923 * disable all interrupts in bus-off mode to ensure that
924 * the CPU is not hogged down
925 */
926 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
927 can_bus_off(dev);
928 break;
929 default:
930 break;
931 }
932
933 netif_receive_skb(skb);
934 stats->rx_packets++;
935 stats->rx_bytes += cf->can_dlc;
936
937 return 1;
938 }
939
940 static int c_can_handle_bus_err(struct net_device *dev,
941 enum c_can_lec_type lec_type)
942 {
943 struct c_can_priv *priv = netdev_priv(dev);
944 struct net_device_stats *stats = &dev->stats;
945 struct can_frame *cf;
946 struct sk_buff *skb;
947
948 /*
949 * early exit if no lec update or no error.
950 * no lec update means that no CAN bus event has been detected
951 * since CPU wrote 0x7 value to status reg.
952 */
953 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
954 return 0;
955
956 /* propagate the error condition to the CAN stack */
957 skb = alloc_can_err_skb(dev, &cf);
958 if (unlikely(!skb))
959 return 0;
960
961 /*
962 * check for 'last error code' which tells us the
963 * type of the last error to occur on the CAN bus
964 */
965
966 /* common for all type of bus errors */
967 priv->can.can_stats.bus_error++;
968 stats->rx_errors++;
969 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
970 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
971
972 switch (lec_type) {
973 case LEC_STUFF_ERROR:
974 netdev_dbg(dev, "stuff error\n");
975 cf->data[2] |= CAN_ERR_PROT_STUFF;
976 break;
977 case LEC_FORM_ERROR:
978 netdev_dbg(dev, "form error\n");
979 cf->data[2] |= CAN_ERR_PROT_FORM;
980 break;
981 case LEC_ACK_ERROR:
982 netdev_dbg(dev, "ack error\n");
983 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
984 CAN_ERR_PROT_LOC_ACK_DEL);
985 break;
986 case LEC_BIT1_ERROR:
987 netdev_dbg(dev, "bit1 error\n");
988 cf->data[2] |= CAN_ERR_PROT_BIT1;
989 break;
990 case LEC_BIT0_ERROR:
991 netdev_dbg(dev, "bit0 error\n");
992 cf->data[2] |= CAN_ERR_PROT_BIT0;
993 break;
994 case LEC_CRC_ERROR:
995 netdev_dbg(dev, "CRC error\n");
996 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
997 CAN_ERR_PROT_LOC_CRC_DEL);
998 break;
999 default:
1000 break;
1001 }
1002
1003 /* set a `lec` value so that we can check for updates later */
1004 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1005
1006 netif_receive_skb(skb);
1007 stats->rx_packets++;
1008 stats->rx_bytes += cf->can_dlc;
1009
1010 return 1;
1011 }
1012
1013 static int c_can_poll(struct napi_struct *napi, int quota)
1014 {
1015 u16 irqstatus;
1016 int lec_type = 0;
1017 int work_done = 0;
1018 struct net_device *dev = napi->dev;
1019 struct c_can_priv *priv = netdev_priv(dev);
1020
1021 irqstatus = priv->irqstatus;
1022 if (!irqstatus)
1023 goto end;
1024
1025 /* status events have the highest priority */
1026 if (irqstatus == STATUS_INTERRUPT) {
1027 priv->current_status = priv->read_reg(priv,
1028 C_CAN_STS_REG);
1029
1030 /* handle Tx/Rx events */
1031 if (priv->current_status & STATUS_TXOK)
1032 priv->write_reg(priv, C_CAN_STS_REG,
1033 priv->current_status & ~STATUS_TXOK);
1034
1035 if (priv->current_status & STATUS_RXOK)
1036 priv->write_reg(priv, C_CAN_STS_REG,
1037 priv->current_status & ~STATUS_RXOK);
1038
1039 /* handle state changes */
1040 if ((priv->current_status & STATUS_EWARN) &&
1041 (!(priv->last_status & STATUS_EWARN))) {
1042 netdev_dbg(dev, "entered error warning state\n");
1043 work_done += c_can_handle_state_change(dev,
1044 C_CAN_ERROR_WARNING);
1045 }
1046 if ((priv->current_status & STATUS_EPASS) &&
1047 (!(priv->last_status & STATUS_EPASS))) {
1048 netdev_dbg(dev, "entered error passive state\n");
1049 work_done += c_can_handle_state_change(dev,
1050 C_CAN_ERROR_PASSIVE);
1051 }
1052 if ((priv->current_status & STATUS_BOFF) &&
1053 (!(priv->last_status & STATUS_BOFF))) {
1054 netdev_dbg(dev, "entered bus off state\n");
1055 work_done += c_can_handle_state_change(dev,
1056 C_CAN_BUS_OFF);
1057 }
1058
1059 /* handle bus recovery events */
1060 if ((!(priv->current_status & STATUS_BOFF)) &&
1061 (priv->last_status & STATUS_BOFF)) {
1062 netdev_dbg(dev, "left bus off state\n");
1063 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1064 }
1065 if ((!(priv->current_status & STATUS_EPASS)) &&
1066 (priv->last_status & STATUS_EPASS)) {
1067 netdev_dbg(dev, "left error passive state\n");
1068 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1069 }
1070
1071 priv->last_status = priv->current_status;
1072
1073 /* handle lec errors on the bus */
1074 lec_type = c_can_has_and_handle_berr(priv);
1075 if (lec_type)
1076 work_done += c_can_handle_bus_err(dev, lec_type);
1077 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
1078 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
1079 /* handle events corresponding to receive message objects */
1080 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1081 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
1082 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
1083 /* handle events corresponding to transmit message objects */
1084 c_can_do_tx(dev);
1085 }
1086
1087 end:
1088 if (work_done < quota) {
1089 napi_complete(napi);
1090 /* enable all IRQs */
1091 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
1092 }
1093
1094 return work_done;
1095 }
1096
1097 static irqreturn_t c_can_isr(int irq, void *dev_id)
1098 {
1099 struct net_device *dev = (struct net_device *)dev_id;
1100 struct c_can_priv *priv = netdev_priv(dev);
1101
1102 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG);
1103 if (!priv->irqstatus)
1104 return IRQ_NONE;
1105
1106 /* disable all interrupts and schedule the NAPI */
1107 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1108 napi_schedule(&priv->napi);
1109
1110 return IRQ_HANDLED;
1111 }
1112
1113 static int c_can_open(struct net_device *dev)
1114 {
1115 int err;
1116 struct c_can_priv *priv = netdev_priv(dev);
1117
1118 c_can_pm_runtime_get_sync(priv);
1119 c_can_reset_ram(priv, true);
1120
1121 /* open the can device */
1122 err = open_candev(dev);
1123 if (err) {
1124 netdev_err(dev, "failed to open can device\n");
1125 goto exit_open_fail;
1126 }
1127
1128 /* register interrupt handler */
1129 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1130 dev);
1131 if (err < 0) {
1132 netdev_err(dev, "failed to request interrupt\n");
1133 goto exit_irq_fail;
1134 }
1135
1136 napi_enable(&priv->napi);
1137
1138 can_led_event(dev, CAN_LED_EVENT_OPEN);
1139
1140 /* start the c_can controller */
1141 c_can_start(dev);
1142
1143 netif_start_queue(dev);
1144
1145 return 0;
1146
1147 exit_irq_fail:
1148 close_candev(dev);
1149 exit_open_fail:
1150 c_can_reset_ram(priv, false);
1151 c_can_pm_runtime_put_sync(priv);
1152 return err;
1153 }
1154
1155 static int c_can_close(struct net_device *dev)
1156 {
1157 struct c_can_priv *priv = netdev_priv(dev);
1158
1159 netif_stop_queue(dev);
1160 napi_disable(&priv->napi);
1161 c_can_stop(dev);
1162 free_irq(dev->irq, dev);
1163 close_candev(dev);
1164
1165 c_can_reset_ram(priv, false);
1166 c_can_pm_runtime_put_sync(priv);
1167
1168 can_led_event(dev, CAN_LED_EVENT_STOP);
1169
1170 return 0;
1171 }
1172
1173 struct net_device *alloc_c_can_dev(void)
1174 {
1175 struct net_device *dev;
1176 struct c_can_priv *priv;
1177
1178 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1179 if (!dev)
1180 return NULL;
1181
1182 priv = netdev_priv(dev);
1183 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1184
1185 priv->dev = dev;
1186 priv->can.bittiming_const = &c_can_bittiming_const;
1187 priv->can.do_set_mode = c_can_set_mode;
1188 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1189 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1190 CAN_CTRLMODE_LISTENONLY |
1191 CAN_CTRLMODE_BERR_REPORTING;
1192
1193 return dev;
1194 }
1195 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1196
1197 #ifdef CONFIG_PM
1198 int c_can_power_down(struct net_device *dev)
1199 {
1200 u32 val;
1201 unsigned long time_out;
1202 struct c_can_priv *priv = netdev_priv(dev);
1203
1204 if (!(dev->flags & IFF_UP))
1205 return 0;
1206
1207 WARN_ON(priv->type != BOSCH_D_CAN);
1208
1209 /* set PDR value so the device goes to power down mode */
1210 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1211 val |= CONTROL_EX_PDR;
1212 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1213
1214 /* Wait for the PDA bit to get set */
1215 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1216 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1217 time_after(time_out, jiffies))
1218 cpu_relax();
1219
1220 if (time_after(jiffies, time_out))
1221 return -ETIMEDOUT;
1222
1223 c_can_stop(dev);
1224
1225 c_can_reset_ram(priv, false);
1226 c_can_pm_runtime_put_sync(priv);
1227
1228 return 0;
1229 }
1230 EXPORT_SYMBOL_GPL(c_can_power_down);
1231
1232 int c_can_power_up(struct net_device *dev)
1233 {
1234 u32 val;
1235 unsigned long time_out;
1236 struct c_can_priv *priv = netdev_priv(dev);
1237
1238 if (!(dev->flags & IFF_UP))
1239 return 0;
1240
1241 WARN_ON(priv->type != BOSCH_D_CAN);
1242
1243 c_can_pm_runtime_get_sync(priv);
1244 c_can_reset_ram(priv, true);
1245
1246 /* Clear PDR and INIT bits */
1247 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1248 val &= ~CONTROL_EX_PDR;
1249 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1250 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1251 val &= ~CONTROL_INIT;
1252 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1253
1254 /* Wait for the PDA bit to get clear */
1255 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1256 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1257 time_after(time_out, jiffies))
1258 cpu_relax();
1259
1260 if (time_after(jiffies, time_out))
1261 return -ETIMEDOUT;
1262
1263 c_can_start(dev);
1264
1265 return 0;
1266 }
1267 EXPORT_SYMBOL_GPL(c_can_power_up);
1268 #endif
1269
1270 void free_c_can_dev(struct net_device *dev)
1271 {
1272 free_candev(dev);
1273 }
1274 EXPORT_SYMBOL_GPL(free_c_can_dev);
1275
1276 static const struct net_device_ops c_can_netdev_ops = {
1277 .ndo_open = c_can_open,
1278 .ndo_stop = c_can_close,
1279 .ndo_start_xmit = c_can_start_xmit,
1280 .ndo_change_mtu = can_change_mtu,
1281 };
1282
1283 int register_c_can_dev(struct net_device *dev)
1284 {
1285 struct c_can_priv *priv = netdev_priv(dev);
1286 int err;
1287
1288 c_can_pm_runtime_enable(priv);
1289
1290 dev->flags |= IFF_ECHO; /* we support local echo */
1291 dev->netdev_ops = &c_can_netdev_ops;
1292
1293 err = register_candev(dev);
1294 if (err)
1295 c_can_pm_runtime_disable(priv);
1296 else
1297 devm_can_led_init(dev);
1298
1299 return err;
1300 }
1301 EXPORT_SYMBOL_GPL(register_c_can_dev);
1302
1303 void unregister_c_can_dev(struct net_device *dev)
1304 {
1305 struct c_can_priv *priv = netdev_priv(dev);
1306
1307 unregister_candev(dev);
1308
1309 c_can_pm_runtime_disable(priv);
1310 }
1311 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1312
1313 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1314 MODULE_LICENSE("GPL v2");
1315 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");
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