2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/pinctrl/consumer.h>
40 #include <linux/can.h>
41 #include <linux/can/dev.h>
42 #include <linux/can/error.h>
43 #include <linux/can/led.h>
47 /* Number of interface registers */
48 #define IF_ENUM_REG_LEN 11
49 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
51 /* control extension register D_CAN specific */
52 #define CONTROL_EX_PDR BIT(8)
54 /* control register */
55 #define CONTROL_TEST BIT(7)
56 #define CONTROL_CCE BIT(6)
57 #define CONTROL_DISABLE_AR BIT(5)
58 #define CONTROL_ENABLE_AR (0 << 5)
59 #define CONTROL_EIE BIT(3)
60 #define CONTROL_SIE BIT(2)
61 #define CONTROL_IE BIT(1)
62 #define CONTROL_INIT BIT(0)
64 #define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
67 #define TEST_RX BIT(7)
68 #define TEST_TX1 BIT(6)
69 #define TEST_TX2 BIT(5)
70 #define TEST_LBACK BIT(4)
71 #define TEST_SILENT BIT(3)
72 #define TEST_BASIC BIT(2)
75 #define STATUS_PDA BIT(10)
76 #define STATUS_BOFF BIT(7)
77 #define STATUS_EWARN BIT(6)
78 #define STATUS_EPASS BIT(5)
79 #define STATUS_RXOK BIT(4)
80 #define STATUS_TXOK BIT(3)
82 /* error counter register */
83 #define ERR_CNT_TEC_MASK 0xff
84 #define ERR_CNT_TEC_SHIFT 0
85 #define ERR_CNT_REC_SHIFT 8
86 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
87 #define ERR_CNT_RP_SHIFT 15
88 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
90 /* bit-timing register */
91 #define BTR_BRP_MASK 0x3f
92 #define BTR_BRP_SHIFT 0
93 #define BTR_SJW_SHIFT 6
94 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
95 #define BTR_TSEG1_SHIFT 8
96 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
97 #define BTR_TSEG2_SHIFT 12
98 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
100 /* brp extension register */
101 #define BRP_EXT_BRPE_MASK 0x0f
102 #define BRP_EXT_BRPE_SHIFT 0
104 /* IFx command request */
105 #define IF_COMR_BUSY BIT(15)
107 /* IFx command mask */
108 #define IF_COMM_WR BIT(7)
109 #define IF_COMM_MASK BIT(6)
110 #define IF_COMM_ARB BIT(5)
111 #define IF_COMM_CONTROL BIT(4)
112 #define IF_COMM_CLR_INT_PND BIT(3)
113 #define IF_COMM_TXRQST BIT(2)
114 #define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
115 #define IF_COMM_DATAA BIT(1)
116 #define IF_COMM_DATAB BIT(0)
118 /* TX buffer setup */
119 #define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \
121 IF_COMM_DATAA | IF_COMM_DATAB)
123 /* For the low buffers we clear the interrupt bit, but keep newdat */
124 #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
125 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
126 IF_COMM_DATAA | IF_COMM_DATAB)
128 /* For the high buffers we clear the interrupt bit and newdat */
129 #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
132 /* Receive setup of message objects */
133 #define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
135 /* Invalidation of message objects */
136 #define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL)
138 /* IFx arbitration */
139 #define IF_ARB_MSGVAL BIT(31)
140 #define IF_ARB_MSGXTD BIT(30)
141 #define IF_ARB_TRANSMIT BIT(29)
143 /* IFx message control */
144 #define IF_MCONT_NEWDAT BIT(15)
145 #define IF_MCONT_MSGLST BIT(14)
146 #define IF_MCONT_INTPND BIT(13)
147 #define IF_MCONT_UMASK BIT(12)
148 #define IF_MCONT_TXIE BIT(11)
149 #define IF_MCONT_RXIE BIT(10)
150 #define IF_MCONT_RMTEN BIT(9)
151 #define IF_MCONT_TXRQST BIT(8)
152 #define IF_MCONT_EOB BIT(7)
153 #define IF_MCONT_DLC_MASK 0xf
155 #define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
156 #define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
158 #define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB)
161 * Use IF1 for RX and IF2 for TX
166 /* minimum timeout for checking BUSY status */
167 #define MIN_TIMEOUT_VALUE 6
169 /* Wait for ~1 sec for INIT bit */
170 #define INIT_WAIT_MS 1000
173 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
175 /* c_can lec values */
176 enum c_can_lec_type
{
185 LEC_MASK
= LEC_UNUSED
,
190 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
192 enum c_can_bus_error_types
{
199 static const struct can_bittiming_const c_can_bittiming_const
= {
200 .name
= KBUILD_MODNAME
,
201 .tseg1_min
= 2, /* Time segment 1 = prop_seg + phase_seg1 */
203 .tseg2_min
= 1, /* Time segment 2 = phase_seg2 */
207 .brp_max
= 1024, /* 6-bit BRP field + 4-bit BRPE field*/
211 static inline void c_can_pm_runtime_enable(const struct c_can_priv
*priv
)
214 pm_runtime_enable(priv
->device
);
217 static inline void c_can_pm_runtime_disable(const struct c_can_priv
*priv
)
220 pm_runtime_disable(priv
->device
);
223 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv
*priv
)
226 pm_runtime_get_sync(priv
->device
);
229 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv
*priv
)
232 pm_runtime_put_sync(priv
->device
);
235 static inline void c_can_reset_ram(const struct c_can_priv
*priv
, bool enable
)
238 priv
->raminit(priv
, enable
);
241 static void c_can_irq_control(struct c_can_priv
*priv
, bool enable
)
243 u32 ctrl
= priv
->read_reg(priv
, C_CAN_CTRL_REG
) & ~CONTROL_IRQMSK
;
246 ctrl
|= CONTROL_IRQMSK
;
248 priv
->write_reg(priv
, C_CAN_CTRL_REG
, ctrl
);
251 static void c_can_obj_update(struct net_device
*dev
, int iface
, u32 cmd
, u32 obj
)
253 struct c_can_priv
*priv
= netdev_priv(dev
);
254 int cnt
, reg
= C_CAN_IFACE(COMREQ_REG
, iface
);
256 priv
->write_reg32(priv
, reg
, (cmd
<< 16) | obj
);
258 for (cnt
= MIN_TIMEOUT_VALUE
; cnt
; cnt
--) {
259 if (!(priv
->read_reg(priv
, reg
) & IF_COMR_BUSY
))
263 netdev_err(dev
, "Updating object timed out\n");
267 static inline void c_can_object_get(struct net_device
*dev
, int iface
,
270 c_can_obj_update(dev
, iface
, cmd
, obj
);
273 static inline void c_can_object_put(struct net_device
*dev
, int iface
,
276 c_can_obj_update(dev
, iface
, cmd
| IF_COMM_WR
, obj
);
280 * Note: According to documentation clearing TXIE while MSGVAL is set
281 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
282 * load significantly.
284 static void c_can_inval_tx_object(struct net_device
*dev
, int iface
, int obj
)
286 struct c_can_priv
*priv
= netdev_priv(dev
);
288 priv
->write_reg(priv
, C_CAN_IFACE(MSGCTRL_REG
, iface
), 0);
289 c_can_object_put(dev
, iface
, obj
, IF_COMM_INVAL
);
292 static void c_can_inval_msg_object(struct net_device
*dev
, int iface
, int obj
)
294 struct c_can_priv
*priv
= netdev_priv(dev
);
296 priv
->write_reg(priv
, C_CAN_IFACE(ARB1_REG
, iface
), 0);
297 priv
->write_reg(priv
, C_CAN_IFACE(ARB2_REG
, iface
), 0);
298 c_can_inval_tx_object(dev
, iface
, obj
);
301 static void c_can_setup_tx_object(struct net_device
*dev
, int iface
,
302 struct can_frame
*frame
, int idx
)
304 struct c_can_priv
*priv
= netdev_priv(dev
);
305 u16 ctrl
= IF_MCONT_TX
| frame
->can_dlc
;
306 bool rtr
= frame
->can_id
& CAN_RTR_FLAG
;
307 u32 arb
= IF_ARB_MSGVAL
;
310 if (frame
->can_id
& CAN_EFF_FLAG
) {
311 arb
|= frame
->can_id
& CAN_EFF_MASK
;
312 arb
|= IF_ARB_MSGXTD
;
314 arb
|= (frame
->can_id
& CAN_SFF_MASK
) << 18;
318 arb
|= IF_ARB_TRANSMIT
;
321 * If we change the DIR bit, we need to invalidate the buffer
322 * first, i.e. clear the MSGVAL flag in the arbiter.
324 if (rtr
!= (bool)test_bit(idx
, &priv
->tx_dir
)) {
325 u32 obj
= idx
+ C_CAN_MSG_OBJ_TX_FIRST
;
327 c_can_inval_msg_object(dev
, iface
, obj
);
328 change_bit(idx
, &priv
->tx_dir
);
331 priv
->write_reg32(priv
, C_CAN_IFACE(ARB1_REG
, iface
), arb
);
333 priv
->write_reg(priv
, C_CAN_IFACE(MSGCTRL_REG
, iface
), ctrl
);
335 for (i
= 0; i
< frame
->can_dlc
; i
+= 2) {
336 priv
->write_reg(priv
, C_CAN_IFACE(DATA1_REG
, iface
) + i
/ 2,
337 frame
->data
[i
] | (frame
->data
[i
+ 1] << 8));
341 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device
*dev
,
346 for (i
= C_CAN_MSG_OBJ_RX_FIRST
; i
<= C_CAN_MSG_RX_LOW_LAST
; i
++)
347 c_can_object_get(dev
, iface
, i
, IF_COMM_CLR_NEWDAT
);
350 static int c_can_handle_lost_msg_obj(struct net_device
*dev
,
351 int iface
, int objno
, u32 ctrl
)
353 struct net_device_stats
*stats
= &dev
->stats
;
354 struct c_can_priv
*priv
= netdev_priv(dev
);
355 struct can_frame
*frame
;
358 ctrl
&= ~(IF_MCONT_MSGLST
| IF_MCONT_INTPND
| IF_MCONT_NEWDAT
);
359 priv
->write_reg(priv
, C_CAN_IFACE(MSGCTRL_REG
, iface
), ctrl
);
360 c_can_object_put(dev
, iface
, objno
, IF_COMM_CONTROL
);
363 stats
->rx_over_errors
++;
365 /* create an error msg */
366 skb
= alloc_can_err_skb(dev
, &frame
);
370 frame
->can_id
|= CAN_ERR_CRTL
;
371 frame
->data
[1] = CAN_ERR_CRTL_RX_OVERFLOW
;
373 netif_receive_skb(skb
);
377 static int c_can_read_msg_object(struct net_device
*dev
, int iface
, u32 ctrl
)
379 struct net_device_stats
*stats
= &dev
->stats
;
380 struct c_can_priv
*priv
= netdev_priv(dev
);
381 struct can_frame
*frame
;
385 skb
= alloc_can_skb(dev
, &frame
);
391 frame
->can_dlc
= get_can_dlc(ctrl
& 0x0F);
393 arb
= priv
->read_reg32(priv
, C_CAN_IFACE(ARB1_REG
, iface
));
395 if (arb
& IF_ARB_MSGXTD
)
396 frame
->can_id
= (arb
& CAN_EFF_MASK
) | CAN_EFF_FLAG
;
398 frame
->can_id
= (arb
>> 18) & CAN_SFF_MASK
;
400 if (arb
& IF_ARB_TRANSMIT
) {
401 frame
->can_id
|= CAN_RTR_FLAG
;
403 int i
, dreg
= C_CAN_IFACE(DATA1_REG
, iface
);
405 for (i
= 0; i
< frame
->can_dlc
; i
+= 2, dreg
++) {
406 data
= priv
->read_reg(priv
, dreg
);
407 frame
->data
[i
] = data
;
408 frame
->data
[i
+ 1] = data
>> 8;
413 stats
->rx_bytes
+= frame
->can_dlc
;
415 netif_receive_skb(skb
);
419 static void c_can_setup_receive_object(struct net_device
*dev
, int iface
,
420 u32 obj
, u32 mask
, u32 id
, u32 mcont
)
422 struct c_can_priv
*priv
= netdev_priv(dev
);
425 priv
->write_reg32(priv
, C_CAN_IFACE(MASK1_REG
, iface
), mask
);
428 priv
->write_reg32(priv
, C_CAN_IFACE(ARB1_REG
, iface
), id
);
430 priv
->write_reg(priv
, C_CAN_IFACE(MSGCTRL_REG
, iface
), mcont
);
431 c_can_object_put(dev
, iface
, obj
, IF_COMM_RCV_SETUP
);
434 static netdev_tx_t
c_can_start_xmit(struct sk_buff
*skb
,
435 struct net_device
*dev
)
437 struct can_frame
*frame
= (struct can_frame
*)skb
->data
;
438 struct c_can_priv
*priv
= netdev_priv(dev
);
441 if (can_dropped_invalid_skb(dev
, skb
))
444 * This is not a FIFO. C/D_CAN sends out the buffers
445 * prioritized. The lowest buffer number wins.
447 idx
= fls(atomic_read(&priv
->tx_active
));
448 obj
= idx
+ C_CAN_MSG_OBJ_TX_FIRST
;
450 /* If this is the last buffer, stop the xmit queue */
451 if (idx
== C_CAN_MSG_OBJ_TX_NUM
- 1)
452 netif_stop_queue(dev
);
454 * Store the message in the interface so we can call
455 * can_put_echo_skb(). We must do this before we enable
456 * transmit as we might race against do_tx().
458 c_can_setup_tx_object(dev
, IF_TX
, frame
, idx
);
459 priv
->dlc
[idx
] = frame
->can_dlc
;
460 can_put_echo_skb(skb
, dev
, idx
);
462 /* Update the active bits */
463 atomic_add((1 << idx
), &priv
->tx_active
);
464 /* Start transmission */
465 c_can_object_put(dev
, IF_TX
, obj
, IF_COMM_TX
);
470 static int c_can_wait_for_ctrl_init(struct net_device
*dev
,
471 struct c_can_priv
*priv
, u32 init
)
475 while (init
!= (priv
->read_reg(priv
, C_CAN_CTRL_REG
) & CONTROL_INIT
)) {
477 if (retry
++ > 1000) {
478 netdev_err(dev
, "CCTRL: set CONTROL_INIT failed\n");
485 static int c_can_set_bittiming(struct net_device
*dev
)
487 unsigned int reg_btr
, reg_brpe
, ctrl_save
;
488 u8 brp
, brpe
, sjw
, tseg1
, tseg2
;
490 struct c_can_priv
*priv
= netdev_priv(dev
);
491 const struct can_bittiming
*bt
= &priv
->can
.bittiming
;
494 /* c_can provides a 6-bit brp and 4-bit brpe fields */
495 ten_bit_brp
= bt
->brp
- 1;
496 brp
= ten_bit_brp
& BTR_BRP_MASK
;
497 brpe
= ten_bit_brp
>> 6;
500 tseg1
= bt
->prop_seg
+ bt
->phase_seg1
- 1;
501 tseg2
= bt
->phase_seg2
- 1;
502 reg_btr
= brp
| (sjw
<< BTR_SJW_SHIFT
) | (tseg1
<< BTR_TSEG1_SHIFT
) |
503 (tseg2
<< BTR_TSEG2_SHIFT
);
504 reg_brpe
= brpe
& BRP_EXT_BRPE_MASK
;
507 "setting BTR=%04x BRPE=%04x\n", reg_btr
, reg_brpe
);
509 ctrl_save
= priv
->read_reg(priv
, C_CAN_CTRL_REG
);
510 ctrl_save
&= ~CONTROL_INIT
;
511 priv
->write_reg(priv
, C_CAN_CTRL_REG
, CONTROL_CCE
| CONTROL_INIT
);
512 res
= c_can_wait_for_ctrl_init(dev
, priv
, CONTROL_INIT
);
516 priv
->write_reg(priv
, C_CAN_BTR_REG
, reg_btr
);
517 priv
->write_reg(priv
, C_CAN_BRPEXT_REG
, reg_brpe
);
518 priv
->write_reg(priv
, C_CAN_CTRL_REG
, ctrl_save
);
520 return c_can_wait_for_ctrl_init(dev
, priv
, 0);
524 * Configure C_CAN message objects for Tx and Rx purposes:
525 * C_CAN provides a total of 32 message objects that can be configured
526 * either for Tx or Rx purposes. Here the first 16 message objects are used as
527 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
528 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
529 * See user guide document for further details on configuring message
532 static void c_can_configure_msg_objects(struct net_device
*dev
)
536 /* first invalidate all message objects */
537 for (i
= C_CAN_MSG_OBJ_RX_FIRST
; i
<= C_CAN_NO_OF_OBJECTS
; i
++)
538 c_can_inval_msg_object(dev
, IF_RX
, i
);
540 /* setup receive message objects */
541 for (i
= C_CAN_MSG_OBJ_RX_FIRST
; i
< C_CAN_MSG_OBJ_RX_LAST
; i
++)
542 c_can_setup_receive_object(dev
, IF_RX
, i
, 0, 0, IF_MCONT_RCV
);
544 c_can_setup_receive_object(dev
, IF_RX
, C_CAN_MSG_OBJ_RX_LAST
, 0, 0,
549 * Configure C_CAN chip:
550 * - enable/disable auto-retransmission
551 * - set operating mode
552 * - configure message objects
554 static int c_can_chip_config(struct net_device
*dev
)
556 struct c_can_priv
*priv
= netdev_priv(dev
);
558 /* enable automatic retransmission */
559 priv
->write_reg(priv
, C_CAN_CTRL_REG
, CONTROL_ENABLE_AR
);
561 if ((priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
) &&
562 (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
)) {
563 /* loopback + silent mode : useful for hot self-test */
564 priv
->write_reg(priv
, C_CAN_CTRL_REG
, CONTROL_TEST
);
565 priv
->write_reg(priv
, C_CAN_TEST_REG
, TEST_LBACK
| TEST_SILENT
);
566 } else if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
) {
567 /* loopback mode : useful for self-test function */
568 priv
->write_reg(priv
, C_CAN_CTRL_REG
, CONTROL_TEST
);
569 priv
->write_reg(priv
, C_CAN_TEST_REG
, TEST_LBACK
);
570 } else if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
) {
571 /* silent mode : bus-monitoring mode */
572 priv
->write_reg(priv
, C_CAN_CTRL_REG
, CONTROL_TEST
);
573 priv
->write_reg(priv
, C_CAN_TEST_REG
, TEST_SILENT
);
576 /* configure message objects */
577 c_can_configure_msg_objects(dev
);
579 /* set a `lec` value so that we can check for updates later */
580 priv
->write_reg(priv
, C_CAN_STS_REG
, LEC_UNUSED
);
582 /* Clear all internal status */
583 atomic_set(&priv
->tx_active
, 0);
587 /* set bittiming params */
588 return c_can_set_bittiming(dev
);
591 static int c_can_start(struct net_device
*dev
)
593 struct c_can_priv
*priv
= netdev_priv(dev
);
597 /* basic c_can configuration */
598 err
= c_can_chip_config(dev
);
602 /* Setup the command for new messages */
603 priv
->comm_rcv_high
= priv
->type
!= BOSCH_D_CAN
?
604 IF_COMM_RCV_LOW
: IF_COMM_RCV_HIGH
;
606 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
608 /* Attempt to use "active" if available else use "default" */
609 p
= pinctrl_get_select(priv
->device
, "active");
613 pinctrl_pm_select_default_state(priv
->device
);
618 static void c_can_stop(struct net_device
*dev
)
620 struct c_can_priv
*priv
= netdev_priv(dev
);
622 c_can_irq_control(priv
, false);
624 /* put ctrl to init on stop to end ongoing transmission */
625 priv
->write_reg(priv
, C_CAN_CTRL_REG
, CONTROL_INIT
);
627 /* deactivate pins */
628 pinctrl_pm_select_sleep_state(dev
->dev
.parent
);
629 priv
->can
.state
= CAN_STATE_STOPPED
;
632 static int c_can_set_mode(struct net_device
*dev
, enum can_mode mode
)
634 struct c_can_priv
*priv
= netdev_priv(dev
);
639 err
= c_can_start(dev
);
642 netif_wake_queue(dev
);
643 c_can_irq_control(priv
, true);
652 static int __c_can_get_berr_counter(const struct net_device
*dev
,
653 struct can_berr_counter
*bec
)
655 unsigned int reg_err_counter
;
656 struct c_can_priv
*priv
= netdev_priv(dev
);
658 reg_err_counter
= priv
->read_reg(priv
, C_CAN_ERR_CNT_REG
);
659 bec
->rxerr
= (reg_err_counter
& ERR_CNT_REC_MASK
) >>
661 bec
->txerr
= reg_err_counter
& ERR_CNT_TEC_MASK
;
666 static int c_can_get_berr_counter(const struct net_device
*dev
,
667 struct can_berr_counter
*bec
)
669 struct c_can_priv
*priv
= netdev_priv(dev
);
672 c_can_pm_runtime_get_sync(priv
);
673 err
= __c_can_get_berr_counter(dev
, bec
);
674 c_can_pm_runtime_put_sync(priv
);
679 static void c_can_do_tx(struct net_device
*dev
)
681 struct c_can_priv
*priv
= netdev_priv(dev
);
682 struct net_device_stats
*stats
= &dev
->stats
;
683 u32 idx
, obj
, pkts
= 0, bytes
= 0, pend
, clr
;
685 clr
= pend
= priv
->read_reg(priv
, C_CAN_INTPND2_REG
);
687 while ((idx
= ffs(pend
))) {
690 obj
= idx
+ C_CAN_MSG_OBJ_TX_FIRST
;
691 c_can_inval_tx_object(dev
, IF_RX
, obj
);
692 can_get_echo_skb(dev
, idx
);
693 bytes
+= priv
->dlc
[idx
];
697 /* Clear the bits in the tx_active mask */
698 atomic_sub(clr
, &priv
->tx_active
);
700 if (clr
& (1 << (C_CAN_MSG_OBJ_TX_NUM
- 1)))
701 netif_wake_queue(dev
);
704 stats
->tx_bytes
+= bytes
;
705 stats
->tx_packets
+= pkts
;
706 can_led_event(dev
, CAN_LED_EVENT_TX
);
711 * If we have a gap in the pending bits, that means we either
712 * raced with the hardware or failed to readout all upper
713 * objects in the last run due to quota limit.
715 static u32
c_can_adjust_pending(u32 pend
)
719 if (pend
== RECEIVE_OBJECT_BITS
)
723 * If the last set bit is larger than the number of pending
724 * bits we have a gap.
726 weight
= hweight32(pend
);
729 /* If the bits are linear, nothing to do */
734 * Find the first set bit after the gap. We walk backwards
735 * from the last set bit.
737 for (lasts
--; pend
& (1 << (lasts
- 1)); lasts
--);
739 return pend
& ~((1 << lasts
) - 1);
742 static inline void c_can_rx_object_get(struct net_device
*dev
,
743 struct c_can_priv
*priv
, u32 obj
)
745 c_can_object_get(dev
, IF_RX
, obj
, priv
->comm_rcv_high
);
748 static inline void c_can_rx_finalize(struct net_device
*dev
,
749 struct c_can_priv
*priv
, u32 obj
)
751 if (priv
->type
!= BOSCH_D_CAN
)
752 c_can_object_get(dev
, IF_RX
, obj
, IF_COMM_CLR_NEWDAT
);
755 static int c_can_read_objects(struct net_device
*dev
, struct c_can_priv
*priv
,
758 u32 pkts
= 0, ctrl
, obj
;
760 while ((obj
= ffs(pend
)) && quota
> 0) {
761 pend
&= ~BIT(obj
- 1);
763 c_can_rx_object_get(dev
, priv
, obj
);
764 ctrl
= priv
->read_reg(priv
, C_CAN_IFACE(MSGCTRL_REG
, IF_RX
));
766 if (ctrl
& IF_MCONT_MSGLST
) {
767 int n
= c_can_handle_lost_msg_obj(dev
, IF_RX
, obj
, ctrl
);
775 * This really should not happen, but this covers some
776 * odd HW behaviour. Do not remove that unless you
777 * want to brick your machine.
779 if (!(ctrl
& IF_MCONT_NEWDAT
))
782 /* read the data from the message object */
783 c_can_read_msg_object(dev
, IF_RX
, ctrl
);
785 c_can_rx_finalize(dev
, priv
, obj
);
794 static inline u32
c_can_get_pending(struct c_can_priv
*priv
)
796 u32 pend
= priv
->read_reg(priv
, C_CAN_NEWDAT1_REG
);
802 * theory of operation:
804 * c_can core saves a received CAN message into the first free message
805 * object it finds free (starting with the lowest). Bits NEWDAT and
806 * INTPND are set for this message object indicating that a new message
807 * has arrived. To work-around this issue, we keep two groups of message
808 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
810 * We clear the newdat bit right away.
812 * This can result in packet reordering when the readout is slow.
814 static int c_can_do_rx_poll(struct net_device
*dev
, int quota
)
816 struct c_can_priv
*priv
= netdev_priv(dev
);
817 u32 pkts
= 0, pend
= 0, toread
, n
;
820 * It is faster to read only one 16bit register. This is only possible
821 * for a maximum number of 16 objects.
823 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST
> 16,
824 "Implementation does not support more message objects than 16");
828 pend
= c_can_get_pending(priv
);
832 * If the pending field has a gap, handle the
833 * bits above the gap first.
835 toread
= c_can_adjust_pending(pend
);
839 /* Remove the bits from pend */
841 /* Read the objects */
842 n
= c_can_read_objects(dev
, priv
, toread
, quota
);
848 can_led_event(dev
, CAN_LED_EVENT_RX
);
853 static int c_can_handle_state_change(struct net_device
*dev
,
854 enum c_can_bus_error_types error_type
)
856 unsigned int reg_err_counter
;
857 unsigned int rx_err_passive
;
858 struct c_can_priv
*priv
= netdev_priv(dev
);
859 struct net_device_stats
*stats
= &dev
->stats
;
860 struct can_frame
*cf
;
862 struct can_berr_counter bec
;
864 switch (error_type
) {
865 case C_CAN_ERROR_WARNING
:
866 /* error warning state */
867 priv
->can
.can_stats
.error_warning
++;
868 priv
->can
.state
= CAN_STATE_ERROR_WARNING
;
870 case C_CAN_ERROR_PASSIVE
:
871 /* error passive state */
872 priv
->can
.can_stats
.error_passive
++;
873 priv
->can
.state
= CAN_STATE_ERROR_PASSIVE
;
877 priv
->can
.state
= CAN_STATE_BUS_OFF
;
878 priv
->can
.can_stats
.bus_off
++;
884 /* propagate the error condition to the CAN stack */
885 skb
= alloc_can_err_skb(dev
, &cf
);
889 __c_can_get_berr_counter(dev
, &bec
);
890 reg_err_counter
= priv
->read_reg(priv
, C_CAN_ERR_CNT_REG
);
891 rx_err_passive
= (reg_err_counter
& ERR_CNT_RP_MASK
) >>
894 switch (error_type
) {
895 case C_CAN_ERROR_WARNING
:
896 /* error warning state */
897 cf
->can_id
|= CAN_ERR_CRTL
;
898 cf
->data
[1] = (bec
.txerr
> bec
.rxerr
) ?
899 CAN_ERR_CRTL_TX_WARNING
:
900 CAN_ERR_CRTL_RX_WARNING
;
901 cf
->data
[6] = bec
.txerr
;
902 cf
->data
[7] = bec
.rxerr
;
905 case C_CAN_ERROR_PASSIVE
:
906 /* error passive state */
907 cf
->can_id
|= CAN_ERR_CRTL
;
909 cf
->data
[1] |= CAN_ERR_CRTL_RX_PASSIVE
;
911 cf
->data
[1] |= CAN_ERR_CRTL_TX_PASSIVE
;
913 cf
->data
[6] = bec
.txerr
;
914 cf
->data
[7] = bec
.rxerr
;
918 cf
->can_id
|= CAN_ERR_BUSOFF
;
926 stats
->rx_bytes
+= cf
->can_dlc
;
927 netif_receive_skb(skb
);
932 static int c_can_handle_bus_err(struct net_device
*dev
,
933 enum c_can_lec_type lec_type
)
935 struct c_can_priv
*priv
= netdev_priv(dev
);
936 struct net_device_stats
*stats
= &dev
->stats
;
937 struct can_frame
*cf
;
941 * early exit if no lec update or no error.
942 * no lec update means that no CAN bus event has been detected
943 * since CPU wrote 0x7 value to status reg.
945 if (lec_type
== LEC_UNUSED
|| lec_type
== LEC_NO_ERROR
)
948 if (!(priv
->can
.ctrlmode
& CAN_CTRLMODE_BERR_REPORTING
))
951 /* common for all type of bus errors */
952 priv
->can
.can_stats
.bus_error
++;
955 /* propagate the error condition to the CAN stack */
956 skb
= alloc_can_err_skb(dev
, &cf
);
961 * check for 'last error code' which tells us the
962 * type of the last error to occur on the CAN bus
964 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
967 case LEC_STUFF_ERROR
:
968 netdev_dbg(dev
, "stuff error\n");
969 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
972 netdev_dbg(dev
, "form error\n");
973 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
976 netdev_dbg(dev
, "ack error\n");
977 cf
->data
[3] = CAN_ERR_PROT_LOC_ACK
;
980 netdev_dbg(dev
, "bit1 error\n");
981 cf
->data
[2] |= CAN_ERR_PROT_BIT1
;
984 netdev_dbg(dev
, "bit0 error\n");
985 cf
->data
[2] |= CAN_ERR_PROT_BIT0
;
988 netdev_dbg(dev
, "CRC error\n");
989 cf
->data
[3] = CAN_ERR_PROT_LOC_CRC_SEQ
;
996 stats
->rx_bytes
+= cf
->can_dlc
;
997 netif_receive_skb(skb
);
1001 static int c_can_poll(struct napi_struct
*napi
, int quota
)
1003 struct net_device
*dev
= napi
->dev
;
1004 struct c_can_priv
*priv
= netdev_priv(dev
);
1005 u16 curr
, last
= priv
->last_status
;
1008 priv
->last_status
= curr
= priv
->read_reg(priv
, C_CAN_STS_REG
);
1009 /* Ack status on C_CAN. D_CAN is self clearing */
1010 if (priv
->type
!= BOSCH_D_CAN
)
1011 priv
->write_reg(priv
, C_CAN_STS_REG
, LEC_UNUSED
);
1013 /* handle state changes */
1014 if ((curr
& STATUS_EWARN
) && (!(last
& STATUS_EWARN
))) {
1015 netdev_dbg(dev
, "entered error warning state\n");
1016 work_done
+= c_can_handle_state_change(dev
, C_CAN_ERROR_WARNING
);
1019 if ((curr
& STATUS_EPASS
) && (!(last
& STATUS_EPASS
))) {
1020 netdev_dbg(dev
, "entered error passive state\n");
1021 work_done
+= c_can_handle_state_change(dev
, C_CAN_ERROR_PASSIVE
);
1024 if ((curr
& STATUS_BOFF
) && (!(last
& STATUS_BOFF
))) {
1025 netdev_dbg(dev
, "entered bus off state\n");
1026 work_done
+= c_can_handle_state_change(dev
, C_CAN_BUS_OFF
);
1030 /* handle bus recovery events */
1031 if ((!(curr
& STATUS_BOFF
)) && (last
& STATUS_BOFF
)) {
1032 netdev_dbg(dev
, "left bus off state\n");
1033 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
1035 if ((!(curr
& STATUS_EPASS
)) && (last
& STATUS_EPASS
)) {
1036 netdev_dbg(dev
, "left error passive state\n");
1037 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
1040 /* handle lec errors on the bus */
1041 work_done
+= c_can_handle_bus_err(dev
, curr
& LEC_MASK
);
1043 /* Handle Tx/Rx events. We do this unconditionally */
1044 work_done
+= c_can_do_rx_poll(dev
, (quota
- work_done
));
1048 if (work_done
< quota
) {
1049 napi_complete(napi
);
1050 /* enable all IRQs if we are not in bus off state */
1051 if (priv
->can
.state
!= CAN_STATE_BUS_OFF
)
1052 c_can_irq_control(priv
, true);
1058 static irqreturn_t
c_can_isr(int irq
, void *dev_id
)
1060 struct net_device
*dev
= (struct net_device
*)dev_id
;
1061 struct c_can_priv
*priv
= netdev_priv(dev
);
1063 if (!priv
->read_reg(priv
, C_CAN_INT_REG
))
1066 /* disable all interrupts and schedule the NAPI */
1067 c_can_irq_control(priv
, false);
1068 napi_schedule(&priv
->napi
);
1073 static int c_can_open(struct net_device
*dev
)
1076 struct c_can_priv
*priv
= netdev_priv(dev
);
1078 c_can_pm_runtime_get_sync(priv
);
1079 c_can_reset_ram(priv
, true);
1081 /* open the can device */
1082 err
= open_candev(dev
);
1084 netdev_err(dev
, "failed to open can device\n");
1085 goto exit_open_fail
;
1088 /* register interrupt handler */
1089 err
= request_irq(dev
->irq
, &c_can_isr
, IRQF_SHARED
, dev
->name
,
1092 netdev_err(dev
, "failed to request interrupt\n");
1096 /* start the c_can controller */
1097 err
= c_can_start(dev
);
1099 goto exit_start_fail
;
1101 can_led_event(dev
, CAN_LED_EVENT_OPEN
);
1103 napi_enable(&priv
->napi
);
1104 /* enable status change, error and module interrupts */
1105 c_can_irq_control(priv
, true);
1106 netif_start_queue(dev
);
1111 free_irq(dev
->irq
, dev
);
1115 c_can_reset_ram(priv
, false);
1116 c_can_pm_runtime_put_sync(priv
);
1120 static int c_can_close(struct net_device
*dev
)
1122 struct c_can_priv
*priv
= netdev_priv(dev
);
1124 netif_stop_queue(dev
);
1125 napi_disable(&priv
->napi
);
1127 free_irq(dev
->irq
, dev
);
1130 c_can_reset_ram(priv
, false);
1131 c_can_pm_runtime_put_sync(priv
);
1133 can_led_event(dev
, CAN_LED_EVENT_STOP
);
1138 struct net_device
*alloc_c_can_dev(void)
1140 struct net_device
*dev
;
1141 struct c_can_priv
*priv
;
1143 dev
= alloc_candev(sizeof(struct c_can_priv
), C_CAN_MSG_OBJ_TX_NUM
);
1147 priv
= netdev_priv(dev
);
1148 netif_napi_add(dev
, &priv
->napi
, c_can_poll
, C_CAN_NAPI_WEIGHT
);
1151 priv
->can
.bittiming_const
= &c_can_bittiming_const
;
1152 priv
->can
.do_set_mode
= c_can_set_mode
;
1153 priv
->can
.do_get_berr_counter
= c_can_get_berr_counter
;
1154 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_LOOPBACK
|
1155 CAN_CTRLMODE_LISTENONLY
|
1156 CAN_CTRLMODE_BERR_REPORTING
;
1160 EXPORT_SYMBOL_GPL(alloc_c_can_dev
);
1163 int c_can_power_down(struct net_device
*dev
)
1166 unsigned long time_out
;
1167 struct c_can_priv
*priv
= netdev_priv(dev
);
1169 if (!(dev
->flags
& IFF_UP
))
1172 WARN_ON(priv
->type
!= BOSCH_D_CAN
);
1174 /* set PDR value so the device goes to power down mode */
1175 val
= priv
->read_reg(priv
, C_CAN_CTRL_EX_REG
);
1176 val
|= CONTROL_EX_PDR
;
1177 priv
->write_reg(priv
, C_CAN_CTRL_EX_REG
, val
);
1179 /* Wait for the PDA bit to get set */
1180 time_out
= jiffies
+ msecs_to_jiffies(INIT_WAIT_MS
);
1181 while (!(priv
->read_reg(priv
, C_CAN_STS_REG
) & STATUS_PDA
) &&
1182 time_after(time_out
, jiffies
))
1185 if (time_after(jiffies
, time_out
))
1190 c_can_reset_ram(priv
, false);
1191 c_can_pm_runtime_put_sync(priv
);
1195 EXPORT_SYMBOL_GPL(c_can_power_down
);
1197 int c_can_power_up(struct net_device
*dev
)
1200 unsigned long time_out
;
1201 struct c_can_priv
*priv
= netdev_priv(dev
);
1204 if (!(dev
->flags
& IFF_UP
))
1207 WARN_ON(priv
->type
!= BOSCH_D_CAN
);
1209 c_can_pm_runtime_get_sync(priv
);
1210 c_can_reset_ram(priv
, true);
1212 /* Clear PDR and INIT bits */
1213 val
= priv
->read_reg(priv
, C_CAN_CTRL_EX_REG
);
1214 val
&= ~CONTROL_EX_PDR
;
1215 priv
->write_reg(priv
, C_CAN_CTRL_EX_REG
, val
);
1216 val
= priv
->read_reg(priv
, C_CAN_CTRL_REG
);
1217 val
&= ~CONTROL_INIT
;
1218 priv
->write_reg(priv
, C_CAN_CTRL_REG
, val
);
1220 /* Wait for the PDA bit to get clear */
1221 time_out
= jiffies
+ msecs_to_jiffies(INIT_WAIT_MS
);
1222 while ((priv
->read_reg(priv
, C_CAN_STS_REG
) & STATUS_PDA
) &&
1223 time_after(time_out
, jiffies
))
1226 if (time_after(jiffies
, time_out
))
1229 ret
= c_can_start(dev
);
1231 c_can_irq_control(priv
, true);
1235 EXPORT_SYMBOL_GPL(c_can_power_up
);
1238 void free_c_can_dev(struct net_device
*dev
)
1240 struct c_can_priv
*priv
= netdev_priv(dev
);
1242 netif_napi_del(&priv
->napi
);
1245 EXPORT_SYMBOL_GPL(free_c_can_dev
);
1247 static const struct net_device_ops c_can_netdev_ops
= {
1248 .ndo_open
= c_can_open
,
1249 .ndo_stop
= c_can_close
,
1250 .ndo_start_xmit
= c_can_start_xmit
,
1251 .ndo_change_mtu
= can_change_mtu
,
1254 int register_c_can_dev(struct net_device
*dev
)
1256 struct c_can_priv
*priv
= netdev_priv(dev
);
1259 /* Deactivate pins to prevent DRA7 DCAN IP from being
1260 * stuck in transition when module is disabled.
1261 * Pins are activated in c_can_start() and deactivated
1264 pinctrl_pm_select_sleep_state(dev
->dev
.parent
);
1266 c_can_pm_runtime_enable(priv
);
1268 dev
->flags
|= IFF_ECHO
; /* we support local echo */
1269 dev
->netdev_ops
= &c_can_netdev_ops
;
1271 err
= register_candev(dev
);
1273 c_can_pm_runtime_disable(priv
);
1275 devm_can_led_init(dev
);
1279 EXPORT_SYMBOL_GPL(register_c_can_dev
);
1281 void unregister_c_can_dev(struct net_device
*dev
)
1283 struct c_can_priv
*priv
= netdev_priv(dev
);
1285 unregister_candev(dev
);
1287 c_can_pm_runtime_disable(priv
);
1289 EXPORT_SYMBOL_GPL(unregister_c_can_dev
);
1291 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1292 MODULE_LICENSE("GPL v2");
1293 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");