]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/net/can/flexcan.c
projects / mirror_ubuntu-hirsute-kernel.git / blob
? search:


148c0a3fab24626cb9be725dc0f866ef09a0b391
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / can / flexcan.c
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // flexcan.c - FLEXCAN CAN controller driver
4 //
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
9 //
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11
12 #include <linux/netdevice.h>
13 #include <linux/can.h>
14 #include <linux/can/dev.h>
15 #include <linux/can/error.h>
16 #include <linux/can/led.h>
17 #include <linux/can/rx-offload.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/regmap.h>
30
31 #define DRV_NAME "flexcan"
32
33 /* 8 for RX fifo and 2 error handling */
34 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
35
36 /* FLEXCAN module configuration register (CANMCR) bits */
37 #define FLEXCAN_MCR_MDIS BIT(31)
38 #define FLEXCAN_MCR_FRZ BIT(30)
39 #define FLEXCAN_MCR_FEN BIT(29)
40 #define FLEXCAN_MCR_HALT BIT(28)
41 #define FLEXCAN_MCR_NOT_RDY BIT(27)
42 #define FLEXCAN_MCR_WAK_MSK BIT(26)
43 #define FLEXCAN_MCR_SOFTRST BIT(25)
44 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
45 #define FLEXCAN_MCR_SUPV BIT(23)
46 #define FLEXCAN_MCR_SLF_WAK BIT(22)
47 #define FLEXCAN_MCR_WRN_EN BIT(21)
48 #define FLEXCAN_MCR_LPM_ACK BIT(20)
49 #define FLEXCAN_MCR_WAK_SRC BIT(19)
50 #define FLEXCAN_MCR_DOZE BIT(18)
51 #define FLEXCAN_MCR_SRX_DIS BIT(17)
52 #define FLEXCAN_MCR_IRMQ BIT(16)
53 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
54 #define FLEXCAN_MCR_AEN BIT(12)
55 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
56 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
57 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
58 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
59 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
60 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
61
62 /* FLEXCAN control register (CANCTRL) bits */
63 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
64 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
65 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
66 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
67 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
68 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
69 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
70 #define FLEXCAN_CTRL_LPB BIT(12)
71 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
72 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
73 #define FLEXCAN_CTRL_SMP BIT(7)
74 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
75 #define FLEXCAN_CTRL_TSYN BIT(5)
76 #define FLEXCAN_CTRL_LBUF BIT(4)
77 #define FLEXCAN_CTRL_LOM BIT(3)
78 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
79 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
80 #define FLEXCAN_CTRL_ERR_STATE \
81 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
82 FLEXCAN_CTRL_BOFF_MSK)
83 #define FLEXCAN_CTRL_ERR_ALL \
84 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
85
86 /* FLEXCAN control register 2 (CTRL2) bits */
87 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
88 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
89 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
90 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
91 #define FLEXCAN_CTRL2_MRP BIT(18)
92 #define FLEXCAN_CTRL2_RRS BIT(17)
93 #define FLEXCAN_CTRL2_EACEN BIT(16)
94
95 /* FLEXCAN memory error control register (MECR) bits */
96 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
97 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
98 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
99 #define FLEXCAN_MECR_CEI_MSK BIT(16)
100 #define FLEXCAN_MECR_HAERRIE BIT(15)
101 #define FLEXCAN_MECR_FAERRIE BIT(14)
102 #define FLEXCAN_MECR_EXTERRIE BIT(13)
103 #define FLEXCAN_MECR_RERRDIS BIT(9)
104 #define FLEXCAN_MECR_ECCDIS BIT(8)
105 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
106
107 /* FLEXCAN error and status register (ESR) bits */
108 #define FLEXCAN_ESR_TWRN_INT BIT(17)
109 #define FLEXCAN_ESR_RWRN_INT BIT(16)
110 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
111 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
112 #define FLEXCAN_ESR_ACK_ERR BIT(13)
113 #define FLEXCAN_ESR_CRC_ERR BIT(12)
114 #define FLEXCAN_ESR_FRM_ERR BIT(11)
115 #define FLEXCAN_ESR_STF_ERR BIT(10)
116 #define FLEXCAN_ESR_TX_WRN BIT(9)
117 #define FLEXCAN_ESR_RX_WRN BIT(8)
118 #define FLEXCAN_ESR_IDLE BIT(7)
119 #define FLEXCAN_ESR_TXRX BIT(6)
120 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
121 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
122 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
123 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
124 #define FLEXCAN_ESR_BOFF_INT BIT(2)
125 #define FLEXCAN_ESR_ERR_INT BIT(1)
126 #define FLEXCAN_ESR_WAK_INT BIT(0)
127 #define FLEXCAN_ESR_ERR_BUS \
128 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
129 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
130 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
131 #define FLEXCAN_ESR_ERR_STATE \
132 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
133 #define FLEXCAN_ESR_ERR_ALL \
134 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
135 #define FLEXCAN_ESR_ALL_INT \
136 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
137 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
138 FLEXCAN_ESR_WAK_INT)
139
140 /* FLEXCAN interrupt flag register (IFLAG) bits */
141 /* Errata ERR005829 step7: Reserve first valid MB */
142 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
143 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
144 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
145 #define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f)
146 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
147 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
148 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
149
150 /* FLEXCAN message buffers */
151 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
152 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
153 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
154 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
155 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
156 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
157 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
158
159 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
160 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
161 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
162 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
163
164 #define FLEXCAN_MB_CNT_SRR BIT(22)
165 #define FLEXCAN_MB_CNT_IDE BIT(21)
166 #define FLEXCAN_MB_CNT_RTR BIT(20)
167 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
168 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
169
170 #define FLEXCAN_TIMEOUT_US (250)
171
172 /* FLEXCAN hardware feature flags
173 *
174 * Below is some version info we got:
175 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
176 * Filter? connected? Passive detection ception in MB
177 * MX25 FlexCAN2 03.00.00.00 no no no no no
178 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
179 * MX35 FlexCAN2 03.00.00.00 no no no no no
180 * MX53 FlexCAN2 03.00.00.00 yes no no no no
181 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
182 * VF610 FlexCAN3 ? no yes no yes yes?
183 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes
184 *
185 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
186 */
187 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
188 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
189 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
190 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
191 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
192 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
193 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */
194 #define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8) /* Setup stop mode to support wakeup */
195
196 /* Structure of the message buffer */
197 struct flexcan_mb {
198 u32 can_ctrl;
199 u32 can_id;
200 u32 data[];
201 };
202
203 /* Structure of the hardware registers */
204 struct flexcan_regs {
205 u32 mcr; /* 0x00 */
206 u32 ctrl; /* 0x04 */
207 u32 timer; /* 0x08 */
208 u32 _reserved1; /* 0x0c */
209 u32 rxgmask; /* 0x10 */
210 u32 rx14mask; /* 0x14 */
211 u32 rx15mask; /* 0x18 */
212 u32 ecr; /* 0x1c */
213 u32 esr; /* 0x20 */
214 u32 imask2; /* 0x24 */
215 u32 imask1; /* 0x28 */
216 u32 iflag2; /* 0x2c */
217 u32 iflag1; /* 0x30 */
218 union { /* 0x34 */
219 u32 gfwr_mx28; /* MX28, MX53 */
220 u32 ctrl2; /* MX6, VF610 */
221 };
222 u32 esr2; /* 0x38 */
223 u32 imeur; /* 0x3c */
224 u32 lrfr; /* 0x40 */
225 u32 crcr; /* 0x44 */
226 u32 rxfgmask; /* 0x48 */
227 u32 rxfir; /* 0x4c */
228 u32 _reserved3[12]; /* 0x50 */
229 u8 mb[2][512]; /* 0x80 */
230 /* FIFO-mode:
231 * MB
232 * 0x080...0x08f 0 RX message buffer
233 * 0x090...0x0df 1-5 reserverd
234 * 0x0e0...0x0ff 6-7 8 entry ID table
235 * (mx25, mx28, mx35, mx53)
236 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
237 * size conf'ed via ctrl2::RFFN
238 * (mx6, vf610)
239 */
240 u32 _reserved4[256]; /* 0x480 */
241 u32 rximr[64]; /* 0x880 */
242 u32 _reserved5[24]; /* 0x980 */
243 u32 gfwr_mx6; /* 0x9e0 - MX6 */
244 u32 _reserved6[63]; /* 0x9e4 */
245 u32 mecr; /* 0xae0 */
246 u32 erriar; /* 0xae4 */
247 u32 erridpr; /* 0xae8 */
248 u32 errippr; /* 0xaec */
249 u32 rerrar; /* 0xaf0 */
250 u32 rerrdr; /* 0xaf4 */
251 u32 rerrsynr; /* 0xaf8 */
252 u32 errsr; /* 0xafc */
253 };
254
255 struct flexcan_devtype_data {
256 u32 quirks; /* quirks needed for different IP cores */
257 };
258
259 struct flexcan_stop_mode {
260 struct regmap *gpr;
261 u8 req_gpr;
262 u8 req_bit;
263 u8 ack_gpr;
264 u8 ack_bit;
265 };
266
267 struct flexcan_priv {
268 struct can_priv can;
269 struct can_rx_offload offload;
270 struct device *dev;
271
272 struct flexcan_regs __iomem *regs;
273 struct flexcan_mb __iomem *tx_mb;
274 struct flexcan_mb __iomem *tx_mb_reserved;
275 u8 tx_mb_idx;
276 u8 mb_count;
277 u8 mb_size;
278 u8 clk_src; /* clock source of CAN Protocol Engine */
279
280 u32 reg_ctrl_default;
281 u32 reg_imask1_default;
282 u32 reg_imask2_default;
283
284 struct clk *clk_ipg;
285 struct clk *clk_per;
286 const struct flexcan_devtype_data *devtype_data;
287 struct regulator *reg_xceiver;
288 struct flexcan_stop_mode stm;
289
290 /* Read and Write APIs */
291 u32 (*read)(void __iomem *addr);
292 void (*write)(u32 val, void __iomem *addr);
293 };
294
295 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
296 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
297 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
298 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
299 };
300
301 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
302 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
303 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
304 };
305
306 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
307 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
308 };
309
310 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
311 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
312 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
313 FLEXCAN_QUIRK_SETUP_STOP_MODE,
314 };
315
316 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
317 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
318 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
319 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
320 };
321
322 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
323 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
324 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
325 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
326 };
327
328 static const struct can_bittiming_const flexcan_bittiming_const = {
329 .name = DRV_NAME,
330 .tseg1_min = 4,
331 .tseg1_max = 16,
332 .tseg2_min = 2,
333 .tseg2_max = 8,
334 .sjw_max = 4,
335 .brp_min = 1,
336 .brp_max = 256,
337 .brp_inc = 1,
338 };
339
340 /* FlexCAN module is essentially modelled as a little-endian IP in most
341 * SoCs, i.e the registers as well as the message buffer areas are
342 * implemented in a little-endian fashion.
343 *
344 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
345 * module in a big-endian fashion (i.e the registers as well as the
346 * message buffer areas are implemented in a big-endian way).
347 *
348 * In addition, the FlexCAN module can be found on SoCs having ARM or
349 * PPC cores. So, we need to abstract off the register read/write
350 * functions, ensuring that these cater to all the combinations of module
351 * endianness and underlying CPU endianness.
352 */
353 static inline u32 flexcan_read_be(void __iomem *addr)
354 {
355 return ioread32be(addr);
356 }
357
358 static inline void flexcan_write_be(u32 val, void __iomem *addr)
359 {
360 iowrite32be(val, addr);
361 }
362
363 static inline u32 flexcan_read_le(void __iomem *addr)
364 {
365 return ioread32(addr);
366 }
367
368 static inline void flexcan_write_le(u32 val, void __iomem *addr)
369 {
370 iowrite32(val, addr);
371 }
372
373 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
374 u8 mb_index)
375 {
376 u8 bank_size;
377 bool bank;
378
379 if (WARN_ON(mb_index >= priv->mb_count))
380 return NULL;
381
382 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
383
384 bank = mb_index >= bank_size;
385 if (bank)
386 mb_index -= bank_size;
387
388 return (struct flexcan_mb __iomem *)
389 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
390 }
391
392 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
393 {
394 struct flexcan_regs __iomem *regs = priv->regs;
395 u32 reg_mcr;
396
397 reg_mcr = priv->read(&regs->mcr);
398
399 if (enable)
400 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
401 else
402 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
403
404 priv->write(reg_mcr, &regs->mcr);
405 }
406
407 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
408 {
409 struct flexcan_regs __iomem *regs = priv->regs;
410 unsigned int ackval;
411 u32 reg_mcr;
412
413 reg_mcr = priv->read(&regs->mcr);
414 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
415 priv->write(reg_mcr, &regs->mcr);
416
417 /* enable stop request */
418 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
419 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
420
421 /* get stop acknowledgment */
422 if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
423 ackval, ackval & (1 << priv->stm.ack_bit),
424 0, FLEXCAN_TIMEOUT_US))
425 return -ETIMEDOUT;
426
427 return 0;
428 }
429
430 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
431 {
432 struct flexcan_regs __iomem *regs = priv->regs;
433 unsigned int ackval;
434 u32 reg_mcr;
435
436 /* remove stop request */
437 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
438 1 << priv->stm.req_bit, 0);
439
440 /* get stop acknowledgment */
441 if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
442 ackval, !(ackval & (1 << priv->stm.ack_bit)),
443 0, FLEXCAN_TIMEOUT_US))
444 return -ETIMEDOUT;
445
446 reg_mcr = priv->read(&regs->mcr);
447 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
448 priv->write(reg_mcr, &regs->mcr);
449
450 return 0;
451 }
452
453 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
454 {
455 struct flexcan_regs __iomem *regs = priv->regs;
456 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
457
458 priv->write(reg_ctrl, &regs->ctrl);
459 }
460
461 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
462 {
463 struct flexcan_regs __iomem *regs = priv->regs;
464 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
465
466 priv->write(reg_ctrl, &regs->ctrl);
467 }
468
469 static int flexcan_clks_enable(const struct flexcan_priv *priv)
470 {
471 int err;
472
473 err = clk_prepare_enable(priv->clk_ipg);
474 if (err)
475 return err;
476
477 err = clk_prepare_enable(priv->clk_per);
478 if (err)
479 clk_disable_unprepare(priv->clk_ipg);
480
481 return err;
482 }
483
484 static void flexcan_clks_disable(const struct flexcan_priv *priv)
485 {
486 clk_disable_unprepare(priv->clk_per);
487 clk_disable_unprepare(priv->clk_ipg);
488 }
489
490 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
491 {
492 if (!priv->reg_xceiver)
493 return 0;
494
495 return regulator_enable(priv->reg_xceiver);
496 }
497
498 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
499 {
500 if (!priv->reg_xceiver)
501 return 0;
502
503 return regulator_disable(priv->reg_xceiver);
504 }
505
506 static int flexcan_chip_enable(struct flexcan_priv *priv)
507 {
508 struct flexcan_regs __iomem *regs = priv->regs;
509 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
510 u32 reg;
511
512 reg = priv->read(&regs->mcr);
513 reg &= ~FLEXCAN_MCR_MDIS;
514 priv->write(reg, &regs->mcr);
515
516 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
517 udelay(10);
518
519 if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
520 return -ETIMEDOUT;
521
522 return 0;
523 }
524
525 static int flexcan_chip_disable(struct flexcan_priv *priv)
526 {
527 struct flexcan_regs __iomem *regs = priv->regs;
528 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
529 u32 reg;
530
531 reg = priv->read(&regs->mcr);
532 reg |= FLEXCAN_MCR_MDIS;
533 priv->write(reg, &regs->mcr);
534
535 while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
536 udelay(10);
537
538 if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
539 return -ETIMEDOUT;
540
541 return 0;
542 }
543
544 static int flexcan_chip_freeze(struct flexcan_priv *priv)
545 {
546 struct flexcan_regs __iomem *regs = priv->regs;
547 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
548 u32 reg;
549
550 reg = priv->read(&regs->mcr);
551 reg |= FLEXCAN_MCR_HALT;
552 priv->write(reg, &regs->mcr);
553
554 while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
555 udelay(100);
556
557 if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
558 return -ETIMEDOUT;
559
560 return 0;
561 }
562
563 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
564 {
565 struct flexcan_regs __iomem *regs = priv->regs;
566 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
567 u32 reg;
568
569 reg = priv->read(&regs->mcr);
570 reg &= ~FLEXCAN_MCR_HALT;
571 priv->write(reg, &regs->mcr);
572
573 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
574 udelay(10);
575
576 if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
577 return -ETIMEDOUT;
578
579 return 0;
580 }
581
582 static int flexcan_chip_softreset(struct flexcan_priv *priv)
583 {
584 struct flexcan_regs __iomem *regs = priv->regs;
585 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
586
587 priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
588 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
589 udelay(10);
590
591 if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
592 return -ETIMEDOUT;
593
594 return 0;
595 }
596
597 static int __flexcan_get_berr_counter(const struct net_device *dev,
598 struct can_berr_counter *bec)
599 {
600 const struct flexcan_priv *priv = netdev_priv(dev);
601 struct flexcan_regs __iomem *regs = priv->regs;
602 u32 reg = priv->read(&regs->ecr);
603
604 bec->txerr = (reg >> 0) & 0xff;
605 bec->rxerr = (reg >> 8) & 0xff;
606
607 return 0;
608 }
609
610 static int flexcan_get_berr_counter(const struct net_device *dev,
611 struct can_berr_counter *bec)
612 {
613 const struct flexcan_priv *priv = netdev_priv(dev);
614 int err;
615
616 err = pm_runtime_get_sync(priv->dev);
617 if (err < 0)
618 return err;
619
620 err = __flexcan_get_berr_counter(dev, bec);
621
622 pm_runtime_put(priv->dev);
623
624 return err;
625 }
626
627 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
628 {
629 const struct flexcan_priv *priv = netdev_priv(dev);
630 struct can_frame *cf = (struct can_frame *)skb->data;
631 u32 can_id;
632 u32 data;
633 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
634 int i;
635
636 if (can_dropped_invalid_skb(dev, skb))
637 return NETDEV_TX_OK;
638
639 netif_stop_queue(dev);
640
641 if (cf->can_id & CAN_EFF_FLAG) {
642 can_id = cf->can_id & CAN_EFF_MASK;
643 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
644 } else {
645 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
646 }
647
648 if (cf->can_id & CAN_RTR_FLAG)
649 ctrl |= FLEXCAN_MB_CNT_RTR;
650
651 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
652 data = be32_to_cpup((__be32 *)&cf->data[i]);
653 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
654 }
655
656 can_put_echo_skb(skb, dev, 0);
657
658 priv->write(can_id, &priv->tx_mb->can_id);
659 priv->write(ctrl, &priv->tx_mb->can_ctrl);
660
661 /* Errata ERR005829 step8:
662 * Write twice INACTIVE(0x8) code to first MB.
663 */
664 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
665 &priv->tx_mb_reserved->can_ctrl);
666 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
667 &priv->tx_mb_reserved->can_ctrl);
668
669 return NETDEV_TX_OK;
670 }
671
672 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
673 {
674 struct flexcan_priv *priv = netdev_priv(dev);
675 struct flexcan_regs __iomem *regs = priv->regs;
676 struct sk_buff *skb;
677 struct can_frame *cf;
678 bool rx_errors = false, tx_errors = false;
679 u32 timestamp;
680 int err;
681
682 timestamp = priv->read(&regs->timer) << 16;
683
684 skb = alloc_can_err_skb(dev, &cf);
685 if (unlikely(!skb))
686 return;
687
688 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
689
690 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
691 netdev_dbg(dev, "BIT1_ERR irq\n");
692 cf->data[2] |= CAN_ERR_PROT_BIT1;
693 tx_errors = true;
694 }
695 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
696 netdev_dbg(dev, "BIT0_ERR irq\n");
697 cf->data[2] |= CAN_ERR_PROT_BIT0;
698 tx_errors = true;
699 }
700 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
701 netdev_dbg(dev, "ACK_ERR irq\n");
702 cf->can_id |= CAN_ERR_ACK;
703 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
704 tx_errors = true;
705 }
706 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
707 netdev_dbg(dev, "CRC_ERR irq\n");
708 cf->data[2] |= CAN_ERR_PROT_BIT;
709 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
710 rx_errors = true;
711 }
712 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
713 netdev_dbg(dev, "FRM_ERR irq\n");
714 cf->data[2] |= CAN_ERR_PROT_FORM;
715 rx_errors = true;
716 }
717 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
718 netdev_dbg(dev, "STF_ERR irq\n");
719 cf->data[2] |= CAN_ERR_PROT_STUFF;
720 rx_errors = true;
721 }
722
723 priv->can.can_stats.bus_error++;
724 if (rx_errors)
725 dev->stats.rx_errors++;
726 if (tx_errors)
727 dev->stats.tx_errors++;
728
729 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
730 if (err)
731 dev->stats.rx_fifo_errors++;
732 }
733
734 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
735 {
736 struct flexcan_priv *priv = netdev_priv(dev);
737 struct flexcan_regs __iomem *regs = priv->regs;
738 struct sk_buff *skb;
739 struct can_frame *cf;
740 enum can_state new_state, rx_state, tx_state;
741 int flt;
742 struct can_berr_counter bec;
743 u32 timestamp;
744 int err;
745
746 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
747 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
748 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
749 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
750 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
751 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
752 new_state = max(tx_state, rx_state);
753 } else {
754 __flexcan_get_berr_counter(dev, &bec);
755 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
756 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
757 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
758 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
759 }
760
761 /* state hasn't changed */
762 if (likely(new_state == priv->can.state))
763 return;
764
765 timestamp = priv->read(&regs->timer) << 16;
766
767 skb = alloc_can_err_skb(dev, &cf);
768 if (unlikely(!skb))
769 return;
770
771 can_change_state(dev, cf, tx_state, rx_state);
772
773 if (unlikely(new_state == CAN_STATE_BUS_OFF))
774 can_bus_off(dev);
775
776 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
777 if (err)
778 dev->stats.rx_fifo_errors++;
779 }
780
781 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
782 {
783 return container_of(offload, struct flexcan_priv, offload);
784 }
785
786 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
787 unsigned int n, u32 *timestamp,
788 bool drop)
789 {
790 struct flexcan_priv *priv = rx_offload_to_priv(offload);
791 struct flexcan_regs __iomem *regs = priv->regs;
792 struct flexcan_mb __iomem *mb;
793 struct sk_buff *skb;
794 struct can_frame *cf;
795 u32 reg_ctrl, reg_id, reg_iflag1;
796 int i;
797
798 if (unlikely(drop)) {
799 skb = ERR_PTR(-ENOBUFS);
800 goto mark_as_read;
801 }
802
803 mb = flexcan_get_mb(priv, n);
804
805 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
806 u32 code;
807
808 do {
809 reg_ctrl = priv->read(&mb->can_ctrl);
810 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
811
812 /* is this MB empty? */
813 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
814 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
815 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
816 return NULL;
817
818 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
819 /* This MB was overrun, we lost data */
820 offload->dev->stats.rx_over_errors++;
821 offload->dev->stats.rx_errors++;
822 }
823 } else {
824 reg_iflag1 = priv->read(&regs->iflag1);
825 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
826 return NULL;
827
828 reg_ctrl = priv->read(&mb->can_ctrl);
829 }
830
831 skb = alloc_can_skb(offload->dev, &cf);
832 if (!skb) {
833 skb = ERR_PTR(-ENOMEM);
834 goto mark_as_read;
835 }
836
837 /* increase timstamp to full 32 bit */
838 *timestamp = reg_ctrl << 16;
839
840 reg_id = priv->read(&mb->can_id);
841 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
842 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
843 else
844 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
845
846 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
847 cf->can_id |= CAN_RTR_FLAG;
848 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
849
850 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
851 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
852 *(__be32 *)(cf->data + i) = data;
853 }
854
855 mark_as_read:
856 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
857 /* Clear IRQ */
858 if (n < 32)
859 priv->write(BIT(n), &regs->iflag1);
860 else
861 priv->write(BIT(n - 32), &regs->iflag2);
862 } else {
863 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
864 }
865
866 /* Read the Free Running Timer. It is optional but recommended
867 * to unlock Mailbox as soon as possible and make it available
868 * for reception.
869 */
870 priv->read(&regs->timer);
871
872 return skb;
873 }
874
875
876 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
877 {
878 struct flexcan_regs __iomem *regs = priv->regs;
879 u32 iflag1, iflag2;
880
881 iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
882 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
883 iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
884
885 return (u64)iflag2 << 32 | iflag1;
886 }
887
888 static irqreturn_t flexcan_irq(int irq, void *dev_id)
889 {
890 struct net_device *dev = dev_id;
891 struct net_device_stats *stats = &dev->stats;
892 struct flexcan_priv *priv = netdev_priv(dev);
893 struct flexcan_regs __iomem *regs = priv->regs;
894 irqreturn_t handled = IRQ_NONE;
895 u32 reg_iflag2, reg_esr;
896 enum can_state last_state = priv->can.state;
897
898 /* reception interrupt */
899 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
900 u64 reg_iflag;
901 int ret;
902
903 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
904 handled = IRQ_HANDLED;
905 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
906 reg_iflag);
907 if (!ret)
908 break;
909 }
910 } else {
911 u32 reg_iflag1;
912
913 reg_iflag1 = priv->read(&regs->iflag1);
914 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
915 handled = IRQ_HANDLED;
916 can_rx_offload_irq_offload_fifo(&priv->offload);
917 }
918
919 /* FIFO overflow interrupt */
920 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
921 handled = IRQ_HANDLED;
922 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
923 &regs->iflag1);
924 dev->stats.rx_over_errors++;
925 dev->stats.rx_errors++;
926 }
927 }
928
929 reg_iflag2 = priv->read(&regs->iflag2);
930
931 /* transmission complete interrupt */
932 if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
933 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
934
935 handled = IRQ_HANDLED;
936 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
937 0, reg_ctrl << 16);
938 stats->tx_packets++;
939 can_led_event(dev, CAN_LED_EVENT_TX);
940
941 /* after sending a RTR frame MB is in RX mode */
942 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
943 &priv->tx_mb->can_ctrl);
944 priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
945 netif_wake_queue(dev);
946 }
947
948 reg_esr = priv->read(&regs->esr);
949
950 /* ACK all bus error and state change IRQ sources */
951 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
952 handled = IRQ_HANDLED;
953 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
954 }
955
956 /* state change interrupt or broken error state quirk fix is enabled */
957 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
958 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
959 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
960 flexcan_irq_state(dev, reg_esr);
961
962 /* bus error IRQ - handle if bus error reporting is activated */
963 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
964 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
965 flexcan_irq_bus_err(dev, reg_esr);
966
967 /* availability of error interrupt among state transitions in case
968 * bus error reporting is de-activated and
969 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
970 * +--------------------------------------------------------------+
971 * | +----------------------------------------------+ [stopped / |
972 * | | | sleeping] -+
973 * +-+-> active <-> warning <-> passive -> bus off -+
974 * ___________^^^^^^^^^^^^_______________________________
975 * disabled(1) enabled disabled
976 *
977 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
978 */
979 if ((last_state != priv->can.state) &&
980 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
981 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
982 switch (priv->can.state) {
983 case CAN_STATE_ERROR_ACTIVE:
984 if (priv->devtype_data->quirks &
985 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
986 flexcan_error_irq_enable(priv);
987 else
988 flexcan_error_irq_disable(priv);
989 break;
990
991 case CAN_STATE_ERROR_WARNING:
992 flexcan_error_irq_enable(priv);
993 break;
994
995 case CAN_STATE_ERROR_PASSIVE:
996 case CAN_STATE_BUS_OFF:
997 flexcan_error_irq_disable(priv);
998 break;
999
1000 default:
1001 break;
1002 }
1003 }
1004
1005 return handled;
1006 }
1007
1008 static void flexcan_set_bittiming(struct net_device *dev)
1009 {
1010 const struct flexcan_priv *priv = netdev_priv(dev);
1011 const struct can_bittiming *bt = &priv->can.bittiming;
1012 struct flexcan_regs __iomem *regs = priv->regs;
1013 u32 reg;
1014
1015 reg = priv->read(&regs->ctrl);
1016 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1017 FLEXCAN_CTRL_RJW(0x3) |
1018 FLEXCAN_CTRL_PSEG1(0x7) |
1019 FLEXCAN_CTRL_PSEG2(0x7) |
1020 FLEXCAN_CTRL_PROPSEG(0x7) |
1021 FLEXCAN_CTRL_LPB |
1022 FLEXCAN_CTRL_SMP |
1023 FLEXCAN_CTRL_LOM);
1024
1025 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1026 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1027 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1028 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1029 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1030
1031 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1032 reg |= FLEXCAN_CTRL_LPB;
1033 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1034 reg |= FLEXCAN_CTRL_LOM;
1035 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1036 reg |= FLEXCAN_CTRL_SMP;
1037
1038 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1039 priv->write(reg, &regs->ctrl);
1040
1041 /* print chip status */
1042 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1043 priv->read(&regs->mcr), priv->read(&regs->ctrl));
1044 }
1045
1046 /* flexcan_chip_start
1047 *
1048 * this functions is entered with clocks enabled
1049 *
1050 */
1051 static int flexcan_chip_start(struct net_device *dev)
1052 {
1053 struct flexcan_priv *priv = netdev_priv(dev);
1054 struct flexcan_regs __iomem *regs = priv->regs;
1055 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1056 int err, i;
1057 struct flexcan_mb __iomem *mb;
1058
1059 /* enable module */
1060 err = flexcan_chip_enable(priv);
1061 if (err)
1062 return err;
1063
1064 /* soft reset */
1065 err = flexcan_chip_softreset(priv);
1066 if (err)
1067 goto out_chip_disable;
1068
1069 flexcan_set_bittiming(dev);
1070
1071 /* MCR
1072 *
1073 * enable freeze
1074 * halt now
1075 * only supervisor access
1076 * enable warning int
1077 * enable individual RX masking
1078 * choose format C
1079 * set max mailbox number
1080 */
1081 reg_mcr = priv->read(&regs->mcr);
1082 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1083 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1084 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1085 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1086
1087 /* MCR
1088 *
1089 * FIFO:
1090 * - disable for timestamp mode
1091 * - enable for FIFO mode
1092 */
1093 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1094 reg_mcr &= ~FLEXCAN_MCR_FEN;
1095 else
1096 reg_mcr |= FLEXCAN_MCR_FEN;
1097
1098 /* MCR
1099 *
1100 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1101 * asserted because this will impede the self reception
1102 * of a transmitted message. This is not documented in
1103 * earlier versions of flexcan block guide.
1104 *
1105 * Self Reception:
1106 * - enable Self Reception for loopback mode
1107 * (by clearing "Self Reception Disable" bit)
1108 * - disable for normal operation
1109 */
1110 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1111 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1112 else
1113 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1114
1115 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1116 priv->write(reg_mcr, &regs->mcr);
1117
1118 /* CTRL
1119 *
1120 * disable timer sync feature
1121 *
1122 * disable auto busoff recovery
1123 * transmit lowest buffer first
1124 *
1125 * enable tx and rx warning interrupt
1126 * enable bus off interrupt
1127 * (== FLEXCAN_CTRL_ERR_STATE)
1128 */
1129 reg_ctrl = priv->read(&regs->ctrl);
1130 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1131 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1132 FLEXCAN_CTRL_ERR_STATE;
1133
1134 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1135 * on most Flexcan cores, too. Otherwise we don't get
1136 * any error warning or passive interrupts.
1137 */
1138 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1139 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1140 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1141 else
1142 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1143
1144 /* save for later use */
1145 priv->reg_ctrl_default = reg_ctrl;
1146 /* leave interrupts disabled for now */
1147 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1148 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1149 priv->write(reg_ctrl, &regs->ctrl);
1150
1151 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1152 reg_ctrl2 = priv->read(&regs->ctrl2);
1153 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1154 priv->write(reg_ctrl2, &regs->ctrl2);
1155 }
1156
1157 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1158 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1159 mb = flexcan_get_mb(priv, i);
1160 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1161 &mb->can_ctrl);
1162 }
1163 } else {
1164 /* clear and invalidate unused mailboxes first */
1165 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1166 mb = flexcan_get_mb(priv, i);
1167 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1168 &mb->can_ctrl);
1169 }
1170 }
1171
1172 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1173 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1174 &priv->tx_mb_reserved->can_ctrl);
1175
1176 /* mark TX mailbox as INACTIVE */
1177 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1178 &priv->tx_mb->can_ctrl);
1179
1180 /* acceptance mask/acceptance code (accept everything) */
1181 priv->write(0x0, &regs->rxgmask);
1182 priv->write(0x0, &regs->rx14mask);
1183 priv->write(0x0, &regs->rx15mask);
1184
1185 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1186 priv->write(0x0, &regs->rxfgmask);
1187
1188 /* clear acceptance filters */
1189 for (i = 0; i < priv->mb_count; i++)
1190 priv->write(0, &regs->rximr[i]);
1191
1192 /* On Vybrid, disable memory error detection interrupts
1193 * and freeze mode.
1194 * This also works around errata e5295 which generates
1195 * false positive memory errors and put the device in
1196 * freeze mode.
1197 */
1198 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1199 /* Follow the protocol as described in "Detection
1200 * and Correction of Memory Errors" to write to
1201 * MECR register
1202 */
1203 reg_ctrl2 = priv->read(&regs->ctrl2);
1204 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1205 priv->write(reg_ctrl2, &regs->ctrl2);
1206
1207 reg_mecr = priv->read(&regs->mecr);
1208 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1209 priv->write(reg_mecr, &regs->mecr);
1210 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1211 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1212 FLEXCAN_MECR_FANCEI_MSK);
1213 priv->write(reg_mecr, &regs->mecr);
1214 }
1215
1216 err = flexcan_transceiver_enable(priv);
1217 if (err)
1218 goto out_chip_disable;
1219
1220 /* synchronize with the can bus */
1221 err = flexcan_chip_unfreeze(priv);
1222 if (err)
1223 goto out_transceiver_disable;
1224
1225 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1226
1227 /* enable interrupts atomically */
1228 disable_irq(dev->irq);
1229 priv->write(priv->reg_ctrl_default, &regs->ctrl);
1230 priv->write(priv->reg_imask1_default, &regs->imask1);
1231 priv->write(priv->reg_imask2_default, &regs->imask2);
1232 enable_irq(dev->irq);
1233
1234 /* print chip status */
1235 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1236 priv->read(&regs->mcr), priv->read(&regs->ctrl));
1237
1238 return 0;
1239
1240 out_transceiver_disable:
1241 flexcan_transceiver_disable(priv);
1242 out_chip_disable:
1243 flexcan_chip_disable(priv);
1244 return err;
1245 }
1246
1247 /* flexcan_chip_stop
1248 *
1249 * this functions is entered with clocks enabled
1250 */
1251 static void flexcan_chip_stop(struct net_device *dev)
1252 {
1253 struct flexcan_priv *priv = netdev_priv(dev);
1254 struct flexcan_regs __iomem *regs = priv->regs;
1255
1256 /* freeze + disable module */
1257 flexcan_chip_freeze(priv);
1258 flexcan_chip_disable(priv);
1259
1260 /* Disable all interrupts */
1261 priv->write(0, &regs->imask2);
1262 priv->write(0, &regs->imask1);
1263 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1264 &regs->ctrl);
1265
1266 flexcan_transceiver_disable(priv);
1267 priv->can.state = CAN_STATE_STOPPED;
1268 }
1269
1270 static int flexcan_open(struct net_device *dev)
1271 {
1272 struct flexcan_priv *priv = netdev_priv(dev);
1273 int err;
1274
1275 err = pm_runtime_get_sync(priv->dev);
1276 if (err < 0)
1277 return err;
1278
1279 err = open_candev(dev);
1280 if (err)
1281 goto out_runtime_put;
1282
1283 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1284 if (err)
1285 goto out_close;
1286
1287 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1288 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1289 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1290
1291 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1292 priv->tx_mb_reserved =
1293 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1294 else
1295 priv->tx_mb_reserved =
1296 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1297 priv->tx_mb_idx = priv->mb_count - 1;
1298 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1299
1300 priv->reg_imask1_default = 0;
1301 priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1302
1303 priv->offload.mailbox_read = flexcan_mailbox_read;
1304
1305 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1306 u64 imask;
1307
1308 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1309 priv->offload.mb_last = priv->mb_count - 2;
1310
1311 imask = GENMASK_ULL(priv->offload.mb_last,
1312 priv->offload.mb_first);
1313 priv->reg_imask1_default |= imask;
1314 priv->reg_imask2_default |= imask >> 32;
1315
1316 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1317 } else {
1318 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1319 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1320 err = can_rx_offload_add_fifo(dev, &priv->offload,
1321 FLEXCAN_NAPI_WEIGHT);
1322 }
1323 if (err)
1324 goto out_free_irq;
1325
1326 /* start chip and queuing */
1327 err = flexcan_chip_start(dev);
1328 if (err)
1329 goto out_offload_del;
1330
1331 can_led_event(dev, CAN_LED_EVENT_OPEN);
1332
1333 can_rx_offload_enable(&priv->offload);
1334 netif_start_queue(dev);
1335
1336 return 0;
1337
1338 out_offload_del:
1339 can_rx_offload_del(&priv->offload);
1340 out_free_irq:
1341 free_irq(dev->irq, dev);
1342 out_close:
1343 close_candev(dev);
1344 out_runtime_put:
1345 pm_runtime_put(priv->dev);
1346
1347 return err;
1348 }
1349
1350 static int flexcan_close(struct net_device *dev)
1351 {
1352 struct flexcan_priv *priv = netdev_priv(dev);
1353
1354 netif_stop_queue(dev);
1355 can_rx_offload_disable(&priv->offload);
1356 flexcan_chip_stop(dev);
1357
1358 can_rx_offload_del(&priv->offload);
1359 free_irq(dev->irq, dev);
1360
1361 close_candev(dev);
1362 pm_runtime_put(priv->dev);
1363
1364 can_led_event(dev, CAN_LED_EVENT_STOP);
1365
1366 return 0;
1367 }
1368
1369 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1370 {
1371 int err;
1372
1373 switch (mode) {
1374 case CAN_MODE_START:
1375 err = flexcan_chip_start(dev);
1376 if (err)
1377 return err;
1378
1379 netif_wake_queue(dev);
1380 break;
1381
1382 default:
1383 return -EOPNOTSUPP;
1384 }
1385
1386 return 0;
1387 }
1388
1389 static const struct net_device_ops flexcan_netdev_ops = {
1390 .ndo_open = flexcan_open,
1391 .ndo_stop = flexcan_close,
1392 .ndo_start_xmit = flexcan_start_xmit,
1393 .ndo_change_mtu = can_change_mtu,
1394 };
1395
1396 static int register_flexcandev(struct net_device *dev)
1397 {
1398 struct flexcan_priv *priv = netdev_priv(dev);
1399 struct flexcan_regs __iomem *regs = priv->regs;
1400 u32 reg, err;
1401
1402 err = flexcan_clks_enable(priv);
1403 if (err)
1404 return err;
1405
1406 /* select "bus clock", chip must be disabled */
1407 err = flexcan_chip_disable(priv);
1408 if (err)
1409 goto out_clks_disable;
1410
1411 reg = priv->read(&regs->ctrl);
1412 if (priv->clk_src)
1413 reg |= FLEXCAN_CTRL_CLK_SRC;
1414 else
1415 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1416 priv->write(reg, &regs->ctrl);
1417
1418 err = flexcan_chip_enable(priv);
1419 if (err)
1420 goto out_chip_disable;
1421
1422 /* set freeze, halt and activate FIFO, restrict register access */
1423 reg = priv->read(&regs->mcr);
1424 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1425 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1426 priv->write(reg, &regs->mcr);
1427
1428 /* Currently we only support newer versions of this core
1429 * featuring a RX hardware FIFO (although this driver doesn't
1430 * make use of it on some cores). Older cores, found on some
1431 * Coldfire derivates are not tested.
1432 */
1433 reg = priv->read(&regs->mcr);
1434 if (!(reg & FLEXCAN_MCR_FEN)) {
1435 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1436 err = -ENODEV;
1437 goto out_chip_disable;
1438 }
1439
1440 err = register_candev(dev);
1441 if (err)
1442 goto out_chip_disable;
1443
1444 /* Disable core and let pm_runtime_put() disable the clocks.
1445 * If CONFIG_PM is not enabled, the clocks will stay powered.
1446 */
1447 flexcan_chip_disable(priv);
1448 pm_runtime_put(priv->dev);
1449
1450 return 0;
1451
1452 out_chip_disable:
1453 flexcan_chip_disable(priv);
1454 out_clks_disable:
1455 flexcan_clks_disable(priv);
1456 return err;
1457 }
1458
1459 static void unregister_flexcandev(struct net_device *dev)
1460 {
1461 unregister_candev(dev);
1462 }
1463
1464 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1465 {
1466 struct net_device *dev = platform_get_drvdata(pdev);
1467 struct device_node *np = pdev->dev.of_node;
1468 struct device_node *gpr_np;
1469 struct flexcan_priv *priv;
1470 phandle phandle;
1471 u32 out_val[5];
1472 int ret;
1473
1474 if (!np)
1475 return -EINVAL;
1476
1477 /* stop mode property format is:
1478 * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1479 */
1480 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1481 ARRAY_SIZE(out_val));
1482 if (ret) {
1483 dev_dbg(&pdev->dev, "no stop-mode property\n");
1484 return ret;
1485 }
1486 phandle = *out_val;
1487
1488 gpr_np = of_find_node_by_phandle(phandle);
1489 if (!gpr_np) {
1490 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1491 return -ENODEV;
1492 }
1493
1494 priv = netdev_priv(dev);
1495 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1496 if (IS_ERR(priv->stm.gpr)) {
1497 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1498 ret = PTR_ERR(priv->stm.gpr);
1499 goto out_put_node;
1500 }
1501
1502 priv->stm.req_gpr = out_val[1];
1503 priv->stm.req_bit = out_val[2];
1504 priv->stm.ack_gpr = out_val[3];
1505 priv->stm.ack_bit = out_val[4];
1506
1507 dev_dbg(&pdev->dev,
1508 "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1509 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1510 priv->stm.ack_gpr, priv->stm.ack_bit);
1511
1512 device_set_wakeup_capable(&pdev->dev, true);
1513
1514 if (of_property_read_bool(np, "wakeup-source"))
1515 device_set_wakeup_enable(&pdev->dev, true);
1516
1517 return 0;
1518
1519 out_put_node:
1520 of_node_put(gpr_np);
1521 return ret;
1522 }
1523
1524 static const struct of_device_id flexcan_of_match[] = {
1525 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1526 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1527 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1528 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1529 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1530 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1531 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1532 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1533 { /* sentinel */ },
1534 };
1535 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1536
1537 static const struct platform_device_id flexcan_id_table[] = {
1538 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1539 { /* sentinel */ },
1540 };
1541 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1542
1543 static int flexcan_probe(struct platform_device *pdev)
1544 {
1545 const struct of_device_id *of_id;
1546 const struct flexcan_devtype_data *devtype_data;
1547 struct net_device *dev;
1548 struct flexcan_priv *priv;
1549 struct regulator *reg_xceiver;
1550 struct clk *clk_ipg = NULL, *clk_per = NULL;
1551 struct flexcan_regs __iomem *regs;
1552 int err, irq;
1553 u8 clk_src = 1;
1554 u32 clock_freq = 0;
1555
1556 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1557 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1558 return -EPROBE_DEFER;
1559 else if (IS_ERR(reg_xceiver))
1560 reg_xceiver = NULL;
1561
1562 if (pdev->dev.of_node) {
1563 of_property_read_u32(pdev->dev.of_node,
1564 "clock-frequency", &clock_freq);
1565 of_property_read_u8(pdev->dev.of_node,
1566 "fsl,clk-source", &clk_src);
1567 }
1568
1569 if (!clock_freq) {
1570 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1571 if (IS_ERR(clk_ipg)) {
1572 dev_err(&pdev->dev, "no ipg clock defined\n");
1573 return PTR_ERR(clk_ipg);
1574 }
1575
1576 clk_per = devm_clk_get(&pdev->dev, "per");
1577 if (IS_ERR(clk_per)) {
1578 dev_err(&pdev->dev, "no per clock defined\n");
1579 return PTR_ERR(clk_per);
1580 }
1581 clock_freq = clk_get_rate(clk_per);
1582 }
1583
1584 irq = platform_get_irq(pdev, 0);
1585 if (irq <= 0)
1586 return -ENODEV;
1587
1588 regs = devm_platform_ioremap_resource(pdev, 0);
1589 if (IS_ERR(regs))
1590 return PTR_ERR(regs);
1591
1592 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1593 if (of_id) {
1594 devtype_data = of_id->data;
1595 } else if (platform_get_device_id(pdev)->driver_data) {
1596 devtype_data = (struct flexcan_devtype_data *)
1597 platform_get_device_id(pdev)->driver_data;
1598 } else {
1599 return -ENODEV;
1600 }
1601
1602 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1603 if (!dev)
1604 return -ENOMEM;
1605
1606 platform_set_drvdata(pdev, dev);
1607 SET_NETDEV_DEV(dev, &pdev->dev);
1608
1609 dev->netdev_ops = &flexcan_netdev_ops;
1610 dev->irq = irq;
1611 dev->flags |= IFF_ECHO;
1612
1613 priv = netdev_priv(dev);
1614
1615 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1616 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1617 priv->read = flexcan_read_be;
1618 priv->write = flexcan_write_be;
1619 } else {
1620 priv->read = flexcan_read_le;
1621 priv->write = flexcan_write_le;
1622 }
1623
1624 priv->dev = &pdev->dev;
1625 priv->can.clock.freq = clock_freq;
1626 priv->can.bittiming_const = &flexcan_bittiming_const;
1627 priv->can.do_set_mode = flexcan_set_mode;
1628 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1629 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1630 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1631 CAN_CTRLMODE_BERR_REPORTING;
1632 priv->regs = regs;
1633 priv->clk_ipg = clk_ipg;
1634 priv->clk_per = clk_per;
1635 priv->clk_src = clk_src;
1636 priv->devtype_data = devtype_data;
1637 priv->reg_xceiver = reg_xceiver;
1638
1639 pm_runtime_get_noresume(&pdev->dev);
1640 pm_runtime_set_active(&pdev->dev);
1641 pm_runtime_enable(&pdev->dev);
1642
1643 err = register_flexcandev(dev);
1644 if (err) {
1645 dev_err(&pdev->dev, "registering netdev failed\n");
1646 goto failed_register;
1647 }
1648
1649 devm_can_led_init(dev);
1650
1651 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1652 err = flexcan_setup_stop_mode(pdev);
1653 if (err)
1654 dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1655 }
1656
1657 return 0;
1658
1659 failed_register:
1660 free_candev(dev);
1661 return err;
1662 }
1663
1664 static int flexcan_remove(struct platform_device *pdev)
1665 {
1666 struct net_device *dev = platform_get_drvdata(pdev);
1667
1668 unregister_flexcandev(dev);
1669 pm_runtime_disable(&pdev->dev);
1670 free_candev(dev);
1671
1672 return 0;
1673 }
1674
1675 static int __maybe_unused flexcan_suspend(struct device *device)
1676 {
1677 struct net_device *dev = dev_get_drvdata(device);
1678 struct flexcan_priv *priv = netdev_priv(dev);
1679 int err = 0;
1680
1681 if (netif_running(dev)) {
1682 /* if wakeup is enabled, enter stop mode
1683 * else enter disabled mode.
1684 */
1685 if (device_may_wakeup(device)) {
1686 enable_irq_wake(dev->irq);
1687 err = flexcan_enter_stop_mode(priv);
1688 if (err)
1689 return err;
1690 } else {
1691 err = flexcan_chip_disable(priv);
1692 if (err)
1693 return err;
1694
1695 err = pm_runtime_force_suspend(device);
1696 }
1697 netif_stop_queue(dev);
1698 netif_device_detach(dev);
1699 }
1700 priv->can.state = CAN_STATE_SLEEPING;
1701
1702 return err;
1703 }
1704
1705 static int __maybe_unused flexcan_resume(struct device *device)
1706 {
1707 struct net_device *dev = dev_get_drvdata(device);
1708 struct flexcan_priv *priv = netdev_priv(dev);
1709 int err = 0;
1710
1711 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1712 if (netif_running(dev)) {
1713 netif_device_attach(dev);
1714 netif_start_queue(dev);
1715 if (device_may_wakeup(device)) {
1716 disable_irq_wake(dev->irq);
1717 } else {
1718 err = pm_runtime_force_resume(device);
1719 if (err)
1720 return err;
1721
1722 err = flexcan_chip_enable(priv);
1723 }
1724 }
1725
1726 return err;
1727 }
1728
1729 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
1730 {
1731 struct net_device *dev = dev_get_drvdata(device);
1732 struct flexcan_priv *priv = netdev_priv(dev);
1733
1734 flexcan_clks_disable(priv);
1735
1736 return 0;
1737 }
1738
1739 static int __maybe_unused flexcan_runtime_resume(struct device *device)
1740 {
1741 struct net_device *dev = dev_get_drvdata(device);
1742 struct flexcan_priv *priv = netdev_priv(dev);
1743
1744 return flexcan_clks_enable(priv);
1745 }
1746
1747 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1748 {
1749 struct net_device *dev = dev_get_drvdata(device);
1750 struct flexcan_priv *priv = netdev_priv(dev);
1751
1752 if (netif_running(dev) && device_may_wakeup(device))
1753 flexcan_enable_wakeup_irq(priv, true);
1754
1755 return 0;
1756 }
1757
1758 static int __maybe_unused flexcan_noirq_resume(struct device *device)
1759 {
1760 struct net_device *dev = dev_get_drvdata(device);
1761 struct flexcan_priv *priv = netdev_priv(dev);
1762 int err;
1763
1764 if (netif_running(dev) && device_may_wakeup(device)) {
1765 flexcan_enable_wakeup_irq(priv, false);
1766 err = flexcan_exit_stop_mode(priv);
1767 if (err)
1768 return err;
1769 }
1770
1771 return 0;
1772 }
1773
1774 static const struct dev_pm_ops flexcan_pm_ops = {
1775 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1776 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
1777 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1778 };
1779
1780 static struct platform_driver flexcan_driver = {
1781 .driver = {
1782 .name = DRV_NAME,
1783 .pm = &flexcan_pm_ops,
1784 .of_match_table = flexcan_of_match,
1785 },
1786 .probe = flexcan_probe,
1787 .remove = flexcan_remove,
1788 .id_table = flexcan_id_table,
1789 };
1790
1791 module_platform_driver(flexcan_driver);
1792
1793 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1794 "Marc Kleine-Budde <kernel@pengutronix.de>");
1795 MODULE_LICENSE("GPL v2");
1796 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Ubuntu Hirsute Linux kernel mirror