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Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm
[mirror_ubuntu-bionic-kernel.git] / drivers / net / can / flexcan.c
1 /*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
7 * Copyright (c) 2014 David Jander, Protonic Holland
8 *
9 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
10 *
11 * LICENCE:
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 #include <linux/netdevice.h>
24 #include <linux/can.h>
25 #include <linux/can/dev.h>
26 #include <linux/can/error.h>
27 #include <linux/can/led.h>
28 #include <linux/can/rx-offload.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/module.h>
34 #include <linux/of.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/regulator/consumer.h>
38
39 #define DRV_NAME "flexcan"
40
41 /* 8 for RX fifo and 2 error handling */
42 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
43
44 /* FLEXCAN module configuration register (CANMCR) bits */
45 #define FLEXCAN_MCR_MDIS BIT(31)
46 #define FLEXCAN_MCR_FRZ BIT(30)
47 #define FLEXCAN_MCR_FEN BIT(29)
48 #define FLEXCAN_MCR_HALT BIT(28)
49 #define FLEXCAN_MCR_NOT_RDY BIT(27)
50 #define FLEXCAN_MCR_WAK_MSK BIT(26)
51 #define FLEXCAN_MCR_SOFTRST BIT(25)
52 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
53 #define FLEXCAN_MCR_SUPV BIT(23)
54 #define FLEXCAN_MCR_SLF_WAK BIT(22)
55 #define FLEXCAN_MCR_WRN_EN BIT(21)
56 #define FLEXCAN_MCR_LPM_ACK BIT(20)
57 #define FLEXCAN_MCR_WAK_SRC BIT(19)
58 #define FLEXCAN_MCR_DOZE BIT(18)
59 #define FLEXCAN_MCR_SRX_DIS BIT(17)
60 #define FLEXCAN_MCR_IRMQ BIT(16)
61 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
62 #define FLEXCAN_MCR_AEN BIT(12)
63 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
64 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
65 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
66 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
67 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
68 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
69
70 /* FLEXCAN control register (CANCTRL) bits */
71 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
72 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
73 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
74 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
75 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
76 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
77 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
78 #define FLEXCAN_CTRL_LPB BIT(12)
79 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
80 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
81 #define FLEXCAN_CTRL_SMP BIT(7)
82 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
83 #define FLEXCAN_CTRL_TSYN BIT(5)
84 #define FLEXCAN_CTRL_LBUF BIT(4)
85 #define FLEXCAN_CTRL_LOM BIT(3)
86 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
87 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
88 #define FLEXCAN_CTRL_ERR_STATE \
89 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
90 FLEXCAN_CTRL_BOFF_MSK)
91 #define FLEXCAN_CTRL_ERR_ALL \
92 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
93
94 /* FLEXCAN control register 2 (CTRL2) bits */
95 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
96 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
97 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
98 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
99 #define FLEXCAN_CTRL2_MRP BIT(18)
100 #define FLEXCAN_CTRL2_RRS BIT(17)
101 #define FLEXCAN_CTRL2_EACEN BIT(16)
102
103 /* FLEXCAN memory error control register (MECR) bits */
104 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
105 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
106 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
107 #define FLEXCAN_MECR_CEI_MSK BIT(16)
108 #define FLEXCAN_MECR_HAERRIE BIT(15)
109 #define FLEXCAN_MECR_FAERRIE BIT(14)
110 #define FLEXCAN_MECR_EXTERRIE BIT(13)
111 #define FLEXCAN_MECR_RERRDIS BIT(9)
112 #define FLEXCAN_MECR_ECCDIS BIT(8)
113 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
114
115 /* FLEXCAN error and status register (ESR) bits */
116 #define FLEXCAN_ESR_TWRN_INT BIT(17)
117 #define FLEXCAN_ESR_RWRN_INT BIT(16)
118 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
119 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
120 #define FLEXCAN_ESR_ACK_ERR BIT(13)
121 #define FLEXCAN_ESR_CRC_ERR BIT(12)
122 #define FLEXCAN_ESR_FRM_ERR BIT(11)
123 #define FLEXCAN_ESR_STF_ERR BIT(10)
124 #define FLEXCAN_ESR_TX_WRN BIT(9)
125 #define FLEXCAN_ESR_RX_WRN BIT(8)
126 #define FLEXCAN_ESR_IDLE BIT(7)
127 #define FLEXCAN_ESR_TXRX BIT(6)
128 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
129 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_BOFF_INT BIT(2)
133 #define FLEXCAN_ESR_ERR_INT BIT(1)
134 #define FLEXCAN_ESR_WAK_INT BIT(0)
135 #define FLEXCAN_ESR_ERR_BUS \
136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139 #define FLEXCAN_ESR_ERR_STATE \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141 #define FLEXCAN_ESR_ERR_ALL \
142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143 #define FLEXCAN_ESR_ALL_INT \
144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
146
147 /* FLEXCAN interrupt flag register (IFLAG) bits */
148 /* Errata ERR005829 step7: Reserve first valid MB */
149 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
150 #define FLEXCAN_TX_MB_OFF_FIFO 9
151 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
152 #define FLEXCAN_TX_MB_OFF_TIMESTAMP 1
153 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_OFF_TIMESTAMP + 1)
154 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST 63
155 #define FLEXCAN_IFLAG_MB(x) BIT(x)
156 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
157 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
158 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
159
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
162 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
163 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
164 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
165 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
166 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
167 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
168
169 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
170 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
171 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
172 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
173
174 #define FLEXCAN_MB_CNT_SRR BIT(22)
175 #define FLEXCAN_MB_CNT_IDE BIT(21)
176 #define FLEXCAN_MB_CNT_RTR BIT(20)
177 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
178 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
179
180 #define FLEXCAN_TIMEOUT_US (50)
181
182 /* FLEXCAN hardware feature flags
183 *
184 * Below is some version info we got:
185 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
186 * Filter? connected? Passive detection ception in MB
187 * MX25 FlexCAN2 03.00.00.00 no no ? no no
188 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
189 * MX35 FlexCAN2 03.00.00.00 no no ? no no
190 * MX53 FlexCAN2 03.00.00.00 yes no no no no
191 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
192 * VF610 FlexCAN3 ? no yes ? yes yes?
193 *
194 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
195 */
196 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
197 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
198 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
199 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
200 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
201 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
202
203 /* Structure of the message buffer */
204 struct flexcan_mb {
205 u32 can_ctrl;
206 u32 can_id;
207 u32 data[2];
208 };
209
210 /* Structure of the hardware registers */
211 struct flexcan_regs {
212 u32 mcr; /* 0x00 */
213 u32 ctrl; /* 0x04 */
214 u32 timer; /* 0x08 */
215 u32 _reserved1; /* 0x0c */
216 u32 rxgmask; /* 0x10 */
217 u32 rx14mask; /* 0x14 */
218 u32 rx15mask; /* 0x18 */
219 u32 ecr; /* 0x1c */
220 u32 esr; /* 0x20 */
221 u32 imask2; /* 0x24 */
222 u32 imask1; /* 0x28 */
223 u32 iflag2; /* 0x2c */
224 u32 iflag1; /* 0x30 */
225 union { /* 0x34 */
226 u32 gfwr_mx28; /* MX28, MX53 */
227 u32 ctrl2; /* MX6, VF610 */
228 };
229 u32 esr2; /* 0x38 */
230 u32 imeur; /* 0x3c */
231 u32 lrfr; /* 0x40 */
232 u32 crcr; /* 0x44 */
233 u32 rxfgmask; /* 0x48 */
234 u32 rxfir; /* 0x4c */
235 u32 _reserved3[12]; /* 0x50 */
236 struct flexcan_mb mb[64]; /* 0x80 */
237 /* FIFO-mode:
238 * MB
239 * 0x080...0x08f 0 RX message buffer
240 * 0x090...0x0df 1-5 reserverd
241 * 0x0e0...0x0ff 6-7 8 entry ID table
242 * (mx25, mx28, mx35, mx53)
243 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
244 * size conf'ed via ctrl2::RFFN
245 * (mx6, vf610)
246 */
247 u32 _reserved4[256]; /* 0x480 */
248 u32 rximr[64]; /* 0x880 */
249 u32 _reserved5[24]; /* 0x980 */
250 u32 gfwr_mx6; /* 0x9e0 - MX6 */
251 u32 _reserved6[63]; /* 0x9e4 */
252 u32 mecr; /* 0xae0 */
253 u32 erriar; /* 0xae4 */
254 u32 erridpr; /* 0xae8 */
255 u32 errippr; /* 0xaec */
256 u32 rerrar; /* 0xaf0 */
257 u32 rerrdr; /* 0xaf4 */
258 u32 rerrsynr; /* 0xaf8 */
259 u32 errsr; /* 0xafc */
260 };
261
262 struct flexcan_devtype_data {
263 u32 quirks; /* quirks needed for different IP cores */
264 };
265
266 struct flexcan_priv {
267 struct can_priv can;
268 struct can_rx_offload offload;
269
270 struct flexcan_regs __iomem *regs;
271 struct flexcan_mb __iomem *tx_mb;
272 struct flexcan_mb __iomem *tx_mb_reserved;
273 u8 tx_mb_idx;
274 u32 reg_ctrl_default;
275 u32 reg_imask1_default;
276 u32 reg_imask2_default;
277
278 struct clk *clk_ipg;
279 struct clk *clk_per;
280 const struct flexcan_devtype_data *devtype_data;
281 struct regulator *reg_xceiver;
282 };
283
284 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
285 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
286 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
287 };
288
289 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
290 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
291 };
292
293 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
294 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
295 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
296 };
297
298 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
299 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
300 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
301 };
302
303 static const struct can_bittiming_const flexcan_bittiming_const = {
304 .name = DRV_NAME,
305 .tseg1_min = 4,
306 .tseg1_max = 16,
307 .tseg2_min = 2,
308 .tseg2_max = 8,
309 .sjw_max = 4,
310 .brp_min = 1,
311 .brp_max = 256,
312 .brp_inc = 1,
313 };
314
315 /* Abstract off the read/write for arm versus ppc. This
316 * assumes that PPC uses big-endian registers and everything
317 * else uses little-endian registers, independent of CPU
318 * endianness.
319 */
320 #if defined(CONFIG_PPC)
321 static inline u32 flexcan_read(void __iomem *addr)
322 {
323 return in_be32(addr);
324 }
325
326 static inline void flexcan_write(u32 val, void __iomem *addr)
327 {
328 out_be32(addr, val);
329 }
330 #else
331 static inline u32 flexcan_read(void __iomem *addr)
332 {
333 return readl(addr);
334 }
335
336 static inline void flexcan_write(u32 val, void __iomem *addr)
337 {
338 writel(val, addr);
339 }
340 #endif
341
342 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
343 {
344 struct flexcan_regs __iomem *regs = priv->regs;
345 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
346
347 flexcan_write(reg_ctrl, &regs->ctrl);
348 }
349
350 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
351 {
352 struct flexcan_regs __iomem *regs = priv->regs;
353 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
354
355 flexcan_write(reg_ctrl, &regs->ctrl);
356 }
357
358 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
359 {
360 if (!priv->reg_xceiver)
361 return 0;
362
363 return regulator_enable(priv->reg_xceiver);
364 }
365
366 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
367 {
368 if (!priv->reg_xceiver)
369 return 0;
370
371 return regulator_disable(priv->reg_xceiver);
372 }
373
374 static int flexcan_chip_enable(struct flexcan_priv *priv)
375 {
376 struct flexcan_regs __iomem *regs = priv->regs;
377 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
378 u32 reg;
379
380 reg = flexcan_read(&regs->mcr);
381 reg &= ~FLEXCAN_MCR_MDIS;
382 flexcan_write(reg, &regs->mcr);
383
384 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
385 udelay(10);
386
387 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
388 return -ETIMEDOUT;
389
390 return 0;
391 }
392
393 static int flexcan_chip_disable(struct flexcan_priv *priv)
394 {
395 struct flexcan_regs __iomem *regs = priv->regs;
396 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
397 u32 reg;
398
399 reg = flexcan_read(&regs->mcr);
400 reg |= FLEXCAN_MCR_MDIS;
401 flexcan_write(reg, &regs->mcr);
402
403 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
404 udelay(10);
405
406 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
407 return -ETIMEDOUT;
408
409 return 0;
410 }
411
412 static int flexcan_chip_freeze(struct flexcan_priv *priv)
413 {
414 struct flexcan_regs __iomem *regs = priv->regs;
415 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
416 u32 reg;
417
418 reg = flexcan_read(&regs->mcr);
419 reg |= FLEXCAN_MCR_HALT;
420 flexcan_write(reg, &regs->mcr);
421
422 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
423 udelay(100);
424
425 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
426 return -ETIMEDOUT;
427
428 return 0;
429 }
430
431 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
432 {
433 struct flexcan_regs __iomem *regs = priv->regs;
434 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
435 u32 reg;
436
437 reg = flexcan_read(&regs->mcr);
438 reg &= ~FLEXCAN_MCR_HALT;
439 flexcan_write(reg, &regs->mcr);
440
441 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
442 udelay(10);
443
444 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
445 return -ETIMEDOUT;
446
447 return 0;
448 }
449
450 static int flexcan_chip_softreset(struct flexcan_priv *priv)
451 {
452 struct flexcan_regs __iomem *regs = priv->regs;
453 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
454
455 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
456 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
457 udelay(10);
458
459 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
460 return -ETIMEDOUT;
461
462 return 0;
463 }
464
465 static int __flexcan_get_berr_counter(const struct net_device *dev,
466 struct can_berr_counter *bec)
467 {
468 const struct flexcan_priv *priv = netdev_priv(dev);
469 struct flexcan_regs __iomem *regs = priv->regs;
470 u32 reg = flexcan_read(&regs->ecr);
471
472 bec->txerr = (reg >> 0) & 0xff;
473 bec->rxerr = (reg >> 8) & 0xff;
474
475 return 0;
476 }
477
478 static int flexcan_get_berr_counter(const struct net_device *dev,
479 struct can_berr_counter *bec)
480 {
481 const struct flexcan_priv *priv = netdev_priv(dev);
482 int err;
483
484 err = clk_prepare_enable(priv->clk_ipg);
485 if (err)
486 return err;
487
488 err = clk_prepare_enable(priv->clk_per);
489 if (err)
490 goto out_disable_ipg;
491
492 err = __flexcan_get_berr_counter(dev, bec);
493
494 clk_disable_unprepare(priv->clk_per);
495 out_disable_ipg:
496 clk_disable_unprepare(priv->clk_ipg);
497
498 return err;
499 }
500
501 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
502 {
503 const struct flexcan_priv *priv = netdev_priv(dev);
504 struct can_frame *cf = (struct can_frame *)skb->data;
505 u32 can_id;
506 u32 data;
507 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
508
509 if (can_dropped_invalid_skb(dev, skb))
510 return NETDEV_TX_OK;
511
512 netif_stop_queue(dev);
513
514 if (cf->can_id & CAN_EFF_FLAG) {
515 can_id = cf->can_id & CAN_EFF_MASK;
516 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
517 } else {
518 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
519 }
520
521 if (cf->can_id & CAN_RTR_FLAG)
522 ctrl |= FLEXCAN_MB_CNT_RTR;
523
524 if (cf->can_dlc > 0) {
525 data = be32_to_cpup((__be32 *)&cf->data[0]);
526 flexcan_write(data, &priv->tx_mb->data[0]);
527 }
528 if (cf->can_dlc > 3) {
529 data = be32_to_cpup((__be32 *)&cf->data[4]);
530 flexcan_write(data, &priv->tx_mb->data[1]);
531 }
532
533 can_put_echo_skb(skb, dev, 0);
534
535 flexcan_write(can_id, &priv->tx_mb->can_id);
536 flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
537
538 /* Errata ERR005829 step8:
539 * Write twice INACTIVE(0x8) code to first MB.
540 */
541 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
542 &priv->tx_mb_reserved->can_ctrl);
543 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
544 &priv->tx_mb_reserved->can_ctrl);
545
546 return NETDEV_TX_OK;
547 }
548
549 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
550 {
551 struct flexcan_priv *priv = netdev_priv(dev);
552 struct sk_buff *skb;
553 struct can_frame *cf;
554 bool rx_errors = false, tx_errors = false;
555
556 skb = alloc_can_err_skb(dev, &cf);
557 if (unlikely(!skb))
558 return;
559
560 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
561
562 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
563 netdev_dbg(dev, "BIT1_ERR irq\n");
564 cf->data[2] |= CAN_ERR_PROT_BIT1;
565 tx_errors = true;
566 }
567 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
568 netdev_dbg(dev, "BIT0_ERR irq\n");
569 cf->data[2] |= CAN_ERR_PROT_BIT0;
570 tx_errors = true;
571 }
572 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
573 netdev_dbg(dev, "ACK_ERR irq\n");
574 cf->can_id |= CAN_ERR_ACK;
575 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
576 tx_errors = true;
577 }
578 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
579 netdev_dbg(dev, "CRC_ERR irq\n");
580 cf->data[2] |= CAN_ERR_PROT_BIT;
581 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
582 rx_errors = true;
583 }
584 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
585 netdev_dbg(dev, "FRM_ERR irq\n");
586 cf->data[2] |= CAN_ERR_PROT_FORM;
587 rx_errors = true;
588 }
589 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
590 netdev_dbg(dev, "STF_ERR irq\n");
591 cf->data[2] |= CAN_ERR_PROT_STUFF;
592 rx_errors = true;
593 }
594
595 priv->can.can_stats.bus_error++;
596 if (rx_errors)
597 dev->stats.rx_errors++;
598 if (tx_errors)
599 dev->stats.tx_errors++;
600
601 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
602 }
603
604 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
605 {
606 struct flexcan_priv *priv = netdev_priv(dev);
607 struct sk_buff *skb;
608 struct can_frame *cf;
609 enum can_state new_state, rx_state, tx_state;
610 int flt;
611 struct can_berr_counter bec;
612
613 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
614 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
615 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
616 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
617 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
618 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
619 new_state = max(tx_state, rx_state);
620 } else {
621 __flexcan_get_berr_counter(dev, &bec);
622 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
623 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
624 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
625 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
626 }
627
628 /* state hasn't changed */
629 if (likely(new_state == priv->can.state))
630 return;
631
632 skb = alloc_can_err_skb(dev, &cf);
633 if (unlikely(!skb))
634 return;
635
636 can_change_state(dev, cf, tx_state, rx_state);
637
638 if (unlikely(new_state == CAN_STATE_BUS_OFF))
639 can_bus_off(dev);
640
641 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
642 }
643
644 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
645 {
646 return container_of(offload, struct flexcan_priv, offload);
647 }
648
649 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
650 struct can_frame *cf,
651 u32 *timestamp, unsigned int n)
652 {
653 struct flexcan_priv *priv = rx_offload_to_priv(offload);
654 struct flexcan_regs __iomem *regs = priv->regs;
655 struct flexcan_mb __iomem *mb = &regs->mb[n];
656 u32 reg_ctrl, reg_id, reg_iflag1;
657
658 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
659 u32 code;
660
661 do {
662 reg_ctrl = flexcan_read(&mb->can_ctrl);
663 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
664
665 /* is this MB empty? */
666 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
667 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
668 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
669 return 0;
670
671 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
672 /* This MB was overrun, we lost data */
673 offload->dev->stats.rx_over_errors++;
674 offload->dev->stats.rx_errors++;
675 }
676 } else {
677 reg_iflag1 = flexcan_read(&regs->iflag1);
678 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
679 return 0;
680
681 reg_ctrl = flexcan_read(&mb->can_ctrl);
682 }
683
684 /* increase timstamp to full 32 bit */
685 *timestamp = reg_ctrl << 16;
686
687 reg_id = flexcan_read(&mb->can_id);
688 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
689 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
690 else
691 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
692
693 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
694 cf->can_id |= CAN_RTR_FLAG;
695 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
696
697 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
698 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
699
700 /* mark as read */
701 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
702 /* Clear IRQ */
703 if (n < 32)
704 flexcan_write(BIT(n), &regs->iflag1);
705 else
706 flexcan_write(BIT(n - 32), &regs->iflag2);
707 } else {
708 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
709 flexcan_read(&regs->timer);
710 }
711
712 return 1;
713 }
714
715
716 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
717 {
718 struct flexcan_regs __iomem *regs = priv->regs;
719 u32 iflag1, iflag2;
720
721 iflag2 = flexcan_read(&regs->iflag2) & priv->reg_imask2_default;
722 iflag1 = flexcan_read(&regs->iflag1) & priv->reg_imask1_default &
723 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
724
725 return (u64)iflag2 << 32 | iflag1;
726 }
727
728 static irqreturn_t flexcan_irq(int irq, void *dev_id)
729 {
730 struct net_device *dev = dev_id;
731 struct net_device_stats *stats = &dev->stats;
732 struct flexcan_priv *priv = netdev_priv(dev);
733 struct flexcan_regs __iomem *regs = priv->regs;
734 irqreturn_t handled = IRQ_NONE;
735 u32 reg_iflag1, reg_esr;
736 enum can_state last_state = priv->can.state;
737
738 reg_iflag1 = flexcan_read(&regs->iflag1);
739
740 /* reception interrupt */
741 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
742 u64 reg_iflag;
743 int ret;
744
745 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
746 handled = IRQ_HANDLED;
747 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
748 reg_iflag);
749 if (!ret)
750 break;
751 }
752 } else {
753 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
754 handled = IRQ_HANDLED;
755 can_rx_offload_irq_offload_fifo(&priv->offload);
756 }
757
758 /* FIFO overflow interrupt */
759 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
760 handled = IRQ_HANDLED;
761 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
762 dev->stats.rx_over_errors++;
763 dev->stats.rx_errors++;
764 }
765 }
766
767 /* transmission complete interrupt */
768 if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
769 handled = IRQ_HANDLED;
770 stats->tx_bytes += can_get_echo_skb(dev, 0);
771 stats->tx_packets++;
772 can_led_event(dev, CAN_LED_EVENT_TX);
773
774 /* after sending a RTR frame MB is in RX mode */
775 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
776 &priv->tx_mb->can_ctrl);
777 flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
778 netif_wake_queue(dev);
779 }
780
781 reg_esr = flexcan_read(&regs->esr);
782
783 /* ACK all bus error and state change IRQ sources */
784 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
785 handled = IRQ_HANDLED;
786 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
787 }
788
789 /* state change interrupt or broken error state quirk fix is enabled */
790 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
791 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
792 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
793 flexcan_irq_state(dev, reg_esr);
794
795 /* bus error IRQ - handle if bus error reporting is activated */
796 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
797 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
798 flexcan_irq_bus_err(dev, reg_esr);
799
800 /* availability of error interrupt among state transitions in case
801 * bus error reporting is de-activated and
802 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
803 * +--------------------------------------------------------------+
804 * | +----------------------------------------------+ [stopped / |
805 * | | | sleeping] -+
806 * +-+-> active <-> warning <-> passive -> bus off -+
807 * ___________^^^^^^^^^^^^_______________________________
808 * disabled(1) enabled disabled
809 *
810 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
811 */
812 if ((last_state != priv->can.state) &&
813 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
814 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
815 switch (priv->can.state) {
816 case CAN_STATE_ERROR_ACTIVE:
817 if (priv->devtype_data->quirks &
818 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
819 flexcan_error_irq_enable(priv);
820 else
821 flexcan_error_irq_disable(priv);
822 break;
823
824 case CAN_STATE_ERROR_WARNING:
825 flexcan_error_irq_enable(priv);
826 break;
827
828 case CAN_STATE_ERROR_PASSIVE:
829 case CAN_STATE_BUS_OFF:
830 flexcan_error_irq_disable(priv);
831 break;
832
833 default:
834 break;
835 }
836 }
837
838 return handled;
839 }
840
841 static void flexcan_set_bittiming(struct net_device *dev)
842 {
843 const struct flexcan_priv *priv = netdev_priv(dev);
844 const struct can_bittiming *bt = &priv->can.bittiming;
845 struct flexcan_regs __iomem *regs = priv->regs;
846 u32 reg;
847
848 reg = flexcan_read(&regs->ctrl);
849 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
850 FLEXCAN_CTRL_RJW(0x3) |
851 FLEXCAN_CTRL_PSEG1(0x7) |
852 FLEXCAN_CTRL_PSEG2(0x7) |
853 FLEXCAN_CTRL_PROPSEG(0x7) |
854 FLEXCAN_CTRL_LPB |
855 FLEXCAN_CTRL_SMP |
856 FLEXCAN_CTRL_LOM);
857
858 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
859 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
860 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
861 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
862 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
863
864 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
865 reg |= FLEXCAN_CTRL_LPB;
866 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
867 reg |= FLEXCAN_CTRL_LOM;
868 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
869 reg |= FLEXCAN_CTRL_SMP;
870
871 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
872 flexcan_write(reg, &regs->ctrl);
873
874 /* print chip status */
875 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
876 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
877 }
878
879 /* flexcan_chip_start
880 *
881 * this functions is entered with clocks enabled
882 *
883 */
884 static int flexcan_chip_start(struct net_device *dev)
885 {
886 struct flexcan_priv *priv = netdev_priv(dev);
887 struct flexcan_regs __iomem *regs = priv->regs;
888 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
889 int err, i;
890
891 /* enable module */
892 err = flexcan_chip_enable(priv);
893 if (err)
894 return err;
895
896 /* soft reset */
897 err = flexcan_chip_softreset(priv);
898 if (err)
899 goto out_chip_disable;
900
901 flexcan_set_bittiming(dev);
902
903 /* MCR
904 *
905 * enable freeze
906 * enable fifo
907 * halt now
908 * only supervisor access
909 * enable warning int
910 * disable local echo
911 * enable individual RX masking
912 * choose format C
913 * set max mailbox number
914 */
915 reg_mcr = flexcan_read(&regs->mcr);
916 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
917 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
918 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
919 FLEXCAN_MCR_IDAM_C;
920
921 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
922 reg_mcr &= ~FLEXCAN_MCR_FEN;
923 reg_mcr |= FLEXCAN_MCR_MAXMB(priv->offload.mb_last);
924 } else {
925 reg_mcr |= FLEXCAN_MCR_FEN |
926 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
927 }
928 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
929 flexcan_write(reg_mcr, &regs->mcr);
930
931 /* CTRL
932 *
933 * disable timer sync feature
934 *
935 * disable auto busoff recovery
936 * transmit lowest buffer first
937 *
938 * enable tx and rx warning interrupt
939 * enable bus off interrupt
940 * (== FLEXCAN_CTRL_ERR_STATE)
941 */
942 reg_ctrl = flexcan_read(&regs->ctrl);
943 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
944 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
945 FLEXCAN_CTRL_ERR_STATE;
946
947 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
948 * on most Flexcan cores, too. Otherwise we don't get
949 * any error warning or passive interrupts.
950 */
951 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
952 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
953 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
954 else
955 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
956
957 /* save for later use */
958 priv->reg_ctrl_default = reg_ctrl;
959 /* leave interrupts disabled for now */
960 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
961 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
962 flexcan_write(reg_ctrl, &regs->ctrl);
963
964 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
965 reg_ctrl2 = flexcan_read(&regs->ctrl2);
966 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
967 flexcan_write(reg_ctrl2, &regs->ctrl2);
968 }
969
970 /* clear and invalidate all mailboxes first */
971 for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
972 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
973 &regs->mb[i].can_ctrl);
974 }
975
976 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
977 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
978 flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
979 &regs->mb[i].can_ctrl);
980 }
981
982 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
983 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
984 &priv->tx_mb_reserved->can_ctrl);
985
986 /* mark TX mailbox as INACTIVE */
987 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
988 &priv->tx_mb->can_ctrl);
989
990 /* acceptance mask/acceptance code (accept everything) */
991 flexcan_write(0x0, &regs->rxgmask);
992 flexcan_write(0x0, &regs->rx14mask);
993 flexcan_write(0x0, &regs->rx15mask);
994
995 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
996 flexcan_write(0x0, &regs->rxfgmask);
997
998 /* clear acceptance filters */
999 for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1000 flexcan_write(0, &regs->rximr[i]);
1001
1002 /* On Vybrid, disable memory error detection interrupts
1003 * and freeze mode.
1004 * This also works around errata e5295 which generates
1005 * false positive memory errors and put the device in
1006 * freeze mode.
1007 */
1008 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1009 /* Follow the protocol as described in "Detection
1010 * and Correction of Memory Errors" to write to
1011 * MECR register
1012 */
1013 reg_ctrl2 = flexcan_read(&regs->ctrl2);
1014 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1015 flexcan_write(reg_ctrl2, &regs->ctrl2);
1016
1017 reg_mecr = flexcan_read(&regs->mecr);
1018 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1019 flexcan_write(reg_mecr, &regs->mecr);
1020 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1021 FLEXCAN_MECR_FANCEI_MSK);
1022 flexcan_write(reg_mecr, &regs->mecr);
1023 }
1024
1025 err = flexcan_transceiver_enable(priv);
1026 if (err)
1027 goto out_chip_disable;
1028
1029 /* synchronize with the can bus */
1030 err = flexcan_chip_unfreeze(priv);
1031 if (err)
1032 goto out_transceiver_disable;
1033
1034 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1035
1036 /* enable interrupts atomically */
1037 disable_irq(dev->irq);
1038 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
1039 flexcan_write(priv->reg_imask1_default, &regs->imask1);
1040 flexcan_write(priv->reg_imask2_default, &regs->imask2);
1041 enable_irq(dev->irq);
1042
1043 /* print chip status */
1044 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1045 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
1046
1047 return 0;
1048
1049 out_transceiver_disable:
1050 flexcan_transceiver_disable(priv);
1051 out_chip_disable:
1052 flexcan_chip_disable(priv);
1053 return err;
1054 }
1055
1056 /* flexcan_chip_stop
1057 *
1058 * this functions is entered with clocks enabled
1059 */
1060 static void flexcan_chip_stop(struct net_device *dev)
1061 {
1062 struct flexcan_priv *priv = netdev_priv(dev);
1063 struct flexcan_regs __iomem *regs = priv->regs;
1064
1065 /* freeze + disable module */
1066 flexcan_chip_freeze(priv);
1067 flexcan_chip_disable(priv);
1068
1069 /* Disable all interrupts */
1070 flexcan_write(0, &regs->imask2);
1071 flexcan_write(0, &regs->imask1);
1072 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1073 &regs->ctrl);
1074
1075 flexcan_transceiver_disable(priv);
1076 priv->can.state = CAN_STATE_STOPPED;
1077 }
1078
1079 static int flexcan_open(struct net_device *dev)
1080 {
1081 struct flexcan_priv *priv = netdev_priv(dev);
1082 int err;
1083
1084 err = clk_prepare_enable(priv->clk_ipg);
1085 if (err)
1086 return err;
1087
1088 err = clk_prepare_enable(priv->clk_per);
1089 if (err)
1090 goto out_disable_ipg;
1091
1092 err = open_candev(dev);
1093 if (err)
1094 goto out_disable_per;
1095
1096 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1097 if (err)
1098 goto out_close;
1099
1100 /* start chip and queuing */
1101 err = flexcan_chip_start(dev);
1102 if (err)
1103 goto out_free_irq;
1104
1105 can_led_event(dev, CAN_LED_EVENT_OPEN);
1106
1107 can_rx_offload_enable(&priv->offload);
1108 netif_start_queue(dev);
1109
1110 return 0;
1111
1112 out_free_irq:
1113 free_irq(dev->irq, dev);
1114 out_close:
1115 close_candev(dev);
1116 out_disable_per:
1117 clk_disable_unprepare(priv->clk_per);
1118 out_disable_ipg:
1119 clk_disable_unprepare(priv->clk_ipg);
1120
1121 return err;
1122 }
1123
1124 static int flexcan_close(struct net_device *dev)
1125 {
1126 struct flexcan_priv *priv = netdev_priv(dev);
1127
1128 netif_stop_queue(dev);
1129 can_rx_offload_disable(&priv->offload);
1130 flexcan_chip_stop(dev);
1131
1132 free_irq(dev->irq, dev);
1133 clk_disable_unprepare(priv->clk_per);
1134 clk_disable_unprepare(priv->clk_ipg);
1135
1136 close_candev(dev);
1137
1138 can_led_event(dev, CAN_LED_EVENT_STOP);
1139
1140 return 0;
1141 }
1142
1143 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1144 {
1145 int err;
1146
1147 switch (mode) {
1148 case CAN_MODE_START:
1149 err = flexcan_chip_start(dev);
1150 if (err)
1151 return err;
1152
1153 netif_wake_queue(dev);
1154 break;
1155
1156 default:
1157 return -EOPNOTSUPP;
1158 }
1159
1160 return 0;
1161 }
1162
1163 static const struct net_device_ops flexcan_netdev_ops = {
1164 .ndo_open = flexcan_open,
1165 .ndo_stop = flexcan_close,
1166 .ndo_start_xmit = flexcan_start_xmit,
1167 .ndo_change_mtu = can_change_mtu,
1168 };
1169
1170 static int register_flexcandev(struct net_device *dev)
1171 {
1172 struct flexcan_priv *priv = netdev_priv(dev);
1173 struct flexcan_regs __iomem *regs = priv->regs;
1174 u32 reg, err;
1175
1176 err = clk_prepare_enable(priv->clk_ipg);
1177 if (err)
1178 return err;
1179
1180 err = clk_prepare_enable(priv->clk_per);
1181 if (err)
1182 goto out_disable_ipg;
1183
1184 /* select "bus clock", chip must be disabled */
1185 err = flexcan_chip_disable(priv);
1186 if (err)
1187 goto out_disable_per;
1188 reg = flexcan_read(&regs->ctrl);
1189 reg |= FLEXCAN_CTRL_CLK_SRC;
1190 flexcan_write(reg, &regs->ctrl);
1191
1192 err = flexcan_chip_enable(priv);
1193 if (err)
1194 goto out_chip_disable;
1195
1196 /* set freeze, halt and activate FIFO, restrict register access */
1197 reg = flexcan_read(&regs->mcr);
1198 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1199 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1200 flexcan_write(reg, &regs->mcr);
1201
1202 /* Currently we only support newer versions of this core
1203 * featuring a RX hardware FIFO (although this driver doesn't
1204 * make use of it on some cores). Older cores, found on some
1205 * Coldfire derivates are not tested.
1206 */
1207 reg = flexcan_read(&regs->mcr);
1208 if (!(reg & FLEXCAN_MCR_FEN)) {
1209 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1210 err = -ENODEV;
1211 goto out_chip_disable;
1212 }
1213
1214 err = register_candev(dev);
1215
1216 /* disable core and turn off clocks */
1217 out_chip_disable:
1218 flexcan_chip_disable(priv);
1219 out_disable_per:
1220 clk_disable_unprepare(priv->clk_per);
1221 out_disable_ipg:
1222 clk_disable_unprepare(priv->clk_ipg);
1223
1224 return err;
1225 }
1226
1227 static void unregister_flexcandev(struct net_device *dev)
1228 {
1229 unregister_candev(dev);
1230 }
1231
1232 static const struct of_device_id flexcan_of_match[] = {
1233 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1234 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1235 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1236 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1237 { /* sentinel */ },
1238 };
1239 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1240
1241 static const struct platform_device_id flexcan_id_table[] = {
1242 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1243 { /* sentinel */ },
1244 };
1245 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1246
1247 static int flexcan_probe(struct platform_device *pdev)
1248 {
1249 const struct of_device_id *of_id;
1250 const struct flexcan_devtype_data *devtype_data;
1251 struct net_device *dev;
1252 struct flexcan_priv *priv;
1253 struct regulator *reg_xceiver;
1254 struct resource *mem;
1255 struct clk *clk_ipg = NULL, *clk_per = NULL;
1256 struct flexcan_regs __iomem *regs;
1257 int err, irq;
1258 u32 clock_freq = 0;
1259
1260 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1261 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1262 return -EPROBE_DEFER;
1263 else if (IS_ERR(reg_xceiver))
1264 reg_xceiver = NULL;
1265
1266 if (pdev->dev.of_node)
1267 of_property_read_u32(pdev->dev.of_node,
1268 "clock-frequency", &clock_freq);
1269
1270 if (!clock_freq) {
1271 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1272 if (IS_ERR(clk_ipg)) {
1273 dev_err(&pdev->dev, "no ipg clock defined\n");
1274 return PTR_ERR(clk_ipg);
1275 }
1276
1277 clk_per = devm_clk_get(&pdev->dev, "per");
1278 if (IS_ERR(clk_per)) {
1279 dev_err(&pdev->dev, "no per clock defined\n");
1280 return PTR_ERR(clk_per);
1281 }
1282 clock_freq = clk_get_rate(clk_per);
1283 }
1284
1285 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1286 irq = platform_get_irq(pdev, 0);
1287 if (irq <= 0)
1288 return -ENODEV;
1289
1290 regs = devm_ioremap_resource(&pdev->dev, mem);
1291 if (IS_ERR(regs))
1292 return PTR_ERR(regs);
1293
1294 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1295 if (of_id) {
1296 devtype_data = of_id->data;
1297 } else if (platform_get_device_id(pdev)->driver_data) {
1298 devtype_data = (struct flexcan_devtype_data *)
1299 platform_get_device_id(pdev)->driver_data;
1300 } else {
1301 return -ENODEV;
1302 }
1303
1304 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1305 if (!dev)
1306 return -ENOMEM;
1307
1308 platform_set_drvdata(pdev, dev);
1309 SET_NETDEV_DEV(dev, &pdev->dev);
1310
1311 dev->netdev_ops = &flexcan_netdev_ops;
1312 dev->irq = irq;
1313 dev->flags |= IFF_ECHO;
1314
1315 priv = netdev_priv(dev);
1316 priv->can.clock.freq = clock_freq;
1317 priv->can.bittiming_const = &flexcan_bittiming_const;
1318 priv->can.do_set_mode = flexcan_set_mode;
1319 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1320 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1321 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1322 CAN_CTRLMODE_BERR_REPORTING;
1323 priv->regs = regs;
1324 priv->clk_ipg = clk_ipg;
1325 priv->clk_per = clk_per;
1326 priv->devtype_data = devtype_data;
1327 priv->reg_xceiver = reg_xceiver;
1328
1329 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1330 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_TIMESTAMP;
1331 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1332 } else {
1333 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
1334 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1335 }
1336 priv->tx_mb = &regs->mb[priv->tx_mb_idx];
1337
1338 priv->reg_imask1_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1339 priv->reg_imask2_default = 0;
1340
1341 priv->offload.mailbox_read = flexcan_mailbox_read;
1342
1343 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1344 u64 imask;
1345
1346 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1347 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1348
1349 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1350 priv->reg_imask1_default |= imask;
1351 priv->reg_imask2_default |= imask >> 32;
1352
1353 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1354 } else {
1355 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1356 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1357 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1358 }
1359 if (err)
1360 goto failed_offload;
1361
1362 err = register_flexcandev(dev);
1363 if (err) {
1364 dev_err(&pdev->dev, "registering netdev failed\n");
1365 goto failed_register;
1366 }
1367
1368 devm_can_led_init(dev);
1369
1370 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1371 priv->regs, dev->irq);
1372
1373 return 0;
1374
1375 failed_offload:
1376 failed_register:
1377 free_candev(dev);
1378 return err;
1379 }
1380
1381 static int flexcan_remove(struct platform_device *pdev)
1382 {
1383 struct net_device *dev = platform_get_drvdata(pdev);
1384 struct flexcan_priv *priv = netdev_priv(dev);
1385
1386 unregister_flexcandev(dev);
1387 can_rx_offload_del(&priv->offload);
1388 free_candev(dev);
1389
1390 return 0;
1391 }
1392
1393 static int __maybe_unused flexcan_suspend(struct device *device)
1394 {
1395 struct net_device *dev = dev_get_drvdata(device);
1396 struct flexcan_priv *priv = netdev_priv(dev);
1397 int err;
1398
1399 if (netif_running(dev)) {
1400 err = flexcan_chip_disable(priv);
1401 if (err)
1402 return err;
1403 netif_stop_queue(dev);
1404 netif_device_detach(dev);
1405 }
1406 priv->can.state = CAN_STATE_SLEEPING;
1407
1408 return 0;
1409 }
1410
1411 static int __maybe_unused flexcan_resume(struct device *device)
1412 {
1413 struct net_device *dev = dev_get_drvdata(device);
1414 struct flexcan_priv *priv = netdev_priv(dev);
1415 int err;
1416
1417 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1418 if (netif_running(dev)) {
1419 netif_device_attach(dev);
1420 netif_start_queue(dev);
1421 err = flexcan_chip_enable(priv);
1422 if (err)
1423 return err;
1424 }
1425 return 0;
1426 }
1427
1428 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1429
1430 static struct platform_driver flexcan_driver = {
1431 .driver = {
1432 .name = DRV_NAME,
1433 .pm = &flexcan_pm_ops,
1434 .of_match_table = flexcan_of_match,
1435 },
1436 .probe = flexcan_probe,
1437 .remove = flexcan_remove,
1438 .id_table = flexcan_id_table,
1439 };
1440
1441 module_platform_driver(flexcan_driver);
1442
1443 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1444 "Marc Kleine-Budde <kernel@pengutronix.de>");
1445 MODULE_LICENSE("GPL v2");
1446 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
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