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efi/arm: Fix boot crash with CONFIG_CPUMASK_OFFSTACK=y
[mirror_ubuntu-artful-kernel.git] / drivers / net / can / flexcan.c
1 /*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
7 * Copyright (c) 2014 David Jander, Protonic Holland
8 *
9 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
10 *
11 * LICENCE:
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 #include <linux/netdevice.h>
24 #include <linux/can.h>
25 #include <linux/can/dev.h>
26 #include <linux/can/error.h>
27 #include <linux/can/led.h>
28 #include <linux/can/rx-offload.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/module.h>
34 #include <linux/of.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/regulator/consumer.h>
38
39 #define DRV_NAME "flexcan"
40
41 /* 8 for RX fifo and 2 error handling */
42 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
43
44 /* FLEXCAN module configuration register (CANMCR) bits */
45 #define FLEXCAN_MCR_MDIS BIT(31)
46 #define FLEXCAN_MCR_FRZ BIT(30)
47 #define FLEXCAN_MCR_FEN BIT(29)
48 #define FLEXCAN_MCR_HALT BIT(28)
49 #define FLEXCAN_MCR_NOT_RDY BIT(27)
50 #define FLEXCAN_MCR_WAK_MSK BIT(26)
51 #define FLEXCAN_MCR_SOFTRST BIT(25)
52 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
53 #define FLEXCAN_MCR_SUPV BIT(23)
54 #define FLEXCAN_MCR_SLF_WAK BIT(22)
55 #define FLEXCAN_MCR_WRN_EN BIT(21)
56 #define FLEXCAN_MCR_LPM_ACK BIT(20)
57 #define FLEXCAN_MCR_WAK_SRC BIT(19)
58 #define FLEXCAN_MCR_DOZE BIT(18)
59 #define FLEXCAN_MCR_SRX_DIS BIT(17)
60 #define FLEXCAN_MCR_IRMQ BIT(16)
61 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
62 #define FLEXCAN_MCR_AEN BIT(12)
63 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
64 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
65 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
66 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
67 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
68 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
69
70 /* FLEXCAN control register (CANCTRL) bits */
71 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
72 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
73 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
74 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
75 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
76 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
77 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
78 #define FLEXCAN_CTRL_LPB BIT(12)
79 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
80 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
81 #define FLEXCAN_CTRL_SMP BIT(7)
82 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
83 #define FLEXCAN_CTRL_TSYN BIT(5)
84 #define FLEXCAN_CTRL_LBUF BIT(4)
85 #define FLEXCAN_CTRL_LOM BIT(3)
86 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
87 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
88 #define FLEXCAN_CTRL_ERR_STATE \
89 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
90 FLEXCAN_CTRL_BOFF_MSK)
91 #define FLEXCAN_CTRL_ERR_ALL \
92 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
93
94 /* FLEXCAN control register 2 (CTRL2) bits */
95 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
96 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
97 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
98 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
99 #define FLEXCAN_CTRL2_MRP BIT(18)
100 #define FLEXCAN_CTRL2_RRS BIT(17)
101 #define FLEXCAN_CTRL2_EACEN BIT(16)
102
103 /* FLEXCAN memory error control register (MECR) bits */
104 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
105 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
106 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
107 #define FLEXCAN_MECR_CEI_MSK BIT(16)
108 #define FLEXCAN_MECR_HAERRIE BIT(15)
109 #define FLEXCAN_MECR_FAERRIE BIT(14)
110 #define FLEXCAN_MECR_EXTERRIE BIT(13)
111 #define FLEXCAN_MECR_RERRDIS BIT(9)
112 #define FLEXCAN_MECR_ECCDIS BIT(8)
113 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
114
115 /* FLEXCAN error and status register (ESR) bits */
116 #define FLEXCAN_ESR_TWRN_INT BIT(17)
117 #define FLEXCAN_ESR_RWRN_INT BIT(16)
118 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
119 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
120 #define FLEXCAN_ESR_ACK_ERR BIT(13)
121 #define FLEXCAN_ESR_CRC_ERR BIT(12)
122 #define FLEXCAN_ESR_FRM_ERR BIT(11)
123 #define FLEXCAN_ESR_STF_ERR BIT(10)
124 #define FLEXCAN_ESR_TX_WRN BIT(9)
125 #define FLEXCAN_ESR_RX_WRN BIT(8)
126 #define FLEXCAN_ESR_IDLE BIT(7)
127 #define FLEXCAN_ESR_TXRX BIT(6)
128 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
129 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_BOFF_INT BIT(2)
133 #define FLEXCAN_ESR_ERR_INT BIT(1)
134 #define FLEXCAN_ESR_WAK_INT BIT(0)
135 #define FLEXCAN_ESR_ERR_BUS \
136 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139 #define FLEXCAN_ESR_ERR_STATE \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141 #define FLEXCAN_ESR_ERR_ALL \
142 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143 #define FLEXCAN_ESR_ALL_INT \
144 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
146
147 /* FLEXCAN interrupt flag register (IFLAG) bits */
148 /* Errata ERR005829 step7: Reserve first valid MB */
149 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
150 #define FLEXCAN_TX_MB_OFF_FIFO 9
151 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
152 #define FLEXCAN_TX_MB_OFF_TIMESTAMP 1
153 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_OFF_TIMESTAMP + 1)
154 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST 63
155 #define FLEXCAN_IFLAG_MB(x) BIT(x)
156 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
157 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
158 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
159
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
162 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
163 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
164 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
165 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
166 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
167 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
168
169 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
170 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
171 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
172 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
173
174 #define FLEXCAN_MB_CNT_SRR BIT(22)
175 #define FLEXCAN_MB_CNT_IDE BIT(21)
176 #define FLEXCAN_MB_CNT_RTR BIT(20)
177 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
178 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
179
180 #define FLEXCAN_TIMEOUT_US (50)
181
182 /* FLEXCAN hardware feature flags
183 *
184 * Below is some version info we got:
185 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
186 * Filter? connected? detection ception in MB
187 * MX25 FlexCAN2 03.00.00.00 no no no no
188 * MX28 FlexCAN2 03.00.04.00 yes yes no no
189 * MX35 FlexCAN2 03.00.00.00 no no no no
190 * MX53 FlexCAN2 03.00.00.00 yes no no no
191 * MX6s FlexCAN3 10.00.12.00 yes yes no yes
192 * VF610 FlexCAN3 ? no yes yes yes?
193 *
194 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
195 */
196 #define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
197 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
198 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
199 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disble Memory error detection */
200 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
201
202 /* Structure of the message buffer */
203 struct flexcan_mb {
204 u32 can_ctrl;
205 u32 can_id;
206 u32 data[2];
207 };
208
209 /* Structure of the hardware registers */
210 struct flexcan_regs {
211 u32 mcr; /* 0x00 */
212 u32 ctrl; /* 0x04 */
213 u32 timer; /* 0x08 */
214 u32 _reserved1; /* 0x0c */
215 u32 rxgmask; /* 0x10 */
216 u32 rx14mask; /* 0x14 */
217 u32 rx15mask; /* 0x18 */
218 u32 ecr; /* 0x1c */
219 u32 esr; /* 0x20 */
220 u32 imask2; /* 0x24 */
221 u32 imask1; /* 0x28 */
222 u32 iflag2; /* 0x2c */
223 u32 iflag1; /* 0x30 */
224 union { /* 0x34 */
225 u32 gfwr_mx28; /* MX28, MX53 */
226 u32 ctrl2; /* MX6, VF610 */
227 };
228 u32 esr2; /* 0x38 */
229 u32 imeur; /* 0x3c */
230 u32 lrfr; /* 0x40 */
231 u32 crcr; /* 0x44 */
232 u32 rxfgmask; /* 0x48 */
233 u32 rxfir; /* 0x4c */
234 u32 _reserved3[12]; /* 0x50 */
235 struct flexcan_mb mb[64]; /* 0x80 */
236 /* FIFO-mode:
237 * MB
238 * 0x080...0x08f 0 RX message buffer
239 * 0x090...0x0df 1-5 reserverd
240 * 0x0e0...0x0ff 6-7 8 entry ID table
241 * (mx25, mx28, mx35, mx53)
242 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
243 * size conf'ed via ctrl2::RFFN
244 * (mx6, vf610)
245 */
246 u32 _reserved4[256]; /* 0x480 */
247 u32 rximr[64]; /* 0x880 */
248 u32 _reserved5[24]; /* 0x980 */
249 u32 gfwr_mx6; /* 0x9e0 - MX6 */
250 u32 _reserved6[63]; /* 0x9e4 */
251 u32 mecr; /* 0xae0 */
252 u32 erriar; /* 0xae4 */
253 u32 erridpr; /* 0xae8 */
254 u32 errippr; /* 0xaec */
255 u32 rerrar; /* 0xaf0 */
256 u32 rerrdr; /* 0xaf4 */
257 u32 rerrsynr; /* 0xaf8 */
258 u32 errsr; /* 0xafc */
259 };
260
261 struct flexcan_devtype_data {
262 u32 quirks; /* quirks needed for different IP cores */
263 };
264
265 struct flexcan_priv {
266 struct can_priv can;
267 struct can_rx_offload offload;
268
269 struct flexcan_regs __iomem *regs;
270 struct flexcan_mb __iomem *tx_mb;
271 struct flexcan_mb __iomem *tx_mb_reserved;
272 u8 tx_mb_idx;
273 u32 reg_ctrl_default;
274 u32 reg_imask1_default;
275 u32 reg_imask2_default;
276
277 struct clk *clk_ipg;
278 struct clk *clk_per;
279 const struct flexcan_devtype_data *devtype_data;
280 struct regulator *reg_xceiver;
281 };
282
283 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
284 .quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
285 };
286
287 static const struct flexcan_devtype_data fsl_imx28_devtype_data;
288
289 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
290 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
291 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
292 };
293
294 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
295 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
296 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
297 };
298
299 static const struct can_bittiming_const flexcan_bittiming_const = {
300 .name = DRV_NAME,
301 .tseg1_min = 4,
302 .tseg1_max = 16,
303 .tseg2_min = 2,
304 .tseg2_max = 8,
305 .sjw_max = 4,
306 .brp_min = 1,
307 .brp_max = 256,
308 .brp_inc = 1,
309 };
310
311 /* Abstract off the read/write for arm versus ppc. This
312 * assumes that PPC uses big-endian registers and everything
313 * else uses little-endian registers, independent of CPU
314 * endianness.
315 */
316 #if defined(CONFIG_PPC)
317 static inline u32 flexcan_read(void __iomem *addr)
318 {
319 return in_be32(addr);
320 }
321
322 static inline void flexcan_write(u32 val, void __iomem *addr)
323 {
324 out_be32(addr, val);
325 }
326 #else
327 static inline u32 flexcan_read(void __iomem *addr)
328 {
329 return readl(addr);
330 }
331
332 static inline void flexcan_write(u32 val, void __iomem *addr)
333 {
334 writel(val, addr);
335 }
336 #endif
337
338 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
339 {
340 if (!priv->reg_xceiver)
341 return 0;
342
343 return regulator_enable(priv->reg_xceiver);
344 }
345
346 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
347 {
348 if (!priv->reg_xceiver)
349 return 0;
350
351 return regulator_disable(priv->reg_xceiver);
352 }
353
354 static int flexcan_chip_enable(struct flexcan_priv *priv)
355 {
356 struct flexcan_regs __iomem *regs = priv->regs;
357 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
358 u32 reg;
359
360 reg = flexcan_read(&regs->mcr);
361 reg &= ~FLEXCAN_MCR_MDIS;
362 flexcan_write(reg, &regs->mcr);
363
364 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
365 udelay(10);
366
367 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
368 return -ETIMEDOUT;
369
370 return 0;
371 }
372
373 static int flexcan_chip_disable(struct flexcan_priv *priv)
374 {
375 struct flexcan_regs __iomem *regs = priv->regs;
376 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
377 u32 reg;
378
379 reg = flexcan_read(&regs->mcr);
380 reg |= FLEXCAN_MCR_MDIS;
381 flexcan_write(reg, &regs->mcr);
382
383 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
384 udelay(10);
385
386 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
387 return -ETIMEDOUT;
388
389 return 0;
390 }
391
392 static int flexcan_chip_freeze(struct flexcan_priv *priv)
393 {
394 struct flexcan_regs __iomem *regs = priv->regs;
395 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
396 u32 reg;
397
398 reg = flexcan_read(&regs->mcr);
399 reg |= FLEXCAN_MCR_HALT;
400 flexcan_write(reg, &regs->mcr);
401
402 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
403 udelay(100);
404
405 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
406 return -ETIMEDOUT;
407
408 return 0;
409 }
410
411 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
412 {
413 struct flexcan_regs __iomem *regs = priv->regs;
414 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
415 u32 reg;
416
417 reg = flexcan_read(&regs->mcr);
418 reg &= ~FLEXCAN_MCR_HALT;
419 flexcan_write(reg, &regs->mcr);
420
421 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
422 udelay(10);
423
424 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
425 return -ETIMEDOUT;
426
427 return 0;
428 }
429
430 static int flexcan_chip_softreset(struct flexcan_priv *priv)
431 {
432 struct flexcan_regs __iomem *regs = priv->regs;
433 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
434
435 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
436 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
437 udelay(10);
438
439 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
440 return -ETIMEDOUT;
441
442 return 0;
443 }
444
445 static int __flexcan_get_berr_counter(const struct net_device *dev,
446 struct can_berr_counter *bec)
447 {
448 const struct flexcan_priv *priv = netdev_priv(dev);
449 struct flexcan_regs __iomem *regs = priv->regs;
450 u32 reg = flexcan_read(&regs->ecr);
451
452 bec->txerr = (reg >> 0) & 0xff;
453 bec->rxerr = (reg >> 8) & 0xff;
454
455 return 0;
456 }
457
458 static int flexcan_get_berr_counter(const struct net_device *dev,
459 struct can_berr_counter *bec)
460 {
461 const struct flexcan_priv *priv = netdev_priv(dev);
462 int err;
463
464 err = clk_prepare_enable(priv->clk_ipg);
465 if (err)
466 return err;
467
468 err = clk_prepare_enable(priv->clk_per);
469 if (err)
470 goto out_disable_ipg;
471
472 err = __flexcan_get_berr_counter(dev, bec);
473
474 clk_disable_unprepare(priv->clk_per);
475 out_disable_ipg:
476 clk_disable_unprepare(priv->clk_ipg);
477
478 return err;
479 }
480
481 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
482 {
483 const struct flexcan_priv *priv = netdev_priv(dev);
484 struct can_frame *cf = (struct can_frame *)skb->data;
485 u32 can_id;
486 u32 data;
487 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
488
489 if (can_dropped_invalid_skb(dev, skb))
490 return NETDEV_TX_OK;
491
492 netif_stop_queue(dev);
493
494 if (cf->can_id & CAN_EFF_FLAG) {
495 can_id = cf->can_id & CAN_EFF_MASK;
496 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
497 } else {
498 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
499 }
500
501 if (cf->can_id & CAN_RTR_FLAG)
502 ctrl |= FLEXCAN_MB_CNT_RTR;
503
504 if (cf->can_dlc > 0) {
505 data = be32_to_cpup((__be32 *)&cf->data[0]);
506 flexcan_write(data, &priv->tx_mb->data[0]);
507 }
508 if (cf->can_dlc > 3) {
509 data = be32_to_cpup((__be32 *)&cf->data[4]);
510 flexcan_write(data, &priv->tx_mb->data[1]);
511 }
512
513 can_put_echo_skb(skb, dev, 0);
514
515 flexcan_write(can_id, &priv->tx_mb->can_id);
516 flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
517
518 /* Errata ERR005829 step8:
519 * Write twice INACTIVE(0x8) code to first MB.
520 */
521 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
522 &priv->tx_mb_reserved->can_ctrl);
523 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
524 &priv->tx_mb_reserved->can_ctrl);
525
526 return NETDEV_TX_OK;
527 }
528
529 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
530 {
531 struct flexcan_priv *priv = netdev_priv(dev);
532 struct sk_buff *skb;
533 struct can_frame *cf;
534 bool rx_errors = false, tx_errors = false;
535
536 skb = alloc_can_err_skb(dev, &cf);
537 if (unlikely(!skb))
538 return;
539
540 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
541
542 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
543 netdev_dbg(dev, "BIT1_ERR irq\n");
544 cf->data[2] |= CAN_ERR_PROT_BIT1;
545 tx_errors = true;
546 }
547 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
548 netdev_dbg(dev, "BIT0_ERR irq\n");
549 cf->data[2] |= CAN_ERR_PROT_BIT0;
550 tx_errors = true;
551 }
552 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
553 netdev_dbg(dev, "ACK_ERR irq\n");
554 cf->can_id |= CAN_ERR_ACK;
555 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
556 tx_errors = true;
557 }
558 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
559 netdev_dbg(dev, "CRC_ERR irq\n");
560 cf->data[2] |= CAN_ERR_PROT_BIT;
561 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
562 rx_errors = true;
563 }
564 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
565 netdev_dbg(dev, "FRM_ERR irq\n");
566 cf->data[2] |= CAN_ERR_PROT_FORM;
567 rx_errors = true;
568 }
569 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
570 netdev_dbg(dev, "STF_ERR irq\n");
571 cf->data[2] |= CAN_ERR_PROT_STUFF;
572 rx_errors = true;
573 }
574
575 priv->can.can_stats.bus_error++;
576 if (rx_errors)
577 dev->stats.rx_errors++;
578 if (tx_errors)
579 dev->stats.tx_errors++;
580
581 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
582 }
583
584 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
585 {
586 struct flexcan_priv *priv = netdev_priv(dev);
587 struct sk_buff *skb;
588 struct can_frame *cf;
589 enum can_state new_state, rx_state, tx_state;
590 int flt;
591 struct can_berr_counter bec;
592
593 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
594 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
595 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
596 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
597 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
598 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
599 new_state = max(tx_state, rx_state);
600 } else {
601 __flexcan_get_berr_counter(dev, &bec);
602 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
603 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
604 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
605 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
606 }
607
608 /* state hasn't changed */
609 if (likely(new_state == priv->can.state))
610 return;
611
612 skb = alloc_can_err_skb(dev, &cf);
613 if (unlikely(!skb))
614 return;
615
616 can_change_state(dev, cf, tx_state, rx_state);
617
618 if (unlikely(new_state == CAN_STATE_BUS_OFF))
619 can_bus_off(dev);
620
621 can_rx_offload_irq_queue_err_skb(&priv->offload, skb);
622 }
623
624 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
625 {
626 return container_of(offload, struct flexcan_priv, offload);
627 }
628
629 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
630 struct can_frame *cf,
631 u32 *timestamp, unsigned int n)
632 {
633 struct flexcan_priv *priv = rx_offload_to_priv(offload);
634 struct flexcan_regs __iomem *regs = priv->regs;
635 struct flexcan_mb __iomem *mb = &regs->mb[n];
636 u32 reg_ctrl, reg_id, reg_iflag1;
637
638 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
639 u32 code;
640
641 do {
642 reg_ctrl = flexcan_read(&mb->can_ctrl);
643 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
644
645 /* is this MB empty? */
646 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
647 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
648 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
649 return 0;
650
651 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
652 /* This MB was overrun, we lost data */
653 offload->dev->stats.rx_over_errors++;
654 offload->dev->stats.rx_errors++;
655 }
656 } else {
657 reg_iflag1 = flexcan_read(&regs->iflag1);
658 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
659 return 0;
660
661 reg_ctrl = flexcan_read(&mb->can_ctrl);
662 }
663
664 /* increase timstamp to full 32 bit */
665 *timestamp = reg_ctrl << 16;
666
667 reg_id = flexcan_read(&mb->can_id);
668 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
669 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
670 else
671 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
672
673 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
674 cf->can_id |= CAN_RTR_FLAG;
675 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
676
677 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
678 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
679
680 /* mark as read */
681 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
682 /* Clear IRQ */
683 if (n < 32)
684 flexcan_write(BIT(n), &regs->iflag1);
685 else
686 flexcan_write(BIT(n - 32), &regs->iflag2);
687 } else {
688 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
689 flexcan_read(&regs->timer);
690 }
691
692 return 1;
693 }
694
695
696 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
697 {
698 struct flexcan_regs __iomem *regs = priv->regs;
699 u32 iflag1, iflag2;
700
701 iflag2 = flexcan_read(&regs->iflag2) & priv->reg_imask2_default;
702 iflag1 = flexcan_read(&regs->iflag1) & priv->reg_imask1_default &
703 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
704
705 return (u64)iflag2 << 32 | iflag1;
706 }
707
708 static irqreturn_t flexcan_irq(int irq, void *dev_id)
709 {
710 struct net_device *dev = dev_id;
711 struct net_device_stats *stats = &dev->stats;
712 struct flexcan_priv *priv = netdev_priv(dev);
713 struct flexcan_regs __iomem *regs = priv->regs;
714 irqreturn_t handled = IRQ_NONE;
715 u32 reg_iflag1, reg_esr;
716
717 reg_iflag1 = flexcan_read(&regs->iflag1);
718
719 /* reception interrupt */
720 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
721 u64 reg_iflag;
722 int ret;
723
724 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
725 handled = IRQ_HANDLED;
726 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
727 reg_iflag);
728 if (!ret)
729 break;
730 }
731 } else {
732 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
733 handled = IRQ_HANDLED;
734 can_rx_offload_irq_offload_fifo(&priv->offload);
735 }
736
737 /* FIFO overflow interrupt */
738 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
739 handled = IRQ_HANDLED;
740 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
741 dev->stats.rx_over_errors++;
742 dev->stats.rx_errors++;
743 }
744 }
745
746 /* transmission complete interrupt */
747 if (reg_iflag1 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
748 handled = IRQ_HANDLED;
749 stats->tx_bytes += can_get_echo_skb(dev, 0);
750 stats->tx_packets++;
751 can_led_event(dev, CAN_LED_EVENT_TX);
752
753 /* after sending a RTR frame MB is in RX mode */
754 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
755 &priv->tx_mb->can_ctrl);
756 flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
757 netif_wake_queue(dev);
758 }
759
760 reg_esr = flexcan_read(&regs->esr);
761
762 /* ACK all bus error and state change IRQ sources */
763 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
764 handled = IRQ_HANDLED;
765 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
766 }
767
768 /* state change interrupt */
769 if (reg_esr & FLEXCAN_ESR_ERR_STATE)
770 flexcan_irq_state(dev, reg_esr);
771
772 /* bus error IRQ - handle if bus error reporting is activated */
773 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
774 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
775 flexcan_irq_bus_err(dev, reg_esr);
776
777 return handled;
778 }
779
780 static void flexcan_set_bittiming(struct net_device *dev)
781 {
782 const struct flexcan_priv *priv = netdev_priv(dev);
783 const struct can_bittiming *bt = &priv->can.bittiming;
784 struct flexcan_regs __iomem *regs = priv->regs;
785 u32 reg;
786
787 reg = flexcan_read(&regs->ctrl);
788 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
789 FLEXCAN_CTRL_RJW(0x3) |
790 FLEXCAN_CTRL_PSEG1(0x7) |
791 FLEXCAN_CTRL_PSEG2(0x7) |
792 FLEXCAN_CTRL_PROPSEG(0x7) |
793 FLEXCAN_CTRL_LPB |
794 FLEXCAN_CTRL_SMP |
795 FLEXCAN_CTRL_LOM);
796
797 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
798 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
799 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
800 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
801 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
802
803 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
804 reg |= FLEXCAN_CTRL_LPB;
805 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
806 reg |= FLEXCAN_CTRL_LOM;
807 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
808 reg |= FLEXCAN_CTRL_SMP;
809
810 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
811 flexcan_write(reg, &regs->ctrl);
812
813 /* print chip status */
814 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
815 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
816 }
817
818 /* flexcan_chip_start
819 *
820 * this functions is entered with clocks enabled
821 *
822 */
823 static int flexcan_chip_start(struct net_device *dev)
824 {
825 struct flexcan_priv *priv = netdev_priv(dev);
826 struct flexcan_regs __iomem *regs = priv->regs;
827 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
828 int err, i;
829
830 /* enable module */
831 err = flexcan_chip_enable(priv);
832 if (err)
833 return err;
834
835 /* soft reset */
836 err = flexcan_chip_softreset(priv);
837 if (err)
838 goto out_chip_disable;
839
840 flexcan_set_bittiming(dev);
841
842 /* MCR
843 *
844 * enable freeze
845 * enable fifo
846 * halt now
847 * only supervisor access
848 * enable warning int
849 * disable local echo
850 * enable individual RX masking
851 * choose format C
852 * set max mailbox number
853 */
854 reg_mcr = flexcan_read(&regs->mcr);
855 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
856 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
857 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
858 FLEXCAN_MCR_IDAM_C;
859
860 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
861 reg_mcr &= ~FLEXCAN_MCR_FEN;
862 reg_mcr |= FLEXCAN_MCR_MAXMB(priv->offload.mb_last);
863 } else {
864 reg_mcr |= FLEXCAN_MCR_FEN |
865 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
866 }
867 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
868 flexcan_write(reg_mcr, &regs->mcr);
869
870 /* CTRL
871 *
872 * disable timer sync feature
873 *
874 * disable auto busoff recovery
875 * transmit lowest buffer first
876 *
877 * enable tx and rx warning interrupt
878 * enable bus off interrupt
879 * (== FLEXCAN_CTRL_ERR_STATE)
880 */
881 reg_ctrl = flexcan_read(&regs->ctrl);
882 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
883 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
884 FLEXCAN_CTRL_ERR_STATE;
885
886 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
887 * on most Flexcan cores, too. Otherwise we don't get
888 * any error warning or passive interrupts.
889 */
890 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
891 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
892 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
893 else
894 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
895
896 /* save for later use */
897 priv->reg_ctrl_default = reg_ctrl;
898 /* leave interrupts disabled for now */
899 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
900 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
901 flexcan_write(reg_ctrl, &regs->ctrl);
902
903 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
904 reg_ctrl2 = flexcan_read(&regs->ctrl2);
905 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
906 flexcan_write(reg_ctrl2, &regs->ctrl2);
907 }
908
909 /* clear and invalidate all mailboxes first */
910 for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
911 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
912 &regs->mb[i].can_ctrl);
913 }
914
915 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
916 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
917 flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
918 &regs->mb[i].can_ctrl);
919 }
920
921 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
922 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
923 &priv->tx_mb_reserved->can_ctrl);
924
925 /* mark TX mailbox as INACTIVE */
926 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
927 &priv->tx_mb->can_ctrl);
928
929 /* acceptance mask/acceptance code (accept everything) */
930 flexcan_write(0x0, &regs->rxgmask);
931 flexcan_write(0x0, &regs->rx14mask);
932 flexcan_write(0x0, &regs->rx15mask);
933
934 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
935 flexcan_write(0x0, &regs->rxfgmask);
936
937 /* clear acceptance filters */
938 for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
939 flexcan_write(0, &regs->rximr[i]);
940
941 /* On Vybrid, disable memory error detection interrupts
942 * and freeze mode.
943 * This also works around errata e5295 which generates
944 * false positive memory errors and put the device in
945 * freeze mode.
946 */
947 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
948 /* Follow the protocol as described in "Detection
949 * and Correction of Memory Errors" to write to
950 * MECR register
951 */
952 reg_ctrl2 = flexcan_read(&regs->ctrl2);
953 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
954 flexcan_write(reg_ctrl2, &regs->ctrl2);
955
956 reg_mecr = flexcan_read(&regs->mecr);
957 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
958 flexcan_write(reg_mecr, &regs->mecr);
959 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
960 FLEXCAN_MECR_FANCEI_MSK);
961 flexcan_write(reg_mecr, &regs->mecr);
962 }
963
964 err = flexcan_transceiver_enable(priv);
965 if (err)
966 goto out_chip_disable;
967
968 /* synchronize with the can bus */
969 err = flexcan_chip_unfreeze(priv);
970 if (err)
971 goto out_transceiver_disable;
972
973 priv->can.state = CAN_STATE_ERROR_ACTIVE;
974
975 /* enable interrupts atomically */
976 disable_irq(dev->irq);
977 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
978 flexcan_write(priv->reg_imask1_default, &regs->imask1);
979 flexcan_write(priv->reg_imask2_default, &regs->imask2);
980 enable_irq(dev->irq);
981
982 /* print chip status */
983 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
984 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
985
986 return 0;
987
988 out_transceiver_disable:
989 flexcan_transceiver_disable(priv);
990 out_chip_disable:
991 flexcan_chip_disable(priv);
992 return err;
993 }
994
995 /* flexcan_chip_stop
996 *
997 * this functions is entered with clocks enabled
998 */
999 static void flexcan_chip_stop(struct net_device *dev)
1000 {
1001 struct flexcan_priv *priv = netdev_priv(dev);
1002 struct flexcan_regs __iomem *regs = priv->regs;
1003
1004 /* freeze + disable module */
1005 flexcan_chip_freeze(priv);
1006 flexcan_chip_disable(priv);
1007
1008 /* Disable all interrupts */
1009 flexcan_write(0, &regs->imask2);
1010 flexcan_write(0, &regs->imask1);
1011 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1012 &regs->ctrl);
1013
1014 flexcan_transceiver_disable(priv);
1015 priv->can.state = CAN_STATE_STOPPED;
1016 }
1017
1018 static int flexcan_open(struct net_device *dev)
1019 {
1020 struct flexcan_priv *priv = netdev_priv(dev);
1021 int err;
1022
1023 err = clk_prepare_enable(priv->clk_ipg);
1024 if (err)
1025 return err;
1026
1027 err = clk_prepare_enable(priv->clk_per);
1028 if (err)
1029 goto out_disable_ipg;
1030
1031 err = open_candev(dev);
1032 if (err)
1033 goto out_disable_per;
1034
1035 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1036 if (err)
1037 goto out_close;
1038
1039 /* start chip and queuing */
1040 err = flexcan_chip_start(dev);
1041 if (err)
1042 goto out_free_irq;
1043
1044 can_led_event(dev, CAN_LED_EVENT_OPEN);
1045
1046 can_rx_offload_enable(&priv->offload);
1047 netif_start_queue(dev);
1048
1049 return 0;
1050
1051 out_free_irq:
1052 free_irq(dev->irq, dev);
1053 out_close:
1054 close_candev(dev);
1055 out_disable_per:
1056 clk_disable_unprepare(priv->clk_per);
1057 out_disable_ipg:
1058 clk_disable_unprepare(priv->clk_ipg);
1059
1060 return err;
1061 }
1062
1063 static int flexcan_close(struct net_device *dev)
1064 {
1065 struct flexcan_priv *priv = netdev_priv(dev);
1066
1067 netif_stop_queue(dev);
1068 can_rx_offload_disable(&priv->offload);
1069 flexcan_chip_stop(dev);
1070
1071 free_irq(dev->irq, dev);
1072 clk_disable_unprepare(priv->clk_per);
1073 clk_disable_unprepare(priv->clk_ipg);
1074
1075 close_candev(dev);
1076
1077 can_led_event(dev, CAN_LED_EVENT_STOP);
1078
1079 return 0;
1080 }
1081
1082 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1083 {
1084 int err;
1085
1086 switch (mode) {
1087 case CAN_MODE_START:
1088 err = flexcan_chip_start(dev);
1089 if (err)
1090 return err;
1091
1092 netif_wake_queue(dev);
1093 break;
1094
1095 default:
1096 return -EOPNOTSUPP;
1097 }
1098
1099 return 0;
1100 }
1101
1102 static const struct net_device_ops flexcan_netdev_ops = {
1103 .ndo_open = flexcan_open,
1104 .ndo_stop = flexcan_close,
1105 .ndo_start_xmit = flexcan_start_xmit,
1106 .ndo_change_mtu = can_change_mtu,
1107 };
1108
1109 static int register_flexcandev(struct net_device *dev)
1110 {
1111 struct flexcan_priv *priv = netdev_priv(dev);
1112 struct flexcan_regs __iomem *regs = priv->regs;
1113 u32 reg, err;
1114
1115 err = clk_prepare_enable(priv->clk_ipg);
1116 if (err)
1117 return err;
1118
1119 err = clk_prepare_enable(priv->clk_per);
1120 if (err)
1121 goto out_disable_ipg;
1122
1123 /* select "bus clock", chip must be disabled */
1124 err = flexcan_chip_disable(priv);
1125 if (err)
1126 goto out_disable_per;
1127 reg = flexcan_read(&regs->ctrl);
1128 reg |= FLEXCAN_CTRL_CLK_SRC;
1129 flexcan_write(reg, &regs->ctrl);
1130
1131 err = flexcan_chip_enable(priv);
1132 if (err)
1133 goto out_chip_disable;
1134
1135 /* set freeze, halt and activate FIFO, restrict register access */
1136 reg = flexcan_read(&regs->mcr);
1137 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1138 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1139 flexcan_write(reg, &regs->mcr);
1140
1141 /* Currently we only support newer versions of this core
1142 * featuring a RX hardware FIFO (although this driver doesn't
1143 * make use of it on some cores). Older cores, found on some
1144 * Coldfire derivates are not tested.
1145 */
1146 reg = flexcan_read(&regs->mcr);
1147 if (!(reg & FLEXCAN_MCR_FEN)) {
1148 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1149 err = -ENODEV;
1150 goto out_chip_disable;
1151 }
1152
1153 err = register_candev(dev);
1154
1155 /* disable core and turn off clocks */
1156 out_chip_disable:
1157 flexcan_chip_disable(priv);
1158 out_disable_per:
1159 clk_disable_unprepare(priv->clk_per);
1160 out_disable_ipg:
1161 clk_disable_unprepare(priv->clk_ipg);
1162
1163 return err;
1164 }
1165
1166 static void unregister_flexcandev(struct net_device *dev)
1167 {
1168 unregister_candev(dev);
1169 }
1170
1171 static const struct of_device_id flexcan_of_match[] = {
1172 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1173 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1174 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1175 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1176 { /* sentinel */ },
1177 };
1178 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1179
1180 static const struct platform_device_id flexcan_id_table[] = {
1181 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1182 { /* sentinel */ },
1183 };
1184 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1185
1186 static int flexcan_probe(struct platform_device *pdev)
1187 {
1188 const struct of_device_id *of_id;
1189 const struct flexcan_devtype_data *devtype_data;
1190 struct net_device *dev;
1191 struct flexcan_priv *priv;
1192 struct regulator *reg_xceiver;
1193 struct resource *mem;
1194 struct clk *clk_ipg = NULL, *clk_per = NULL;
1195 struct flexcan_regs __iomem *regs;
1196 int err, irq;
1197 u32 clock_freq = 0;
1198
1199 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1200 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1201 return -EPROBE_DEFER;
1202 else if (IS_ERR(reg_xceiver))
1203 reg_xceiver = NULL;
1204
1205 if (pdev->dev.of_node)
1206 of_property_read_u32(pdev->dev.of_node,
1207 "clock-frequency", &clock_freq);
1208
1209 if (!clock_freq) {
1210 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1211 if (IS_ERR(clk_ipg)) {
1212 dev_err(&pdev->dev, "no ipg clock defined\n");
1213 return PTR_ERR(clk_ipg);
1214 }
1215
1216 clk_per = devm_clk_get(&pdev->dev, "per");
1217 if (IS_ERR(clk_per)) {
1218 dev_err(&pdev->dev, "no per clock defined\n");
1219 return PTR_ERR(clk_per);
1220 }
1221 clock_freq = clk_get_rate(clk_per);
1222 }
1223
1224 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1225 irq = platform_get_irq(pdev, 0);
1226 if (irq <= 0)
1227 return -ENODEV;
1228
1229 regs = devm_ioremap_resource(&pdev->dev, mem);
1230 if (IS_ERR(regs))
1231 return PTR_ERR(regs);
1232
1233 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1234 if (of_id) {
1235 devtype_data = of_id->data;
1236 } else if (platform_get_device_id(pdev)->driver_data) {
1237 devtype_data = (struct flexcan_devtype_data *)
1238 platform_get_device_id(pdev)->driver_data;
1239 } else {
1240 return -ENODEV;
1241 }
1242
1243 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1244 if (!dev)
1245 return -ENOMEM;
1246
1247 platform_set_drvdata(pdev, dev);
1248 SET_NETDEV_DEV(dev, &pdev->dev);
1249
1250 dev->netdev_ops = &flexcan_netdev_ops;
1251 dev->irq = irq;
1252 dev->flags |= IFF_ECHO;
1253
1254 priv = netdev_priv(dev);
1255 priv->can.clock.freq = clock_freq;
1256 priv->can.bittiming_const = &flexcan_bittiming_const;
1257 priv->can.do_set_mode = flexcan_set_mode;
1258 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1259 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1260 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1261 CAN_CTRLMODE_BERR_REPORTING;
1262 priv->regs = regs;
1263 priv->clk_ipg = clk_ipg;
1264 priv->clk_per = clk_per;
1265 priv->devtype_data = devtype_data;
1266 priv->reg_xceiver = reg_xceiver;
1267
1268 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1269 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_TIMESTAMP;
1270 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1271 } else {
1272 priv->tx_mb_idx = FLEXCAN_TX_MB_OFF_FIFO;
1273 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1274 }
1275 priv->tx_mb = &regs->mb[priv->tx_mb_idx];
1276
1277 priv->reg_imask1_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1278 priv->reg_imask2_default = 0;
1279
1280 priv->offload.mailbox_read = flexcan_mailbox_read;
1281
1282 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1283 u64 imask;
1284
1285 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1286 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1287
1288 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1289 priv->reg_imask1_default |= imask;
1290 priv->reg_imask2_default |= imask >> 32;
1291
1292 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1293 } else {
1294 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1295 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1296 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1297 }
1298 if (err)
1299 goto failed_offload;
1300
1301 err = register_flexcandev(dev);
1302 if (err) {
1303 dev_err(&pdev->dev, "registering netdev failed\n");
1304 goto failed_register;
1305 }
1306
1307 devm_can_led_init(dev);
1308
1309 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1310 priv->regs, dev->irq);
1311
1312 return 0;
1313
1314 failed_offload:
1315 failed_register:
1316 free_candev(dev);
1317 return err;
1318 }
1319
1320 static int flexcan_remove(struct platform_device *pdev)
1321 {
1322 struct net_device *dev = platform_get_drvdata(pdev);
1323 struct flexcan_priv *priv = netdev_priv(dev);
1324
1325 unregister_flexcandev(dev);
1326 can_rx_offload_del(&priv->offload);
1327 free_candev(dev);
1328
1329 return 0;
1330 }
1331
1332 static int __maybe_unused flexcan_suspend(struct device *device)
1333 {
1334 struct net_device *dev = dev_get_drvdata(device);
1335 struct flexcan_priv *priv = netdev_priv(dev);
1336 int err;
1337
1338 if (netif_running(dev)) {
1339 err = flexcan_chip_disable(priv);
1340 if (err)
1341 return err;
1342 netif_stop_queue(dev);
1343 netif_device_detach(dev);
1344 }
1345 priv->can.state = CAN_STATE_SLEEPING;
1346
1347 return 0;
1348 }
1349
1350 static int __maybe_unused flexcan_resume(struct device *device)
1351 {
1352 struct net_device *dev = dev_get_drvdata(device);
1353 struct flexcan_priv *priv = netdev_priv(dev);
1354 int err;
1355
1356 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1357 if (netif_running(dev)) {
1358 netif_device_attach(dev);
1359 netif_start_queue(dev);
1360 err = flexcan_chip_enable(priv);
1361 if (err)
1362 return err;
1363 }
1364 return 0;
1365 }
1366
1367 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1368
1369 static struct platform_driver flexcan_driver = {
1370 .driver = {
1371 .name = DRV_NAME,
1372 .pm = &flexcan_pm_ops,
1373 .of_match_table = flexcan_of_match,
1374 },
1375 .probe = flexcan_probe,
1376 .remove = flexcan_remove,
1377 .id_table = flexcan_id_table,
1378 };
1379
1380 module_platform_driver(flexcan_driver);
1381
1382 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1383 "Marc Kleine-Budde <kernel@pengutronix.de>");
1384 MODULE_LICENSE("GPL v2");
1385 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
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