]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/net/can/m_can/m_can.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:


5d4e61741476660b925e80a81ca1d41c17587f3b
[mirror_ubuntu-bionic-kernel.git] / drivers / net / can / m_can / m_can.c
1 /*
2 * CAN bus driver for Bosch M_CAN controller
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 * Dong Aisheng <b29396@freescale.com>
6 *
7 * Bosch M_CAN user manual can be obtained from:
8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9 * mcan_users_manual_v302.pdf
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/iopoll.h>
27 #include <linux/can/dev.h>
28 #include <linux/pinctrl/consumer.h>
29
30 /* napi related */
31 #define M_CAN_NAPI_WEIGHT 64
32
33 /* message ram configuration data length */
34 #define MRAM_CFG_LEN 8
35
36 /* registers definition */
37 enum m_can_reg {
38 M_CAN_CREL = 0x0,
39 M_CAN_ENDN = 0x4,
40 M_CAN_CUST = 0x8,
41 M_CAN_DBTP = 0xc,
42 M_CAN_TEST = 0x10,
43 M_CAN_RWD = 0x14,
44 M_CAN_CCCR = 0x18,
45 M_CAN_NBTP = 0x1c,
46 M_CAN_TSCC = 0x20,
47 M_CAN_TSCV = 0x24,
48 M_CAN_TOCC = 0x28,
49 M_CAN_TOCV = 0x2c,
50 M_CAN_ECR = 0x40,
51 M_CAN_PSR = 0x44,
52 /* TDCR Register only available for version >=3.1.x */
53 M_CAN_TDCR = 0x48,
54 M_CAN_IR = 0x50,
55 M_CAN_IE = 0x54,
56 M_CAN_ILS = 0x58,
57 M_CAN_ILE = 0x5c,
58 M_CAN_GFC = 0x80,
59 M_CAN_SIDFC = 0x84,
60 M_CAN_XIDFC = 0x88,
61 M_CAN_XIDAM = 0x90,
62 M_CAN_HPMS = 0x94,
63 M_CAN_NDAT1 = 0x98,
64 M_CAN_NDAT2 = 0x9c,
65 M_CAN_RXF0C = 0xa0,
66 M_CAN_RXF0S = 0xa4,
67 M_CAN_RXF0A = 0xa8,
68 M_CAN_RXBC = 0xac,
69 M_CAN_RXF1C = 0xb0,
70 M_CAN_RXF1S = 0xb4,
71 M_CAN_RXF1A = 0xb8,
72 M_CAN_RXESC = 0xbc,
73 M_CAN_TXBC = 0xc0,
74 M_CAN_TXFQS = 0xc4,
75 M_CAN_TXESC = 0xc8,
76 M_CAN_TXBRP = 0xcc,
77 M_CAN_TXBAR = 0xd0,
78 M_CAN_TXBCR = 0xd4,
79 M_CAN_TXBTO = 0xd8,
80 M_CAN_TXBCF = 0xdc,
81 M_CAN_TXBTIE = 0xe0,
82 M_CAN_TXBCIE = 0xe4,
83 M_CAN_TXEFC = 0xf0,
84 M_CAN_TXEFS = 0xf4,
85 M_CAN_TXEFA = 0xf8,
86 };
87
88 /* m_can lec values */
89 enum m_can_lec_type {
90 LEC_NO_ERROR = 0,
91 LEC_STUFF_ERROR,
92 LEC_FORM_ERROR,
93 LEC_ACK_ERROR,
94 LEC_BIT1_ERROR,
95 LEC_BIT0_ERROR,
96 LEC_CRC_ERROR,
97 LEC_UNUSED,
98 };
99
100 enum m_can_mram_cfg {
101 MRAM_SIDF = 0,
102 MRAM_XIDF,
103 MRAM_RXF0,
104 MRAM_RXF1,
105 MRAM_RXB,
106 MRAM_TXE,
107 MRAM_TXB,
108 MRAM_CFG_NUM,
109 };
110
111 /* Core Release Register (CREL) */
112 #define CREL_REL_SHIFT 28
113 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT)
114 #define CREL_STEP_SHIFT 24
115 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT)
116 #define CREL_SUBSTEP_SHIFT 20
117 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT)
118
119 /* Data Bit Timing & Prescaler Register (DBTP) */
120 #define DBTP_TDC BIT(23)
121 #define DBTP_DBRP_SHIFT 16
122 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
123 #define DBTP_DTSEG1_SHIFT 8
124 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
125 #define DBTP_DTSEG2_SHIFT 4
126 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
127 #define DBTP_DSJW_SHIFT 0
128 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
129
130 /* Test Register (TEST) */
131 #define TEST_LBCK BIT(4)
132
133 /* CC Control Register(CCCR) */
134 #define CCCR_CMR_MASK 0x3
135 #define CCCR_CMR_SHIFT 10
136 #define CCCR_CMR_CANFD 0x1
137 #define CCCR_CMR_CANFD_BRS 0x2
138 #define CCCR_CMR_CAN 0x3
139 #define CCCR_CME_MASK 0x3
140 #define CCCR_CME_SHIFT 8
141 #define CCCR_CME_CAN 0
142 #define CCCR_CME_CANFD 0x1
143 #define CCCR_CME_CANFD_BRS 0x2
144 #define CCCR_TXP BIT(14)
145 #define CCCR_TEST BIT(7)
146 #define CCCR_MON BIT(5)
147 #define CCCR_CSR BIT(4)
148 #define CCCR_CSA BIT(3)
149 #define CCCR_ASM BIT(2)
150 #define CCCR_CCE BIT(1)
151 #define CCCR_INIT BIT(0)
152 #define CCCR_CANFD 0x10
153 /* for version >=3.1.x */
154 #define CCCR_EFBI BIT(13)
155 #define CCCR_PXHD BIT(12)
156 #define CCCR_BRSE BIT(9)
157 #define CCCR_FDOE BIT(8)
158 /* only for version >=3.2.x */
159 #define CCCR_NISO BIT(15)
160
161 /* Nominal Bit Timing & Prescaler Register (NBTP) */
162 #define NBTP_NSJW_SHIFT 25
163 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
164 #define NBTP_NBRP_SHIFT 16
165 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
166 #define NBTP_NTSEG1_SHIFT 8
167 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
168 #define NBTP_NTSEG2_SHIFT 0
169 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
170
171 /* Error Counter Register(ECR) */
172 #define ECR_RP BIT(15)
173 #define ECR_REC_SHIFT 8
174 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
175 #define ECR_TEC_SHIFT 0
176 #define ECR_TEC_MASK 0xff
177
178 /* Protocol Status Register(PSR) */
179 #define PSR_BO BIT(7)
180 #define PSR_EW BIT(6)
181 #define PSR_EP BIT(5)
182 #define PSR_LEC_MASK 0x7
183
184 /* Interrupt Register(IR) */
185 #define IR_ALL_INT 0xffffffff
186
187 /* Renamed bits for versions > 3.1.x */
188 #define IR_ARA BIT(29)
189 #define IR_PED BIT(28)
190 #define IR_PEA BIT(27)
191
192 /* Bits for version 3.0.x */
193 #define IR_STE BIT(31)
194 #define IR_FOE BIT(30)
195 #define IR_ACKE BIT(29)
196 #define IR_BE BIT(28)
197 #define IR_CRCE BIT(27)
198 #define IR_WDI BIT(26)
199 #define IR_BO BIT(25)
200 #define IR_EW BIT(24)
201 #define IR_EP BIT(23)
202 #define IR_ELO BIT(22)
203 #define IR_BEU BIT(21)
204 #define IR_BEC BIT(20)
205 #define IR_DRX BIT(19)
206 #define IR_TOO BIT(18)
207 #define IR_MRAF BIT(17)
208 #define IR_TSW BIT(16)
209 #define IR_TEFL BIT(15)
210 #define IR_TEFF BIT(14)
211 #define IR_TEFW BIT(13)
212 #define IR_TEFN BIT(12)
213 #define IR_TFE BIT(11)
214 #define IR_TCF BIT(10)
215 #define IR_TC BIT(9)
216 #define IR_HPM BIT(8)
217 #define IR_RF1L BIT(7)
218 #define IR_RF1F BIT(6)
219 #define IR_RF1W BIT(5)
220 #define IR_RF1N BIT(4)
221 #define IR_RF0L BIT(3)
222 #define IR_RF0F BIT(2)
223 #define IR_RF0W BIT(1)
224 #define IR_RF0N BIT(0)
225 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
226
227 /* Interrupts for version 3.0.x */
228 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
229 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
230 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
231 IR_RF1L | IR_RF0L)
232 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
233 /* Interrupts for version >= 3.1.x */
234 #define IR_ERR_LEC_31X (IR_PED | IR_PEA)
235 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
236 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
237 IR_RF1L | IR_RF0L)
238 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
239
240 /* Interrupt Line Select (ILS) */
241 #define ILS_ALL_INT0 0x0
242 #define ILS_ALL_INT1 0xFFFFFFFF
243
244 /* Interrupt Line Enable (ILE) */
245 #define ILE_EINT1 BIT(1)
246 #define ILE_EINT0 BIT(0)
247
248 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
249 #define RXFC_FWM_SHIFT 24
250 #define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT)
251 #define RXFC_FS_SHIFT 16
252 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
253
254 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
255 #define RXFS_RFL BIT(25)
256 #define RXFS_FF BIT(24)
257 #define RXFS_FPI_SHIFT 16
258 #define RXFS_FPI_MASK 0x3f0000
259 #define RXFS_FGI_SHIFT 8
260 #define RXFS_FGI_MASK 0x3f00
261 #define RXFS_FFL_MASK 0x7f
262
263 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
264 #define M_CAN_RXESC_8BYTES 0x0
265 #define M_CAN_RXESC_64BYTES 0x777
266
267 /* Tx Buffer Configuration(TXBC) */
268 #define TXBC_NDTB_SHIFT 16
269 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
270 #define TXBC_TFQS_SHIFT 24
271 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
272
273 /* Tx FIFO/Queue Status (TXFQS) */
274 #define TXFQS_TFQF BIT(21)
275 #define TXFQS_TFQPI_SHIFT 16
276 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
277 #define TXFQS_TFGI_SHIFT 8
278 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
279 #define TXFQS_TFFL_SHIFT 0
280 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
281
282 /* Tx Buffer Element Size Configuration(TXESC) */
283 #define TXESC_TBDS_8BYTES 0x0
284 #define TXESC_TBDS_64BYTES 0x7
285
286 /* Tx Event FIFO Configuration (TXEFC) */
287 #define TXEFC_EFS_SHIFT 16
288 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
289
290 /* Tx Event FIFO Status (TXEFS) */
291 #define TXEFS_TEFL BIT(25)
292 #define TXEFS_EFF BIT(24)
293 #define TXEFS_EFGI_SHIFT 8
294 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
295 #define TXEFS_EFFL_SHIFT 0
296 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
297
298 /* Tx Event FIFO Acknowledge (TXEFA) */
299 #define TXEFA_EFAI_SHIFT 0
300 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
301
302 /* Message RAM Configuration (in bytes) */
303 #define SIDF_ELEMENT_SIZE 4
304 #define XIDF_ELEMENT_SIZE 8
305 #define RXF0_ELEMENT_SIZE 72
306 #define RXF1_ELEMENT_SIZE 72
307 #define RXB_ELEMENT_SIZE 72
308 #define TXE_ELEMENT_SIZE 8
309 #define TXB_ELEMENT_SIZE 72
310
311 /* Message RAM Elements */
312 #define M_CAN_FIFO_ID 0x0
313 #define M_CAN_FIFO_DLC 0x4
314 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
315
316 /* Rx Buffer Element */
317 /* R0 */
318 #define RX_BUF_ESI BIT(31)
319 #define RX_BUF_XTD BIT(30)
320 #define RX_BUF_RTR BIT(29)
321 /* R1 */
322 #define RX_BUF_ANMF BIT(31)
323 #define RX_BUF_FDF BIT(21)
324 #define RX_BUF_BRS BIT(20)
325
326 /* Tx Buffer Element */
327 /* T0 */
328 #define TX_BUF_ESI BIT(31)
329 #define TX_BUF_XTD BIT(30)
330 #define TX_BUF_RTR BIT(29)
331 /* T1 */
332 #define TX_BUF_EFC BIT(23)
333 #define TX_BUF_FDF BIT(21)
334 #define TX_BUF_BRS BIT(20)
335 #define TX_BUF_MM_SHIFT 24
336 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
337
338 /* Tx event FIFO Element */
339 /* E1 */
340 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
341 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
342
343 /* address offset and element number for each FIFO/Buffer in the Message RAM */
344 struct mram_cfg {
345 u16 off;
346 u8 num;
347 };
348
349 /* m_can private data structure */
350 struct m_can_priv {
351 struct can_priv can; /* must be the first member */
352 struct napi_struct napi;
353 struct net_device *dev;
354 struct device *device;
355 struct clk *hclk;
356 struct clk *cclk;
357 void __iomem *base;
358 u32 irqstatus;
359 int version;
360
361 /* message ram configuration */
362 void __iomem *mram_base;
363 struct mram_cfg mcfg[MRAM_CFG_NUM];
364 };
365
366 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
367 {
368 return readl(priv->base + reg);
369 }
370
371 static inline void m_can_write(const struct m_can_priv *priv,
372 enum m_can_reg reg, u32 val)
373 {
374 writel(val, priv->base + reg);
375 }
376
377 static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
378 u32 fgi, unsigned int offset)
379 {
380 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
381 fgi * RXF0_ELEMENT_SIZE + offset);
382 }
383
384 static inline void m_can_fifo_write(const struct m_can_priv *priv,
385 u32 fpi, unsigned int offset, u32 val)
386 {
387 writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
388 fpi * TXB_ELEMENT_SIZE + offset);
389 }
390
391 static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv,
392 u32 fgi,
393 u32 offset) {
394 return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off +
395 fgi * TXE_ELEMENT_SIZE + offset);
396 }
397
398 static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv)
399 {
400 return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF);
401 }
402
403 static inline void m_can_config_endisable(const struct m_can_priv *priv,
404 bool enable)
405 {
406 u32 cccr = m_can_read(priv, M_CAN_CCCR);
407 u32 timeout = 10;
408 u32 val = 0;
409
410 if (enable) {
411 /* enable m_can configuration */
412 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
413 udelay(5);
414 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
415 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
416 } else {
417 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
418 }
419
420 /* there's a delay for module initialization */
421 if (enable)
422 val = CCCR_INIT | CCCR_CCE;
423
424 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
425 if (timeout == 0) {
426 netdev_warn(priv->dev, "Failed to init module\n");
427 return;
428 }
429 timeout--;
430 udelay(1);
431 }
432 }
433
434 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
435 {
436 /* Only interrupt line 0 is used in this driver */
437 m_can_write(priv, M_CAN_ILE, ILE_EINT0);
438 }
439
440 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
441 {
442 m_can_write(priv, M_CAN_ILE, 0x0);
443 }
444
445 static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
446 {
447 struct net_device_stats *stats = &dev->stats;
448 struct m_can_priv *priv = netdev_priv(dev);
449 struct canfd_frame *cf;
450 struct sk_buff *skb;
451 u32 id, fgi, dlc;
452 int i;
453
454 /* calculate the fifo get index for where to read data */
455 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
456 dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
457 if (dlc & RX_BUF_FDF)
458 skb = alloc_canfd_skb(dev, &cf);
459 else
460 skb = alloc_can_skb(dev, (struct can_frame **)&cf);
461 if (!skb) {
462 stats->rx_dropped++;
463 return;
464 }
465
466 if (dlc & RX_BUF_FDF)
467 cf->len = can_dlc2len((dlc >> 16) & 0x0F);
468 else
469 cf->len = get_can_dlc((dlc >> 16) & 0x0F);
470
471 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
472 if (id & RX_BUF_XTD)
473 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
474 else
475 cf->can_id = (id >> 18) & CAN_SFF_MASK;
476
477 if (id & RX_BUF_ESI) {
478 cf->flags |= CANFD_ESI;
479 netdev_dbg(dev, "ESI Error\n");
480 }
481
482 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) {
483 cf->can_id |= CAN_RTR_FLAG;
484 } else {
485 if (dlc & RX_BUF_BRS)
486 cf->flags |= CANFD_BRS;
487
488 for (i = 0; i < cf->len; i += 4)
489 *(u32 *)(cf->data + i) =
490 m_can_fifo_read(priv, fgi,
491 M_CAN_FIFO_DATA(i / 4));
492 }
493
494 /* acknowledge rx fifo 0 */
495 m_can_write(priv, M_CAN_RXF0A, fgi);
496
497 stats->rx_packets++;
498 stats->rx_bytes += cf->len;
499
500 netif_receive_skb(skb);
501 }
502
503 static int m_can_do_rx_poll(struct net_device *dev, int quota)
504 {
505 struct m_can_priv *priv = netdev_priv(dev);
506 u32 pkts = 0;
507 u32 rxfs;
508
509 rxfs = m_can_read(priv, M_CAN_RXF0S);
510 if (!(rxfs & RXFS_FFL_MASK)) {
511 netdev_dbg(dev, "no messages in fifo0\n");
512 return 0;
513 }
514
515 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
516 if (rxfs & RXFS_RFL)
517 netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
518
519 m_can_read_fifo(dev, rxfs);
520
521 quota--;
522 pkts++;
523 rxfs = m_can_read(priv, M_CAN_RXF0S);
524 }
525
526 if (pkts)
527 can_led_event(dev, CAN_LED_EVENT_RX);
528
529 return pkts;
530 }
531
532 static int m_can_handle_lost_msg(struct net_device *dev)
533 {
534 struct net_device_stats *stats = &dev->stats;
535 struct sk_buff *skb;
536 struct can_frame *frame;
537
538 netdev_err(dev, "msg lost in rxf0\n");
539
540 stats->rx_errors++;
541 stats->rx_over_errors++;
542
543 skb = alloc_can_err_skb(dev, &frame);
544 if (unlikely(!skb))
545 return 0;
546
547 frame->can_id |= CAN_ERR_CRTL;
548 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
549
550 netif_receive_skb(skb);
551
552 return 1;
553 }
554
555 static int m_can_handle_lec_err(struct net_device *dev,
556 enum m_can_lec_type lec_type)
557 {
558 struct m_can_priv *priv = netdev_priv(dev);
559 struct net_device_stats *stats = &dev->stats;
560 struct can_frame *cf;
561 struct sk_buff *skb;
562
563 priv->can.can_stats.bus_error++;
564 stats->rx_errors++;
565
566 /* propagate the error condition to the CAN stack */
567 skb = alloc_can_err_skb(dev, &cf);
568 if (unlikely(!skb))
569 return 0;
570
571 /* check for 'last error code' which tells us the
572 * type of the last error to occur on the CAN bus
573 */
574 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
575
576 switch (lec_type) {
577 case LEC_STUFF_ERROR:
578 netdev_dbg(dev, "stuff error\n");
579 cf->data[2] |= CAN_ERR_PROT_STUFF;
580 break;
581 case LEC_FORM_ERROR:
582 netdev_dbg(dev, "form error\n");
583 cf->data[2] |= CAN_ERR_PROT_FORM;
584 break;
585 case LEC_ACK_ERROR:
586 netdev_dbg(dev, "ack error\n");
587 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
588 break;
589 case LEC_BIT1_ERROR:
590 netdev_dbg(dev, "bit1 error\n");
591 cf->data[2] |= CAN_ERR_PROT_BIT1;
592 break;
593 case LEC_BIT0_ERROR:
594 netdev_dbg(dev, "bit0 error\n");
595 cf->data[2] |= CAN_ERR_PROT_BIT0;
596 break;
597 case LEC_CRC_ERROR:
598 netdev_dbg(dev, "CRC error\n");
599 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
600 break;
601 default:
602 break;
603 }
604
605 stats->rx_packets++;
606 stats->rx_bytes += cf->can_dlc;
607 netif_receive_skb(skb);
608
609 return 1;
610 }
611
612 static int __m_can_get_berr_counter(const struct net_device *dev,
613 struct can_berr_counter *bec)
614 {
615 struct m_can_priv *priv = netdev_priv(dev);
616 unsigned int ecr;
617
618 ecr = m_can_read(priv, M_CAN_ECR);
619 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
620 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
621
622 return 0;
623 }
624
625 static int m_can_clk_start(struct m_can_priv *priv)
626 {
627 int err;
628
629 err = clk_prepare_enable(priv->hclk);
630 if (err)
631 return err;
632
633 err = clk_prepare_enable(priv->cclk);
634 if (err)
635 clk_disable_unprepare(priv->hclk);
636
637 return err;
638 }
639
640 static void m_can_clk_stop(struct m_can_priv *priv)
641 {
642 clk_disable_unprepare(priv->cclk);
643 clk_disable_unprepare(priv->hclk);
644 }
645
646 static int m_can_get_berr_counter(const struct net_device *dev,
647 struct can_berr_counter *bec)
648 {
649 struct m_can_priv *priv = netdev_priv(dev);
650 int err;
651
652 err = m_can_clk_start(priv);
653 if (err)
654 return err;
655
656 __m_can_get_berr_counter(dev, bec);
657
658 m_can_clk_stop(priv);
659
660 return 0;
661 }
662
663 static int m_can_handle_state_change(struct net_device *dev,
664 enum can_state new_state)
665 {
666 struct m_can_priv *priv = netdev_priv(dev);
667 struct net_device_stats *stats = &dev->stats;
668 struct can_frame *cf;
669 struct sk_buff *skb;
670 struct can_berr_counter bec;
671 unsigned int ecr;
672
673 switch (new_state) {
674 case CAN_STATE_ERROR_ACTIVE:
675 /* error warning state */
676 priv->can.can_stats.error_warning++;
677 priv->can.state = CAN_STATE_ERROR_WARNING;
678 break;
679 case CAN_STATE_ERROR_PASSIVE:
680 /* error passive state */
681 priv->can.can_stats.error_passive++;
682 priv->can.state = CAN_STATE_ERROR_PASSIVE;
683 break;
684 case CAN_STATE_BUS_OFF:
685 /* bus-off state */
686 priv->can.state = CAN_STATE_BUS_OFF;
687 m_can_disable_all_interrupts(priv);
688 priv->can.can_stats.bus_off++;
689 can_bus_off(dev);
690 break;
691 default:
692 break;
693 }
694
695 /* propagate the error condition to the CAN stack */
696 skb = alloc_can_err_skb(dev, &cf);
697 if (unlikely(!skb))
698 return 0;
699
700 __m_can_get_berr_counter(dev, &bec);
701
702 switch (new_state) {
703 case CAN_STATE_ERROR_ACTIVE:
704 /* error warning state */
705 cf->can_id |= CAN_ERR_CRTL;
706 cf->data[1] = (bec.txerr > bec.rxerr) ?
707 CAN_ERR_CRTL_TX_WARNING :
708 CAN_ERR_CRTL_RX_WARNING;
709 cf->data[6] = bec.txerr;
710 cf->data[7] = bec.rxerr;
711 break;
712 case CAN_STATE_ERROR_PASSIVE:
713 /* error passive state */
714 cf->can_id |= CAN_ERR_CRTL;
715 ecr = m_can_read(priv, M_CAN_ECR);
716 if (ecr & ECR_RP)
717 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
718 if (bec.txerr > 127)
719 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
720 cf->data[6] = bec.txerr;
721 cf->data[7] = bec.rxerr;
722 break;
723 case CAN_STATE_BUS_OFF:
724 /* bus-off state */
725 cf->can_id |= CAN_ERR_BUSOFF;
726 break;
727 default:
728 break;
729 }
730
731 stats->rx_packets++;
732 stats->rx_bytes += cf->can_dlc;
733 netif_receive_skb(skb);
734
735 return 1;
736 }
737
738 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
739 {
740 struct m_can_priv *priv = netdev_priv(dev);
741 int work_done = 0;
742
743 if ((psr & PSR_EW) &&
744 (priv->can.state != CAN_STATE_ERROR_WARNING)) {
745 netdev_dbg(dev, "entered error warning state\n");
746 work_done += m_can_handle_state_change(dev,
747 CAN_STATE_ERROR_WARNING);
748 }
749
750 if ((psr & PSR_EP) &&
751 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
752 netdev_dbg(dev, "entered error passive state\n");
753 work_done += m_can_handle_state_change(dev,
754 CAN_STATE_ERROR_PASSIVE);
755 }
756
757 if ((psr & PSR_BO) &&
758 (priv->can.state != CAN_STATE_BUS_OFF)) {
759 netdev_dbg(dev, "entered error bus off state\n");
760 work_done += m_can_handle_state_change(dev,
761 CAN_STATE_BUS_OFF);
762 }
763
764 return work_done;
765 }
766
767 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
768 {
769 if (irqstatus & IR_WDI)
770 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
771 if (irqstatus & IR_ELO)
772 netdev_err(dev, "Error Logging Overflow\n");
773 if (irqstatus & IR_BEU)
774 netdev_err(dev, "Bit Error Uncorrected\n");
775 if (irqstatus & IR_BEC)
776 netdev_err(dev, "Bit Error Corrected\n");
777 if (irqstatus & IR_TOO)
778 netdev_err(dev, "Timeout reached\n");
779 if (irqstatus & IR_MRAF)
780 netdev_err(dev, "Message RAM access failure occurred\n");
781 }
782
783 static inline bool is_lec_err(u32 psr)
784 {
785 psr &= LEC_UNUSED;
786
787 return psr && (psr != LEC_UNUSED);
788 }
789
790 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
791 u32 psr)
792 {
793 struct m_can_priv *priv = netdev_priv(dev);
794 int work_done = 0;
795
796 if (irqstatus & IR_RF0L)
797 work_done += m_can_handle_lost_msg(dev);
798
799 /* handle lec errors on the bus */
800 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
801 is_lec_err(psr))
802 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
803
804 /* other unproccessed error interrupts */
805 m_can_handle_other_err(dev, irqstatus);
806
807 return work_done;
808 }
809
810 static int m_can_poll(struct napi_struct *napi, int quota)
811 {
812 struct net_device *dev = napi->dev;
813 struct m_can_priv *priv = netdev_priv(dev);
814 int work_done = 0;
815 u32 irqstatus, psr;
816
817 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR);
818 if (!irqstatus)
819 goto end;
820
821 psr = m_can_read(priv, M_CAN_PSR);
822 if (irqstatus & IR_ERR_STATE)
823 work_done += m_can_handle_state_errors(dev, psr);
824
825 if (irqstatus & IR_ERR_BUS_30X)
826 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
827
828 if (irqstatus & IR_RF0N)
829 work_done += m_can_do_rx_poll(dev, (quota - work_done));
830
831 if (work_done < quota) {
832 napi_complete_done(napi, work_done);
833 m_can_enable_all_interrupts(priv);
834 }
835
836 end:
837 return work_done;
838 }
839
840 static void m_can_echo_tx_event(struct net_device *dev)
841 {
842 u32 txe_count = 0;
843 u32 m_can_txefs;
844 u32 fgi = 0;
845 int i = 0;
846 unsigned int msg_mark;
847
848 struct m_can_priv *priv = netdev_priv(dev);
849 struct net_device_stats *stats = &dev->stats;
850
851 /* read tx event fifo status */
852 m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
853
854 /* Get Tx Event fifo element count */
855 txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
856 >> TXEFS_EFFL_SHIFT;
857
858 /* Get and process all sent elements */
859 for (i = 0; i < txe_count; i++) {
860 /* retrieve get index */
861 fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
862 >> TXEFS_EFGI_SHIFT;
863
864 /* get message marker */
865 msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
866 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
867
868 /* ack txe element */
869 m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
870 (fgi << TXEFA_EFAI_SHIFT)));
871
872 /* update stats */
873 stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
874 stats->tx_packets++;
875 }
876 }
877
878 static irqreturn_t m_can_isr(int irq, void *dev_id)
879 {
880 struct net_device *dev = (struct net_device *)dev_id;
881 struct m_can_priv *priv = netdev_priv(dev);
882 struct net_device_stats *stats = &dev->stats;
883 u32 ir;
884
885 ir = m_can_read(priv, M_CAN_IR);
886 if (!ir)
887 return IRQ_NONE;
888
889 /* ACK all irqs */
890 if (ir & IR_ALL_INT)
891 m_can_write(priv, M_CAN_IR, ir);
892
893 /* schedule NAPI in case of
894 * - rx IRQ
895 * - state change IRQ
896 * - bus error IRQ and bus error reporting
897 */
898 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
899 priv->irqstatus = ir;
900 m_can_disable_all_interrupts(priv);
901 napi_schedule(&priv->napi);
902 }
903
904 if (priv->version == 30) {
905 if (ir & IR_TC) {
906 /* Transmission Complete Interrupt*/
907 stats->tx_bytes += can_get_echo_skb(dev, 0);
908 stats->tx_packets++;
909 can_led_event(dev, CAN_LED_EVENT_TX);
910 netif_wake_queue(dev);
911 }
912 } else {
913 if (ir & IR_TEFN) {
914 /* New TX FIFO Element arrived */
915 m_can_echo_tx_event(dev);
916 can_led_event(dev, CAN_LED_EVENT_TX);
917 if (netif_queue_stopped(dev) &&
918 !m_can_tx_fifo_full(priv))
919 netif_wake_queue(dev);
920 }
921 }
922
923 return IRQ_HANDLED;
924 }
925
926 static const struct can_bittiming_const m_can_bittiming_const_30X = {
927 .name = KBUILD_MODNAME,
928 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
929 .tseg1_max = 64,
930 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
931 .tseg2_max = 16,
932 .sjw_max = 16,
933 .brp_min = 1,
934 .brp_max = 1024,
935 .brp_inc = 1,
936 };
937
938 static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
939 .name = KBUILD_MODNAME,
940 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
941 .tseg1_max = 16,
942 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
943 .tseg2_max = 8,
944 .sjw_max = 4,
945 .brp_min = 1,
946 .brp_max = 32,
947 .brp_inc = 1,
948 };
949
950 static const struct can_bittiming_const m_can_bittiming_const_31X = {
951 .name = KBUILD_MODNAME,
952 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
953 .tseg1_max = 256,
954 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
955 .tseg2_max = 128,
956 .sjw_max = 128,
957 .brp_min = 1,
958 .brp_max = 512,
959 .brp_inc = 1,
960 };
961
962 static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
963 .name = KBUILD_MODNAME,
964 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
965 .tseg1_max = 32,
966 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
967 .tseg2_max = 16,
968 .sjw_max = 16,
969 .brp_min = 1,
970 .brp_max = 32,
971 .brp_inc = 1,
972 };
973
974 static int m_can_set_bittiming(struct net_device *dev)
975 {
976 struct m_can_priv *priv = netdev_priv(dev);
977 const struct can_bittiming *bt = &priv->can.bittiming;
978 const struct can_bittiming *dbt = &priv->can.data_bittiming;
979 u16 brp, sjw, tseg1, tseg2;
980 u32 reg_btp;
981
982 brp = bt->brp - 1;
983 sjw = bt->sjw - 1;
984 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
985 tseg2 = bt->phase_seg2 - 1;
986 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
987 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
988 m_can_write(priv, M_CAN_NBTP, reg_btp);
989
990 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
991 brp = dbt->brp - 1;
992 sjw = dbt->sjw - 1;
993 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
994 tseg2 = dbt->phase_seg2 - 1;
995 reg_btp = (brp << DBTP_DBRP_SHIFT) | (sjw << DBTP_DSJW_SHIFT) |
996 (tseg1 << DBTP_DTSEG1_SHIFT) |
997 (tseg2 << DBTP_DTSEG2_SHIFT);
998 m_can_write(priv, M_CAN_DBTP, reg_btp);
999 }
1000
1001 return 0;
1002 }
1003
1004 /* Configure M_CAN chip:
1005 * - set rx buffer/fifo element size
1006 * - configure rx fifo
1007 * - accept non-matching frame into fifo 0
1008 * - configure tx buffer
1009 * - >= v3.1.x: TX FIFO is used
1010 * - configure mode
1011 * - setup bittiming
1012 */
1013 static void m_can_chip_config(struct net_device *dev)
1014 {
1015 struct m_can_priv *priv = netdev_priv(dev);
1016 u32 cccr, test;
1017
1018 m_can_config_endisable(priv, true);
1019
1020 /* RX Buffer/FIFO Element Size 64 bytes data field */
1021 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
1022
1023 /* Accept Non-matching Frames Into FIFO 0 */
1024 m_can_write(priv, M_CAN_GFC, 0x0);
1025
1026 if (priv->version == 30) {
1027 /* only support one Tx Buffer currently */
1028 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
1029 priv->mcfg[MRAM_TXB].off);
1030 } else {
1031 /* TX FIFO is used for newer IP Core versions */
1032 m_can_write(priv, M_CAN_TXBC,
1033 (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |
1034 (priv->mcfg[MRAM_TXB].off));
1035 }
1036
1037 /* support 64 bytes payload */
1038 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
1039
1040 /* TX Event FIFO */
1041 if (priv->version == 30) {
1042 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
1043 priv->mcfg[MRAM_TXE].off);
1044 } else {
1045 /* Full TX Event FIFO is used */
1046 m_can_write(priv, M_CAN_TXEFC,
1047 ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
1048 & TXEFC_EFS_MASK) |
1049 priv->mcfg[MRAM_TXE].off);
1050 }
1051
1052 /* rx fifo configuration, blocking mode, fifo size 1 */
1053 m_can_write(priv, M_CAN_RXF0C,
1054 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
1055 priv->mcfg[MRAM_RXF0].off);
1056
1057 m_can_write(priv, M_CAN_RXF1C,
1058 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
1059 priv->mcfg[MRAM_RXF1].off);
1060
1061 cccr = m_can_read(priv, M_CAN_CCCR);
1062 test = m_can_read(priv, M_CAN_TEST);
1063 test &= ~TEST_LBCK;
1064 if (priv->version == 30) {
1065 /* Version 3.0.x */
1066
1067 cccr &= ~(CCCR_TEST | CCCR_MON |
1068 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
1069 (CCCR_CME_MASK << CCCR_CME_SHIFT));
1070
1071 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1072 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
1073
1074 } else {
1075 /* Version 3.1.x or 3.2.x */
1076 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE);
1077
1078 /* Only 3.2.x has NISO Bit implemented */
1079 if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1080 cccr |= CCCR_NISO;
1081
1082 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1083 cccr |= (CCCR_BRSE | CCCR_FDOE);
1084 }
1085
1086 /* Loopback Mode */
1087 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1088 cccr |= CCCR_TEST | CCCR_MON;
1089 test |= TEST_LBCK;
1090 }
1091
1092 /* Enable Monitoring (all versions) */
1093 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1094 cccr |= CCCR_MON;
1095
1096 /* Write config */
1097 m_can_write(priv, M_CAN_CCCR, cccr);
1098 m_can_write(priv, M_CAN_TEST, test);
1099
1100 /* Enable interrupts */
1101 m_can_write(priv, M_CAN_IR, IR_ALL_INT);
1102 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1103 if (priv->version == 30)
1104 m_can_write(priv, M_CAN_IE, IR_ALL_INT &
1105 ~(IR_ERR_LEC_30X));
1106 else
1107 m_can_write(priv, M_CAN_IE, IR_ALL_INT &
1108 ~(IR_ERR_LEC_31X));
1109 else
1110 m_can_write(priv, M_CAN_IE, IR_ALL_INT);
1111
1112 /* route all interrupts to INT0 */
1113 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
1114
1115 /* set bittiming params */
1116 m_can_set_bittiming(dev);
1117
1118 m_can_config_endisable(priv, false);
1119 }
1120
1121 static void m_can_start(struct net_device *dev)
1122 {
1123 struct m_can_priv *priv = netdev_priv(dev);
1124
1125 /* basic m_can configuration */
1126 m_can_chip_config(dev);
1127
1128 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1129
1130 m_can_enable_all_interrupts(priv);
1131 }
1132
1133 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1134 {
1135 switch (mode) {
1136 case CAN_MODE_START:
1137 m_can_start(dev);
1138 netif_wake_queue(dev);
1139 break;
1140 default:
1141 return -EOPNOTSUPP;
1142 }
1143
1144 return 0;
1145 }
1146
1147 static void free_m_can_dev(struct net_device *dev)
1148 {
1149 free_candev(dev);
1150 }
1151
1152 /* Checks core release number of M_CAN
1153 * returns 0 if an unsupported device is detected
1154 * else it returns the release and step coded as:
1155 * return value = 10 * <release> + 1 * <step>
1156 */
1157 static int m_can_check_core_release(void __iomem *m_can_base)
1158 {
1159 u32 crel_reg;
1160 u8 rel;
1161 u8 step;
1162 int res;
1163 struct m_can_priv temp_priv = {
1164 .base = m_can_base
1165 };
1166
1167 /* Read Core Release Version and split into version number
1168 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1169 */
1170 crel_reg = m_can_read(&temp_priv, M_CAN_CREL);
1171 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
1172 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
1173
1174 if (rel == 3) {
1175 /* M_CAN v3.x.y: create return value */
1176 res = 30 + step;
1177 } else {
1178 /* Unsupported M_CAN version */
1179 res = 0;
1180 }
1181
1182 return res;
1183 }
1184
1185 /* Selectable Non ISO support only in version 3.2.x
1186 * This function checks if the bit is writable.
1187 */
1188 static bool m_can_niso_supported(const struct m_can_priv *priv)
1189 {
1190 u32 cccr_reg, cccr_poll;
1191 int niso_timeout;
1192
1193 m_can_config_endisable(priv, true);
1194 cccr_reg = m_can_read(priv, M_CAN_CCCR);
1195 cccr_reg |= CCCR_NISO;
1196 m_can_write(priv, M_CAN_CCCR, cccr_reg);
1197
1198 niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll,
1199 (cccr_poll == cccr_reg), 0, 10);
1200
1201 /* Clear NISO */
1202 cccr_reg &= ~(CCCR_NISO);
1203 m_can_write(priv, M_CAN_CCCR, cccr_reg);
1204
1205 m_can_config_endisable(priv, false);
1206
1207 /* return false if time out (-ETIMEDOUT), else return true */
1208 return !niso_timeout;
1209 }
1210
1211 static struct net_device *alloc_m_can_dev(struct platform_device *pdev,
1212 void __iomem *addr, u32 tx_fifo_size)
1213 {
1214 struct net_device *dev;
1215 struct m_can_priv *priv;
1216 int m_can_version;
1217 unsigned int echo_buffer_count;
1218
1219 m_can_version = m_can_check_core_release(addr);
1220 /* return if unsupported version */
1221 if (!m_can_version) {
1222 dev = NULL;
1223 goto return_dev;
1224 }
1225
1226 /* If version < 3.1.x, then only one echo buffer is used */
1227 echo_buffer_count = ((m_can_version == 30)
1228 ? 1U
1229 : (unsigned int)tx_fifo_size);
1230
1231 dev = alloc_candev(sizeof(*priv), echo_buffer_count);
1232 if (!dev) {
1233 dev = NULL;
1234 goto return_dev;
1235 }
1236 priv = netdev_priv(dev);
1237 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
1238
1239 /* Shared properties of all M_CAN versions */
1240 priv->version = m_can_version;
1241 priv->dev = dev;
1242 priv->base = addr;
1243 priv->can.do_set_mode = m_can_set_mode;
1244 priv->can.do_get_berr_counter = m_can_get_berr_counter;
1245
1246 /* Set M_CAN supported operations */
1247 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1248 CAN_CTRLMODE_LISTENONLY |
1249 CAN_CTRLMODE_BERR_REPORTING |
1250 CAN_CTRLMODE_FD;
1251
1252 /* Set properties depending on M_CAN version */
1253 switch (priv->version) {
1254 case 30:
1255 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1256 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1257 priv->can.bittiming_const = &m_can_bittiming_const_30X;
1258 priv->can.data_bittiming_const =
1259 &m_can_data_bittiming_const_30X;
1260 break;
1261 case 31:
1262 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1263 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1264 priv->can.bittiming_const = &m_can_bittiming_const_31X;
1265 priv->can.data_bittiming_const =
1266 &m_can_data_bittiming_const_31X;
1267 break;
1268 case 32:
1269 priv->can.bittiming_const = &m_can_bittiming_const_31X;
1270 priv->can.data_bittiming_const =
1271 &m_can_data_bittiming_const_31X;
1272 priv->can.ctrlmode_supported |= (m_can_niso_supported(priv)
1273 ? CAN_CTRLMODE_FD_NON_ISO
1274 : 0);
1275 break;
1276 default:
1277 /* Unsupported device: free candev */
1278 free_m_can_dev(dev);
1279 dev_err(&pdev->dev, "Unsupported version number: %2d",
1280 priv->version);
1281 dev = NULL;
1282 break;
1283 }
1284
1285 return_dev:
1286 return dev;
1287 }
1288
1289 static int m_can_open(struct net_device *dev)
1290 {
1291 struct m_can_priv *priv = netdev_priv(dev);
1292 int err;
1293
1294 err = m_can_clk_start(priv);
1295 if (err)
1296 return err;
1297
1298 /* open the can device */
1299 err = open_candev(dev);
1300 if (err) {
1301 netdev_err(dev, "failed to open can device\n");
1302 goto exit_disable_clks;
1303 }
1304
1305 /* register interrupt handler */
1306 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
1307 dev);
1308 if (err < 0) {
1309 netdev_err(dev, "failed to request interrupt\n");
1310 goto exit_irq_fail;
1311 }
1312
1313 /* start the m_can controller */
1314 m_can_start(dev);
1315
1316 can_led_event(dev, CAN_LED_EVENT_OPEN);
1317 napi_enable(&priv->napi);
1318 netif_start_queue(dev);
1319
1320 return 0;
1321
1322 exit_irq_fail:
1323 close_candev(dev);
1324 exit_disable_clks:
1325 m_can_clk_stop(priv);
1326 return err;
1327 }
1328
1329 static void m_can_stop(struct net_device *dev)
1330 {
1331 struct m_can_priv *priv = netdev_priv(dev);
1332
1333 /* disable all interrupts */
1334 m_can_disable_all_interrupts(priv);
1335
1336 /* set the state as STOPPED */
1337 priv->can.state = CAN_STATE_STOPPED;
1338 }
1339
1340 static int m_can_close(struct net_device *dev)
1341 {
1342 struct m_can_priv *priv = netdev_priv(dev);
1343
1344 netif_stop_queue(dev);
1345 napi_disable(&priv->napi);
1346 m_can_stop(dev);
1347 m_can_clk_stop(priv);
1348 free_irq(dev->irq, dev);
1349 close_candev(dev);
1350 can_led_event(dev, CAN_LED_EVENT_STOP);
1351
1352 return 0;
1353 }
1354
1355 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
1356 {
1357 struct m_can_priv *priv = netdev_priv(dev);
1358 /*get wrap around for loopback skb index */
1359 unsigned int wrap = priv->can.echo_skb_max;
1360 int next_idx;
1361
1362 /* calculate next index */
1363 next_idx = (++putidx >= wrap ? 0 : putidx);
1364
1365 /* check if occupied */
1366 return !!priv->can.echo_skb[next_idx];
1367 }
1368
1369 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1370 struct net_device *dev)
1371 {
1372 struct m_can_priv *priv = netdev_priv(dev);
1373 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1374 u32 id, cccr, fdflags;
1375 int i;
1376 int putidx;
1377
1378 if (can_dropped_invalid_skb(dev, skb))
1379 return NETDEV_TX_OK;
1380
1381 /* Generate ID field for TX buffer Element */
1382 /* Common to all supported M_CAN versions */
1383 if (cf->can_id & CAN_EFF_FLAG) {
1384 id = cf->can_id & CAN_EFF_MASK;
1385 id |= TX_BUF_XTD;
1386 } else {
1387 id = ((cf->can_id & CAN_SFF_MASK) << 18);
1388 }
1389
1390 if (cf->can_id & CAN_RTR_FLAG)
1391 id |= TX_BUF_RTR;
1392
1393 if (priv->version == 30) {
1394 netif_stop_queue(dev);
1395
1396 /* message ram configuration */
1397 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
1398 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
1399 can_len2dlc(cf->len) << 16);
1400
1401 for (i = 0; i < cf->len; i += 4)
1402 m_can_fifo_write(priv, 0,
1403 M_CAN_FIFO_DATA(i / 4),
1404 *(u32 *)(cf->data + i));
1405
1406 can_put_echo_skb(skb, dev, 0);
1407
1408 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1409 cccr = m_can_read(priv, M_CAN_CCCR);
1410 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
1411 if (can_is_canfd_skb(skb)) {
1412 if (cf->flags & CANFD_BRS)
1413 cccr |= CCCR_CMR_CANFD_BRS <<
1414 CCCR_CMR_SHIFT;
1415 else
1416 cccr |= CCCR_CMR_CANFD <<
1417 CCCR_CMR_SHIFT;
1418 } else {
1419 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
1420 }
1421 m_can_write(priv, M_CAN_CCCR, cccr);
1422 }
1423 m_can_write(priv, M_CAN_TXBTIE, 0x1);
1424 m_can_write(priv, M_CAN_TXBAR, 0x1);
1425 /* End of xmit function for version 3.0.x */
1426 } else {
1427 /* Transmit routine for version >= v3.1.x */
1428
1429 /* Check if FIFO full */
1430 if (m_can_tx_fifo_full(priv)) {
1431 /* This shouldn't happen */
1432 netif_stop_queue(dev);
1433 netdev_warn(dev,
1434 "TX queue active although FIFO is full.");
1435 return NETDEV_TX_BUSY;
1436 }
1437
1438 /* get put index for frame */
1439 putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
1440 >> TXFQS_TFQPI_SHIFT);
1441 /* Write ID Field to FIFO Element */
1442 m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
1443
1444 /* get CAN FD configuration of frame */
1445 fdflags = 0;
1446 if (can_is_canfd_skb(skb)) {
1447 fdflags |= TX_BUF_FDF;
1448 if (cf->flags & CANFD_BRS)
1449 fdflags |= TX_BUF_BRS;
1450 }
1451
1452 /* Construct DLC Field. Also contains CAN-FD configuration
1453 * use put index of fifo as message marker
1454 * it is used in TX interrupt for
1455 * sending the correct echo frame
1456 */
1457 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
1458 ((putidx << TX_BUF_MM_SHIFT) &
1459 TX_BUF_MM_MASK) |
1460 (can_len2dlc(cf->len) << 16) |
1461 fdflags | TX_BUF_EFC);
1462
1463 for (i = 0; i < cf->len; i += 4)
1464 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
1465 *(u32 *)(cf->data + i));
1466
1467 /* Push loopback echo.
1468 * Will be looped back on TX interrupt based on message marker
1469 */
1470 can_put_echo_skb(skb, dev, putidx);
1471
1472 /* Enable TX FIFO element to start transfer */
1473 m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
1474
1475 /* stop network queue if fifo full */
1476 if (m_can_tx_fifo_full(priv) ||
1477 m_can_next_echo_skb_occupied(dev, putidx))
1478 netif_stop_queue(dev);
1479 }
1480
1481 return NETDEV_TX_OK;
1482 }
1483
1484 static const struct net_device_ops m_can_netdev_ops = {
1485 .ndo_open = m_can_open,
1486 .ndo_stop = m_can_close,
1487 .ndo_start_xmit = m_can_start_xmit,
1488 .ndo_change_mtu = can_change_mtu,
1489 };
1490
1491 static int register_m_can_dev(struct net_device *dev)
1492 {
1493 dev->flags |= IFF_ECHO; /* we support local echo */
1494 dev->netdev_ops = &m_can_netdev_ops;
1495
1496 return register_candev(dev);
1497 }
1498
1499 static void m_can_init_ram(struct m_can_priv *priv)
1500 {
1501 int end, i, start;
1502
1503 /* initialize the entire Message RAM in use to avoid possible
1504 * ECC/parity checksum errors when reading an uninitialized buffer
1505 */
1506 start = priv->mcfg[MRAM_SIDF].off;
1507 end = priv->mcfg[MRAM_TXB].off +
1508 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1509 for (i = start; i < end; i += 4)
1510 writel(0x0, priv->mram_base + i);
1511 }
1512
1513 static void m_can_of_parse_mram(struct m_can_priv *priv,
1514 const u32 *mram_config_vals)
1515 {
1516 priv->mcfg[MRAM_SIDF].off = mram_config_vals[0];
1517 priv->mcfg[MRAM_SIDF].num = mram_config_vals[1];
1518 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
1519 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1520 priv->mcfg[MRAM_XIDF].num = mram_config_vals[2];
1521 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
1522 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1523 priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
1524 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1525 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
1526 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1527 priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
1528 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1529 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
1530 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1531 priv->mcfg[MRAM_RXB].num = mram_config_vals[5];
1532 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
1533 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1534 priv->mcfg[MRAM_TXE].num = mram_config_vals[6];
1535 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
1536 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1537 priv->mcfg[MRAM_TXB].num = mram_config_vals[7] &
1538 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
1539
1540 dev_dbg(priv->device,
1541 "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1542 priv->mram_base,
1543 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
1544 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
1545 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
1546 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
1547 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
1548 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
1549 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
1550
1551 m_can_init_ram(priv);
1552 }
1553
1554 static int m_can_plat_probe(struct platform_device *pdev)
1555 {
1556 struct net_device *dev;
1557 struct m_can_priv *priv;
1558 struct resource *res;
1559 void __iomem *addr;
1560 void __iomem *mram_addr;
1561 struct clk *hclk, *cclk;
1562 int irq, ret;
1563 struct device_node *np;
1564 u32 mram_config_vals[MRAM_CFG_LEN];
1565 u32 tx_fifo_size;
1566
1567 np = pdev->dev.of_node;
1568
1569 hclk = devm_clk_get(&pdev->dev, "hclk");
1570 cclk = devm_clk_get(&pdev->dev, "cclk");
1571
1572 if (IS_ERR(hclk) || IS_ERR(cclk)) {
1573 dev_err(&pdev->dev, "no clock found\n");
1574 ret = -ENODEV;
1575 goto failed_ret;
1576 }
1577
1578 /* Enable clocks. Necessary to read Core Release in order to determine
1579 * M_CAN version
1580 */
1581 ret = clk_prepare_enable(hclk);
1582 if (ret)
1583 goto disable_hclk_ret;
1584
1585 ret = clk_prepare_enable(cclk);
1586 if (ret)
1587 goto disable_cclk_ret;
1588
1589 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
1590 addr = devm_ioremap_resource(&pdev->dev, res);
1591 irq = platform_get_irq_byname(pdev, "int0");
1592
1593 if (IS_ERR(addr) || irq < 0) {
1594 ret = -EINVAL;
1595 goto disable_cclk_ret;
1596 }
1597
1598 /* message ram could be shared */
1599 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
1600 if (!res) {
1601 ret = -ENODEV;
1602 goto disable_cclk_ret;
1603 }
1604
1605 mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1606 if (!mram_addr) {
1607 ret = -ENOMEM;
1608 goto disable_cclk_ret;
1609 }
1610
1611 /* get message ram configuration */
1612 ret = of_property_read_u32_array(np, "bosch,mram-cfg",
1613 mram_config_vals,
1614 sizeof(mram_config_vals) / 4);
1615 if (ret) {
1616 dev_err(&pdev->dev, "Could not get Message RAM configuration.");
1617 goto disable_cclk_ret;
1618 }
1619
1620 /* Get TX FIFO size
1621 * Defines the total amount of echo buffers for loopback
1622 */
1623 tx_fifo_size = mram_config_vals[7];
1624
1625 /* allocate the m_can device */
1626 dev = alloc_m_can_dev(pdev, addr, tx_fifo_size);
1627 if (!dev) {
1628 ret = -ENOMEM;
1629 goto disable_cclk_ret;
1630 }
1631 priv = netdev_priv(dev);
1632 dev->irq = irq;
1633 priv->device = &pdev->dev;
1634 priv->hclk = hclk;
1635 priv->cclk = cclk;
1636 priv->can.clock.freq = clk_get_rate(cclk);
1637 priv->mram_base = mram_addr;
1638
1639 m_can_of_parse_mram(priv, mram_config_vals);
1640
1641 platform_set_drvdata(pdev, dev);
1642 SET_NETDEV_DEV(dev, &pdev->dev);
1643
1644 ret = register_m_can_dev(dev);
1645 if (ret) {
1646 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1647 KBUILD_MODNAME, ret);
1648 goto failed_free_dev;
1649 }
1650
1651 devm_can_led_init(dev);
1652
1653 dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n",
1654 KBUILD_MODNAME, dev->irq, priv->version);
1655
1656 /* Probe finished
1657 * Stop clocks. They will be reactivated once the M_CAN device is opened
1658 */
1659
1660 goto disable_cclk_ret;
1661
1662 failed_free_dev:
1663 free_m_can_dev(dev);
1664 disable_cclk_ret:
1665 clk_disable_unprepare(cclk);
1666 disable_hclk_ret:
1667 clk_disable_unprepare(hclk);
1668 failed_ret:
1669 return ret;
1670 }
1671
1672 /* TODO: runtime PM with power down or sleep mode */
1673
1674 static __maybe_unused int m_can_suspend(struct device *dev)
1675 {
1676 struct net_device *ndev = dev_get_drvdata(dev);
1677 struct m_can_priv *priv = netdev_priv(ndev);
1678
1679 if (netif_running(ndev)) {
1680 netif_stop_queue(ndev);
1681 netif_device_detach(ndev);
1682 m_can_stop(ndev);
1683 m_can_clk_stop(priv);
1684 }
1685
1686 pinctrl_pm_select_sleep_state(dev);
1687
1688 priv->can.state = CAN_STATE_SLEEPING;
1689
1690 return 0;
1691 }
1692
1693 static __maybe_unused int m_can_resume(struct device *dev)
1694 {
1695 struct net_device *ndev = dev_get_drvdata(dev);
1696 struct m_can_priv *priv = netdev_priv(ndev);
1697
1698 pinctrl_pm_select_default_state(dev);
1699
1700 m_can_init_ram(priv);
1701
1702 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1703
1704 if (netif_running(ndev)) {
1705 int ret;
1706
1707 ret = m_can_clk_start(priv);
1708 if (ret)
1709 return ret;
1710
1711 m_can_start(ndev);
1712 netif_device_attach(ndev);
1713 netif_start_queue(ndev);
1714 }
1715
1716 return 0;
1717 }
1718
1719 static void unregister_m_can_dev(struct net_device *dev)
1720 {
1721 unregister_candev(dev);
1722 }
1723
1724 static int m_can_plat_remove(struct platform_device *pdev)
1725 {
1726 struct net_device *dev = platform_get_drvdata(pdev);
1727
1728 unregister_m_can_dev(dev);
1729 platform_set_drvdata(pdev, NULL);
1730
1731 free_m_can_dev(dev);
1732
1733 return 0;
1734 }
1735
1736 static const struct dev_pm_ops m_can_pmops = {
1737 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
1738 };
1739
1740 static const struct of_device_id m_can_of_table[] = {
1741 { .compatible = "bosch,m_can", .data = NULL },
1742 { /* sentinel */ },
1743 };
1744 MODULE_DEVICE_TABLE(of, m_can_of_table);
1745
1746 static struct platform_driver m_can_plat_driver = {
1747 .driver = {
1748 .name = KBUILD_MODNAME,
1749 .of_match_table = m_can_of_table,
1750 .pm = &m_can_pmops,
1751 },
1752 .probe = m_can_plat_probe,
1753 .remove = m_can_plat_remove,
1754 };
1755
1756 module_platform_driver(m_can_plat_driver);
1757
1758 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
1759 MODULE_LICENSE("GPL v2");
1760 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
ubuntu-bionic-kernel mirror