2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 * Your platform definition file should specify something like:
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .model = CAN_MCP251X_MCP2510,
42 * .power_enable = mcp251x_power_enable,
43 * .transceiver_enable = NULL,
46 * static struct spi_board_info spi_board_info[] = {
48 * .modalias = "mcp251x",
49 * .platform_data = &mcp251x_info,
51 * .max_speed_hz = 2*1000*1000,
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
61 #include <linux/can.h>
62 #include <linux/can/core.h>
63 #include <linux/can/dev.h>
64 #include <linux/can/platform/mcp251x.h>
65 #include <linux/completion.h>
66 #include <linux/delay.h>
67 #include <linux/device.h>
68 #include <linux/dma-mapping.h>
69 #include <linux/freezer.h>
70 #include <linux/interrupt.h>
72 #include <linux/kernel.h>
73 #include <linux/module.h>
74 #include <linux/netdevice.h>
75 #include <linux/platform_device.h>
76 #include <linux/slab.h>
77 #include <linux/spi/spi.h>
78 #include <linux/uaccess.h>
80 /* SPI interface instruction set */
81 #define INSTRUCTION_WRITE 0x02
82 #define INSTRUCTION_READ 0x03
83 #define INSTRUCTION_BIT_MODIFY 0x05
84 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
85 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
86 #define INSTRUCTION_RESET 0xC0
88 /* MPC251x registers */
91 # define CANCTRL_REQOP_MASK 0xe0
92 # define CANCTRL_REQOP_CONF 0x80
93 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
94 # define CANCTRL_REQOP_LOOPBACK 0x40
95 # define CANCTRL_REQOP_SLEEP 0x20
96 # define CANCTRL_REQOP_NORMAL 0x00
97 # define CANCTRL_OSM 0x08
98 # define CANCTRL_ABAT 0x10
102 # define CNF1_SJW_SHIFT 6
104 # define CNF2_BTLMODE 0x80
105 # define CNF2_SAM 0x40
106 # define CNF2_PS1_SHIFT 3
108 # define CNF3_SOF 0x08
109 # define CNF3_WAKFIL 0x04
110 # define CNF3_PHSEG2_MASK 0x07
112 # define CANINTE_MERRE 0x80
113 # define CANINTE_WAKIE 0x40
114 # define CANINTE_ERRIE 0x20
115 # define CANINTE_TX2IE 0x10
116 # define CANINTE_TX1IE 0x08
117 # define CANINTE_TX0IE 0x04
118 # define CANINTE_RX1IE 0x02
119 # define CANINTE_RX0IE 0x01
121 # define CANINTF_MERRF 0x80
122 # define CANINTF_WAKIF 0x40
123 # define CANINTF_ERRIF 0x20
124 # define CANINTF_TX2IF 0x10
125 # define CANINTF_TX1IF 0x08
126 # define CANINTF_TX0IF 0x04
127 # define CANINTF_RX1IF 0x02
128 # define CANINTF_RX0IF 0x01
130 # define EFLG_EWARN 0x01
131 # define EFLG_RXWAR 0x02
132 # define EFLG_TXWAR 0x04
133 # define EFLG_RXEP 0x08
134 # define EFLG_TXEP 0x10
135 # define EFLG_TXBO 0x20
136 # define EFLG_RX0OVR 0x40
137 # define EFLG_RX1OVR 0x80
138 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
139 # define TXBCTRL_ABTF 0x40
140 # define TXBCTRL_MLOA 0x20
141 # define TXBCTRL_TXERR 0x10
142 # define TXBCTRL_TXREQ 0x08
143 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
144 # define SIDH_SHIFT 3
145 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
146 # define SIDL_SID_MASK 7
147 # define SIDL_SID_SHIFT 5
148 # define SIDL_EXIDE_SHIFT 3
149 # define SIDL_EID_SHIFT 16
150 # define SIDL_EID_MASK 3
151 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
152 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
153 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
154 # define DLC_RTR_SHIFT 6
155 #define TXBCTRL_OFF 0
156 #define TXBSIDH_OFF 1
157 #define TXBSIDL_OFF 2
158 #define TXBEID8_OFF 3
159 #define TXBEID0_OFF 4
162 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
163 # define RXBCTRL_BUKT 0x04
164 # define RXBCTRL_RXM0 0x20
165 # define RXBCTRL_RXM1 0x40
166 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
167 # define RXBSIDH_SHIFT 3
168 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
169 # define RXBSIDL_IDE 0x08
170 # define RXBSIDL_EID 3
171 # define RXBSIDL_SHIFT 5
172 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
173 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
174 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
175 # define RXBDLC_LEN_MASK 0x0f
176 # define RXBDLC_RTR 0x40
177 #define RXBCTRL_OFF 0
178 #define RXBSIDH_OFF 1
179 #define RXBSIDL_OFF 2
180 #define RXBEID8_OFF 3
181 #define RXBEID0_OFF 4
184 #define RXFSIDH(n) ((n) * 4)
185 #define RXFSIDL(n) ((n) * 4 + 1)
186 #define RXFEID8(n) ((n) * 4 + 2)
187 #define RXFEID0(n) ((n) * 4 + 3)
188 #define RXMSIDH(n) ((n) * 4 + 0x20)
189 #define RXMSIDL(n) ((n) * 4 + 0x21)
190 #define RXMEID8(n) ((n) * 4 + 0x22)
191 #define RXMEID0(n) ((n) * 4 + 0x23)
193 #define GET_BYTE(val, byte) \
194 (((val) >> ((byte) * 8)) & 0xff)
195 #define SET_BYTE(val, byte) \
196 (((val) & 0xff) << ((byte) * 8))
199 * Buffer size required for the largest SPI transfer (i.e., reading a
202 #define CAN_FRAME_MAX_DATA_LEN 8
203 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
204 #define CAN_FRAME_MAX_BITS 128
206 #define TX_ECHO_SKB_MAX 1
208 #define DEVICE_NAME "mcp251x"
210 static int mcp251x_enable_dma
; /* Enable SPI DMA. Default: 0 (Off) */
211 module_param(mcp251x_enable_dma
, int, S_IRUGO
);
212 MODULE_PARM_DESC(mcp251x_enable_dma
, "Enable SPI DMA. Default: 0 (Off)");
214 static struct can_bittiming_const mcp251x_bittiming_const
= {
226 struct mcp251x_priv
{
228 struct net_device
*net
;
229 struct spi_device
*spi
;
231 struct mutex mcp_lock
; /* SPI device lock */
235 dma_addr_t spi_tx_dma
;
236 dma_addr_t spi_rx_dma
;
238 struct sk_buff
*tx_skb
;
241 struct workqueue_struct
*wq
;
242 struct work_struct tx_work
;
243 struct work_struct restart_work
;
247 #define AFTER_SUSPEND_UP 1
248 #define AFTER_SUSPEND_DOWN 2
249 #define AFTER_SUSPEND_POWER 4
250 #define AFTER_SUSPEND_RESTART 8
254 static void mcp251x_clean(struct net_device
*net
)
256 struct mcp251x_priv
*priv
= netdev_priv(net
);
258 if (priv
->tx_skb
|| priv
->tx_len
)
259 net
->stats
.tx_errors
++;
261 dev_kfree_skb(priv
->tx_skb
);
263 can_free_echo_skb(priv
->net
, 0);
269 * Note about handling of error return of mcp251x_spi_trans: accessing
270 * registers via SPI is not really different conceptually than using
271 * normal I/O assembler instructions, although it's much more
272 * complicated from a practical POV. So it's not advisable to always
273 * check the return value of this function. Imagine that every
274 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
275 * error();", it would be a great mess (well there are some situation
276 * when exception handling C++ like could be useful after all). So we
277 * just check that transfers are OK at the beginning of our
278 * conversation with the chip and to avoid doing really nasty things
279 * (like injecting bogus packets in the network stack).
281 static int mcp251x_spi_trans(struct spi_device
*spi
, int len
)
283 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
284 struct spi_transfer t
= {
285 .tx_buf
= priv
->spi_tx_buf
,
286 .rx_buf
= priv
->spi_rx_buf
,
290 struct spi_message m
;
293 spi_message_init(&m
);
295 if (mcp251x_enable_dma
) {
296 t
.tx_dma
= priv
->spi_tx_dma
;
297 t
.rx_dma
= priv
->spi_rx_dma
;
301 spi_message_add_tail(&t
, &m
);
303 ret
= spi_sync(spi
, &m
);
305 dev_err(&spi
->dev
, "spi transfer failed: ret = %d\n", ret
);
309 static u8
mcp251x_read_reg(struct spi_device
*spi
, uint8_t reg
)
311 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
314 priv
->spi_tx_buf
[0] = INSTRUCTION_READ
;
315 priv
->spi_tx_buf
[1] = reg
;
317 mcp251x_spi_trans(spi
, 3);
318 val
= priv
->spi_rx_buf
[2];
323 static void mcp251x_write_reg(struct spi_device
*spi
, u8 reg
, uint8_t val
)
325 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
327 priv
->spi_tx_buf
[0] = INSTRUCTION_WRITE
;
328 priv
->spi_tx_buf
[1] = reg
;
329 priv
->spi_tx_buf
[2] = val
;
331 mcp251x_spi_trans(spi
, 3);
334 static void mcp251x_write_bits(struct spi_device
*spi
, u8 reg
,
335 u8 mask
, uint8_t val
)
337 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
339 priv
->spi_tx_buf
[0] = INSTRUCTION_BIT_MODIFY
;
340 priv
->spi_tx_buf
[1] = reg
;
341 priv
->spi_tx_buf
[2] = mask
;
342 priv
->spi_tx_buf
[3] = val
;
344 mcp251x_spi_trans(spi
, 4);
347 static void mcp251x_hw_tx_frame(struct spi_device
*spi
, u8
*buf
,
348 int len
, int tx_buf_idx
)
350 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
351 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
353 if (pdata
->model
== CAN_MCP251X_MCP2510
) {
356 for (i
= 1; i
< TXBDAT_OFF
+ len
; i
++)
357 mcp251x_write_reg(spi
, TXBCTRL(tx_buf_idx
) + i
,
360 memcpy(priv
->spi_tx_buf
, buf
, TXBDAT_OFF
+ len
);
361 mcp251x_spi_trans(spi
, TXBDAT_OFF
+ len
);
365 static void mcp251x_hw_tx(struct spi_device
*spi
, struct can_frame
*frame
,
368 u32 sid
, eid
, exide
, rtr
;
369 u8 buf
[SPI_TRANSFER_BUF_LEN
];
371 exide
= (frame
->can_id
& CAN_EFF_FLAG
) ? 1 : 0; /* Extended ID Enable */
373 sid
= (frame
->can_id
& CAN_EFF_MASK
) >> 18;
375 sid
= frame
->can_id
& CAN_SFF_MASK
; /* Standard ID */
376 eid
= frame
->can_id
& CAN_EFF_MASK
; /* Extended ID */
377 rtr
= (frame
->can_id
& CAN_RTR_FLAG
) ? 1 : 0; /* Remote transmission */
379 buf
[TXBCTRL_OFF
] = INSTRUCTION_LOAD_TXB(tx_buf_idx
);
380 buf
[TXBSIDH_OFF
] = sid
>> SIDH_SHIFT
;
381 buf
[TXBSIDL_OFF
] = ((sid
& SIDL_SID_MASK
) << SIDL_SID_SHIFT
) |
382 (exide
<< SIDL_EXIDE_SHIFT
) |
383 ((eid
>> SIDL_EID_SHIFT
) & SIDL_EID_MASK
);
384 buf
[TXBEID8_OFF
] = GET_BYTE(eid
, 1);
385 buf
[TXBEID0_OFF
] = GET_BYTE(eid
, 0);
386 buf
[TXBDLC_OFF
] = (rtr
<< DLC_RTR_SHIFT
) | frame
->can_dlc
;
387 memcpy(buf
+ TXBDAT_OFF
, frame
->data
, frame
->can_dlc
);
388 mcp251x_hw_tx_frame(spi
, buf
, frame
->can_dlc
, tx_buf_idx
);
389 mcp251x_write_reg(spi
, TXBCTRL(tx_buf_idx
), TXBCTRL_TXREQ
);
392 static void mcp251x_hw_rx_frame(struct spi_device
*spi
, u8
*buf
,
395 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
396 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
398 if (pdata
->model
== CAN_MCP251X_MCP2510
) {
401 for (i
= 1; i
< RXBDAT_OFF
; i
++)
402 buf
[i
] = mcp251x_read_reg(spi
, RXBCTRL(buf_idx
) + i
);
404 len
= get_can_dlc(buf
[RXBDLC_OFF
] & RXBDLC_LEN_MASK
);
405 for (; i
< (RXBDAT_OFF
+ len
); i
++)
406 buf
[i
] = mcp251x_read_reg(spi
, RXBCTRL(buf_idx
) + i
);
408 priv
->spi_tx_buf
[RXBCTRL_OFF
] = INSTRUCTION_READ_RXB(buf_idx
);
409 mcp251x_spi_trans(spi
, SPI_TRANSFER_BUF_LEN
);
410 memcpy(buf
, priv
->spi_rx_buf
, SPI_TRANSFER_BUF_LEN
);
414 static void mcp251x_hw_rx(struct spi_device
*spi
, int buf_idx
)
416 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
418 struct can_frame
*frame
;
419 u8 buf
[SPI_TRANSFER_BUF_LEN
];
421 skb
= alloc_can_skb(priv
->net
, &frame
);
423 dev_err(&spi
->dev
, "cannot allocate RX skb\n");
424 priv
->net
->stats
.rx_dropped
++;
428 mcp251x_hw_rx_frame(spi
, buf
, buf_idx
);
429 if (buf
[RXBSIDL_OFF
] & RXBSIDL_IDE
) {
430 /* Extended ID format */
431 frame
->can_id
= CAN_EFF_FLAG
;
433 /* Extended ID part */
434 SET_BYTE(buf
[RXBSIDL_OFF
] & RXBSIDL_EID
, 2) |
435 SET_BYTE(buf
[RXBEID8_OFF
], 1) |
436 SET_BYTE(buf
[RXBEID0_OFF
], 0) |
437 /* Standard ID part */
438 (((buf
[RXBSIDH_OFF
] << RXBSIDH_SHIFT
) |
439 (buf
[RXBSIDL_OFF
] >> RXBSIDL_SHIFT
)) << 18);
440 /* Remote transmission request */
441 if (buf
[RXBDLC_OFF
] & RXBDLC_RTR
)
442 frame
->can_id
|= CAN_RTR_FLAG
;
444 /* Standard ID format */
446 (buf
[RXBSIDH_OFF
] << RXBSIDH_SHIFT
) |
447 (buf
[RXBSIDL_OFF
] >> RXBSIDL_SHIFT
);
450 frame
->can_dlc
= get_can_dlc(buf
[RXBDLC_OFF
] & RXBDLC_LEN_MASK
);
451 memcpy(frame
->data
, buf
+ RXBDAT_OFF
, frame
->can_dlc
);
453 priv
->net
->stats
.rx_packets
++;
454 priv
->net
->stats
.rx_bytes
+= frame
->can_dlc
;
458 static void mcp251x_hw_sleep(struct spi_device
*spi
)
460 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_SLEEP
);
463 static netdev_tx_t
mcp251x_hard_start_xmit(struct sk_buff
*skb
,
464 struct net_device
*net
)
466 struct mcp251x_priv
*priv
= netdev_priv(net
);
467 struct spi_device
*spi
= priv
->spi
;
469 if (priv
->tx_skb
|| priv
->tx_len
) {
470 dev_warn(&spi
->dev
, "hard_xmit called while tx busy\n");
471 return NETDEV_TX_BUSY
;
474 if (can_dropped_invalid_skb(net
, skb
))
477 netif_stop_queue(net
);
479 net
->trans_start
= jiffies
;
480 queue_work(priv
->wq
, &priv
->tx_work
);
485 static int mcp251x_do_set_mode(struct net_device
*net
, enum can_mode mode
)
487 struct mcp251x_priv
*priv
= netdev_priv(net
);
492 /* We have to delay work since SPI I/O may sleep */
493 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
494 priv
->restart_tx
= 1;
495 if (priv
->can
.restart_ms
== 0)
496 priv
->after_suspend
= AFTER_SUSPEND_RESTART
;
497 queue_work(priv
->wq
, &priv
->restart_work
);
506 static int mcp251x_set_normal_mode(struct spi_device
*spi
)
508 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
509 unsigned long timeout
;
511 /* Enable interrupts */
512 mcp251x_write_reg(spi
, CANINTE
,
513 CANINTE_ERRIE
| CANINTE_TX2IE
| CANINTE_TX1IE
|
514 CANINTE_TX0IE
| CANINTE_RX1IE
| CANINTE_RX0IE
);
516 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
) {
517 /* Put device into loopback mode */
518 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_LOOPBACK
);
519 } else if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
) {
520 /* Put device into listen-only mode */
521 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_LISTEN_ONLY
);
523 /* Put device into normal mode */
524 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_NORMAL
);
526 /* Wait for the device to enter normal mode */
527 timeout
= jiffies
+ HZ
;
528 while (mcp251x_read_reg(spi
, CANSTAT
) & CANCTRL_REQOP_MASK
) {
530 if (time_after(jiffies
, timeout
)) {
531 dev_err(&spi
->dev
, "MCP251x didn't"
532 " enter in normal mode\n");
537 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
541 static int mcp251x_do_set_bittiming(struct net_device
*net
)
543 struct mcp251x_priv
*priv
= netdev_priv(net
);
544 struct can_bittiming
*bt
= &priv
->can
.bittiming
;
545 struct spi_device
*spi
= priv
->spi
;
547 mcp251x_write_reg(spi
, CNF1
, ((bt
->sjw
- 1) << CNF1_SJW_SHIFT
) |
549 mcp251x_write_reg(spi
, CNF2
, CNF2_BTLMODE
|
550 (priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
?
552 ((bt
->phase_seg1
- 1) << CNF2_PS1_SHIFT
) |
554 mcp251x_write_bits(spi
, CNF3
, CNF3_PHSEG2_MASK
,
555 (bt
->phase_seg2
- 1));
556 dev_info(&spi
->dev
, "CNF: 0x%02x 0x%02x 0x%02x\n",
557 mcp251x_read_reg(spi
, CNF1
),
558 mcp251x_read_reg(spi
, CNF2
),
559 mcp251x_read_reg(spi
, CNF3
));
564 static int mcp251x_setup(struct net_device
*net
, struct mcp251x_priv
*priv
,
565 struct spi_device
*spi
)
567 mcp251x_do_set_bittiming(net
);
569 mcp251x_write_reg(spi
, RXBCTRL(0),
570 RXBCTRL_BUKT
| RXBCTRL_RXM0
| RXBCTRL_RXM1
);
571 mcp251x_write_reg(spi
, RXBCTRL(1),
572 RXBCTRL_RXM0
| RXBCTRL_RXM1
);
576 static int mcp251x_hw_reset(struct spi_device
*spi
)
578 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
580 unsigned long timeout
;
582 priv
->spi_tx_buf
[0] = INSTRUCTION_RESET
;
583 ret
= spi_write(spi
, priv
->spi_tx_buf
, 1);
585 dev_err(&spi
->dev
, "reset failed: ret = %d\n", ret
);
589 /* Wait for reset to finish */
590 timeout
= jiffies
+ HZ
;
592 while ((mcp251x_read_reg(spi
, CANSTAT
) & CANCTRL_REQOP_MASK
)
593 != CANCTRL_REQOP_CONF
) {
595 if (time_after(jiffies
, timeout
)) {
596 dev_err(&spi
->dev
, "MCP251x didn't"
597 " enter in conf mode after reset\n");
604 static int mcp251x_hw_probe(struct spi_device
*spi
)
608 mcp251x_hw_reset(spi
);
611 * Please note that these are "magic values" based on after
612 * reset defaults taken from data sheet which allows us to see
613 * if we really have a chip on the bus (we avoid common all
614 * zeroes or all ones situations)
616 st1
= mcp251x_read_reg(spi
, CANSTAT
) & 0xEE;
617 st2
= mcp251x_read_reg(spi
, CANCTRL
) & 0x17;
619 dev_dbg(&spi
->dev
, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1
, st2
);
621 /* Check for power up default values */
622 return (st1
== 0x80 && st2
== 0x07) ? 1 : 0;
625 static void mcp251x_open_clean(struct net_device
*net
)
627 struct mcp251x_priv
*priv
= netdev_priv(net
);
628 struct spi_device
*spi
= priv
->spi
;
629 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
631 free_irq(spi
->irq
, priv
);
632 mcp251x_hw_sleep(spi
);
633 if (pdata
->transceiver_enable
)
634 pdata
->transceiver_enable(0);
638 static int mcp251x_stop(struct net_device
*net
)
640 struct mcp251x_priv
*priv
= netdev_priv(net
);
641 struct spi_device
*spi
= priv
->spi
;
642 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
646 priv
->force_quit
= 1;
647 free_irq(spi
->irq
, priv
);
648 destroy_workqueue(priv
->wq
);
651 mutex_lock(&priv
->mcp_lock
);
653 /* Disable and clear pending interrupts */
654 mcp251x_write_reg(spi
, CANINTE
, 0x00);
655 mcp251x_write_reg(spi
, CANINTF
, 0x00);
657 mcp251x_write_reg(spi
, TXBCTRL(0), 0);
660 mcp251x_hw_sleep(spi
);
662 if (pdata
->transceiver_enable
)
663 pdata
->transceiver_enable(0);
665 priv
->can
.state
= CAN_STATE_STOPPED
;
667 mutex_unlock(&priv
->mcp_lock
);
672 static void mcp251x_error_skb(struct net_device
*net
, int can_id
, int data1
)
675 struct can_frame
*frame
;
677 skb
= alloc_can_err_skb(net
, &frame
);
679 frame
->can_id
= can_id
;
680 frame
->data
[1] = data1
;
684 "cannot allocate error skb\n");
688 static void mcp251x_tx_work_handler(struct work_struct
*ws
)
690 struct mcp251x_priv
*priv
= container_of(ws
, struct mcp251x_priv
,
692 struct spi_device
*spi
= priv
->spi
;
693 struct net_device
*net
= priv
->net
;
694 struct can_frame
*frame
;
696 mutex_lock(&priv
->mcp_lock
);
698 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
701 frame
= (struct can_frame
*)priv
->tx_skb
->data
;
703 if (frame
->can_dlc
> CAN_FRAME_MAX_DATA_LEN
)
704 frame
->can_dlc
= CAN_FRAME_MAX_DATA_LEN
;
705 mcp251x_hw_tx(spi
, frame
, 0);
706 priv
->tx_len
= 1 + frame
->can_dlc
;
707 can_put_echo_skb(priv
->tx_skb
, net
, 0);
711 mutex_unlock(&priv
->mcp_lock
);
714 static void mcp251x_restart_work_handler(struct work_struct
*ws
)
716 struct mcp251x_priv
*priv
= container_of(ws
, struct mcp251x_priv
,
718 struct spi_device
*spi
= priv
->spi
;
719 struct net_device
*net
= priv
->net
;
721 mutex_lock(&priv
->mcp_lock
);
722 if (priv
->after_suspend
) {
724 mcp251x_hw_reset(spi
);
725 mcp251x_setup(net
, priv
, spi
);
726 if (priv
->after_suspend
& AFTER_SUSPEND_RESTART
) {
727 mcp251x_set_normal_mode(spi
);
728 } else if (priv
->after_suspend
& AFTER_SUSPEND_UP
) {
729 netif_device_attach(net
);
731 mcp251x_set_normal_mode(spi
);
732 netif_wake_queue(net
);
734 mcp251x_hw_sleep(spi
);
736 priv
->after_suspend
= 0;
737 priv
->force_quit
= 0;
740 if (priv
->restart_tx
) {
741 priv
->restart_tx
= 0;
742 mcp251x_write_reg(spi
, TXBCTRL(0), 0);
744 netif_wake_queue(net
);
745 mcp251x_error_skb(net
, CAN_ERR_RESTARTED
, 0);
747 mutex_unlock(&priv
->mcp_lock
);
750 static irqreturn_t
mcp251x_can_ist(int irq
, void *dev_id
)
752 struct mcp251x_priv
*priv
= dev_id
;
753 struct spi_device
*spi
= priv
->spi
;
754 struct net_device
*net
= priv
->net
;
756 mutex_lock(&priv
->mcp_lock
);
757 while (!priv
->force_quit
) {
758 enum can_state new_state
;
759 u8 intf
= mcp251x_read_reg(spi
, CANINTF
);
761 int can_id
= 0, data1
= 0;
763 if (intf
& CANINTF_RX0IF
) {
764 mcp251x_hw_rx(spi
, 0);
765 /* Free one buffer ASAP */
766 mcp251x_write_bits(spi
, CANINTF
, intf
& CANINTF_RX0IF
,
770 if (intf
& CANINTF_RX1IF
)
771 mcp251x_hw_rx(spi
, 1);
773 mcp251x_write_bits(spi
, CANINTF
, intf
, 0x00);
775 eflag
= mcp251x_read_reg(spi
, EFLG
);
776 mcp251x_write_reg(spi
, EFLG
, 0x00);
778 /* Update can state */
779 if (eflag
& EFLG_TXBO
) {
780 new_state
= CAN_STATE_BUS_OFF
;
781 can_id
|= CAN_ERR_BUSOFF
;
782 } else if (eflag
& EFLG_TXEP
) {
783 new_state
= CAN_STATE_ERROR_PASSIVE
;
784 can_id
|= CAN_ERR_CRTL
;
785 data1
|= CAN_ERR_CRTL_TX_PASSIVE
;
786 } else if (eflag
& EFLG_RXEP
) {
787 new_state
= CAN_STATE_ERROR_PASSIVE
;
788 can_id
|= CAN_ERR_CRTL
;
789 data1
|= CAN_ERR_CRTL_RX_PASSIVE
;
790 } else if (eflag
& EFLG_TXWAR
) {
791 new_state
= CAN_STATE_ERROR_WARNING
;
792 can_id
|= CAN_ERR_CRTL
;
793 data1
|= CAN_ERR_CRTL_TX_WARNING
;
794 } else if (eflag
& EFLG_RXWAR
) {
795 new_state
= CAN_STATE_ERROR_WARNING
;
796 can_id
|= CAN_ERR_CRTL
;
797 data1
|= CAN_ERR_CRTL_RX_WARNING
;
799 new_state
= CAN_STATE_ERROR_ACTIVE
;
802 /* Update can state statistics */
803 switch (priv
->can
.state
) {
804 case CAN_STATE_ERROR_ACTIVE
:
805 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
806 new_state
<= CAN_STATE_BUS_OFF
)
807 priv
->can
.can_stats
.error_warning
++;
808 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
809 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
810 new_state
<= CAN_STATE_BUS_OFF
)
811 priv
->can
.can_stats
.error_passive
++;
816 priv
->can
.state
= new_state
;
818 if (intf
& CANINTF_ERRIF
) {
819 /* Handle overflow counters */
820 if (eflag
& (EFLG_RX0OVR
| EFLG_RX1OVR
)) {
821 if (eflag
& EFLG_RX0OVR
)
822 net
->stats
.rx_over_errors
++;
823 if (eflag
& EFLG_RX1OVR
)
824 net
->stats
.rx_over_errors
++;
825 can_id
|= CAN_ERR_CRTL
;
826 data1
|= CAN_ERR_CRTL_RX_OVERFLOW
;
828 mcp251x_error_skb(net
, can_id
, data1
);
831 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
832 if (priv
->can
.restart_ms
== 0) {
833 priv
->force_quit
= 1;
835 mcp251x_hw_sleep(spi
);
843 if (intf
& (CANINTF_TX2IF
| CANINTF_TX1IF
| CANINTF_TX0IF
)) {
844 net
->stats
.tx_packets
++;
845 net
->stats
.tx_bytes
+= priv
->tx_len
- 1;
847 can_get_echo_skb(net
, 0);
850 netif_wake_queue(net
);
854 mutex_unlock(&priv
->mcp_lock
);
858 static int mcp251x_open(struct net_device
*net
)
860 struct mcp251x_priv
*priv
= netdev_priv(net
);
861 struct spi_device
*spi
= priv
->spi
;
862 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
865 ret
= open_candev(net
);
867 dev_err(&spi
->dev
, "unable to set initial baudrate!\n");
871 mutex_lock(&priv
->mcp_lock
);
872 if (pdata
->transceiver_enable
)
873 pdata
->transceiver_enable(1);
875 priv
->force_quit
= 0;
879 ret
= request_threaded_irq(spi
->irq
, NULL
, mcp251x_can_ist
,
880 IRQF_TRIGGER_FALLING
, DEVICE_NAME
, priv
);
882 dev_err(&spi
->dev
, "failed to acquire irq %d\n", spi
->irq
);
883 if (pdata
->transceiver_enable
)
884 pdata
->transceiver_enable(0);
889 priv
->wq
= create_freezeable_workqueue("mcp251x_wq");
890 INIT_WORK(&priv
->tx_work
, mcp251x_tx_work_handler
);
891 INIT_WORK(&priv
->restart_work
, mcp251x_restart_work_handler
);
893 ret
= mcp251x_hw_reset(spi
);
895 mcp251x_open_clean(net
);
898 ret
= mcp251x_setup(net
, priv
, spi
);
900 mcp251x_open_clean(net
);
903 ret
= mcp251x_set_normal_mode(spi
);
905 mcp251x_open_clean(net
);
908 netif_wake_queue(net
);
911 mutex_unlock(&priv
->mcp_lock
);
915 static const struct net_device_ops mcp251x_netdev_ops
= {
916 .ndo_open
= mcp251x_open
,
917 .ndo_stop
= mcp251x_stop
,
918 .ndo_start_xmit
= mcp251x_hard_start_xmit
,
921 static int __devinit
mcp251x_can_probe(struct spi_device
*spi
)
923 struct net_device
*net
;
924 struct mcp251x_priv
*priv
;
925 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
929 /* Platform data is required for osc freq */
932 /* Allocate can/net device */
933 net
= alloc_candev(sizeof(struct mcp251x_priv
), TX_ECHO_SKB_MAX
);
939 net
->netdev_ops
= &mcp251x_netdev_ops
;
940 net
->flags
|= IFF_ECHO
;
942 priv
= netdev_priv(net
);
943 priv
->can
.bittiming_const
= &mcp251x_bittiming_const
;
944 priv
->can
.do_set_mode
= mcp251x_do_set_mode
;
945 priv
->can
.clock
.freq
= pdata
->oscillator_frequency
/ 2;
946 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
|
947 CAN_CTRLMODE_LOOPBACK
| CAN_CTRLMODE_LISTENONLY
;
949 dev_set_drvdata(&spi
->dev
, priv
);
952 mutex_init(&priv
->mcp_lock
);
954 /* If requested, allocate DMA buffers */
955 if (mcp251x_enable_dma
) {
956 spi
->dev
.coherent_dma_mask
= ~0;
959 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
960 * that much and share it between Tx and Rx DMA buffers.
962 priv
->spi_tx_buf
= dma_alloc_coherent(&spi
->dev
,
967 if (priv
->spi_tx_buf
) {
968 priv
->spi_rx_buf
= (u8
*)(priv
->spi_tx_buf
+
970 priv
->spi_rx_dma
= (dma_addr_t
)(priv
->spi_tx_dma
+
973 /* Fall back to non-DMA */
974 mcp251x_enable_dma
= 0;
978 /* Allocate non-DMA buffers */
979 if (!mcp251x_enable_dma
) {
980 priv
->spi_tx_buf
= kmalloc(SPI_TRANSFER_BUF_LEN
, GFP_KERNEL
);
981 if (!priv
->spi_tx_buf
) {
985 priv
->spi_rx_buf
= kmalloc(SPI_TRANSFER_BUF_LEN
, GFP_KERNEL
);
986 if (!priv
->spi_rx_buf
) {
992 if (pdata
->power_enable
)
993 pdata
->power_enable(1);
995 /* Call out to platform specific setup */
996 if (pdata
->board_specific_setup
)
997 pdata
->board_specific_setup(spi
);
999 SET_NETDEV_DEV(net
, &spi
->dev
);
1001 /* Configure the SPI bus */
1002 spi
->mode
= SPI_MODE_0
;
1003 spi
->bits_per_word
= 8;
1006 /* Here is OK to not lock the MCP, no one knows about it yet */
1007 if (!mcp251x_hw_probe(spi
)) {
1008 dev_info(&spi
->dev
, "Probe failed\n");
1011 mcp251x_hw_sleep(spi
);
1013 if (pdata
->transceiver_enable
)
1014 pdata
->transceiver_enable(0);
1016 ret
= register_candev(net
);
1018 dev_info(&spi
->dev
, "probed\n");
1022 if (!mcp251x_enable_dma
)
1023 kfree(priv
->spi_rx_buf
);
1025 if (!mcp251x_enable_dma
)
1026 kfree(priv
->spi_tx_buf
);
1029 if (mcp251x_enable_dma
)
1030 dma_free_coherent(&spi
->dev
, PAGE_SIZE
,
1031 priv
->spi_tx_buf
, priv
->spi_tx_dma
);
1033 if (pdata
->power_enable
)
1034 pdata
->power_enable(0);
1035 dev_err(&spi
->dev
, "probe failed\n");
1040 static int __devexit
mcp251x_can_remove(struct spi_device
*spi
)
1042 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1043 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1044 struct net_device
*net
= priv
->net
;
1046 unregister_candev(net
);
1049 if (mcp251x_enable_dma
) {
1050 dma_free_coherent(&spi
->dev
, PAGE_SIZE
,
1051 priv
->spi_tx_buf
, priv
->spi_tx_dma
);
1053 kfree(priv
->spi_tx_buf
);
1054 kfree(priv
->spi_rx_buf
);
1057 if (pdata
->power_enable
)
1058 pdata
->power_enable(0);
1064 static int mcp251x_can_suspend(struct spi_device
*spi
, pm_message_t state
)
1066 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1067 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1068 struct net_device
*net
= priv
->net
;
1070 priv
->force_quit
= 1;
1071 disable_irq(spi
->irq
);
1073 * Note: at this point neither IST nor workqueues are running.
1074 * open/stop cannot be called anyway so locking is not needed
1076 if (netif_running(net
)) {
1077 netif_device_detach(net
);
1079 mcp251x_hw_sleep(spi
);
1080 if (pdata
->transceiver_enable
)
1081 pdata
->transceiver_enable(0);
1082 priv
->after_suspend
= AFTER_SUSPEND_UP
;
1084 priv
->after_suspend
= AFTER_SUSPEND_DOWN
;
1087 if (pdata
->power_enable
) {
1088 pdata
->power_enable(0);
1089 priv
->after_suspend
|= AFTER_SUSPEND_POWER
;
1095 static int mcp251x_can_resume(struct spi_device
*spi
)
1097 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1098 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1100 if (priv
->after_suspend
& AFTER_SUSPEND_POWER
) {
1101 pdata
->power_enable(1);
1102 queue_work(priv
->wq
, &priv
->restart_work
);
1104 if (priv
->after_suspend
& AFTER_SUSPEND_UP
) {
1105 if (pdata
->transceiver_enable
)
1106 pdata
->transceiver_enable(1);
1107 queue_work(priv
->wq
, &priv
->restart_work
);
1109 priv
->after_suspend
= 0;
1112 priv
->force_quit
= 0;
1113 enable_irq(spi
->irq
);
1117 #define mcp251x_can_suspend NULL
1118 #define mcp251x_can_resume NULL
1121 static struct spi_driver mcp251x_can_driver
= {
1123 .name
= DEVICE_NAME
,
1124 .bus
= &spi_bus_type
,
1125 .owner
= THIS_MODULE
,
1128 .probe
= mcp251x_can_probe
,
1129 .remove
= __devexit_p(mcp251x_can_remove
),
1130 .suspend
= mcp251x_can_suspend
,
1131 .resume
= mcp251x_can_resume
,
1134 static int __init
mcp251x_can_init(void)
1136 return spi_register_driver(&mcp251x_can_driver
);
1139 static void __exit
mcp251x_can_exit(void)
1141 spi_unregister_driver(&mcp251x_can_driver
);
1144 module_init(mcp251x_can_init
);
1145 module_exit(mcp251x_can_exit
);
1147 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1148 "Christian Pellegrin <chripell@evolware.org>");
1149 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1150 MODULE_LICENSE("GPL v2");