2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
22 #include <linux/module.h>
23 #include <linux/sched.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/errno.h>
29 #include <linux/netdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/can.h>
32 #include <linux/can/dev.h>
33 #include <linux/can/error.h>
35 #define MAX_MSG_OBJ 32
36 #define MSG_OBJ_RX 0 /* The receive message object flag. */
37 #define MSG_OBJ_TX 1 /* The transmit message object flag. */
39 #define ENABLE 1 /* The enable flag */
40 #define DISABLE 0 /* The disable flag */
41 #define CAN_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
42 #define CAN_CTRL_IE 0x0002 /* The IE bit of CAN control register */
43 #define CAN_CTRL_IE_SIE_EIE 0x000e
44 #define CAN_CTRL_CCE 0x0040
45 #define CAN_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
46 #define CAN_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
47 #define CAN_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
48 #define CAN_CMASK_RX_TX_SET 0x00f3
49 #define CAN_CMASK_RX_TX_GET 0x0073
50 #define CAN_CMASK_ALL 0xff
51 #define CAN_CMASK_RDWR 0x80
52 #define CAN_CMASK_ARB 0x20
53 #define CAN_CMASK_CTRL 0x10
54 #define CAN_CMASK_MASK 0x40
55 #define CAN_CMASK_NEWDAT 0x04
56 #define CAN_CMASK_CLRINTPND 0x08
58 #define CAN_IF_MCONT_NEWDAT 0x8000
59 #define CAN_IF_MCONT_INTPND 0x2000
60 #define CAN_IF_MCONT_UMASK 0x1000
61 #define CAN_IF_MCONT_TXIE 0x0800
62 #define CAN_IF_MCONT_RXIE 0x0400
63 #define CAN_IF_MCONT_RMTEN 0x0200
64 #define CAN_IF_MCONT_TXRQXT 0x0100
65 #define CAN_IF_MCONT_EOB 0x0080
66 #define CAN_IF_MCONT_DLC 0x000f
67 #define CAN_IF_MCONT_MSGLOST 0x4000
68 #define CAN_MASK2_MDIR_MXTD 0xc000
69 #define CAN_ID2_DIR 0x2000
70 #define CAN_ID_MSGVAL 0x8000
72 #define CAN_STATUS_INT 0x8000
73 #define CAN_IF_CREQ_BUSY 0x8000
74 #define CAN_ID2_XTD 0x4000
76 #define CAN_REC 0x00007f00
77 #define CAN_TEC 0x000000ff
79 #define PCH_RX_OK 0x00000010
80 #define PCH_TX_OK 0x00000008
81 #define PCH_BUS_OFF 0x00000080
82 #define PCH_EWARN 0x00000040
83 #define PCH_EPASSIV 0x00000020
84 #define PCH_LEC0 0x00000001
85 #define PCH_LEC1 0x00000002
86 #define PCH_LEC2 0x00000004
87 #define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
88 #define PCH_STUF_ERR PCH_LEC0
89 #define PCH_FORM_ERR PCH_LEC1
90 #define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1)
91 #define PCH_BIT1_ERR PCH_LEC2
92 #define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2)
93 #define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
95 /* bit position of certain controller bits. */
96 #define BIT_BITT_BRP 0
97 #define BIT_BITT_SJW 6
98 #define BIT_BITT_TSEG1 8
99 #define BIT_BITT_TSEG2 12
100 #define BIT_IF1_MCONT_RXIE 10
101 #define BIT_IF2_MCONT_TXIE 11
102 #define BIT_BRPE_BRPE 6
103 #define BIT_ES_TXERRCNT 0
104 #define BIT_ES_RXERRCNT 8
105 #define MSK_BITT_BRP 0x3f
106 #define MSK_BITT_SJW 0xc0
107 #define MSK_BITT_TSEG1 0xf00
108 #define MSK_BITT_TSEG2 0x7000
109 #define MSK_BRPE_BRPE 0x3c0
110 #define MSK_BRPE_GET 0x0f
111 #define MSK_CTRL_IE_SIE_EIE 0x07
112 #define MSK_MCONT_TXIE 0x08
113 #define MSK_MCONT_RXIE 0x10
114 #define PCH_CAN_NO_TX_BUFF 1
115 #define COUNTER_LIMIT 10
117 #define PCH_CAN_CLK 50000000 /* 50MHz */
119 /* Define the number of message object.
120 * PCH CAN communications are done via Message RAM.
121 * The Message RAM consists of 32 message objects. */
122 #define PCH_RX_OBJ_NUM 26 /* 1~ PCH_RX_OBJ_NUM is Rx*/
123 #define PCH_TX_OBJ_NUM 6 /* PCH_RX_OBJ_NUM is RX ~ Tx*/
124 #define PCH_OBJ_NUM (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)
126 #define PCH_FIFO_THRESH 16
137 struct pch_can_regs
{
180 struct pch_can_priv
{
182 unsigned int can_num
;
184 unsigned int tx_enable
[MAX_MSG_OBJ
];
185 unsigned int rx_enable
[MAX_MSG_OBJ
];
186 unsigned int rx_link
[MAX_MSG_OBJ
];
187 unsigned int int_enables
;
188 unsigned int int_stat
;
189 struct net_device
*ndev
;
190 spinlock_t msgif_reg_lock
; /* Message Interface Registers Access Lock*/
191 unsigned int msg_obj
[MAX_MSG_OBJ
];
192 struct pch_can_regs __iomem
*regs
;
193 struct napi_struct napi
;
194 unsigned int tx_obj
; /* Point next Tx Obj index */
195 unsigned int use_msi
;
198 static struct can_bittiming_const pch_can_bittiming_const
= {
199 .name
= KBUILD_MODNAME
,
206 .brp_max
= 1024, /* 6bit + extended 4bit */
210 static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl
) = {
211 {PCI_VENDOR_ID_INTEL
, 0x8818, PCI_ANY_ID
, PCI_ANY_ID
,},
214 MODULE_DEVICE_TABLE(pci
, pch_pci_tbl
);
216 static inline void pch_can_bit_set(u32
*addr
, u32 mask
)
218 iowrite32(ioread32(addr
) | mask
, addr
);
221 static inline void pch_can_bit_clear(u32
*addr
, u32 mask
)
223 iowrite32(ioread32(addr
) & ~mask
, addr
);
226 static void pch_can_set_run_mode(struct pch_can_priv
*priv
,
227 enum pch_can_mode mode
)
231 pch_can_bit_clear(&priv
->regs
->cont
, CAN_CTRL_INIT
);
235 pch_can_bit_set(&priv
->regs
->cont
, CAN_CTRL_INIT
);
239 dev_err(&priv
->ndev
->dev
, "%s -> Invalid Mode.\n", __func__
);
244 static void pch_can_set_optmode(struct pch_can_priv
*priv
)
246 u32 reg_val
= ioread32(&priv
->regs
->opt
);
248 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
)
249 reg_val
|= CAN_OPT_SILENT
;
251 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
)
252 reg_val
|= CAN_OPT_LBACK
;
254 pch_can_bit_set(&priv
->regs
->cont
, CAN_CTRL_OPT
);
255 iowrite32(reg_val
, &priv
->regs
->opt
);
258 static void pch_can_set_int_custom(struct pch_can_priv
*priv
)
260 /* Clearing the IE, SIE and EIE bits of Can control register. */
261 pch_can_bit_clear(&priv
->regs
->cont
, CAN_CTRL_IE_SIE_EIE
);
263 /* Appropriately setting them. */
264 pch_can_bit_set(&priv
->regs
->cont
,
265 ((priv
->int_enables
& MSK_CTRL_IE_SIE_EIE
) << 1));
268 /* This function retrieves interrupt enabled for the CAN device. */
269 static void pch_can_get_int_enables(struct pch_can_priv
*priv
, u32
*enables
)
271 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
272 *enables
= ((ioread32(&priv
->regs
->cont
) & CAN_CTRL_IE_SIE_EIE
) >> 1);
275 static void pch_can_set_int_enables(struct pch_can_priv
*priv
,
276 enum pch_can_mode interrupt_no
)
278 switch (interrupt_no
) {
280 pch_can_bit_set(&priv
->regs
->cont
, CAN_CTRL_IE
);
283 case PCH_CAN_DISABLE
:
284 pch_can_bit_clear(&priv
->regs
->cont
, CAN_CTRL_IE
);
288 pch_can_bit_set(&priv
->regs
->cont
, CAN_CTRL_IE_SIE_EIE
);
292 pch_can_bit_clear(&priv
->regs
->cont
, CAN_CTRL_IE_SIE_EIE
);
296 dev_err(&priv
->ndev
->dev
, "Invalid interrupt number.\n");
301 static void pch_can_check_if_busy(u32 __iomem
*creq_addr
, u32 num
)
303 u32 counter
= COUNTER_LIMIT
;
306 iowrite32(num
, creq_addr
);
308 ifx_creq
= ioread32(creq_addr
) & CAN_IF_CREQ_BUSY
;
315 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__
);
318 static void pch_can_set_rx_enable(struct pch_can_priv
*priv
, u32 buff_num
,
323 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
324 /* Reading the receive buffer data from RAM to Interface1 registers */
325 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if1_cmask
);
326 pch_can_check_if_busy(&priv
->regs
->if1_creq
, buff_num
);
328 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
329 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_ARB
| CAN_CMASK_CTRL
,
330 &priv
->regs
->if1_cmask
);
333 /* Setting the MsgVal and RxIE bits */
334 pch_can_bit_set(&priv
->regs
->if1_mcont
, CAN_IF_MCONT_RXIE
);
335 pch_can_bit_set(&priv
->regs
->if1_id2
, CAN_ID_MSGVAL
);
337 } else if (set
== DISABLE
) {
338 /* Resetting the MsgVal and RxIE bits */
339 pch_can_bit_clear(&priv
->regs
->if1_mcont
, CAN_IF_MCONT_RXIE
);
340 pch_can_bit_clear(&priv
->regs
->if1_id2
, CAN_ID_MSGVAL
);
343 pch_can_check_if_busy(&priv
->regs
->if1_creq
, buff_num
);
344 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
347 static void pch_can_rx_enable_all(struct pch_can_priv
*priv
)
351 /* Traversing to obtain the object configured as receivers. */
352 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
353 if (priv
->msg_obj
[i
] == MSG_OBJ_RX
)
354 pch_can_set_rx_enable(priv
, i
+ 1, ENABLE
);
358 static void pch_can_rx_disable_all(struct pch_can_priv
*priv
)
362 /* Traversing to obtain the object configured as receivers. */
363 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
364 if (priv
->msg_obj
[i
] == MSG_OBJ_RX
)
365 pch_can_set_rx_enable(priv
, i
+ 1, DISABLE
);
369 static void pch_can_set_tx_enable(struct pch_can_priv
*priv
, u32 buff_num
,
374 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
375 /* Reading the Msg buffer from Message RAM to Interface2 registers. */
376 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if2_cmask
);
377 pch_can_check_if_busy(&priv
->regs
->if2_creq
, buff_num
);
379 /* Setting the IF2CMASK register for accessing the
380 MsgVal and TxIE bits */
381 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_ARB
| CAN_CMASK_CTRL
,
382 &priv
->regs
->if2_cmask
);
385 /* Setting the MsgVal and TxIE bits */
386 pch_can_bit_set(&priv
->regs
->if2_mcont
, CAN_IF_MCONT_TXIE
);
387 pch_can_bit_set(&priv
->regs
->if2_id2
, CAN_ID_MSGVAL
);
388 } else if (set
== DISABLE
) {
389 /* Resetting the MsgVal and TxIE bits. */
390 pch_can_bit_clear(&priv
->regs
->if2_mcont
, CAN_IF_MCONT_TXIE
);
391 pch_can_bit_clear(&priv
->regs
->if2_id2
, CAN_ID_MSGVAL
);
394 pch_can_check_if_busy(&priv
->regs
->if2_creq
, buff_num
);
395 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
398 static void pch_can_tx_enable_all(struct pch_can_priv
*priv
)
402 /* Traversing to obtain the object configured as transmit object. */
403 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
404 if (priv
->msg_obj
[i
] == MSG_OBJ_TX
)
405 pch_can_set_tx_enable(priv
, i
+ 1, ENABLE
);
409 static void pch_can_tx_disable_all(struct pch_can_priv
*priv
)
413 /* Traversing to obtain the object configured as transmit object. */
414 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
415 if (priv
->msg_obj
[i
] == MSG_OBJ_TX
)
416 pch_can_set_tx_enable(priv
, i
+ 1, DISABLE
);
420 static void pch_can_get_rx_enable(struct pch_can_priv
*priv
, u32 buff_num
,
425 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
426 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if1_cmask
);
427 pch_can_check_if_busy(&priv
->regs
->if1_creq
, buff_num
);
429 if (((ioread32(&priv
->regs
->if1_id2
)) & CAN_ID_MSGVAL
) &&
430 ((ioread32(&priv
->regs
->if1_mcont
)) &
435 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
438 static void pch_can_get_tx_enable(struct pch_can_priv
*priv
, u32 buff_num
,
443 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
444 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if2_cmask
);
445 pch_can_check_if_busy(&priv
->regs
->if2_creq
, buff_num
);
447 if (((ioread32(&priv
->regs
->if2_id2
)) & CAN_ID_MSGVAL
) &&
448 ((ioread32(&priv
->regs
->if2_mcont
)) &
449 CAN_IF_MCONT_TXIE
)) {
454 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
457 static int pch_can_int_pending(struct pch_can_priv
*priv
)
459 return ioread32(&priv
->regs
->intr
) & 0xffff;
462 static void pch_can_set_rx_buffer_link(struct pch_can_priv
*priv
,
463 u32 buffer_num
, u32 set
)
467 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
468 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if1_cmask
);
469 pch_can_check_if_busy(&priv
->regs
->if1_creq
, buffer_num
);
470 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_CTRL
, &priv
->regs
->if1_cmask
);
472 pch_can_bit_clear(&priv
->regs
->if1_mcont
, CAN_IF_MCONT_EOB
);
474 pch_can_bit_set(&priv
->regs
->if1_mcont
, CAN_IF_MCONT_EOB
);
476 pch_can_check_if_busy(&priv
->regs
->if1_creq
, buffer_num
);
477 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
480 static void pch_can_get_rx_buffer_link(struct pch_can_priv
*priv
,
481 u32 buffer_num
, u32
*link
)
485 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
486 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if1_cmask
);
487 pch_can_check_if_busy(&priv
->regs
->if1_creq
, buffer_num
);
489 if (ioread32(&priv
->regs
->if1_mcont
) & CAN_IF_MCONT_EOB
)
493 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
496 static void pch_can_clear_buffers(struct pch_can_priv
*priv
)
500 for (i
= 0; i
< PCH_RX_OBJ_NUM
; i
++) {
501 iowrite32(CAN_CMASK_RX_TX_SET
, &priv
->regs
->if1_cmask
);
502 iowrite32(0xffff, &priv
->regs
->if1_mask1
);
503 iowrite32(0xffff, &priv
->regs
->if1_mask2
);
504 iowrite32(0x0, &priv
->regs
->if1_id1
);
505 iowrite32(0x0, &priv
->regs
->if1_id2
);
506 iowrite32(0x0, &priv
->regs
->if1_mcont
);
507 iowrite32(0x0, &priv
->regs
->if1_dataa1
);
508 iowrite32(0x0, &priv
->regs
->if1_dataa2
);
509 iowrite32(0x0, &priv
->regs
->if1_datab1
);
510 iowrite32(0x0, &priv
->regs
->if1_datab2
);
511 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_MASK
|
512 CAN_CMASK_ARB
| CAN_CMASK_CTRL
,
513 &priv
->regs
->if1_cmask
);
514 pch_can_check_if_busy(&priv
->regs
->if1_creq
, i
+1);
517 for (i
= i
; i
< PCH_OBJ_NUM
; i
++) {
518 iowrite32(CAN_CMASK_RX_TX_SET
, &priv
->regs
->if2_cmask
);
519 iowrite32(0xffff, &priv
->regs
->if2_mask1
);
520 iowrite32(0xffff, &priv
->regs
->if2_mask2
);
521 iowrite32(0x0, &priv
->regs
->if2_id1
);
522 iowrite32(0x0, &priv
->regs
->if2_id2
);
523 iowrite32(0x0, &priv
->regs
->if2_mcont
);
524 iowrite32(0x0, &priv
->regs
->if2_dataa1
);
525 iowrite32(0x0, &priv
->regs
->if2_dataa2
);
526 iowrite32(0x0, &priv
->regs
->if2_datab1
);
527 iowrite32(0x0, &priv
->regs
->if2_datab2
);
528 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_MASK
|
529 CAN_CMASK_ARB
| CAN_CMASK_CTRL
,
530 &priv
->regs
->if2_cmask
);
531 pch_can_check_if_busy(&priv
->regs
->if2_creq
, i
+1);
535 static void pch_can_config_rx_tx_buffers(struct pch_can_priv
*priv
)
540 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
542 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
543 if (priv
->msg_obj
[i
] == MSG_OBJ_RX
) {
544 iowrite32(CAN_CMASK_RX_TX_GET
,
545 &priv
->regs
->if1_cmask
);
546 pch_can_check_if_busy(&priv
->regs
->if1_creq
, i
+1);
548 iowrite32(0x0, &priv
->regs
->if1_id1
);
549 iowrite32(0x0, &priv
->regs
->if1_id2
);
551 pch_can_bit_set(&priv
->regs
->if1_mcont
,
554 /* Set FIFO mode set to 0 except last Rx Obj*/
555 pch_can_bit_clear(&priv
->regs
->if1_mcont
,
557 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
558 if (i
== (PCH_RX_OBJ_NUM
- 1))
559 pch_can_bit_set(&priv
->regs
->if1_mcont
,
562 iowrite32(0, &priv
->regs
->if1_mask1
);
563 pch_can_bit_clear(&priv
->regs
->if1_mask2
,
564 0x1fff | CAN_MASK2_MDIR_MXTD
);
566 /* Setting CMASK for writing */
567 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_MASK
|
568 CAN_CMASK_ARB
| CAN_CMASK_CTRL
,
569 &priv
->regs
->if1_cmask
);
571 pch_can_check_if_busy(&priv
->regs
->if1_creq
, i
+1);
572 } else if (priv
->msg_obj
[i
] == MSG_OBJ_TX
) {
573 iowrite32(CAN_CMASK_RX_TX_GET
,
574 &priv
->regs
->if2_cmask
);
575 pch_can_check_if_busy(&priv
->regs
->if2_creq
, i
+1);
577 /* Resetting DIR bit for reception */
578 iowrite32(0x0, &priv
->regs
->if2_id1
);
579 iowrite32(0x0, &priv
->regs
->if2_id2
);
580 pch_can_bit_set(&priv
->regs
->if2_id2
, CAN_ID2_DIR
);
582 /* Setting EOB bit for transmitter */
583 iowrite32(CAN_IF_MCONT_EOB
, &priv
->regs
->if2_mcont
);
585 pch_can_bit_set(&priv
->regs
->if2_mcont
,
588 iowrite32(0, &priv
->regs
->if2_mask1
);
589 pch_can_bit_clear(&priv
->regs
->if2_mask2
, 0x1fff);
591 /* Setting CMASK for writing */
592 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_MASK
|
593 CAN_CMASK_ARB
| CAN_CMASK_CTRL
,
594 &priv
->regs
->if2_cmask
);
596 pch_can_check_if_busy(&priv
->regs
->if2_creq
, i
+1);
599 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
602 static void pch_can_init(struct pch_can_priv
*priv
)
604 /* Stopping the Can device. */
605 pch_can_set_run_mode(priv
, PCH_CAN_STOP
);
607 /* Clearing all the message object buffers. */
608 pch_can_clear_buffers(priv
);
610 /* Configuring the respective message object as either rx/tx object. */
611 pch_can_config_rx_tx_buffers(priv
);
613 /* Enabling the interrupts. */
614 pch_can_set_int_enables(priv
, PCH_CAN_ALL
);
617 static void pch_can_release(struct pch_can_priv
*priv
)
619 /* Stooping the CAN device. */
620 pch_can_set_run_mode(priv
, PCH_CAN_STOP
);
622 /* Disabling the interrupts. */
623 pch_can_set_int_enables(priv
, PCH_CAN_NONE
);
625 /* Disabling all the receive object. */
626 pch_can_rx_disable_all(priv
);
628 /* Disabling all the transmit object. */
629 pch_can_tx_disable_all(priv
);
632 /* This function clears interrupt(s) from the CAN device. */
633 static void pch_can_int_clr(struct pch_can_priv
*priv
, u32 mask
)
635 if (mask
== CAN_STATUS_INT
) {
636 ioread32(&priv
->regs
->stat
);
640 /* Clear interrupt for transmit object */
641 if (priv
->msg_obj
[mask
- 1] == MSG_OBJ_TX
) {
642 /* Setting CMASK for clearing interrupts for
643 frame transmission. */
644 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_CTRL
| CAN_CMASK_ARB
,
645 &priv
->regs
->if2_cmask
);
647 /* Resetting the ID registers. */
648 pch_can_bit_set(&priv
->regs
->if2_id2
,
649 CAN_ID2_DIR
| (0x7ff << 2));
650 iowrite32(0x0, &priv
->regs
->if2_id1
);
652 /* Claring NewDat, TxRqst & IntPnd */
653 pch_can_bit_clear(&priv
->regs
->if2_mcont
,
654 CAN_IF_MCONT_NEWDAT
| CAN_IF_MCONT_INTPND
|
655 CAN_IF_MCONT_TXRQXT
);
656 pch_can_check_if_busy(&priv
->regs
->if2_creq
, mask
);
657 } else if (priv
->msg_obj
[mask
- 1] == MSG_OBJ_RX
) {
658 /* Setting CMASK for clearing the reception interrupts. */
659 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_CTRL
| CAN_CMASK_ARB
,
660 &priv
->regs
->if1_cmask
);
662 /* Clearing the Dir bit. */
663 pch_can_bit_clear(&priv
->regs
->if1_id2
, CAN_ID2_DIR
);
665 /* Clearing NewDat & IntPnd */
666 pch_can_bit_clear(&priv
->regs
->if1_mcont
,
667 CAN_IF_MCONT_NEWDAT
| CAN_IF_MCONT_INTPND
);
669 pch_can_check_if_busy(&priv
->regs
->if1_creq
, mask
);
673 static int pch_can_get_buffer_status(struct pch_can_priv
*priv
)
675 return (ioread32(&priv
->regs
->treq1
) & 0xffff) |
676 ((ioread32(&priv
->regs
->treq2
) & 0xffff) << 16);
679 static void pch_can_reset(struct pch_can_priv
*priv
)
681 /* write to sw reset register */
682 iowrite32(1, &priv
->regs
->srst
);
683 iowrite32(0, &priv
->regs
->srst
);
686 static void pch_can_error(struct net_device
*ndev
, u32 status
)
689 struct pch_can_priv
*priv
= netdev_priv(ndev
);
690 struct can_frame
*cf
;
692 struct net_device_stats
*stats
= &(priv
->ndev
->stats
);
693 enum can_state state
= priv
->can
.state
;
695 skb
= alloc_can_err_skb(ndev
, &cf
);
699 if (status
& PCH_BUS_OFF
) {
700 pch_can_tx_disable_all(priv
);
701 pch_can_rx_disable_all(priv
);
702 state
= CAN_STATE_BUS_OFF
;
703 cf
->can_id
|= CAN_ERR_BUSOFF
;
705 pch_can_set_run_mode(priv
, PCH_CAN_RUN
);
706 dev_err(&ndev
->dev
, "%s -> Bus Off occurres.\n", __func__
);
709 /* Warning interrupt. */
710 if (status
& PCH_EWARN
) {
711 state
= CAN_STATE_ERROR_WARNING
;
712 priv
->can
.can_stats
.error_warning
++;
713 cf
->can_id
|= CAN_ERR_CRTL
;
714 errc
= ioread32(&priv
->regs
->errc
);
715 if (((errc
& CAN_REC
) >> 8) > 96)
716 cf
->data
[1] |= CAN_ERR_CRTL_RX_WARNING
;
717 if ((errc
& CAN_TEC
) > 96)
718 cf
->data
[1] |= CAN_ERR_CRTL_TX_WARNING
;
720 "%s -> Error Counter is more than 96.\n", __func__
);
722 /* Error passive interrupt. */
723 if (status
& PCH_EPASSIV
) {
724 priv
->can
.can_stats
.error_passive
++;
725 state
= CAN_STATE_ERROR_PASSIVE
;
726 cf
->can_id
|= CAN_ERR_CRTL
;
727 errc
= ioread32(&priv
->regs
->errc
);
728 if (((errc
& CAN_REC
) >> 8) > 127)
729 cf
->data
[1] |= CAN_ERR_CRTL_RX_PASSIVE
;
730 if ((errc
& CAN_TEC
) > 127)
731 cf
->data
[1] |= CAN_ERR_CRTL_TX_PASSIVE
;
733 "%s -> CAN controller is ERROR PASSIVE .\n", __func__
);
736 if (status
& PCH_LEC_ALL
) {
737 priv
->can
.can_stats
.bus_error
++;
739 switch (status
& PCH_LEC_ALL
) {
741 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
744 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
747 cf
->data
[2] |= CAN_ERR_PROT_LOC_ACK
|
748 CAN_ERR_PROT_LOC_ACK_DEL
;
752 cf
->data
[2] |= CAN_ERR_PROT_BIT
;
755 cf
->data
[2] |= CAN_ERR_PROT_LOC_CRC_SEQ
|
756 CAN_ERR_PROT_LOC_CRC_DEL
;
759 iowrite32(status
| PCH_LEC_ALL
, &priv
->regs
->stat
);
765 priv
->can
.state
= state
;
769 stats
->rx_bytes
+= cf
->can_dlc
;
772 static irqreturn_t
pch_can_interrupt(int irq
, void *dev_id
)
774 struct net_device
*ndev
= (struct net_device
*)dev_id
;
775 struct pch_can_priv
*priv
= netdev_priv(ndev
);
777 pch_can_set_int_enables(priv
, PCH_CAN_NONE
);
779 napi_schedule(&priv
->napi
);
784 static int pch_can_rx_normal(struct net_device
*ndev
, u32 int_stat
)
793 struct can_frame
*cf
;
794 struct pch_can_priv
*priv
= netdev_priv(ndev
);
795 struct net_device_stats
*stats
= &(priv
->ndev
->stats
);
797 /* Reading the messsage object from the Message RAM */
798 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if1_cmask
);
799 pch_can_check_if_busy(&priv
->regs
->if1_creq
, int_stat
);
801 /* Reading the MCONT register. */
802 reg
= ioread32(&priv
->regs
->if1_mcont
);
805 for (k
= int_stat
; !(reg
& CAN_IF_MCONT_EOB
); k
++) {
806 /* If MsgLost bit set. */
807 if (reg
& CAN_IF_MCONT_MSGLOST
) {
808 dev_err(&priv
->ndev
->dev
, "Msg Obj is overwritten.\n");
809 pch_can_bit_clear(&priv
->regs
->if1_mcont
,
810 CAN_IF_MCONT_MSGLOST
);
811 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_CTRL
,
812 &priv
->regs
->if1_cmask
);
813 pch_can_check_if_busy(&priv
->regs
->if1_creq
, k
);
815 skb
= alloc_can_err_skb(ndev
, &cf
);
819 priv
->can
.can_stats
.error_passive
++;
820 priv
->can
.state
= CAN_STATE_ERROR_PASSIVE
;
821 cf
->can_id
|= CAN_ERR_CRTL
;
822 cf
->data
[1] |= CAN_ERR_CRTL_RX_OVERFLOW
;
823 cf
->data
[2] |= CAN_ERR_PROT_OVERLOAD
;
825 stats
->rx_bytes
+= cf
->can_dlc
;
827 netif_receive_skb(skb
);
831 if (!(reg
& CAN_IF_MCONT_NEWDAT
))
834 skb
= alloc_can_skb(priv
->ndev
, &cf
);
838 /* Get Received data */
839 ide
= ((ioread32(&priv
->regs
->if1_id2
)) & CAN_ID2_XTD
) >> 14;
841 id
= (ioread32(&priv
->regs
->if1_id1
) & 0xffff);
842 id
|= (((ioread32(&priv
->regs
->if1_id2
)) &
844 cf
->can_id
= (id
& CAN_EFF_MASK
) | CAN_EFF_FLAG
;
846 id
= (((ioread32(&priv
->regs
->if1_id2
)) &
847 (CAN_SFF_MASK
<< 2)) >> 2);
848 cf
->can_id
= (id
& CAN_SFF_MASK
);
851 rtr
= (ioread32(&priv
->regs
->if1_id2
) & CAN_ID2_DIR
);
854 cf
->can_id
|= CAN_RTR_FLAG
;
856 cf
->can_dlc
= ((ioread32(&priv
->regs
->if1_mcont
)) &
860 for (i
= 0, j
= 0; i
< cf
->can_dlc
; j
++) {
861 reg
= ioread32(&priv
->regs
->if1_dataa1
+ j
*4);
862 cf
->data
[i
++] = cpu_to_le32(reg
& 0xff);
863 if (i
== cf
->can_dlc
)
865 cf
->data
[i
++] = cpu_to_le32((reg
>> 8) & 0xff);
868 netif_receive_skb(skb
);
871 stats
->rx_bytes
+= cf
->can_dlc
;
873 if (k
< PCH_FIFO_THRESH
) {
874 iowrite32(CAN_CMASK_RDWR
| CAN_CMASK_CTRL
|
875 CAN_CMASK_ARB
, &priv
->regs
->if1_cmask
);
877 /* Clearing the Dir bit. */
878 pch_can_bit_clear(&priv
->regs
->if1_id2
, CAN_ID2_DIR
);
880 /* Clearing NewDat & IntPnd */
881 pch_can_bit_clear(&priv
->regs
->if1_mcont
,
882 CAN_IF_MCONT_INTPND
);
883 pch_can_check_if_busy(&priv
->regs
->if1_creq
, k
);
884 } else if (k
> PCH_FIFO_THRESH
) {
885 pch_can_int_clr(priv
, k
);
886 } else if (k
== PCH_FIFO_THRESH
) {
888 for (cnt
= 0; cnt
< PCH_FIFO_THRESH
; cnt
++)
889 pch_can_int_clr(priv
, cnt
+1);
892 /* Reading the messsage object from the Message RAM */
893 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if1_cmask
);
894 pch_can_check_if_busy(&priv
->regs
->if1_creq
, k
+ 1);
895 reg
= ioread32(&priv
->regs
->if1_mcont
);
900 static int pch_can_rx_poll(struct napi_struct
*napi
, int quota
)
902 struct net_device
*ndev
= napi
->dev
;
903 struct pch_can_priv
*priv
= netdev_priv(ndev
);
904 struct net_device_stats
*stats
= &(priv
->ndev
->stats
);
911 int_stat
= pch_can_int_pending(priv
);
916 if (int_stat
== CAN_STATUS_INT
) {
917 reg_stat
= ioread32(&priv
->regs
->stat
);
918 if (reg_stat
& (PCH_BUS_OFF
| PCH_LEC_ALL
)) {
919 if ((reg_stat
& PCH_LEC_ALL
) != PCH_LEC_ALL
)
920 pch_can_error(ndev
, reg_stat
);
923 if (reg_stat
& PCH_TX_OK
) {
924 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
925 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if2_cmask
);
926 pch_can_check_if_busy(&priv
->regs
->if2_creq
,
927 ioread32(&priv
->regs
->intr
));
928 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
929 pch_can_bit_clear(&priv
->regs
->stat
, PCH_TX_OK
);
932 if (reg_stat
& PCH_RX_OK
)
933 pch_can_bit_clear(&priv
->regs
->stat
, PCH_RX_OK
);
935 int_stat
= pch_can_int_pending(priv
);
936 if (int_stat
== CAN_STATUS_INT
)
941 if ((int_stat
>= 1) && (int_stat
<= PCH_RX_OBJ_NUM
)) {
942 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
943 rcv_pkts
= pch_can_rx_normal(ndev
, int_stat
);
944 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
947 } else if ((int_stat
> PCH_RX_OBJ_NUM
) && (int_stat
<= PCH_OBJ_NUM
)) {
948 if (priv
->msg_obj
[int_stat
- 1] == MSG_OBJ_TX
) {
949 /* Handle transmission interrupt */
950 can_get_echo_skb(ndev
, int_stat
- PCH_RX_OBJ_NUM
- 1);
951 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
952 iowrite32(CAN_CMASK_RX_TX_GET
| CAN_CMASK_CLRINTPND
,
953 &priv
->regs
->if2_cmask
);
954 dlc
= ioread32(&priv
->regs
->if2_mcont
) &
956 pch_can_check_if_busy(&priv
->regs
->if2_creq
, int_stat
);
957 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
960 stats
->tx_bytes
+= dlc
;
965 int_stat
= pch_can_int_pending(priv
);
966 if (int_stat
== CAN_STATUS_INT
)
968 else if (int_stat
>= 1 && int_stat
<= 32)
972 pch_can_set_int_enables(priv
, PCH_CAN_ALL
);
977 static int pch_set_bittiming(struct net_device
*ndev
)
979 struct pch_can_priv
*priv
= netdev_priv(ndev
);
980 const struct can_bittiming
*bt
= &priv
->can
.bittiming
;
985 /* Setting the CCE bit for accessing the Can Timing register. */
986 pch_can_bit_set(&priv
->regs
->cont
, CAN_CTRL_CCE
);
988 brp
= (bt
->tq
) / (1000000000/PCH_CAN_CLK
) - 1;
989 canbit
= brp
& MSK_BITT_BRP
;
990 canbit
|= (bt
->sjw
- 1) << BIT_BITT_SJW
;
991 canbit
|= (bt
->phase_seg1
+ bt
->prop_seg
- 1) << BIT_BITT_TSEG1
;
992 canbit
|= (bt
->phase_seg2
- 1) << BIT_BITT_TSEG2
;
993 bepe
= (brp
& MSK_BRPE_BRPE
) >> BIT_BRPE_BRPE
;
994 iowrite32(canbit
, &priv
->regs
->bitt
);
995 iowrite32(bepe
, &priv
->regs
->brpe
);
996 pch_can_bit_clear(&priv
->regs
->cont
, CAN_CTRL_CCE
);
1001 static void pch_can_start(struct net_device
*ndev
)
1003 struct pch_can_priv
*priv
= netdev_priv(ndev
);
1005 if (priv
->can
.state
!= CAN_STATE_STOPPED
)
1006 pch_can_reset(priv
);
1008 pch_set_bittiming(ndev
);
1009 pch_can_set_optmode(priv
);
1011 pch_can_tx_enable_all(priv
);
1012 pch_can_rx_enable_all(priv
);
1014 /* Setting the CAN to run mode. */
1015 pch_can_set_run_mode(priv
, PCH_CAN_RUN
);
1017 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
1022 static int pch_can_do_set_mode(struct net_device
*ndev
, enum can_mode mode
)
1027 case CAN_MODE_START
:
1028 pch_can_start(ndev
);
1029 netif_wake_queue(ndev
);
1039 static int pch_can_open(struct net_device
*ndev
)
1041 struct pch_can_priv
*priv
= netdev_priv(ndev
);
1044 retval
= pci_enable_msi(priv
->dev
);
1046 dev_info(&ndev
->dev
, "PCH CAN opened without MSI\n");
1049 dev_info(&ndev
->dev
, "PCH CAN opened with MSI\n");
1053 /* Regsitering the interrupt. */
1054 retval
= request_irq(priv
->dev
->irq
, pch_can_interrupt
, IRQF_SHARED
,
1057 dev_err(&ndev
->dev
, "request_irq failed.\n");
1061 /* Open common can device */
1062 retval
= open_candev(ndev
);
1064 dev_err(ndev
->dev
.parent
, "open_candev() failed %d\n", retval
);
1065 goto err_open_candev
;
1069 pch_can_start(ndev
);
1070 napi_enable(&priv
->napi
);
1071 netif_start_queue(ndev
);
1076 free_irq(priv
->dev
->irq
, ndev
);
1079 pci_disable_msi(priv
->dev
);
1081 pch_can_release(priv
);
1086 static int pch_close(struct net_device
*ndev
)
1088 struct pch_can_priv
*priv
= netdev_priv(ndev
);
1090 netif_stop_queue(ndev
);
1091 napi_disable(&priv
->napi
);
1092 pch_can_release(priv
);
1093 free_irq(priv
->dev
->irq
, ndev
);
1095 pci_disable_msi(priv
->dev
);
1097 priv
->can
.state
= CAN_STATE_STOPPED
;
1101 static int pch_get_msg_obj_sts(struct net_device
*ndev
, u32 obj_id
)
1103 u32 buffer_status
= 0;
1104 struct pch_can_priv
*priv
= netdev_priv(ndev
);
1106 /* Getting the message object status. */
1107 buffer_status
= (u32
) pch_can_get_buffer_status(priv
);
1109 return buffer_status
& obj_id
;
1113 static netdev_tx_t
pch_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1116 unsigned long flags
;
1117 struct pch_can_priv
*priv
= netdev_priv(ndev
);
1118 struct can_frame
*cf
= (struct can_frame
*)skb
->data
;
1119 int tx_buffer_avail
= 0;
1121 if (can_dropped_invalid_skb(ndev
, skb
))
1122 return NETDEV_TX_OK
;
1124 if (priv
->tx_obj
== (PCH_OBJ_NUM
+ 1)) { /* Point tail Obj */
1125 while (pch_get_msg_obj_sts(ndev
, (((1 << PCH_TX_OBJ_NUM
)-1) <<
1129 priv
->tx_obj
= PCH_RX_OBJ_NUM
+ 1; /* Point head of Tx Obj ID */
1130 tx_buffer_avail
= priv
->tx_obj
; /* Point Tail of Tx Obj */
1132 tx_buffer_avail
= priv
->tx_obj
;
1136 /* Attaining the lock. */
1137 spin_lock_irqsave(&priv
->msgif_reg_lock
, flags
);
1139 /* Reading the Msg Obj from the Msg RAM to the Interface register. */
1140 iowrite32(CAN_CMASK_RX_TX_GET
, &priv
->regs
->if2_cmask
);
1141 pch_can_check_if_busy(&priv
->regs
->if2_creq
, tx_buffer_avail
);
1143 /* Setting the CMASK register. */
1144 pch_can_bit_set(&priv
->regs
->if2_cmask
, CAN_CMASK_ALL
);
1146 /* If ID extended is set. */
1147 pch_can_bit_clear(&priv
->regs
->if2_id1
, 0xffff);
1148 pch_can_bit_clear(&priv
->regs
->if2_id2
, 0x1fff | CAN_ID2_XTD
);
1149 if (cf
->can_id
& CAN_EFF_FLAG
) {
1150 pch_can_bit_set(&priv
->regs
->if2_id1
, cf
->can_id
& 0xffff);
1151 pch_can_bit_set(&priv
->regs
->if2_id2
,
1152 ((cf
->can_id
>> 16) & 0x1fff) | CAN_ID2_XTD
);
1154 pch_can_bit_set(&priv
->regs
->if2_id1
, 0);
1155 pch_can_bit_set(&priv
->regs
->if2_id2
,
1156 (cf
->can_id
& CAN_SFF_MASK
) << 2);
1159 /* If remote frame has to be transmitted.. */
1160 if (cf
->can_id
& CAN_RTR_FLAG
)
1161 pch_can_bit_clear(&priv
->regs
->if2_id2
, CAN_ID2_DIR
);
1163 for (i
= 0, j
= 0; i
< cf
->can_dlc
; j
++) {
1164 iowrite32(le32_to_cpu(cf
->data
[i
++]),
1165 (&priv
->regs
->if2_dataa1
) + j
*4);
1166 if (i
== cf
->can_dlc
)
1168 iowrite32(le32_to_cpu(cf
->data
[i
++] << 8),
1169 (&priv
->regs
->if2_dataa1
) + j
*4);
1172 can_put_echo_skb(skb
, ndev
, tx_buffer_avail
- PCH_RX_OBJ_NUM
- 1);
1174 /* Updating the size of the data. */
1175 pch_can_bit_clear(&priv
->regs
->if2_mcont
, 0x0f);
1176 pch_can_bit_set(&priv
->regs
->if2_mcont
, cf
->can_dlc
);
1178 /* Clearing IntPend, NewDat & TxRqst */
1179 pch_can_bit_clear(&priv
->regs
->if2_mcont
,
1180 CAN_IF_MCONT_NEWDAT
| CAN_IF_MCONT_INTPND
|
1181 CAN_IF_MCONT_TXRQXT
);
1183 /* Setting NewDat, TxRqst bits */
1184 pch_can_bit_set(&priv
->regs
->if2_mcont
,
1185 CAN_IF_MCONT_NEWDAT
| CAN_IF_MCONT_TXRQXT
);
1187 pch_can_check_if_busy(&priv
->regs
->if2_creq
, tx_buffer_avail
);
1189 spin_unlock_irqrestore(&priv
->msgif_reg_lock
, flags
);
1191 return NETDEV_TX_OK
;
1194 static const struct net_device_ops pch_can_netdev_ops
= {
1195 .ndo_open
= pch_can_open
,
1196 .ndo_stop
= pch_close
,
1197 .ndo_start_xmit
= pch_xmit
,
1200 static void __devexit
pch_can_remove(struct pci_dev
*pdev
)
1202 struct net_device
*ndev
= pci_get_drvdata(pdev
);
1203 struct pch_can_priv
*priv
= netdev_priv(ndev
);
1205 unregister_candev(priv
->ndev
);
1206 free_candev(priv
->ndev
);
1207 pci_iounmap(pdev
, priv
->regs
);
1208 pci_release_regions(pdev
);
1209 pci_disable_device(pdev
);
1210 pci_set_drvdata(pdev
, NULL
);
1211 pch_can_reset(priv
);
1215 static int pch_can_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1217 int i
; /* Counter variable. */
1218 int retval
; /* Return value. */
1219 u32 buf_stat
; /* Variable for reading the transmit buffer status. */
1220 u32 counter
= 0xFFFFFF;
1222 struct net_device
*dev
= pci_get_drvdata(pdev
);
1223 struct pch_can_priv
*priv
= netdev_priv(dev
);
1225 /* Stop the CAN controller */
1226 pch_can_set_run_mode(priv
, PCH_CAN_STOP
);
1228 /* Indicate that we are aboutto/in suspend */
1229 priv
->can
.state
= CAN_STATE_SLEEPING
;
1231 /* Waiting for all transmission to complete. */
1233 buf_stat
= pch_can_get_buffer_status(priv
);
1240 dev_err(&pdev
->dev
, "%s -> Transmission time out.\n", __func__
);
1242 /* Save interrupt configuration and then disable them */
1243 pch_can_get_int_enables(priv
, &(priv
->int_enables
));
1244 pch_can_set_int_enables(priv
, PCH_CAN_DISABLE
);
1246 /* Save Tx buffer enable state */
1247 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
1248 if (priv
->msg_obj
[i
] == MSG_OBJ_TX
)
1249 pch_can_get_tx_enable(priv
, i
+ 1,
1250 &(priv
->tx_enable
[i
]));
1253 /* Disable all Transmit buffers */
1254 pch_can_tx_disable_all(priv
);
1256 /* Save Rx buffer enable state */
1257 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
1258 if (priv
->msg_obj
[i
] == MSG_OBJ_RX
) {
1259 pch_can_get_rx_enable(priv
, i
+ 1,
1260 &(priv
->rx_enable
[i
]));
1261 pch_can_get_rx_buffer_link(priv
, i
+ 1,
1262 &(priv
->rx_link
[i
]));
1266 /* Disable all Receive buffers */
1267 pch_can_rx_disable_all(priv
);
1268 retval
= pci_save_state(pdev
);
1270 dev_err(&pdev
->dev
, "pci_save_state failed.\n");
1272 pci_enable_wake(pdev
, PCI_D3hot
, 0);
1273 pci_disable_device(pdev
);
1274 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1280 static int pch_can_resume(struct pci_dev
*pdev
)
1282 int i
; /* Counter variable. */
1283 int retval
; /* Return variable. */
1284 struct net_device
*dev
= pci_get_drvdata(pdev
);
1285 struct pch_can_priv
*priv
= netdev_priv(dev
);
1287 pci_set_power_state(pdev
, PCI_D0
);
1288 pci_restore_state(pdev
);
1289 retval
= pci_enable_device(pdev
);
1291 dev_err(&pdev
->dev
, "pci_enable_device failed.\n");
1295 pci_enable_wake(pdev
, PCI_D3hot
, 0);
1297 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
1299 /* Disabling all interrupts. */
1300 pch_can_set_int_enables(priv
, PCH_CAN_DISABLE
);
1302 /* Setting the CAN device in Stop Mode. */
1303 pch_can_set_run_mode(priv
, PCH_CAN_STOP
);
1305 /* Configuring the transmit and receive buffers. */
1306 pch_can_config_rx_tx_buffers(priv
);
1308 /* Restore the CAN state */
1309 pch_set_bittiming(dev
);
1312 pch_can_set_optmode(priv
);
1314 /* Enabling the transmit buffer. */
1315 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
1316 if (priv
->msg_obj
[i
] == MSG_OBJ_TX
) {
1317 pch_can_set_tx_enable(priv
, i
+ 1,
1318 priv
->tx_enable
[i
]);
1322 /* Configuring the receive buffer and enabling them. */
1323 for (i
= 0; i
< PCH_OBJ_NUM
; i
++) {
1324 if (priv
->msg_obj
[i
] == MSG_OBJ_RX
) {
1325 /* Restore buffer link */
1326 pch_can_set_rx_buffer_link(priv
, i
+ 1,
1329 /* Restore buffer enables */
1330 pch_can_set_rx_enable(priv
, i
+ 1, priv
->rx_enable
[i
]);
1334 /* Enable CAN Interrupts */
1335 pch_can_set_int_custom(priv
);
1337 /* Restore Run Mode */
1338 pch_can_set_run_mode(priv
, PCH_CAN_RUN
);
1343 #define pch_can_suspend NULL
1344 #define pch_can_resume NULL
1347 static int pch_can_get_berr_counter(const struct net_device
*dev
,
1348 struct can_berr_counter
*bec
)
1350 struct pch_can_priv
*priv
= netdev_priv(dev
);
1352 bec
->txerr
= ioread32(&priv
->regs
->errc
) & CAN_TEC
;
1353 bec
->rxerr
= (ioread32(&priv
->regs
->errc
) & CAN_REC
) >> 8;
1358 static int __devinit
pch_can_probe(struct pci_dev
*pdev
,
1359 const struct pci_device_id
*id
)
1361 struct net_device
*ndev
;
1362 struct pch_can_priv
*priv
;
1367 rc
= pci_enable_device(pdev
);
1369 dev_err(&pdev
->dev
, "Failed pci_enable_device %d\n", rc
);
1370 goto probe_exit_endev
;
1373 rc
= pci_request_regions(pdev
, KBUILD_MODNAME
);
1375 dev_err(&pdev
->dev
, "Failed pci_request_regions %d\n", rc
);
1376 goto probe_exit_pcireq
;
1379 addr
= pci_iomap(pdev
, 1, 0);
1382 dev_err(&pdev
->dev
, "Failed pci_iomap\n");
1383 goto probe_exit_ipmap
;
1386 ndev
= alloc_candev(sizeof(struct pch_can_priv
), PCH_TX_OBJ_NUM
);
1389 dev_err(&pdev
->dev
, "Failed alloc_candev\n");
1390 goto probe_exit_alloc_candev
;
1393 priv
= netdev_priv(ndev
);
1397 priv
->can
.bittiming_const
= &pch_can_bittiming_const
;
1398 priv
->can
.do_set_mode
= pch_can_do_set_mode
;
1399 priv
->can
.do_get_berr_counter
= pch_can_get_berr_counter
;
1400 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_LISTENONLY
|
1401 CAN_CTRLMODE_LOOPBACK
;
1402 priv
->tx_obj
= PCH_RX_OBJ_NUM
+ 1; /* Point head of Tx Obj */
1404 ndev
->irq
= pdev
->irq
;
1405 ndev
->flags
|= IFF_ECHO
;
1407 pci_set_drvdata(pdev
, ndev
);
1408 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1409 ndev
->netdev_ops
= &pch_can_netdev_ops
;
1411 priv
->can
.clock
.freq
= PCH_CAN_CLK
; /* Hz */
1412 for (index
= 0; index
< PCH_RX_OBJ_NUM
;)
1413 priv
->msg_obj
[index
++] = MSG_OBJ_RX
;
1415 for (index
= index
; index
< PCH_OBJ_NUM
;)
1416 priv
->msg_obj
[index
++] = MSG_OBJ_TX
;
1418 netif_napi_add(ndev
, &priv
->napi
, pch_can_rx_poll
, PCH_RX_OBJ_NUM
);
1420 rc
= register_candev(ndev
);
1422 dev_err(&pdev
->dev
, "Failed register_candev %d\n", rc
);
1423 goto probe_exit_reg_candev
;
1428 probe_exit_reg_candev
:
1430 probe_exit_alloc_candev
:
1431 pci_iounmap(pdev
, addr
);
1433 pci_release_regions(pdev
);
1435 pci_disable_device(pdev
);
1440 static struct pci_driver pch_can_pcidev
= {
1442 .id_table
= pch_pci_tbl
,
1443 .probe
= pch_can_probe
,
1444 .remove
= __devexit_p(pch_can_remove
),
1445 .suspend
= pch_can_suspend
,
1446 .resume
= pch_can_resume
,
1449 static int __init
pch_can_pci_init(void)
1451 return pci_register_driver(&pch_can_pcidev
);
1453 module_init(pch_can_pci_init
);
1455 static void __exit
pch_can_pci_exit(void)
1457 pci_unregister_driver(&pch_can_pcidev
);
1459 module_exit(pch_can_pci_exit
);
1461 MODULE_DESCRIPTION("Controller Area Network Driver");
1462 MODULE_LICENSE("GPL v2");
1463 MODULE_VERSION("0.94");