1 /* Renesas R-Car CAN device driver
3 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com>
4 * Copyright (C) 2013 Renesas Solutions Corp.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/errno.h>
17 #include <linux/netdevice.h>
18 #include <linux/platform_device.h>
19 #include <linux/can/led.h>
20 #include <linux/can/dev.h>
21 #include <linux/clk.h>
22 #include <linux/can/platform/rcar_can.h>
24 #define RCAR_CAN_DRV_NAME "rcar_can"
26 /* Mailbox configuration:
27 * mailbox 60 - 63 - Rx FIFO mailboxes
28 * mailbox 56 - 59 - Tx FIFO mailboxes
29 * non-FIFO mailboxes are not used
31 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */
32 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */
33 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */
34 #define RCAR_CAN_FIFO_DEPTH 4
36 /* Mailbox registers structure */
37 struct rcar_can_mbox_regs
{
38 u32 id
; /* IDE and RTR bits, SID and EID */
39 u8 stub
; /* Not used */
40 u8 dlc
; /* Data Length Code - bits [0..3] */
41 u8 data
[8]; /* Data Bytes */
42 u8 tsh
; /* Time Stamp Higher Byte */
43 u8 tsl
; /* Time Stamp Lower Byte */
46 struct rcar_can_regs
{
47 struct rcar_can_mbox_regs mb
[RCAR_CAN_N_MBX
]; /* Mailbox registers */
48 u32 mkr_2_9
[8]; /* Mask Registers 2-9 */
49 u32 fidcr
[2]; /* FIFO Received ID Compare Register */
50 u32 mkivlr1
; /* Mask Invalid Register 1 */
51 u32 mier1
; /* Mailbox Interrupt Enable Register 1 */
52 u32 mkr_0_1
[2]; /* Mask Registers 0-1 */
53 u32 mkivlr0
; /* Mask Invalid Register 0*/
54 u32 mier0
; /* Mailbox Interrupt Enable Register 0 */
56 u8 mctl
[64]; /* Message Control Registers */
57 u16 ctlr
; /* Control Register */
58 u16 str
; /* Status register */
59 u8 bcr
[3]; /* Bit Configuration Register */
60 u8 clkr
; /* Clock Select Register */
61 u8 rfcr
; /* Receive FIFO Control Register */
62 u8 rfpcr
; /* Receive FIFO Pointer Control Register */
63 u8 tfcr
; /* Transmit FIFO Control Register */
64 u8 tfpcr
; /* Transmit FIFO Pointer Control Register */
65 u8 eier
; /* Error Interrupt Enable Register */
66 u8 eifr
; /* Error Interrupt Factor Judge Register */
67 u8 recr
; /* Receive Error Count Register */
68 u8 tecr
; /* Transmit Error Count Register */
69 u8 ecsr
; /* Error Code Store Register */
70 u8 cssr
; /* Channel Search Support Register */
71 u8 mssr
; /* Mailbox Search Status Register */
72 u8 msmr
; /* Mailbox Search Mode Register */
73 u16 tsr
; /* Time Stamp Register */
74 u8 afsr
; /* Acceptance Filter Support Register */
76 u8 tcr
; /* Test Control Register */
78 u8 ier
; /* Interrupt Enable Register */
79 u8 isr
; /* Interrupt Status Register */
81 u8 mbsmr
; /* Mailbox Search Mask Register */
84 struct rcar_can_priv
{
85 struct can_priv can
; /* Must be the first member! */
86 struct net_device
*ndev
;
87 struct napi_struct napi
;
88 struct rcar_can_regs __iomem
*regs
;
90 u8 tx_dlc
[RCAR_CAN_FIFO_DEPTH
];
97 static const struct can_bittiming_const rcar_can_bittiming_const
= {
98 .name
= RCAR_CAN_DRV_NAME
,
109 /* Control Register bits */
110 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */
111 #define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */
112 /* at bus-off entry */
113 #define RCAR_CAN_CTLR_SLPM (1 << 10)
114 #define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */
115 #define RCAR_CAN_CTLR_CANM_HALT (1 << 9)
116 #define RCAR_CAN_CTLR_CANM_RESET (1 << 8)
117 #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8)
118 #define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */
119 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */
120 #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */
121 #define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */
123 /* Status Register bits */
124 #define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */
126 /* FIFO Received ID Compare Registers 0 and 1 bits */
127 #define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */
128 #define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */
130 /* Receive FIFO Control Register bits */
131 #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */
132 #define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */
134 /* Transmit FIFO Control Register bits */
135 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */
136 /* Number Status Bits */
137 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */
138 /* Message Number Status Bits */
139 #define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */
141 #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */
142 /* for Rx mailboxes 0-31 */
143 #define RCAR_CAN_N_RX_MKREGS2 8
145 /* Bit Configuration Register settings */
146 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20)
147 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)
148 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)
149 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07)
151 /* Mailbox and Mask Registers bits */
152 #define RCAR_CAN_IDE (1 << 31)
153 #define RCAR_CAN_RTR (1 << 30)
154 #define RCAR_CAN_SID_SHIFT 18
156 /* Mailbox Interrupt Enable Register 1 bits */
157 #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */
158 #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */
160 /* Interrupt Enable Register bits */
161 #define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */
162 #define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */
164 #define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */
166 /* Interrupt Status Register bits */
167 #define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */
168 #define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */
170 #define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */
173 /* Error Interrupt Enable Register bits */
174 #define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */
175 #define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */
176 /* Interrupt Enable */
177 #define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */
178 #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */
179 #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */
180 #define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */
181 #define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */
182 #define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */
184 /* Error Interrupt Factor Judge Register bits */
185 #define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */
186 #define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */
188 #define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */
189 #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */
190 #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */
191 #define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */
192 #define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */
193 #define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */
195 /* Error Code Store Register bits */
196 #define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */
197 #define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */
198 #define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */
199 #define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */
200 #define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */
201 #define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */
202 #define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */
203 #define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */
205 #define RCAR_CAN_NAPI_WEIGHT 4
206 #define MAX_STR_READS 0x100
208 static void tx_failure_cleanup(struct net_device
*ndev
)
212 for (i
= 0; i
< RCAR_CAN_FIFO_DEPTH
; i
++)
213 can_free_echo_skb(ndev
, i
);
216 static void rcar_can_error(struct net_device
*ndev
)
218 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
219 struct net_device_stats
*stats
= &ndev
->stats
;
220 struct can_frame
*cf
;
222 u8 eifr
, txerr
= 0, rxerr
= 0;
224 /* Propagate the error condition to the CAN stack */
225 skb
= alloc_can_err_skb(ndev
, &cf
);
227 eifr
= readb(&priv
->regs
->eifr
);
228 if (eifr
& (RCAR_CAN_EIFR_EWIF
| RCAR_CAN_EIFR_EPIF
)) {
229 txerr
= readb(&priv
->regs
->tecr
);
230 rxerr
= readb(&priv
->regs
->recr
);
232 cf
->can_id
|= CAN_ERR_CRTL
;
237 if (eifr
& RCAR_CAN_EIFR_BEIF
) {
238 int rx_errors
= 0, tx_errors
= 0;
241 netdev_dbg(priv
->ndev
, "Bus error interrupt:\n");
243 cf
->can_id
|= CAN_ERR_BUSERROR
| CAN_ERR_PROT
;
244 cf
->data
[2] = CAN_ERR_PROT_UNSPEC
;
246 ecsr
= readb(&priv
->regs
->ecsr
);
247 if (ecsr
& RCAR_CAN_ECSR_ADEF
) {
248 netdev_dbg(priv
->ndev
, "ACK Delimiter Error\n");
250 writeb(~RCAR_CAN_ECSR_ADEF
, &priv
->regs
->ecsr
);
252 cf
->data
[3] |= CAN_ERR_PROT_LOC_ACK_DEL
;
254 if (ecsr
& RCAR_CAN_ECSR_BE0F
) {
255 netdev_dbg(priv
->ndev
, "Bit Error (dominant)\n");
257 writeb(~RCAR_CAN_ECSR_BE0F
, &priv
->regs
->ecsr
);
259 cf
->data
[2] |= CAN_ERR_PROT_BIT0
;
261 if (ecsr
& RCAR_CAN_ECSR_BE1F
) {
262 netdev_dbg(priv
->ndev
, "Bit Error (recessive)\n");
264 writeb(~RCAR_CAN_ECSR_BE1F
, &priv
->regs
->ecsr
);
266 cf
->data
[2] |= CAN_ERR_PROT_BIT1
;
268 if (ecsr
& RCAR_CAN_ECSR_CEF
) {
269 netdev_dbg(priv
->ndev
, "CRC Error\n");
271 writeb(~RCAR_CAN_ECSR_CEF
, &priv
->regs
->ecsr
);
273 cf
->data
[3] |= CAN_ERR_PROT_LOC_CRC_SEQ
;
275 if (ecsr
& RCAR_CAN_ECSR_AEF
) {
276 netdev_dbg(priv
->ndev
, "ACK Error\n");
278 writeb(~RCAR_CAN_ECSR_AEF
, &priv
->regs
->ecsr
);
280 cf
->can_id
|= CAN_ERR_ACK
;
281 cf
->data
[3] |= CAN_ERR_PROT_LOC_ACK
;
284 if (ecsr
& RCAR_CAN_ECSR_FEF
) {
285 netdev_dbg(priv
->ndev
, "Form Error\n");
287 writeb(~RCAR_CAN_ECSR_FEF
, &priv
->regs
->ecsr
);
289 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
291 if (ecsr
& RCAR_CAN_ECSR_SEF
) {
292 netdev_dbg(priv
->ndev
, "Stuff Error\n");
294 writeb(~RCAR_CAN_ECSR_SEF
, &priv
->regs
->ecsr
);
296 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
299 priv
->can
.can_stats
.bus_error
++;
300 ndev
->stats
.rx_errors
+= rx_errors
;
301 ndev
->stats
.tx_errors
+= tx_errors
;
302 writeb(~RCAR_CAN_EIFR_BEIF
, &priv
->regs
->eifr
);
304 if (eifr
& RCAR_CAN_EIFR_EWIF
) {
305 netdev_dbg(priv
->ndev
, "Error warning interrupt\n");
306 priv
->can
.state
= CAN_STATE_ERROR_WARNING
;
307 priv
->can
.can_stats
.error_warning
++;
308 /* Clear interrupt condition */
309 writeb(~RCAR_CAN_EIFR_EWIF
, &priv
->regs
->eifr
);
311 cf
->data
[1] = txerr
> rxerr
? CAN_ERR_CRTL_TX_WARNING
:
312 CAN_ERR_CRTL_RX_WARNING
;
314 if (eifr
& RCAR_CAN_EIFR_EPIF
) {
315 netdev_dbg(priv
->ndev
, "Error passive interrupt\n");
316 priv
->can
.state
= CAN_STATE_ERROR_PASSIVE
;
317 priv
->can
.can_stats
.error_passive
++;
318 /* Clear interrupt condition */
319 writeb(~RCAR_CAN_EIFR_EPIF
, &priv
->regs
->eifr
);
321 cf
->data
[1] = txerr
> rxerr
? CAN_ERR_CRTL_TX_PASSIVE
:
322 CAN_ERR_CRTL_RX_PASSIVE
;
324 if (eifr
& RCAR_CAN_EIFR_BOEIF
) {
325 netdev_dbg(priv
->ndev
, "Bus-off entry interrupt\n");
326 tx_failure_cleanup(ndev
);
327 priv
->ier
= RCAR_CAN_IER_ERSIE
;
328 writeb(priv
->ier
, &priv
->regs
->ier
);
329 priv
->can
.state
= CAN_STATE_BUS_OFF
;
330 /* Clear interrupt condition */
331 writeb(~RCAR_CAN_EIFR_BOEIF
, &priv
->regs
->eifr
);
334 cf
->can_id
|= CAN_ERR_BUSOFF
;
336 if (eifr
& RCAR_CAN_EIFR_ORIF
) {
337 netdev_dbg(priv
->ndev
, "Receive overrun error interrupt\n");
338 ndev
->stats
.rx_over_errors
++;
339 ndev
->stats
.rx_errors
++;
340 writeb(~RCAR_CAN_EIFR_ORIF
, &priv
->regs
->eifr
);
342 cf
->can_id
|= CAN_ERR_CRTL
;
343 cf
->data
[1] = CAN_ERR_CRTL_RX_OVERFLOW
;
346 if (eifr
& RCAR_CAN_EIFR_OLIF
) {
347 netdev_dbg(priv
->ndev
,
348 "Overload Frame Transmission error interrupt\n");
349 ndev
->stats
.rx_over_errors
++;
350 ndev
->stats
.rx_errors
++;
351 writeb(~RCAR_CAN_EIFR_OLIF
, &priv
->regs
->eifr
);
353 cf
->can_id
|= CAN_ERR_PROT
;
354 cf
->data
[2] |= CAN_ERR_PROT_OVERLOAD
;
360 stats
->rx_bytes
+= cf
->can_dlc
;
365 static void rcar_can_tx_done(struct net_device
*ndev
)
367 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
368 struct net_device_stats
*stats
= &ndev
->stats
;
372 u8 unsent
= readb(&priv
->regs
->tfcr
);
374 unsent
= (unsent
& RCAR_CAN_TFCR_TFUST
) >>
375 RCAR_CAN_TFCR_TFUST_SHIFT
;
376 if (priv
->tx_head
- priv
->tx_tail
<= unsent
)
379 stats
->tx_bytes
+= priv
->tx_dlc
[priv
->tx_tail
%
380 RCAR_CAN_FIFO_DEPTH
];
381 priv
->tx_dlc
[priv
->tx_tail
% RCAR_CAN_FIFO_DEPTH
] = 0;
382 can_get_echo_skb(ndev
, priv
->tx_tail
% RCAR_CAN_FIFO_DEPTH
);
384 netif_wake_queue(ndev
);
386 /* Clear interrupt */
387 isr
= readb(&priv
->regs
->isr
);
388 writeb(isr
& ~RCAR_CAN_ISR_TXFF
, &priv
->regs
->isr
);
389 can_led_event(ndev
, CAN_LED_EVENT_TX
);
392 static irqreturn_t
rcar_can_interrupt(int irq
, void *dev_id
)
394 struct net_device
*ndev
= dev_id
;
395 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
398 isr
= readb(&priv
->regs
->isr
);
399 if (!(isr
& priv
->ier
))
402 if (isr
& RCAR_CAN_ISR_ERSF
)
403 rcar_can_error(ndev
);
405 if (isr
& RCAR_CAN_ISR_TXFF
)
406 rcar_can_tx_done(ndev
);
408 if (isr
& RCAR_CAN_ISR_RXFF
) {
409 if (napi_schedule_prep(&priv
->napi
)) {
410 /* Disable Rx FIFO interrupts */
411 priv
->ier
&= ~RCAR_CAN_IER_RXFIE
;
412 writeb(priv
->ier
, &priv
->regs
->ier
);
413 __napi_schedule(&priv
->napi
);
420 static void rcar_can_set_bittiming(struct net_device
*dev
)
422 struct rcar_can_priv
*priv
= netdev_priv(dev
);
423 struct can_bittiming
*bt
= &priv
->can
.bittiming
;
426 bcr
= RCAR_CAN_BCR_TSEG1(bt
->phase_seg1
+ bt
->prop_seg
- 1) |
427 RCAR_CAN_BCR_BPR(bt
->brp
- 1) | RCAR_CAN_BCR_SJW(bt
->sjw
- 1) |
428 RCAR_CAN_BCR_TSEG2(bt
->phase_seg2
- 1);
429 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
430 * All the registers are big-endian but they get byte-swapped on 32-bit
431 * read/write (but not on 8-bit, contrary to the manuals)...
433 writel((bcr
<< 8) | priv
->clock_select
, &priv
->regs
->bcr
);
436 static void rcar_can_start(struct net_device
*ndev
)
438 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
442 /* Set controller to known mode:
443 * - FIFO mailbox mode
444 * - accept all messages
446 * CAN is in sleep mode after MCU hardware or software reset.
448 ctlr
= readw(&priv
->regs
->ctlr
);
449 ctlr
&= ~RCAR_CAN_CTLR_SLPM
;
450 writew(ctlr
, &priv
->regs
->ctlr
);
451 /* Go to reset mode */
452 ctlr
|= RCAR_CAN_CTLR_CANM_FORCE_RESET
;
453 writew(ctlr
, &priv
->regs
->ctlr
);
454 for (i
= 0; i
< MAX_STR_READS
; i
++) {
455 if (readw(&priv
->regs
->str
) & RCAR_CAN_STR_RSTST
)
458 rcar_can_set_bittiming(ndev
);
459 ctlr
|= RCAR_CAN_CTLR_IDFM_MIXED
; /* Select mixed ID mode */
460 ctlr
|= RCAR_CAN_CTLR_BOM_ENT
; /* Entry to halt mode automatically */
462 ctlr
|= RCAR_CAN_CTLR_MBM
; /* Select FIFO mailbox mode */
463 ctlr
|= RCAR_CAN_CTLR_MLM
; /* Overrun mode */
464 writew(ctlr
, &priv
->regs
->ctlr
);
466 /* Accept all SID and EID */
467 writel(0, &priv
->regs
->mkr_2_9
[6]);
468 writel(0, &priv
->regs
->mkr_2_9
[7]);
469 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */
470 writel(0, &priv
->regs
->mkivlr1
);
471 /* Accept all frames */
472 writel(0, &priv
->regs
->fidcr
[0]);
473 writel(RCAR_CAN_FIDCR_IDE
| RCAR_CAN_FIDCR_RTR
, &priv
->regs
->fidcr
[1]);
474 /* Enable and configure FIFO mailbox interrupts */
475 writel(RCAR_CAN_MIER1_RXFIE
| RCAR_CAN_MIER1_TXFIE
, &priv
->regs
->mier1
);
477 priv
->ier
= RCAR_CAN_IER_ERSIE
| RCAR_CAN_IER_RXFIE
|
479 writeb(priv
->ier
, &priv
->regs
->ier
);
481 /* Accumulate error codes */
482 writeb(RCAR_CAN_ECSR_EDPM
, &priv
->regs
->ecsr
);
483 /* Enable error interrupts */
484 writeb(RCAR_CAN_EIER_EWIE
| RCAR_CAN_EIER_EPIE
| RCAR_CAN_EIER_BOEIE
|
485 (priv
->can
.ctrlmode
& CAN_CTRLMODE_BERR_REPORTING
?
486 RCAR_CAN_EIER_BEIE
: 0) | RCAR_CAN_EIER_ORIE
|
487 RCAR_CAN_EIER_OLIE
, &priv
->regs
->eier
);
488 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
490 /* Go to operation mode */
491 writew(ctlr
& ~RCAR_CAN_CTLR_CANM
, &priv
->regs
->ctlr
);
492 for (i
= 0; i
< MAX_STR_READS
; i
++) {
493 if (!(readw(&priv
->regs
->str
) & RCAR_CAN_STR_RSTST
))
496 /* Enable Rx and Tx FIFO */
497 writeb(RCAR_CAN_RFCR_RFE
, &priv
->regs
->rfcr
);
498 writeb(RCAR_CAN_TFCR_TFE
, &priv
->regs
->tfcr
);
501 static int rcar_can_open(struct net_device
*ndev
)
503 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
506 err
= clk_prepare_enable(priv
->clk
);
508 netdev_err(ndev
, "clk_prepare_enable() failed, error %d\n",
512 err
= open_candev(ndev
);
514 netdev_err(ndev
, "open_candev() failed, error %d\n", err
);
517 napi_enable(&priv
->napi
);
518 err
= request_irq(ndev
->irq
, rcar_can_interrupt
, 0, ndev
->name
, ndev
);
520 netdev_err(ndev
, "error requesting interrupt %x\n", ndev
->irq
);
523 can_led_event(ndev
, CAN_LED_EVENT_OPEN
);
524 rcar_can_start(ndev
);
525 netif_start_queue(ndev
);
528 napi_disable(&priv
->napi
);
531 clk_disable_unprepare(priv
->clk
);
536 static void rcar_can_stop(struct net_device
*ndev
)
538 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
542 /* Go to (force) reset mode */
543 ctlr
= readw(&priv
->regs
->ctlr
);
544 ctlr
|= RCAR_CAN_CTLR_CANM_FORCE_RESET
;
545 writew(ctlr
, &priv
->regs
->ctlr
);
546 for (i
= 0; i
< MAX_STR_READS
; i
++) {
547 if (readw(&priv
->regs
->str
) & RCAR_CAN_STR_RSTST
)
550 writel(0, &priv
->regs
->mier0
);
551 writel(0, &priv
->regs
->mier1
);
552 writeb(0, &priv
->regs
->ier
);
553 writeb(0, &priv
->regs
->eier
);
554 /* Go to sleep mode */
555 ctlr
|= RCAR_CAN_CTLR_SLPM
;
556 writew(ctlr
, &priv
->regs
->ctlr
);
557 priv
->can
.state
= CAN_STATE_STOPPED
;
560 static int rcar_can_close(struct net_device
*ndev
)
562 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
564 netif_stop_queue(ndev
);
566 free_irq(ndev
->irq
, ndev
);
567 napi_disable(&priv
->napi
);
568 clk_disable_unprepare(priv
->clk
);
570 can_led_event(ndev
, CAN_LED_EVENT_STOP
);
574 static netdev_tx_t
rcar_can_start_xmit(struct sk_buff
*skb
,
575 struct net_device
*ndev
)
577 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
578 struct can_frame
*cf
= (struct can_frame
*)skb
->data
;
581 if (can_dropped_invalid_skb(ndev
, skb
))
584 if (cf
->can_id
& CAN_EFF_FLAG
) /* Extended frame format */
585 data
= (cf
->can_id
& CAN_EFF_MASK
) | RCAR_CAN_IDE
;
586 else /* Standard frame format */
587 data
= (cf
->can_id
& CAN_SFF_MASK
) << RCAR_CAN_SID_SHIFT
;
589 if (cf
->can_id
& CAN_RTR_FLAG
) { /* Remote transmission request */
590 data
|= RCAR_CAN_RTR
;
592 for (i
= 0; i
< cf
->can_dlc
; i
++)
594 &priv
->regs
->mb
[RCAR_CAN_TX_FIFO_MBX
].data
[i
]);
597 writel(data
, &priv
->regs
->mb
[RCAR_CAN_TX_FIFO_MBX
].id
);
599 writeb(cf
->can_dlc
, &priv
->regs
->mb
[RCAR_CAN_TX_FIFO_MBX
].dlc
);
601 priv
->tx_dlc
[priv
->tx_head
% RCAR_CAN_FIFO_DEPTH
] = cf
->can_dlc
;
602 can_put_echo_skb(skb
, ndev
, priv
->tx_head
% RCAR_CAN_FIFO_DEPTH
);
604 /* Start Tx: write 0xff to the TFPCR register to increment
605 * the CPU-side pointer for the transmit FIFO to the next
608 writeb(0xff, &priv
->regs
->tfpcr
);
609 /* Stop the queue if we've filled all FIFO entries */
610 if (priv
->tx_head
- priv
->tx_tail
>= RCAR_CAN_FIFO_DEPTH
)
611 netif_stop_queue(ndev
);
616 static const struct net_device_ops rcar_can_netdev_ops
= {
617 .ndo_open
= rcar_can_open
,
618 .ndo_stop
= rcar_can_close
,
619 .ndo_start_xmit
= rcar_can_start_xmit
,
622 static void rcar_can_rx_pkt(struct rcar_can_priv
*priv
)
624 struct net_device_stats
*stats
= &priv
->ndev
->stats
;
625 struct can_frame
*cf
;
630 skb
= alloc_can_skb(priv
->ndev
, &cf
);
636 data
= readl(&priv
->regs
->mb
[RCAR_CAN_RX_FIFO_MBX
].id
);
637 if (data
& RCAR_CAN_IDE
)
638 cf
->can_id
= (data
& CAN_EFF_MASK
) | CAN_EFF_FLAG
;
640 cf
->can_id
= (data
>> RCAR_CAN_SID_SHIFT
) & CAN_SFF_MASK
;
642 dlc
= readb(&priv
->regs
->mb
[RCAR_CAN_RX_FIFO_MBX
].dlc
);
643 cf
->can_dlc
= get_can_dlc(dlc
);
644 if (data
& RCAR_CAN_RTR
) {
645 cf
->can_id
|= CAN_RTR_FLAG
;
647 for (dlc
= 0; dlc
< cf
->can_dlc
; dlc
++)
649 readb(&priv
->regs
->mb
[RCAR_CAN_RX_FIFO_MBX
].data
[dlc
]);
652 can_led_event(priv
->ndev
, CAN_LED_EVENT_RX
);
654 stats
->rx_bytes
+= cf
->can_dlc
;
656 netif_receive_skb(skb
);
659 static int rcar_can_rx_poll(struct napi_struct
*napi
, int quota
)
661 struct rcar_can_priv
*priv
= container_of(napi
,
662 struct rcar_can_priv
, napi
);
665 for (num_pkts
= 0; num_pkts
< quota
; num_pkts
++) {
668 isr
= readb(&priv
->regs
->isr
);
669 /* Clear interrupt bit */
670 if (isr
& RCAR_CAN_ISR_RXFF
)
671 writeb(isr
& ~RCAR_CAN_ISR_RXFF
, &priv
->regs
->isr
);
672 rfcr
= readb(&priv
->regs
->rfcr
);
673 if (rfcr
& RCAR_CAN_RFCR_RFEST
)
675 rcar_can_rx_pkt(priv
);
676 /* Write 0xff to the RFPCR register to increment
677 * the CPU-side pointer for the receive FIFO
678 * to the next mailbox location
680 writeb(0xff, &priv
->regs
->rfpcr
);
682 /* All packets processed */
683 if (num_pkts
< quota
) {
685 priv
->ier
|= RCAR_CAN_IER_RXFIE
;
686 writeb(priv
->ier
, &priv
->regs
->ier
);
691 static int rcar_can_do_set_mode(struct net_device
*ndev
, enum can_mode mode
)
695 rcar_can_start(ndev
);
696 netif_wake_queue(ndev
);
703 static int rcar_can_get_berr_counter(const struct net_device
*dev
,
704 struct can_berr_counter
*bec
)
706 struct rcar_can_priv
*priv
= netdev_priv(dev
);
709 err
= clk_prepare_enable(priv
->clk
);
712 bec
->txerr
= readb(&priv
->regs
->tecr
);
713 bec
->rxerr
= readb(&priv
->regs
->recr
);
714 clk_disable_unprepare(priv
->clk
);
718 static int rcar_can_probe(struct platform_device
*pdev
)
720 struct rcar_can_platform_data
*pdata
;
721 struct rcar_can_priv
*priv
;
722 struct net_device
*ndev
;
723 struct resource
*mem
;
728 pdata
= dev_get_platdata(&pdev
->dev
);
730 dev_err(&pdev
->dev
, "No platform data provided!\n");
734 irq
= platform_get_irq(pdev
, 0);
736 dev_err(&pdev
->dev
, "No IRQ resource\n");
740 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
741 addr
= devm_ioremap_resource(&pdev
->dev
, mem
);
747 ndev
= alloc_candev(sizeof(struct rcar_can_priv
), RCAR_CAN_FIFO_DEPTH
);
749 dev_err(&pdev
->dev
, "alloc_candev() failed\n");
754 priv
= netdev_priv(ndev
);
756 priv
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
757 if (IS_ERR(priv
->clk
)) {
758 err
= PTR_ERR(priv
->clk
);
759 dev_err(&pdev
->dev
, "cannot get clock: %d\n", err
);
763 ndev
->netdev_ops
= &rcar_can_netdev_ops
;
765 ndev
->flags
|= IFF_ECHO
;
768 priv
->clock_select
= pdata
->clock_select
;
769 priv
->can
.clock
.freq
= clk_get_rate(priv
->clk
);
770 priv
->can
.bittiming_const
= &rcar_can_bittiming_const
;
771 priv
->can
.do_set_mode
= rcar_can_do_set_mode
;
772 priv
->can
.do_get_berr_counter
= rcar_can_get_berr_counter
;
773 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_BERR_REPORTING
;
774 platform_set_drvdata(pdev
, ndev
);
775 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
777 netif_napi_add(ndev
, &priv
->napi
, rcar_can_rx_poll
,
778 RCAR_CAN_NAPI_WEIGHT
);
779 err
= register_candev(ndev
);
781 dev_err(&pdev
->dev
, "register_candev() failed, error %d\n",
786 devm_can_led_init(ndev
);
788 dev_info(&pdev
->dev
, "device registered (reg_base=%p, irq=%u)\n",
789 priv
->regs
, ndev
->irq
);
793 netif_napi_del(&priv
->napi
);
800 static int rcar_can_remove(struct platform_device
*pdev
)
802 struct net_device
*ndev
= platform_get_drvdata(pdev
);
803 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
805 unregister_candev(ndev
);
806 netif_napi_del(&priv
->napi
);
811 static int __maybe_unused
rcar_can_suspend(struct device
*dev
)
813 struct net_device
*ndev
= dev_get_drvdata(dev
);
814 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
817 if (netif_running(ndev
)) {
818 netif_stop_queue(ndev
);
819 netif_device_detach(ndev
);
821 ctlr
= readw(&priv
->regs
->ctlr
);
822 ctlr
|= RCAR_CAN_CTLR_CANM_HALT
;
823 writew(ctlr
, &priv
->regs
->ctlr
);
824 ctlr
|= RCAR_CAN_CTLR_SLPM
;
825 writew(ctlr
, &priv
->regs
->ctlr
);
826 priv
->can
.state
= CAN_STATE_SLEEPING
;
828 clk_disable(priv
->clk
);
832 static int __maybe_unused
rcar_can_resume(struct device
*dev
)
834 struct net_device
*ndev
= dev_get_drvdata(dev
);
835 struct rcar_can_priv
*priv
= netdev_priv(ndev
);
839 err
= clk_enable(priv
->clk
);
841 netdev_err(ndev
, "clk_enable() failed, error %d\n", err
);
845 ctlr
= readw(&priv
->regs
->ctlr
);
846 ctlr
&= ~RCAR_CAN_CTLR_SLPM
;
847 writew(ctlr
, &priv
->regs
->ctlr
);
848 ctlr
&= ~RCAR_CAN_CTLR_CANM
;
849 writew(ctlr
, &priv
->regs
->ctlr
);
850 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
852 if (netif_running(ndev
)) {
853 netif_device_attach(ndev
);
854 netif_start_queue(ndev
);
859 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops
, rcar_can_suspend
, rcar_can_resume
);
861 static struct platform_driver rcar_can_driver
= {
863 .name
= RCAR_CAN_DRV_NAME
,
864 .owner
= THIS_MODULE
,
865 .pm
= &rcar_can_pm_ops
,
867 .probe
= rcar_can_probe
,
868 .remove
= rcar_can_remove
,
871 module_platform_driver(rcar_can_driver
);
873 MODULE_AUTHOR("Cogent Embedded, Inc.");
874 MODULE_LICENSE("GPL");
875 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC");
876 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME
);