2 * Digi RightSwitch SE-X loadable device driver for Linux
4 * The RightSwitch is a 4 (EISA) or 6 (PCI) port etherswitch and
5 * a NIC on an internal board.
7 * Author: Rick Richardson, rick@remotepoint.com
8 * Derived from the SVR4.2 (UnixWare) driver for the same card.
10 * Copyright 1995-1996 Digi International Inc.
12 * This software may be used and distributed according to the terms
13 * of the GNU General Public License, incorporated herein by reference.
15 * For information on purchasing a RightSwitch SE-4 or SE-6
16 * board, please contact Digi's sales department at 1-612-912-3444
17 * or 1-800-DIGIBRD. Outside the U.S., please check our Web page
18 * at http://www.dgii.com for sales offices worldwide.
21 * When compiled as a loadable module, this driver can operate
22 * the board as either a 4/6 port switch with a 5th or 7th port
23 * that is a conventional NIC interface as far as the host is
24 * concerned, OR as 4/6 independent NICs. To select multi-NIC
25 * mode, add "nicmode=1" on the insmod load line for the driver.
27 * This driver uses the "dev" common ethernet device structure
28 * and a private "priv" (dev->priv) structure that contains
29 * mostly DGRS-specific information and statistics. To keep
30 * the code for both the switch mode and the multi-NIC mode
31 * as similar as possible, I have introduced the concept of
32 * "dev0"/"priv0" and "devN"/"privN" pointer pairs in subroutines
33 * where needed. The first pair of pointers points to the
34 * "dev" and "priv" structures of the zeroth (0th) device
35 * interface associated with a board. The second pair of
36 * pointers points to the current (Nth) device interface
37 * for the board: the one for which we are processing data.
39 * In switch mode, the pairs of pointers are always the same,
40 * that is, dev0 == devN and priv0 == privN. This is just
41 * like previous releases of this driver which did not support
44 * In multi-NIC mode, the pairs of pointers may be different.
45 * We use the devN and privN pointers to reference just the
46 * name, port number, and statistics for the current interface.
47 * We use the dev0 and priv0 pointers to access the variables
48 * that control access to the board, such as board address
49 * and simulated 82596 variables. This is because there is
50 * only one "fake" 82596 that serves as the interface to
51 * the board. We do not want to try to keep the variables
52 * associated with this 82596 in sync across all devices.
54 * This scheme works well. As you will see, except for
55 * initialization, there is very little difference between
56 * the two modes as far as this driver is concerned. On the
57 * receive side in NIC mode, the interrupt *always* comes in on
58 * the 0th interface (dev0/priv0). We then figure out which
59 * real 82596 port it came in on from looking at the "chan"
60 * member that the board firmware adds at the end of each
61 * RBD (a.k.a. TBD). We get the channel number like this:
62 * int chan = ((I596_RBD *) S2H(cbp->xmit.tbdp))->chan;
64 * On the transmit side in multi-NIC mode, we specify the
65 * output 82596 port by setting the new "dstchan" structure
66 * member that is at the end of the RFD, like this:
67 * priv0->rfdp->dstchan = privN->chan;
70 * - Multi-NIC mode is not yet supported when the driver is linked
72 * - Better handling of multicast addresses.
75 * Arnaldo Carvalho de Melo <acme@conectiva.com.br> - 11/01/2001
76 * - fix dgrs_found_device wrt checking kmalloc return and
77 * rollbacking the partial steps of the whole process when
78 * one of the devices can't be allocated. Fix SET_MODULE_OWNER
79 * on the loop to use devN instead of repeated calls to dev.
81 * davej <davej@suse.de> - 9/2/2001
82 * - Enable PCI device before reading ioaddr/irq
86 #include <linux/module.h>
87 #include <linux/eisa.h>
88 #include <linux/kernel.h>
89 #include <linux/string.h>
90 #include <linux/delay.h>
91 #include <linux/errno.h>
92 #include <linux/ioport.h>
93 #include <linux/slab.h>
94 #include <linux/interrupt.h>
95 #include <linux/pci.h>
96 #include <linux/init.h>
97 #include <linux/netdevice.h>
98 #include <linux/etherdevice.h>
99 #include <linux/skbuff.h>
100 #include <linux/bitops.h>
103 #include <asm/byteorder.h>
104 #include <asm/uaccess.h>
106 static char version
[] __initdata
=
107 "$Id: dgrs.c,v 1.13 2000/06/06 04:07:00 rick Exp $";
112 typedef unsigned char uchar
;
116 #include "dgrs_es4h.h"
117 #include "dgrs_plx9060.h"
118 #include "dgrs_i82596.h"
119 #include "dgrs_ether.h"
120 #include "dgrs_asstruct.h"
121 #include "dgrs_bcomm.h"
124 static struct pci_device_id dgrs_pci_tbl
[] = {
125 { SE6_PCI_VENDOR_ID
, SE6_PCI_DEVICE_ID
, PCI_ANY_ID
, PCI_ANY_ID
, },
126 { } /* Terminating entry */
128 MODULE_DEVICE_TABLE(pci
, dgrs_pci_tbl
);
132 static struct eisa_device_id dgrs_eisa_tbl
[] = {
136 MODULE_DEVICE_TABLE(eisa
, dgrs_eisa_tbl
);
139 MODULE_LICENSE("GPL");
143 * Firmware. Compiled separately for local compilation,
144 * but #included for Linux distribution.
147 #include "dgrs_firmware.c"
149 extern int dgrs_firmnum
;
150 extern char dgrs_firmver
[];
151 extern char dgrs_firmdate
[];
152 extern uchar dgrs_code
[];
153 extern int dgrs_ncode
;
157 * Linux out*() is backwards from all other operating systems
159 #define OUTB(ADDR, VAL) outb(VAL, ADDR)
160 #define OUTW(ADDR, VAL) outw(VAL, ADDR)
161 #define OUTL(ADDR, VAL) outl(VAL, ADDR)
164 * Macros to convert switch to host and host to switch addresses
165 * (assumes a local variable priv points to board dependent struct)
167 #define S2H(A) ( ((unsigned long)(A)&0x00ffffff) + priv0->vmem )
168 #define S2HN(A) ( ((unsigned long)(A)&0x00ffffff) + privN->vmem )
169 #define H2S(A) ( ((char *) (A) - priv0->vmem) + 0xA3000000 )
172 * Convert a switch address to a "safe" address for use with the
173 * PLX 9060 DMA registers and the associated HW kludge that allows
174 * for host access of the DMA registers.
176 #define S2DMA(A) ( (unsigned long)(A) & 0x00ffffff)
179 * "Space.c" variables, now settable from module interface
180 * Use the name below, minus the "dgrs_" prefix. See init_module().
182 static int dgrs_debug
= 1;
183 static int dgrs_dma
= 1;
184 static int dgrs_spantree
= -1;
185 static int dgrs_hashexpire
= -1;
186 static uchar dgrs_ipaddr
[4] = { 0xff, 0xff, 0xff, 0xff};
187 static uchar dgrs_iptrap
[4] = { 0xff, 0xff, 0xff, 0xff};
188 static __u32 dgrs_ipxnet
= -1;
189 static int dgrs_nicmode
;
192 * Private per-board data structure (dev->priv)
201 struct bios_comm
*bcomm
; /* Firmware BIOS comm structure */
202 PORT
*port
; /* Ptr to PORT[0] struct in VM */
203 I596_SCB
*scbp
; /* Ptr to SCB struct in VM */
204 I596_RFD
*rfdp
; /* Current RFD list */
205 I596_RBD
*rbdp
; /* Current RBD list */
207 volatile int intrcnt
; /* Count of interrupts */
210 * SE-4 (EISA) board variables
212 uchar is_reg
; /* EISA: Value for ES4H_IS reg */
215 * SE-6 (PCI) board variables
217 * The PLX "expansion rom" space is used for DMA register
218 * access from the host on the SE-6. These are the physical
219 * and virtual addresses of that space.
221 ulong plxreg
; /* Phys address of PLX chip */
222 char *vplxreg
; /* Virtual address of PLX chip */
223 ulong plxdma
; /* Phys addr of PLX "expansion rom" */
224 ulong
volatile *vplxdma
; /* Virtual addr of "expansion rom" */
225 int use_dma
; /* Flag: use DMA */
226 DMACHAIN
*dmadesc_s
; /* area for DMA chains (SW addr.) */
227 DMACHAIN
*dmadesc_h
; /* area for DMA chains (Host Virtual) */
230 * Multi-NIC mode variables
232 * All entries of the devtbl[] array are valid for the 0th
233 * device (i.e. eth0, but not eth1...eth5). devtbl[0] is
234 * valid for all devices (i.e. eth0, eth1, ..., eth5).
236 int nports
; /* Number of physical ports (4 or 6) */
237 int chan
; /* Channel # (1-6) for this device */
238 struct net_device
*devtbl
[6]; /* Ptrs to N device structs */
244 * reset or un-reset the IDT processor
247 proc_reset(struct net_device
*dev0
, int reset
)
249 DGRS_PRIV
*priv0
= (DGRS_PRIV
*) dev0
->priv
;
254 val
= inl(dev0
->base_addr
+ PLX_MISC_CSR
);
259 OUTL(dev0
->base_addr
+ PLX_MISC_CSR
, val
);
263 OUTB(dev0
->base_addr
+ ES4H_PC
, reset
? ES4H_PC_RESET
: 0);
268 * See if the board supports bus master DMA
271 check_board_dma(struct net_device
*dev0
)
273 DGRS_PRIV
*priv0
= (DGRS_PRIV
*) dev0
->priv
;
277 * If Space.c says not to use DMA, or if it's not a PLX based
278 * PCI board, or if the expansion ROM space is not PCI
279 * configured, then return false.
281 if (!dgrs_dma
|| !priv0
->plxreg
|| !priv0
->plxdma
)
285 * Set the local address remap register of the "expansion rom"
286 * area to 0x80000000 so that we can use it to access the DMA
287 * registers from the host side.
289 OUTL(dev0
->base_addr
+ PLX_ROM_BASE_ADDR
, 0x80000000);
292 * Set the PCI region descriptor to:
294 * disable read-prefetch
297 * 0 internal wait states
298 * Expansion ROM: (used for host DMA register access)
299 * disable read-prefetch
302 * 0 internal wait states
304 OUTL(dev0
->base_addr
+ PLX_BUS_REGION
, 0x49430343);
307 * Now map the DMA registers into our virtual space
309 priv0
->vplxdma
= (ulong
*) ioremap (priv0
->plxdma
, 256);
312 printk("%s: can't *remap() the DMA regs\n", dev0
->name
);
317 * Now test to see if we can access the DMA registers
318 * If we write -1 and get back 1FFF, then we accessed the
319 * DMA register. Otherwise, we probably have an old board
320 * and wrote into regular RAM.
322 priv0
->vplxdma
[PLX_DMA0_MODE
/4] = 0xFFFFFFFF;
323 x
= priv0
->vplxdma
[PLX_DMA0_MODE
/4];
324 if (x
!= 0x00001FFF) {
325 iounmap((void *)priv0
->vplxdma
);
333 * Initiate DMA using PLX part on PCI board. Spin the
334 * processor until completed. All addresses are physical!
336 * If pciaddr is NULL, then it's a chaining DMA, and lcladdr is
337 * the address of the first DMA descriptor in the chain.
339 * If pciaddr is not NULL, then it's a single DMA.
341 * In either case, "lcladdr" must have been fixed up to make
342 * sure the MSB isn't set using the S2DMA macro before passing
343 * the address to this routine.
347 struct net_device
*dev
,
356 DGRS_PRIV
*priv
= (DGRS_PRIV
*) dev
->priv
;
361 * Do a single, non-chain DMA
363 priv
->vplxdma
[PLX_DMA0_PCI_ADDR
/4] = pciaddr
;
364 priv
->vplxdma
[PLX_DMA0_LCL_ADDR
/4] = lcladdr
;
365 priv
->vplxdma
[PLX_DMA0_SIZE
/4] = len
;
366 priv
->vplxdma
[PLX_DMA0_DESCRIPTOR
/4] = to_host
367 ? PLX_DMA_DESC_TO_HOST
368 : PLX_DMA_DESC_TO_BOARD
;
369 priv
->vplxdma
[PLX_DMA0_MODE
/4] =
371 | PLX_DMA_MODE_WAITSTATES(0)
373 | PLX_DMA_MODE_NOBTERM
375 | PLX_DMA_MODE_NOCHAIN
;
382 priv
->vplxdma
[PLX_DMA0_MODE
/4] =
384 | PLX_DMA_MODE_WAITSTATES(0)
386 | PLX_DMA_MODE_NOBTERM
388 | PLX_DMA_MODE_CHAIN
;
389 priv
->vplxdma
[PLX_DMA0_DESCRIPTOR
/4] = lcladdr
;
392 priv
->vplxdma
[PLX_DMA_CSR
/4] =
393 PLX_DMA_CSR_0_ENABLE
| PLX_DMA_CSR_0_START
;
396 * Wait for DMA to complete
398 for (i
= 0; i
< 1000000; ++i
)
401 * Spin the host CPU for 1 usec, so we don't thrash
402 * the PCI bus while the PLX 9060 is doing DMA.
406 csr
= (volatile unsigned long) priv
->vplxdma
[PLX_DMA_CSR
/4];
408 if (csr
& PLX_DMA_CSR_0_DONE
)
412 if ( ! (csr
& PLX_DMA_CSR_0_DONE
) )
414 printk("%s: DMA done never occurred. DMA disabled.\n",
425 * Process a received frame. This is called from the interrupt
426 * routine, and works for both switch mode and multi-NIC mode.
428 * Note that when in multi-NIC mode, we want to always access the
429 * hardware using the dev and priv structures of the first port,
430 * so that we are using only one set of variables to maintain
431 * the board interface status, but we want to use the Nth port
432 * dev and priv structures to maintain statistics and to pass
435 * Only the first device structure is attached to the interrupt.
436 * We use the special "chan" variable at the end of the first RBD
437 * to select the Nth device in multi-NIC mode.
439 * We currently do chained DMA on a per-packet basis when the
440 * packet is "long", and we spin the CPU a short time polling
441 * for DMA completion. This avoids a second interrupt overhead,
442 * and gives the best performance for light traffic to the host.
444 * However, a better scheme that could be implemented would be
445 * to see how many packets are outstanding for the host, and if
446 * the number is "large", create a long chain to DMA several
447 * packets into the host in one go. In this case, we would set
448 * up some state variables to let the host CPU continue doing
449 * other things until a DMA completion interrupt comes along.
453 struct net_device
*dev0
,
463 struct net_device
*devN
;
467 * Determine Nth priv and dev structure pointers
470 { /* Multi-NIC mode */
471 int chan
= ((I596_RBD
*) S2H(cbp
->xmit
.tbdp
))->chan
;
473 devN
= priv0
->devtbl
[chan
-1];
475 * If devN is null, we got an interrupt before the I/F
476 * has been initialized. Pitch the packet.
480 privN
= (DGRS_PRIV
*) devN
->priv
;
488 if (0) printk("%s: rcv len=%ld\n", devN
->name
, cbp
->xmit
.count
);
491 * Allocate a message block big enough to hold the whole frame
493 len
= cbp
->xmit
.count
;
494 if ((skb
= dev_alloc_skb(len
+5)) == NULL
)
496 printk("%s: dev_alloc_skb failed for rcv buffer\n", devN
->name
);
497 ++dev0
->stats
.rx_dropped
;
498 /* discarding the frame */
501 skb_reserve(skb
, 2); /* Align IP header */
504 putp
= p
= skb_put(skb
, len
);
507 * There are three modes here for doing the packet copy.
508 * If we have DMA, and the packet is "long", we use the
509 * chaining mode of DMA. If it's shorter, we use single
510 * DMA's. Otherwise, we use memcpy().
512 if (priv0
->use_dma
&& priv0
->dmadesc_h
&& len
> 64)
515 * If we can use DMA and it's a long frame, copy it using
518 DMACHAIN
*ddp_h
; /* Host virtual DMA desc. pointer */
519 DMACHAIN
*ddp_s
; /* Switch physical DMA desc. pointer */
523 * Get the physical address of the STREAMS buffer.
524 * NOTE: allocb() guarantees that the whole buffer
525 * is in a single page if the length < 4096.
527 phys_p
= (uchar
*) virt_to_phys(putp
);
529 ddp_h
= priv0
->dmadesc_h
;
530 ddp_s
= priv0
->dmadesc_s
;
531 tbdp
= (I596_TBD
*) S2H(cbp
->xmit
.tbdp
);
538 amt
= count
& 0x3fff;
540 break; /* For safety */
541 if ( (p
-putp
) >= len
)
543 printk("%s: cbp = %lx\n", devN
->name
, (long) H2S(cbp
));
544 proc_reset(dev0
, 1); /* Freeze IDT */
545 break; /* For Safety */
548 ddp_h
->pciaddr
= (ulong
) phys_p
;
549 ddp_h
->lcladdr
= S2DMA(tbdp
->buf
);
555 if (count
& I596_TBD_EOF
)
557 ddp_h
->next
= PLX_DMA_DESC_TO_HOST
565 ddp_h
->next
= PLX_DMA_DESC_TO_HOST
567 tbdp
= (I596_TBD
*) S2H(tbdp
->next
);
571 if (ddp_h
- priv0
->dmadesc_h
)
575 rc
= do_plx_dma(dev0
,
576 0, (ulong
) priv0
->dmadesc_s
, len
, 0);
579 printk("%s: Chained DMA failure\n", devN
->name
);
584 else if (priv0
->use_dma
)
587 * If we can use DMA and it's a shorter frame, copy it
588 * using single DMA transfers.
593 * Get the physical address of the STREAMS buffer.
594 * NOTE: allocb() guarantees that the whole buffer
595 * is in a single page if the length < 4096.
597 phys_p
= (uchar
*) virt_to_phys(putp
);
599 tbdp
= (I596_TBD
*) S2H(cbp
->xmit
.tbdp
);
607 amt
= count
& 0x3fff;
609 break; /* For safety */
610 if ( (p
-putp
) >= len
)
612 printk("%s: cbp = %lx\n", devN
->name
, (long) H2S(cbp
));
613 proc_reset(dev0
, 1); /* Freeze IDT */
614 break; /* For Safety */
616 rc
= do_plx_dma(dev0
, (ulong
) phys_p
,
617 S2DMA(tbdp
->buf
), amt
, 1);
620 memcpy(p
, S2H(tbdp
->buf
), amt
);
621 printk("%s: Single DMA failed\n", devN
->name
);
625 if (count
& I596_TBD_EOF
)
627 tbdp
= (I596_TBD
*) S2H(tbdp
->next
);
633 * Otherwise, copy it piece by piece using memcpy()
635 tbdp
= (I596_TBD
*) S2H(cbp
->xmit
.tbdp
);
642 amt
= count
& 0x3fff;
644 break; /* For safety */
645 if ( (p
-putp
) >= len
)
647 printk("%s: cbp = %lx\n", devN
->name
, (long) H2S(cbp
));
648 proc_reset(dev0
, 1); /* Freeze IDT */
649 break; /* For Safety */
651 memcpy(p
, S2H(tbdp
->buf
), amt
);
653 if (count
& I596_TBD_EOF
)
655 tbdp
= (I596_TBD
*) S2H(tbdp
->next
);
660 * Pass the frame to upper half
662 skb
->protocol
= eth_type_trans(skb
, devN
);
664 devN
->last_rx
= jiffies
;
665 ++devN
->stats
.rx_packets
;
666 devN
->stats
.rx_bytes
+= len
;
669 cbp
->xmit
.status
= I596_CB_STATUS_C
| I596_CB_STATUS_OK
;
673 * Start transmission of a frame
675 * The interface to the board is simple: we pretend that we are
676 * a fifth 82596 ethernet controller 'receiving' data, and copy the
677 * data into the same structures that a real 82596 would. This way,
678 * the board firmware handles the host 'port' the same as any other.
680 * NOTE: we do not use Bus master DMA for this routine. Turns out
681 * that it is not needed. Slave writes over the PCI bus are about
682 * as fast as DMA, due to the fact that the PLX part can do burst
683 * writes. The same is not true for data being read from the board.
685 * For multi-NIC mode, we tell the firmware the desired 82596
686 * output port by setting the special "dstchan" member at the
687 * end of the traditional 82596 RFD structure.
690 static int dgrs_start_xmit(struct sk_buff
*skb
, struct net_device
*devN
)
692 DGRS_PRIV
*privN
= (DGRS_PRIV
*) devN
->priv
;
693 struct net_device
*dev0
;
700 * Determine 0th priv and dev structure pointers
704 dev0
= privN
->devtbl
[0];
705 priv0
= (DGRS_PRIV
*) dev0
->priv
;
714 printk("%s: xmit len=%d\n", devN
->name
, (int) skb
->len
);
716 devN
->trans_start
= jiffies
;
717 netif_start_queue(devN
);
719 if (priv0
->rfdp
->cmd
& I596_RFD_EL
)
721 if (0) printk("%s: NO RFD's\n", devN
->name
);
727 priv0
->rfdp
->rbdp
= (I596_RBD
*) H2S(rbdp
);
729 i
= 0; len
= skb
->len
;
732 if (rbdp
->size
& I596_RBD_EL
)
734 if (0) printk("%s: NO RBD's\n", devN
->name
);
738 amt
= min_t(unsigned int, len
, rbdp
->size
- count
);
739 skb_copy_from_linear_data_offset(skb
, i
, S2H(rbdp
->buf
) + count
, amt
);
746 rbdp
->count
= 60 | I596_RBD_EOF
;
748 rbdp
->count
= count
| I596_RBD_EOF
;
749 rbdp
= (I596_RBD
*) S2H(rbdp
->next
);
754 /* More data to come, but we used less than 32
755 * bytes of this RBD. Keep filling this RBD.
757 {} /* Yes, we do nothing here */
762 rbdp
= (I596_RBD
*) S2H(rbdp
->next
);
770 priv0
->rfdp
->dstchan
= privN
->chan
;
771 priv0
->rfdp
->status
= I596_RFD_C
| I596_RFD_OK
;
772 priv0
->rfdp
= (I596_RFD
*) S2H(priv0
->rfdp
->next
);
774 ++devN
->stats
.tx_packets
;
780 priv0
->scbp
->status
|= I596_SCB_RNR
; /* simulate I82596 */
788 dgrs_open( struct net_device
*dev
)
790 netif_start_queue(dev
);
795 * Close the interface
797 static int dgrs_close( struct net_device
*dev
)
799 netif_stop_queue(dev
);
804 * Set multicast list and/or promiscuous mode
807 static void dgrs_set_multicast_list( struct net_device
*dev
)
809 DGRS_PRIV
*priv
= (DGRS_PRIV
*) dev
->priv
;
811 priv
->port
->is_promisc
= (dev
->flags
& IFF_PROMISC
) ? 1 : 0;
817 static int dgrs_ioctl(struct net_device
*devN
, struct ifreq
*ifr
, int cmd
)
819 DGRS_PRIV
*privN
= (DGRS_PRIV
*) devN
->priv
;
823 if (cmd
!= DGRSIOCTL
)
826 if(copy_from_user(&ioc
, ifr
->ifr_data
, sizeof(DGRS_IOCTL
)))
832 if (ioc
.len
!= sizeof(ulong
))
834 if(copy_to_user(ioc
.data
, &devN
->mem_start
, ioc
.len
))
838 if (!capable(CAP_NET_ADMIN
))
840 if (ioc
.port
> privN
->bcomm
->bc_nports
)
842 if (ioc
.filter
>= NFILTERS
)
844 if (ioc
.len
> privN
->bcomm
->bc_filter_area_len
)
847 /* Wait for old command to finish */
848 for (i
= 0; i
< 1000; ++i
)
850 if ( (volatile long) privN
->bcomm
->bc_filter_cmd
<= 0 )
857 privN
->bcomm
->bc_filter_port
= ioc
.port
;
858 privN
->bcomm
->bc_filter_num
= ioc
.filter
;
859 privN
->bcomm
->bc_filter_len
= ioc
.len
;
863 if(copy_from_user(S2HN(privN
->bcomm
->bc_filter_area
),
866 privN
->bcomm
->bc_filter_cmd
= BC_FILTER_SET
;
869 privN
->bcomm
->bc_filter_cmd
= BC_FILTER_CLR
;
879 * dev, priv will always refer to the 0th device in Multi-NIC mode.
882 static irqreturn_t
dgrs_intr(int irq
, void *dev_id
)
884 struct net_device
*dev0
= dev_id
;
885 DGRS_PRIV
*priv0
= dev0
->priv
;
891 if (1) ++priv0
->bcomm
->bc_cnt
[4];
894 static int cnt
= 100;
896 printk("%s: interrupt: irq %d\n", dev0
->name
, irq
);
902 cmd
= priv0
->scbp
->cmd
;
905 * See if RU has been restarted
907 if ( (cmd
& I596_SCB_RUC
) == I596_SCB_RUC_START
)
909 if (0) printk("%s: RUC start\n", dev0
->name
);
910 priv0
->rfdp
= (I596_RFD
*) S2H(priv0
->scbp
->rfdp
);
911 priv0
->rbdp
= (I596_RBD
*) S2H(priv0
->rfdp
->rbdp
);
912 priv0
->scbp
->status
&= ~(I596_SCB_RNR
|I596_SCB_RUS
);
914 * Tell upper half (halves)
918 for (i
= 0; i
< priv0
->nports
; ++i
)
919 netif_wake_queue (priv0
->devtbl
[i
]);
922 netif_wake_queue (dev0
);
923 /* if (bd->flags & TX_QUEUED)
924 DL_sched(bd, bdd); */
928 * See if any CU commands to process
930 if ( (cmd
& I596_SCB_CUC
) != I596_SCB_CUC_START
)
932 priv0
->scbp
->cmd
= 0; /* Ignore all other commands */
935 priv0
->scbp
->status
&= ~(I596_SCB_CNA
|I596_SCB_CUS
);
940 cbp
= (I596_CB
*) S2H(priv0
->scbp
->cbp
);
941 priv0
->scbp
->cmd
= 0; /* Safe to clear the command */
944 switch (cbp
->nop
.cmd
& I596_CB_CMD
)
946 case I596_CB_CMD_XMIT
:
947 dgrs_rcv_frame(dev0
, priv0
, cbp
);
950 cbp
->nop
.status
= I596_CB_STATUS_C
| I596_CB_STATUS_OK
;
953 if (cbp
->nop
.cmd
& I596_CB_CMD_EL
)
955 cbp
= (I596_CB
*) S2H(cbp
->nop
.next
);
957 priv0
->scbp
->status
|= I596_SCB_CNA
;
964 OUTL(dev0
->base_addr
+ PLX_LCL2PCI_DOORBELL
, 1);
970 * Download the board firmware
973 dgrs_download(struct net_device
*dev0
)
975 DGRS_PRIV
*priv0
= (DGRS_PRIV
*) dev0
->priv
;
979 static const int iv2is
[16] = {
980 0, 0, 0, ES4H_IS_INT3
,
981 0, ES4H_IS_INT5
, 0, ES4H_IS_INT7
,
982 0, 0, ES4H_IS_INT10
, ES4H_IS_INT11
,
983 ES4H_IS_INT12
, 0, 0, ES4H_IS_INT15
};
986 * Map in the dual port memory
988 priv0
->vmem
= ioremap(dev0
->mem_start
, 2048*1024);
991 printk("%s: cannot map in board memory\n", dev0
->name
);
996 * Hold the processor and configure the board addresses
1000 proc_reset(dev0
, 1);
1004 is
= iv2is
[dev0
->irq
& 0x0f];
1007 printk("%s: Illegal IRQ %d\n", dev0
->name
, dev0
->irq
);
1008 iounmap(priv0
->vmem
);
1012 OUTB(dev0
->base_addr
+ ES4H_AS_31_24
,
1013 (uchar
) (dev0
->mem_start
>> 24) );
1014 OUTB(dev0
->base_addr
+ ES4H_AS_23_16
,
1015 (uchar
) (dev0
->mem_start
>> 16) );
1016 priv0
->is_reg
= ES4H_IS_LINEAR
| is
|
1017 ((uchar
) (dev0
->mem_start
>> 8) & ES4H_IS_AS15
);
1018 OUTB(dev0
->base_addr
+ ES4H_IS
, priv0
->is_reg
);
1019 OUTB(dev0
->base_addr
+ ES4H_EC
, ES4H_EC_ENABLE
);
1020 OUTB(dev0
->base_addr
+ ES4H_PC
, ES4H_PC_RESET
);
1021 OUTB(dev0
->base_addr
+ ES4H_MW
, ES4H_MW_ENABLE
| 0x00);
1025 * See if we can do DMA on the SE-6
1027 priv0
->use_dma
= check_board_dma(dev0
);
1029 printk("%s: Bus Master DMA is enabled.\n", dev0
->name
);
1032 * Load and verify the code at the desired address
1034 memcpy(priv0
->vmem
, dgrs_code
, dgrs_ncode
); /* Load code */
1035 if (memcmp(priv0
->vmem
, dgrs_code
, dgrs_ncode
))
1037 iounmap(priv0
->vmem
);
1039 printk("%s: download compare failed\n", dev0
->name
);
1046 priv0
->bcomm
= (struct bios_comm
*) (priv0
->vmem
+ 0x0100);
1047 priv0
->bcomm
->bc_nowait
= 1; /* Tell board to make printf not wait */
1048 priv0
->bcomm
->bc_squelch
= 0; /* Flag from Space.c */
1049 priv0
->bcomm
->bc_150ohm
= 0; /* Flag from Space.c */
1051 priv0
->bcomm
->bc_spew
= 0; /* Debug flag from Space.c */
1052 priv0
->bcomm
->bc_maxrfd
= 0; /* Debug flag from Space.c */
1053 priv0
->bcomm
->bc_maxrbd
= 0; /* Debug flag from Space.c */
1056 * Tell board we are operating in switch mode (1) or in
1057 * multi-NIC mode (2).
1059 priv0
->bcomm
->bc_host
= dgrs_nicmode
? BC_MULTINIC
: BC_SWITCH
;
1062 * Request memory space on board for DMA chains
1065 priv0
->bcomm
->bc_hostarea_len
= (2048/64) * 16;
1068 * NVRAM configurables from Space.c
1070 priv0
->bcomm
->bc_spantree
= dgrs_spantree
;
1071 priv0
->bcomm
->bc_hashexpire
= dgrs_hashexpire
;
1072 memcpy(priv0
->bcomm
->bc_ipaddr
, dgrs_ipaddr
, 4);
1073 memcpy(priv0
->bcomm
->bc_iptrap
, dgrs_iptrap
, 4);
1074 memcpy(priv0
->bcomm
->bc_ipxnet
, &dgrs_ipxnet
, 4);
1077 * Release processor, wait 8 seconds for board to initialize
1079 proc_reset(dev0
, 0);
1081 for (i
= jiffies
+ 8 * HZ
; time_after(i
, jiffies
); )
1083 barrier(); /* Gcc 2.95 needs this */
1084 if (priv0
->bcomm
->bc_status
>= BC_RUN
)
1088 if (priv0
->bcomm
->bc_status
< BC_RUN
)
1090 printk("%s: board not operating\n", dev0
->name
);
1091 iounmap(priv0
->vmem
);
1096 priv0
->port
= (PORT
*) S2H(priv0
->bcomm
->bc_port
);
1097 priv0
->scbp
= (I596_SCB
*) S2H(priv0
->port
->scbp
);
1098 priv0
->rfdp
= (I596_RFD
*) S2H(priv0
->scbp
->rfdp
);
1099 priv0
->rbdp
= (I596_RBD
*) S2H(priv0
->rfdp
->rbdp
);
1101 priv0
->scbp
->status
= I596_SCB_CNA
; /* CU is idle */
1104 * Get switch physical and host virtual pointers to DMA
1105 * chaining area. NOTE: the MSB of the switch physical
1106 * address *must* be turned off. Otherwise, the HW kludge
1107 * that allows host access of the PLX DMA registers will
1108 * erroneously select the PLX registers.
1110 priv0
->dmadesc_s
= (DMACHAIN
*) S2DMA(priv0
->bcomm
->bc_hostarea
);
1111 if (priv0
->dmadesc_s
)
1112 priv0
->dmadesc_h
= (DMACHAIN
*) S2H(priv0
->dmadesc_s
);
1114 priv0
->dmadesc_h
= NULL
;
1117 * Enable board interrupts
1121 OUTL(dev0
->base_addr
+ PLX_INT_CSR
,
1122 inl(dev0
->base_addr
+ PLX_INT_CSR
)
1123 | PLX_PCI_DOORBELL_IE
); /* Enable intr to host */
1124 OUTL(dev0
->base_addr
+ PLX_LCL2PCI_DOORBELL
, 1);
1134 * Probe (init) a board
1137 dgrs_probe1(struct net_device
*dev
)
1139 DGRS_PRIV
*priv
= (DGRS_PRIV
*) dev
->priv
;
1143 printk("%s: Digi RightSwitch io=%lx mem=%lx irq=%d plx=%lx dma=%lx\n",
1144 dev
->name
, dev
->base_addr
, dev
->mem_start
, dev
->irq
,
1145 priv
->plxreg
, priv
->plxdma
);
1148 * Download the firmware and light the processor
1150 rc
= dgrs_download(dev
);
1155 * Get ether address of board
1157 printk("%s: Ethernet address", dev
->name
);
1158 memcpy(dev
->dev_addr
, priv
->port
->ethaddr
, 6);
1159 for (i
= 0; i
< 6; ++i
)
1160 printk("%c%2.2x", i
? ':' : ' ', dev
->dev_addr
[i
]);
1163 if (dev
->dev_addr
[0] & 1)
1165 printk("%s: Illegal Ethernet Address\n", dev
->name
);
1171 * ACK outstanding interrupts, hook the interrupt,
1172 * and verify that we are getting interrupts from the board.
1175 OUTL(dev
->base_addr
+ PLX_LCL2PCI_DOORBELL
, 1);
1177 rc
= request_irq(dev
->irq
, &dgrs_intr
, IRQF_SHARED
, "RightSwitch", dev
);
1182 for (i
= jiffies
+ 2*HZ
+ HZ
/2; time_after(i
, jiffies
); )
1185 if (priv
->intrcnt
>= 2)
1188 if (priv
->intrcnt
< 2)
1190 printk(KERN_ERR
"%s: Not interrupting on IRQ %d (%d)\n",
1191 dev
->name
, dev
->irq
, priv
->intrcnt
);
1199 dev
->open
= &dgrs_open
;
1200 dev
->stop
= &dgrs_close
;
1201 dev
->hard_start_xmit
= &dgrs_start_xmit
;
1202 dev
->set_multicast_list
= &dgrs_set_multicast_list
;
1203 dev
->do_ioctl
= &dgrs_ioctl
;
1208 free_irq(dev
->irq
, dev
);
1214 dgrs_initclone(struct net_device
*dev
)
1216 DGRS_PRIV
*priv
= (DGRS_PRIV
*) dev
->priv
;
1219 printk("%s: Digi RightSwitch port %d ",
1220 dev
->name
, priv
->chan
);
1221 for (i
= 0; i
< 6; ++i
)
1222 printk("%c%2.2x", i
? ':' : ' ', dev
->dev_addr
[i
]);
1228 static struct net_device
* __init
1239 struct net_device
*dev
;
1240 int i
, ret
= -ENOMEM
;
1242 dev
= alloc_etherdev(sizeof(DGRS_PRIV
));
1246 priv
= (DGRS_PRIV
*)dev
->priv
;
1248 dev
->base_addr
= io
;
1249 dev
->mem_start
= mem
;
1250 dev
->mem_end
= mem
+ 2048 * 1024 - 1;
1252 priv
->plxreg
= plxreg
;
1253 priv
->plxdma
= plxdma
;
1254 priv
->vplxdma
= NULL
;
1257 priv
->devtbl
[0] = dev
;
1259 SET_NETDEV_DEV(dev
, pdev
);
1261 ret
= dgrs_probe1(dev
);
1265 ret
= register_netdev(dev
);
1269 if ( !dgrs_nicmode
)
1270 return dev
; /* Switch mode, we are done */
1273 * Operating card as N separate NICs
1276 priv
->nports
= priv
->bcomm
->bc_nports
;
1278 for (i
= 1; i
< priv
->nports
; ++i
)
1280 struct net_device
*devN
;
1282 /* Allocate new dev and priv structures */
1283 devN
= alloc_etherdev(sizeof(DGRS_PRIV
));
1288 /* Don't copy the network device structure! */
1290 /* copy the priv structure of dev[0] */
1291 privN
= (DGRS_PRIV
*)devN
->priv
;
1294 /* ... and zero out VM areas */
1296 privN
->vplxdma
= NULL
;
1297 /* ... and zero out IRQ */
1299 /* ... and base MAC address off address of 1st port */
1300 devN
->dev_addr
[5] += i
;
1302 ret
= dgrs_initclone(devN
);
1306 SET_NETDEV_DEV(dev
, pdev
);
1308 ret
= register_netdev(devN
);
1314 priv
->devtbl
[i
] = devN
;
1320 struct net_device
*d
= priv
->devtbl
[i
--];
1321 unregister_netdev(d
);
1326 free_irq(dev
->irq
, dev
);
1330 return ERR_PTR(ret
);
1333 static void __devexit
dgrs_remove(struct net_device
*dev
)
1335 DGRS_PRIV
*priv
= dev
->priv
;
1338 unregister_netdev(dev
);
1340 for (i
= 1; i
< priv
->nports
; ++i
) {
1341 struct net_device
*d
= priv
->devtbl
[i
];
1343 unregister_netdev(d
);
1348 proc_reset(priv
->devtbl
[0], 1);
1351 iounmap(priv
->vmem
);
1353 iounmap((uchar
*) priv
->vplxdma
);
1356 free_irq(dev
->irq
, dev
);
1358 for (i
= 1; i
< priv
->nports
; ++i
) {
1359 if (priv
->devtbl
[i
])
1360 unregister_netdev(priv
->devtbl
[i
]);
1365 static int __init
dgrs_pci_probe(struct pci_dev
*pdev
,
1366 const struct pci_device_id
*ent
)
1368 struct net_device
*dev
;
1377 * Get and check the bus-master and latency values.
1378 * Some PCI BIOSes fail to set the master-enable bit,
1379 * and the latency timer must be set to the maximum
1380 * value to avoid data corruption that occurs when the
1381 * timer expires during a transfer. Yes, it's a bug.
1383 err
= pci_enable_device(pdev
);
1386 err
= pci_request_regions(pdev
, "RightSwitch");
1390 pci_set_master(pdev
);
1392 plxreg
= pci_resource_start (pdev
, 0);
1393 io
= pci_resource_start (pdev
, 1);
1394 mem
= pci_resource_start (pdev
, 2);
1395 pci_read_config_dword(pdev
, 0x30, &plxdma
);
1400 * On some BIOSES, the PLX "expansion rom" (used for DMA)
1401 * address comes up as "0". This is probably because
1402 * the BIOS doesn't see a valid 55 AA ROM signature at
1403 * the "ROM" start and zeroes the address. To get
1404 * around this problem the SE-6 is configured to ask
1405 * for 4 MB of space for the dual port memory. We then
1406 * must set its range back to 2 MB, and use the upper
1407 * half for DMA register access
1409 OUTL(io
+ PLX_SPACE0_RANGE
, 0xFFE00000L
);
1411 plxdma
= mem
+ (2048L * 1024L);
1412 pci_write_config_dword(pdev
, 0x30, plxdma
+ 1);
1413 pci_read_config_dword(pdev
, 0x30, &plxdma
);
1416 dev
= dgrs_found_device(io
, mem
, irq
, plxreg
, plxdma
, &pdev
->dev
);
1418 pci_release_regions(pdev
);
1419 return PTR_ERR(dev
);
1422 pci_set_drvdata(pdev
, dev
);
1426 static void __devexit
dgrs_pci_remove(struct pci_dev
*pdev
)
1428 struct net_device
*dev
= pci_get_drvdata(pdev
);
1431 pci_release_regions(pdev
);
1435 static struct pci_driver dgrs_pci_driver
= {
1437 .id_table
= dgrs_pci_tbl
,
1438 .probe
= dgrs_pci_probe
,
1439 .remove
= __devexit_p(dgrs_pci_remove
),
1442 static struct pci_driver dgrs_pci_driver
= {};
1447 static int is2iv
[8] __initdata
= { 0, 3, 5, 7, 10, 11, 12, 15 };
1449 static int __init
dgrs_eisa_probe (struct device
*gendev
)
1451 struct net_device
*dev
;
1452 struct eisa_device
*edev
= to_eisa_device(gendev
);
1453 uint io
= edev
->base_addr
;
1456 int rc
= -ENODEV
; /* Not EISA configured */
1458 if (!request_region(io
, 256, "RightSwitch")) {
1459 printk(KERN_ERR
"dgrs: eisa io 0x%x, which is busy.\n", io
);
1463 if ( ! (inb(io
+ES4H_EC
) & ES4H_EC_ENABLE
) )
1466 mem
= (inb(io
+ES4H_AS_31_24
) << 24)
1467 + (inb(io
+ES4H_AS_23_16
) << 16);
1469 irq
= is2iv
[ inb(io
+ES4H_IS
) & ES4H_IS_INTMASK
];
1471 dev
= dgrs_found_device(io
, mem
, irq
, 0L, 0L, gendev
);
1477 gendev
->driver_data
= dev
;
1480 release_region(io
, 256);
1484 static int __devexit
dgrs_eisa_remove(struct device
*gendev
)
1486 struct net_device
*dev
= gendev
->driver_data
;
1490 release_region(dev
->base_addr
, 256);
1497 static struct eisa_driver dgrs_eisa_driver
= {
1498 .id_table
= dgrs_eisa_tbl
,
1501 .probe
= dgrs_eisa_probe
,
1502 .remove
= __devexit_p(dgrs_eisa_remove
),
1508 * Variables that can be overriden from module command line
1510 static int debug
= -1;
1511 static int dma
= -1;
1512 static int hashexpire
= -1;
1513 static int spantree
= -1;
1514 static int ipaddr
[4] = { -1 };
1515 static int iptrap
[4] = { -1 };
1516 static __u32 ipxnet
= -1;
1517 static int nicmode
= -1;
1519 module_param(debug
, int, 0);
1520 module_param(dma
, int, 0);
1521 module_param(hashexpire
, int, 0);
1522 module_param(spantree
, int, 0);
1523 module_param_array(ipaddr
, int, NULL
, 0);
1524 module_param_array(iptrap
, int, NULL
, 0);
1525 module_param(ipxnet
, int, 0);
1526 module_param(nicmode
, int, 0);
1527 MODULE_PARM_DESC(debug
, "Digi RightSwitch enable debugging (0-1)");
1528 MODULE_PARM_DESC(dma
, "Digi RightSwitch enable BM DMA (0-1)");
1529 MODULE_PARM_DESC(nicmode
, "Digi RightSwitch operating mode (1: switch, 2: multi-NIC)");
1531 static int __init
dgrs_init_module (void)
1537 * Command line variable overrides
1552 dgrs_nicmode
= nicmode
;
1553 if (hashexpire
>= 0)
1554 dgrs_hashexpire
= hashexpire
;
1556 dgrs_spantree
= spantree
;
1557 if (ipaddr
[0] != -1)
1558 for (i
= 0; i
< 4; ++i
)
1559 dgrs_ipaddr
[i
] = ipaddr
[i
];
1560 if (iptrap
[0] != -1)
1561 for (i
= 0; i
< 4; ++i
)
1562 dgrs_iptrap
[i
] = iptrap
[i
];
1564 dgrs_ipxnet
= htonl( ipxnet
);
1568 printk(KERN_INFO
"dgrs: SW=%s FW=Build %d %s\nFW Version=%s\n",
1569 version
, dgrs_firmnum
, dgrs_firmdate
, dgrs_firmver
);
1573 * Find and configure all the cards
1576 err
= eisa_driver_register(&dgrs_eisa_driver
);
1580 err
= pci_register_driver(&dgrs_pci_driver
);
1586 static void __exit
dgrs_cleanup_module (void)
1589 eisa_driver_unregister (&dgrs_eisa_driver
);
1592 pci_unregister_driver (&dgrs_pci_driver
);
1596 module_init(dgrs_init_module
);
1597 module_exit(dgrs_cleanup_module
);