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[mirror_ubuntu-zesty-kernel.git] / drivers / net / dm9000.c
1 /*
2 * Davicom DM9000 Fast Ethernet driver for Linux.
3 * Copyright (C) 1997 Sten Wang
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
16 *
17 * Additional updates, Copyright:
18 * Ben Dooks <ben@simtec.co.uk>
19 * Sascha Hauer <s.hauer@pengutronix.de>
20 */
21
22 #include <linux/module.h>
23 #include <linux/ioport.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/init.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
29 #include <linux/crc32.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/dm9000.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/irq.h>
36
37 #include <asm/delay.h>
38 #include <asm/irq.h>
39 #include <asm/io.h>
40
41 #include "dm9000.h"
42
43 /* Board/System/Debug information/definition ---------------- */
44
45 #define DM9000_PHY 0x40 /* PHY address 0x01 */
46
47 #define CARDNAME "dm9000"
48 #define PFX CARDNAME ": "
49 #define DRV_VERSION "1.30"
50
51 #ifdef CONFIG_BLACKFIN
52 #define readsb insb
53 #define readsw insw
54 #define readsl insl
55 #define writesb outsb
56 #define writesw outsw
57 #define writesl outsl
58 #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH
59 #else
60 #define DEFAULT_TRIGGER (0)
61 #endif
62
63 /*
64 * Transmit timeout, default 5 seconds.
65 */
66 static int watchdog = 5000;
67 module_param(watchdog, int, 0400);
68 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
69
70 /* DM9000 register address locking.
71 *
72 * The DM9000 uses an address register to control where data written
73 * to the data register goes. This means that the address register
74 * must be preserved over interrupts or similar calls.
75 *
76 * During interrupt and other critical calls, a spinlock is used to
77 * protect the system, but the calls themselves save the address
78 * in the address register in case they are interrupting another
79 * access to the device.
80 *
81 * For general accesses a lock is provided so that calls which are
82 * allowed to sleep are serialised so that the address register does
83 * not need to be saved. This lock also serves to serialise access
84 * to the EEPROM and PHY access registers which are shared between
85 * these two devices.
86 */
87
88 /* Structure/enum declaration ------------------------------- */
89 typedef struct board_info {
90
91 void __iomem *io_addr; /* Register I/O base address */
92 void __iomem *io_data; /* Data I/O address */
93 u16 irq; /* IRQ */
94
95 u16 tx_pkt_cnt;
96 u16 queue_pkt_len;
97 u16 queue_start_addr;
98 u16 dbug_cnt;
99 u8 io_mode; /* 0:word, 2:byte */
100 u8 phy_addr;
101 unsigned int flags;
102 unsigned int in_suspend :1;
103
104 int debug_level;
105
106 void (*inblk)(void __iomem *port, void *data, int length);
107 void (*outblk)(void __iomem *port, void *data, int length);
108 void (*dumpblk)(void __iomem *port, int length);
109
110 struct device *dev; /* parent device */
111
112 struct resource *addr_res; /* resources found */
113 struct resource *data_res;
114 struct resource *addr_req; /* resources requested */
115 struct resource *data_req;
116 struct resource *irq_res;
117
118 struct mutex addr_lock; /* phy and eeprom access lock */
119
120 struct delayed_work phy_poll;
121 struct net_device *ndev;
122
123 spinlock_t lock;
124
125 struct mii_if_info mii;
126 u32 msg_enable;
127 } board_info_t;
128
129 /* debug code */
130
131 #define dm9000_dbg(db, lev, msg...) do { \
132 if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \
133 (lev) < db->debug_level) { \
134 dev_dbg(db->dev, msg); \
135 } \
136 } while (0)
137
138 static inline board_info_t *to_dm9000_board(struct net_device *dev)
139 {
140 return dev->priv;
141 }
142
143 /* function declaration ------------------------------------- */
144 static int dm9000_probe(struct platform_device *);
145 static int dm9000_open(struct net_device *);
146 static int dm9000_start_xmit(struct sk_buff *, struct net_device *);
147 static int dm9000_stop(struct net_device *);
148 static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd);
149
150 static void dm9000_init_dm9000(struct net_device *);
151
152 static irqreturn_t dm9000_interrupt(int, void *);
153
154 static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg);
155 static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg,
156 int value);
157
158 static void dm9000_read_eeprom(board_info_t *, int addr, u8 *to);
159 static void dm9000_write_eeprom(board_info_t *, int addr, u8 *dp);
160 static void dm9000_rx(struct net_device *);
161 static void dm9000_hash_table(struct net_device *);
162
163 /* DM9000 network board routine ---------------------------- */
164
165 static void
166 dm9000_reset(board_info_t * db)
167 {
168 dev_dbg(db->dev, "resetting device\n");
169
170 /* RESET device */
171 writeb(DM9000_NCR, db->io_addr);
172 udelay(200);
173 writeb(NCR_RST, db->io_data);
174 udelay(200);
175 }
176
177 /*
178 * Read a byte from I/O port
179 */
180 static u8
181 ior(board_info_t * db, int reg)
182 {
183 writeb(reg, db->io_addr);
184 return readb(db->io_data);
185 }
186
187 /*
188 * Write a byte to I/O port
189 */
190
191 static void
192 iow(board_info_t * db, int reg, int value)
193 {
194 writeb(reg, db->io_addr);
195 writeb(value, db->io_data);
196 }
197
198 /* routines for sending block to chip */
199
200 static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
201 {
202 writesb(reg, data, count);
203 }
204
205 static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
206 {
207 writesw(reg, data, (count+1) >> 1);
208 }
209
210 static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
211 {
212 writesl(reg, data, (count+3) >> 2);
213 }
214
215 /* input block from chip to memory */
216
217 static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
218 {
219 readsb(reg, data, count);
220 }
221
222
223 static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
224 {
225 readsw(reg, data, (count+1) >> 1);
226 }
227
228 static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
229 {
230 readsl(reg, data, (count+3) >> 2);
231 }
232
233 /* dump block from chip to null */
234
235 static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
236 {
237 int i;
238 int tmp;
239
240 for (i = 0; i < count; i++)
241 tmp = readb(reg);
242 }
243
244 static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
245 {
246 int i;
247 int tmp;
248
249 count = (count + 1) >> 1;
250
251 for (i = 0; i < count; i++)
252 tmp = readw(reg);
253 }
254
255 static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
256 {
257 int i;
258 int tmp;
259
260 count = (count + 3) >> 2;
261
262 for (i = 0; i < count; i++)
263 tmp = readl(reg);
264 }
265
266 /* dm9000_set_io
267 *
268 * select the specified set of io routines to use with the
269 * device
270 */
271
272 static void dm9000_set_io(struct board_info *db, int byte_width)
273 {
274 /* use the size of the data resource to work out what IO
275 * routines we want to use
276 */
277
278 switch (byte_width) {
279 case 1:
280 db->dumpblk = dm9000_dumpblk_8bit;
281 db->outblk = dm9000_outblk_8bit;
282 db->inblk = dm9000_inblk_8bit;
283 break;
284
285
286 case 3:
287 dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n");
288 case 2:
289 db->dumpblk = dm9000_dumpblk_16bit;
290 db->outblk = dm9000_outblk_16bit;
291 db->inblk = dm9000_inblk_16bit;
292 break;
293
294 case 4:
295 default:
296 db->dumpblk = dm9000_dumpblk_32bit;
297 db->outblk = dm9000_outblk_32bit;
298 db->inblk = dm9000_inblk_32bit;
299 break;
300 }
301 }
302
303 static void dm9000_schedule_poll(board_info_t *db)
304 {
305 schedule_delayed_work(&db->phy_poll, HZ * 2);
306 }
307
308 /* Our watchdog timed out. Called by the networking layer */
309 static void dm9000_timeout(struct net_device *dev)
310 {
311 board_info_t *db = (board_info_t *) dev->priv;
312 u8 reg_save;
313 unsigned long flags;
314
315 /* Save previous register address */
316 reg_save = readb(db->io_addr);
317 spin_lock_irqsave(&db->lock,flags);
318
319 netif_stop_queue(dev);
320 dm9000_reset(db);
321 dm9000_init_dm9000(dev);
322 /* We can accept TX packets again */
323 dev->trans_start = jiffies;
324 netif_wake_queue(dev);
325
326 /* Restore previous register address */
327 writeb(reg_save, db->io_addr);
328 spin_unlock_irqrestore(&db->lock,flags);
329 }
330
331 #ifdef CONFIG_NET_POLL_CONTROLLER
332 /*
333 *Used by netconsole
334 */
335 static void dm9000_poll_controller(struct net_device *dev)
336 {
337 disable_irq(dev->irq);
338 dm9000_interrupt(dev->irq,dev);
339 enable_irq(dev->irq);
340 }
341 #endif
342
343 static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
344 {
345 board_info_t *dm = to_dm9000_board(dev);
346
347 if (!netif_running(dev))
348 return -EINVAL;
349
350 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL);
351 }
352
353 /* ethtool ops */
354
355 static void dm9000_get_drvinfo(struct net_device *dev,
356 struct ethtool_drvinfo *info)
357 {
358 board_info_t *dm = to_dm9000_board(dev);
359
360 strcpy(info->driver, CARDNAME);
361 strcpy(info->version, DRV_VERSION);
362 strcpy(info->bus_info, to_platform_device(dm->dev)->name);
363 }
364
365 static u32 dm9000_get_msglevel(struct net_device *dev)
366 {
367 board_info_t *dm = to_dm9000_board(dev);
368
369 return dm->msg_enable;
370 }
371
372 static void dm9000_set_msglevel(struct net_device *dev, u32 value)
373 {
374 board_info_t *dm = to_dm9000_board(dev);
375
376 dm->msg_enable = value;
377 }
378
379 static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
380 {
381 board_info_t *dm = to_dm9000_board(dev);
382
383 mii_ethtool_gset(&dm->mii, cmd);
384 return 0;
385 }
386
387 static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
388 {
389 board_info_t *dm = to_dm9000_board(dev);
390
391 return mii_ethtool_sset(&dm->mii, cmd);
392 }
393
394 static int dm9000_nway_reset(struct net_device *dev)
395 {
396 board_info_t *dm = to_dm9000_board(dev);
397 return mii_nway_restart(&dm->mii);
398 }
399
400 static u32 dm9000_get_link(struct net_device *dev)
401 {
402 board_info_t *dm = to_dm9000_board(dev);
403 return mii_link_ok(&dm->mii);
404 }
405
406 #define DM_EEPROM_MAGIC (0x444D394B)
407
408 static int dm9000_get_eeprom_len(struct net_device *dev)
409 {
410 return 128;
411 }
412
413 static int dm9000_get_eeprom(struct net_device *dev,
414 struct ethtool_eeprom *ee, u8 *data)
415 {
416 board_info_t *dm = to_dm9000_board(dev);
417 int offset = ee->offset;
418 int len = ee->len;
419 int i;
420
421 /* EEPROM access is aligned to two bytes */
422
423 if ((len & 1) != 0 || (offset & 1) != 0)
424 return -EINVAL;
425
426 if (dm->flags & DM9000_PLATF_NO_EEPROM)
427 return -ENOENT;
428
429 ee->magic = DM_EEPROM_MAGIC;
430
431 for (i = 0; i < len; i += 2)
432 dm9000_read_eeprom(dm, (offset + i) / 2, data + i);
433
434 return 0;
435 }
436
437 static int dm9000_set_eeprom(struct net_device *dev,
438 struct ethtool_eeprom *ee, u8 *data)
439 {
440 board_info_t *dm = to_dm9000_board(dev);
441 int offset = ee->offset;
442 int len = ee->len;
443 int i;
444
445 /* EEPROM access is aligned to two bytes */
446
447 if ((len & 1) != 0 || (offset & 1) != 0)
448 return -EINVAL;
449
450 if (dm->flags & DM9000_PLATF_NO_EEPROM)
451 return -ENOENT;
452
453 if (ee->magic != DM_EEPROM_MAGIC)
454 return -EINVAL;
455
456 for (i = 0; i < len; i += 2)
457 dm9000_write_eeprom(dm, (offset + i) / 2, data + i);
458
459 return 0;
460 }
461
462 static const struct ethtool_ops dm9000_ethtool_ops = {
463 .get_drvinfo = dm9000_get_drvinfo,
464 .get_settings = dm9000_get_settings,
465 .set_settings = dm9000_set_settings,
466 .get_msglevel = dm9000_get_msglevel,
467 .set_msglevel = dm9000_set_msglevel,
468 .nway_reset = dm9000_nway_reset,
469 .get_link = dm9000_get_link,
470 .get_eeprom_len = dm9000_get_eeprom_len,
471 .get_eeprom = dm9000_get_eeprom,
472 .set_eeprom = dm9000_set_eeprom,
473 };
474
475 static void
476 dm9000_poll_work(struct work_struct *w)
477 {
478 struct delayed_work *dw = container_of(w, struct delayed_work, work);
479 board_info_t *db = container_of(dw, board_info_t, phy_poll);
480
481 mii_check_media(&db->mii, netif_msg_link(db), 0);
482
483 if (netif_running(db->ndev))
484 dm9000_schedule_poll(db);
485 }
486
487 /* dm9000_release_board
488 *
489 * release a board, and any mapped resources
490 */
491
492 static void
493 dm9000_release_board(struct platform_device *pdev, struct board_info *db)
494 {
495 if (db->data_res == NULL) {
496 if (db->addr_res != NULL)
497 release_mem_region((unsigned long)db->io_addr, 4);
498 return;
499 }
500
501 /* unmap our resources */
502
503 iounmap(db->io_addr);
504 iounmap(db->io_data);
505
506 /* release the resources */
507
508 if (db->data_req != NULL) {
509 release_resource(db->data_req);
510 kfree(db->data_req);
511 }
512
513 if (db->addr_req != NULL) {
514 release_resource(db->addr_req);
515 kfree(db->addr_req);
516 }
517 }
518
519 #define res_size(_r) (((_r)->end - (_r)->start) + 1)
520
521 /*
522 * Search DM9000 board, allocate space and register it
523 */
524 static int __devinit
525 dm9000_probe(struct platform_device *pdev)
526 {
527 struct dm9000_plat_data *pdata = pdev->dev.platform_data;
528 struct board_info *db; /* Point a board information structure */
529 struct net_device *ndev;
530 const unsigned char *mac_src;
531 unsigned long base;
532 int ret = 0;
533 int iosize;
534 int i;
535 u32 id_val;
536
537 /* Init network device */
538 ndev = alloc_etherdev(sizeof (struct board_info));
539 if (!ndev) {
540 dev_err(&pdev->dev, "could not allocate device.\n");
541 return -ENOMEM;
542 }
543
544 SET_NETDEV_DEV(ndev, &pdev->dev);
545
546 dev_dbg(&pdev->dev, "dm9000_probe()\n");
547
548 /* setup board info structure */
549 db = (struct board_info *) ndev->priv;
550 memset(db, 0, sizeof (*db));
551
552 db->dev = &pdev->dev;
553 db->ndev = ndev;
554
555 spin_lock_init(&db->lock);
556 mutex_init(&db->addr_lock);
557
558 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work);
559
560
561 if (pdev->num_resources < 2) {
562 ret = -ENODEV;
563 goto out;
564 } else if (pdev->num_resources == 2) {
565 base = pdev->resource[0].start;
566
567 if (!request_mem_region(base, 4, ndev->name)) {
568 ret = -EBUSY;
569 goto out;
570 }
571
572 ndev->base_addr = base;
573 ndev->irq = pdev->resource[1].start;
574 db->io_addr = (void __iomem *)base;
575 db->io_data = (void __iomem *)(base + 4);
576
577 /* ensure at least we have a default set of IO routines */
578 dm9000_set_io(db, 2);
579
580 } else {
581 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
582 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
583 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
584
585 if (db->addr_res == NULL || db->data_res == NULL ||
586 db->irq_res == NULL) {
587 dev_err(db->dev, "insufficient resources\n");
588 ret = -ENOENT;
589 goto out;
590 }
591
592 i = res_size(db->addr_res);
593 db->addr_req = request_mem_region(db->addr_res->start, i,
594 pdev->name);
595
596 if (db->addr_req == NULL) {
597 dev_err(db->dev, "cannot claim address reg area\n");
598 ret = -EIO;
599 goto out;
600 }
601
602 db->io_addr = ioremap(db->addr_res->start, i);
603
604 if (db->io_addr == NULL) {
605 dev_err(db->dev, "failed to ioremap address reg\n");
606 ret = -EINVAL;
607 goto out;
608 }
609
610 iosize = res_size(db->data_res);
611 db->data_req = request_mem_region(db->data_res->start, iosize,
612 pdev->name);
613
614 if (db->data_req == NULL) {
615 dev_err(db->dev, "cannot claim data reg area\n");
616 ret = -EIO;
617 goto out;
618 }
619
620 db->io_data = ioremap(db->data_res->start, iosize);
621
622 if (db->io_data == NULL) {
623 dev_err(db->dev,"failed to ioremap data reg\n");
624 ret = -EINVAL;
625 goto out;
626 }
627
628 /* fill in parameters for net-dev structure */
629
630 ndev->base_addr = (unsigned long)db->io_addr;
631 ndev->irq = db->irq_res->start;
632
633 /* ensure at least we have a default set of IO routines */
634 dm9000_set_io(db, iosize);
635 }
636
637 /* check to see if anything is being over-ridden */
638 if (pdata != NULL) {
639 /* check to see if the driver wants to over-ride the
640 * default IO width */
641
642 if (pdata->flags & DM9000_PLATF_8BITONLY)
643 dm9000_set_io(db, 1);
644
645 if (pdata->flags & DM9000_PLATF_16BITONLY)
646 dm9000_set_io(db, 2);
647
648 if (pdata->flags & DM9000_PLATF_32BITONLY)
649 dm9000_set_io(db, 4);
650
651 /* check to see if there are any IO routine
652 * over-rides */
653
654 if (pdata->inblk != NULL)
655 db->inblk = pdata->inblk;
656
657 if (pdata->outblk != NULL)
658 db->outblk = pdata->outblk;
659
660 if (pdata->dumpblk != NULL)
661 db->dumpblk = pdata->dumpblk;
662
663 db->flags = pdata->flags;
664 }
665
666 dm9000_reset(db);
667
668 /* try two times, DM9000 sometimes gets the first read wrong */
669 for (i = 0; i < 8; i++) {
670 id_val = ior(db, DM9000_VIDL);
671 id_val |= (u32)ior(db, DM9000_VIDH) << 8;
672 id_val |= (u32)ior(db, DM9000_PIDL) << 16;
673 id_val |= (u32)ior(db, DM9000_PIDH) << 24;
674
675 if (id_val == DM9000_ID)
676 break;
677 dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
678 }
679
680 if (id_val != DM9000_ID) {
681 dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
682 ret = -ENODEV;
683 goto out;
684 }
685
686 /* from this point we assume that we have found a DM9000 */
687
688 /* driver system function */
689 ether_setup(ndev);
690
691 ndev->open = &dm9000_open;
692 ndev->hard_start_xmit = &dm9000_start_xmit;
693 ndev->tx_timeout = &dm9000_timeout;
694 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
695 ndev->stop = &dm9000_stop;
696 ndev->set_multicast_list = &dm9000_hash_table;
697 ndev->ethtool_ops = &dm9000_ethtool_ops;
698 ndev->do_ioctl = &dm9000_ioctl;
699
700 #ifdef CONFIG_NET_POLL_CONTROLLER
701 ndev->poll_controller = &dm9000_poll_controller;
702 #endif
703
704 db->msg_enable = NETIF_MSG_LINK;
705 db->mii.phy_id_mask = 0x1f;
706 db->mii.reg_num_mask = 0x1f;
707 db->mii.force_media = 0;
708 db->mii.full_duplex = 0;
709 db->mii.dev = ndev;
710 db->mii.mdio_read = dm9000_phy_read;
711 db->mii.mdio_write = dm9000_phy_write;
712
713 mac_src = "eeprom";
714
715 /* try reading the node address from the attached EEPROM */
716 for (i = 0; i < 6; i += 2)
717 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
718
719 if (!is_valid_ether_addr(ndev->dev_addr)) {
720 /* try reading from mac */
721
722 mac_src = "chip";
723 for (i = 0; i < 6; i++)
724 ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
725 }
726
727 if (!is_valid_ether_addr(ndev->dev_addr))
728 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
729 "set using ifconfig\n", ndev->name);
730
731 platform_set_drvdata(pdev, ndev);
732 ret = register_netdev(ndev);
733
734 if (ret == 0) {
735 DECLARE_MAC_BUF(mac);
736 printk("%s: dm9000 at %p,%p IRQ %d MAC: %s (%s)\n",
737 ndev->name, db->io_addr, db->io_data, ndev->irq,
738 print_mac(mac, ndev->dev_addr), mac_src);
739 }
740 return 0;
741
742 out:
743 dev_err(db->dev, "not found (%d).\n", ret);
744
745 dm9000_release_board(pdev, db);
746 free_netdev(ndev);
747
748 return ret;
749 }
750
751 /*
752 * Open the interface.
753 * The interface is opened whenever "ifconfig" actives it.
754 */
755 static int
756 dm9000_open(struct net_device *dev)
757 {
758 board_info_t *db = (board_info_t *) dev->priv;
759 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
760
761 if (netif_msg_ifup(db))
762 dev_dbg(db->dev, "enabling %s\n", dev->name);
763
764 /* If there is no IRQ type specified, default to something that
765 * may work, and tell the user that this is a problem */
766
767 if (irqflags == IRQF_TRIGGER_NONE) {
768 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
769 irqflags = DEFAULT_TRIGGER;
770 }
771
772 irqflags |= IRQF_SHARED;
773
774 if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev))
775 return -EAGAIN;
776
777 /* Initialize DM9000 board */
778 dm9000_reset(db);
779 dm9000_init_dm9000(dev);
780
781 /* Init driver variable */
782 db->dbug_cnt = 0;
783
784 mii_check_media(&db->mii, netif_msg_link(db), 1);
785 netif_start_queue(dev);
786
787 dm9000_schedule_poll(db);
788
789 return 0;
790 }
791
792 /*
793 * Initilize dm9000 board
794 */
795 static void
796 dm9000_init_dm9000(struct net_device *dev)
797 {
798 board_info_t *db = (board_info_t *) dev->priv;
799
800 dm9000_dbg(db, 1, "entering %s\n", __func__);
801
802 /* I/O mode */
803 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
804
805 /* GPIO0 on pre-activate PHY */
806 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
807 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
808 iow(db, DM9000_GPR, 0); /* Enable PHY */
809
810 if (db->flags & DM9000_PLATF_EXT_PHY)
811 iow(db, DM9000_NCR, NCR_EXT_PHY);
812
813 /* Program operating register */
814 iow(db, DM9000_TCR, 0); /* TX Polling clear */
815 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
816 iow(db, DM9000_FCR, 0xff); /* Flow Control */
817 iow(db, DM9000_SMCR, 0); /* Special Mode */
818 /* clear TX status */
819 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
820 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
821
822 /* Set address filter table */
823 dm9000_hash_table(dev);
824
825 /* Enable TX/RX interrupt mask */
826 iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
827
828 /* Init Driver variable */
829 db->tx_pkt_cnt = 0;
830 db->queue_pkt_len = 0;
831 dev->trans_start = 0;
832 }
833
834 /*
835 * Hardware start transmission.
836 * Send a packet to media from the upper layer.
837 */
838 static int
839 dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
840 {
841 unsigned long flags;
842 board_info_t *db = (board_info_t *) dev->priv;
843
844 dm9000_dbg(db, 3, "%s:\n", __func__);
845
846 if (db->tx_pkt_cnt > 1)
847 return 1;
848
849 spin_lock_irqsave(&db->lock, flags);
850
851 /* Move data to DM9000 TX RAM */
852 writeb(DM9000_MWCMD, db->io_addr);
853
854 (db->outblk)(db->io_data, skb->data, skb->len);
855 dev->stats.tx_bytes += skb->len;
856
857 db->tx_pkt_cnt++;
858 /* TX control: First packet immediately send, second packet queue */
859 if (db->tx_pkt_cnt == 1) {
860 /* Set TX length to DM9000 */
861 iow(db, DM9000_TXPLL, skb->len);
862 iow(db, DM9000_TXPLH, skb->len >> 8);
863
864 /* Issue TX polling command */
865 iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
866
867 dev->trans_start = jiffies; /* save the time stamp */
868 } else {
869 /* Second packet */
870 db->queue_pkt_len = skb->len;
871 netif_stop_queue(dev);
872 }
873
874 spin_unlock_irqrestore(&db->lock, flags);
875
876 /* free this SKB */
877 dev_kfree_skb(skb);
878
879 return 0;
880 }
881
882 static void
883 dm9000_shutdown(struct net_device *dev)
884 {
885 board_info_t *db = (board_info_t *) dev->priv;
886
887 /* RESET device */
888 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
889 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
890 iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
891 iow(db, DM9000_RCR, 0x00); /* Disable RX */
892 }
893
894 /*
895 * Stop the interface.
896 * The interface is stopped when it is brought.
897 */
898 static int
899 dm9000_stop(struct net_device *ndev)
900 {
901 board_info_t *db = (board_info_t *) ndev->priv;
902
903 if (netif_msg_ifdown(db))
904 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
905
906 cancel_delayed_work_sync(&db->phy_poll);
907
908 netif_stop_queue(ndev);
909 netif_carrier_off(ndev);
910
911 /* free interrupt */
912 free_irq(ndev->irq, ndev);
913
914 dm9000_shutdown(ndev);
915
916 return 0;
917 }
918
919 /*
920 * DM9000 interrupt handler
921 * receive the packet to upper layer, free the transmitted packet
922 */
923
924 static void
925 dm9000_tx_done(struct net_device *dev, board_info_t * db)
926 {
927 int tx_status = ior(db, DM9000_NSR); /* Got TX status */
928
929 if (tx_status & (NSR_TX2END | NSR_TX1END)) {
930 /* One packet sent complete */
931 db->tx_pkt_cnt--;
932 dev->stats.tx_packets++;
933
934 if (netif_msg_tx_done(db))
935 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
936
937 /* Queue packet check & send */
938 if (db->tx_pkt_cnt > 0) {
939 iow(db, DM9000_TXPLL, db->queue_pkt_len);
940 iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8);
941 iow(db, DM9000_TCR, TCR_TXREQ);
942 dev->trans_start = jiffies;
943 }
944 netif_wake_queue(dev);
945 }
946 }
947
948 static irqreturn_t
949 dm9000_interrupt(int irq, void *dev_id)
950 {
951 struct net_device *dev = dev_id;
952 board_info_t *db = (board_info_t *) dev->priv;
953 int int_status;
954 u8 reg_save;
955
956 dm9000_dbg(db, 3, "entering %s\n", __func__);
957
958 /* A real interrupt coming */
959
960 spin_lock(&db->lock);
961
962 /* Save previous register address */
963 reg_save = readb(db->io_addr);
964
965 /* Disable all interrupts */
966 iow(db, DM9000_IMR, IMR_PAR);
967
968 /* Got DM9000 interrupt status */
969 int_status = ior(db, DM9000_ISR); /* Got ISR */
970 iow(db, DM9000_ISR, int_status); /* Clear ISR status */
971
972 if (netif_msg_intr(db))
973 dev_dbg(db->dev, "interrupt status %02x\n", int_status);
974
975 /* Received the coming packet */
976 if (int_status & ISR_PRS)
977 dm9000_rx(dev);
978
979 /* Trnasmit Interrupt check */
980 if (int_status & ISR_PTS)
981 dm9000_tx_done(dev, db);
982
983 /* Re-enable interrupt mask */
984 iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
985
986 /* Restore previous register address */
987 writeb(reg_save, db->io_addr);
988
989 spin_unlock(&db->lock);
990
991 return IRQ_HANDLED;
992 }
993
994 struct dm9000_rxhdr {
995 u8 RxPktReady;
996 u8 RxStatus;
997 __le16 RxLen;
998 } __attribute__((__packed__));
999
1000 /*
1001 * Received a packet and pass to upper layer
1002 */
1003 static void
1004 dm9000_rx(struct net_device *dev)
1005 {
1006 board_info_t *db = (board_info_t *) dev->priv;
1007 struct dm9000_rxhdr rxhdr;
1008 struct sk_buff *skb;
1009 u8 rxbyte, *rdptr;
1010 bool GoodPacket;
1011 int RxLen;
1012
1013 /* Check packet ready or not */
1014 do {
1015 ior(db, DM9000_MRCMDX); /* Dummy read */
1016
1017 /* Get most updated data */
1018 rxbyte = readb(db->io_data);
1019
1020 /* Status check: this byte must be 0 or 1 */
1021 if (rxbyte > DM9000_PKT_RDY) {
1022 dev_warn(db->dev, "status check fail: %d\n", rxbyte);
1023 iow(db, DM9000_RCR, 0x00); /* Stop Device */
1024 iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
1025 return;
1026 }
1027
1028 if (rxbyte != DM9000_PKT_RDY)
1029 return;
1030
1031 /* A packet ready now & Get status/length */
1032 GoodPacket = true;
1033 writeb(DM9000_MRCMD, db->io_addr);
1034
1035 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
1036
1037 RxLen = le16_to_cpu(rxhdr.RxLen);
1038
1039 if (netif_msg_rx_status(db))
1040 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
1041 rxhdr.RxStatus, RxLen);
1042
1043 /* Packet Status check */
1044 if (RxLen < 0x40) {
1045 GoodPacket = false;
1046 if (netif_msg_rx_err(db))
1047 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
1048 }
1049
1050 if (RxLen > DM9000_PKT_MAX) {
1051 dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
1052 }
1053
1054 if (rxhdr.RxStatus & 0xbf) {
1055 GoodPacket = false;
1056 if (rxhdr.RxStatus & 0x01) {
1057 if (netif_msg_rx_err(db))
1058 dev_dbg(db->dev, "fifo error\n");
1059 dev->stats.rx_fifo_errors++;
1060 }
1061 if (rxhdr.RxStatus & 0x02) {
1062 if (netif_msg_rx_err(db))
1063 dev_dbg(db->dev, "crc error\n");
1064 dev->stats.rx_crc_errors++;
1065 }
1066 if (rxhdr.RxStatus & 0x80) {
1067 if (netif_msg_rx_err(db))
1068 dev_dbg(db->dev, "length error\n");
1069 dev->stats.rx_length_errors++;
1070 }
1071 }
1072
1073 /* Move data from DM9000 */
1074 if (GoodPacket
1075 && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) {
1076 skb_reserve(skb, 2);
1077 rdptr = (u8 *) skb_put(skb, RxLen - 4);
1078
1079 /* Read received packet from RX SRAM */
1080
1081 (db->inblk)(db->io_data, rdptr, RxLen);
1082 dev->stats.rx_bytes += RxLen;
1083
1084 /* Pass to upper layer */
1085 skb->protocol = eth_type_trans(skb, dev);
1086 netif_rx(skb);
1087 dev->stats.rx_packets++;
1088
1089 } else {
1090 /* need to dump the packet's data */
1091
1092 (db->dumpblk)(db->io_data, RxLen);
1093 }
1094 } while (rxbyte == DM9000_PKT_RDY);
1095 }
1096
1097 static unsigned int
1098 dm9000_read_locked(board_info_t *db, int reg)
1099 {
1100 unsigned long flags;
1101 unsigned int ret;
1102
1103 spin_lock_irqsave(&db->lock, flags);
1104 ret = ior(db, reg);
1105 spin_unlock_irqrestore(&db->lock, flags);
1106
1107 return ret;
1108 }
1109
1110 static int dm9000_wait_eeprom(board_info_t *db)
1111 {
1112 unsigned int status;
1113 int timeout = 8; /* wait max 8msec */
1114
1115 /* The DM9000 data sheets say we should be able to
1116 * poll the ERRE bit in EPCR to wait for the EEPROM
1117 * operation. From testing several chips, this bit
1118 * does not seem to work.
1119 *
1120 * We attempt to use the bit, but fall back to the
1121 * timeout (which is why we do not return an error
1122 * on expiry) to say that the EEPROM operation has
1123 * completed.
1124 */
1125
1126 while (1) {
1127 status = dm9000_read_locked(db, DM9000_EPCR);
1128
1129 if ((status & EPCR_ERRE) == 0)
1130 break;
1131
1132 if (timeout-- < 0) {
1133 dev_dbg(db->dev, "timeout waiting EEPROM\n");
1134 break;
1135 }
1136 }
1137
1138 return 0;
1139 }
1140
1141 /*
1142 * Read a word data from EEPROM
1143 */
1144 static void
1145 dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
1146 {
1147 unsigned long flags;
1148
1149 if (db->flags & DM9000_PLATF_NO_EEPROM) {
1150 to[0] = 0xff;
1151 to[1] = 0xff;
1152 return;
1153 }
1154
1155 mutex_lock(&db->addr_lock);
1156
1157 spin_lock_irqsave(&db->lock, flags);
1158
1159 iow(db, DM9000_EPAR, offset);
1160 iow(db, DM9000_EPCR, EPCR_ERPRR);
1161
1162 spin_unlock_irqrestore(&db->lock, flags);
1163
1164 dm9000_wait_eeprom(db);
1165
1166 /* delay for at-least 150uS */
1167 msleep(1);
1168
1169 spin_lock_irqsave(&db->lock, flags);
1170
1171 iow(db, DM9000_EPCR, 0x0);
1172
1173 to[0] = ior(db, DM9000_EPDRL);
1174 to[1] = ior(db, DM9000_EPDRH);
1175
1176 spin_unlock_irqrestore(&db->lock, flags);
1177
1178 mutex_unlock(&db->addr_lock);
1179 }
1180
1181 /*
1182 * Write a word data to SROM
1183 */
1184 static void
1185 dm9000_write_eeprom(board_info_t *db, int offset, u8 *data)
1186 {
1187 unsigned long flags;
1188
1189 if (db->flags & DM9000_PLATF_NO_EEPROM)
1190 return;
1191
1192 mutex_lock(&db->addr_lock);
1193
1194 spin_lock_irqsave(&db->lock, flags);
1195 iow(db, DM9000_EPAR, offset);
1196 iow(db, DM9000_EPDRH, data[1]);
1197 iow(db, DM9000_EPDRL, data[0]);
1198 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
1199 spin_unlock_irqrestore(&db->lock, flags);
1200
1201 dm9000_wait_eeprom(db);
1202
1203 mdelay(1); /* wait at least 150uS to clear */
1204
1205 spin_lock_irqsave(&db->lock, flags);
1206 iow(db, DM9000_EPCR, 0);
1207 spin_unlock_irqrestore(&db->lock, flags);
1208
1209 mutex_unlock(&db->addr_lock);
1210 }
1211
1212 /*
1213 * Set DM9000 multicast address
1214 */
1215 static void
1216 dm9000_hash_table(struct net_device *dev)
1217 {
1218 board_info_t *db = (board_info_t *) dev->priv;
1219 struct dev_mc_list *mcptr = dev->mc_list;
1220 int mc_cnt = dev->mc_count;
1221 int i, oft;
1222 u32 hash_val;
1223 u16 hash_table[4];
1224 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
1225 unsigned long flags;
1226
1227 dm9000_dbg(db, 1, "entering %s\n", __func__);
1228
1229 spin_lock_irqsave(&db->lock, flags);
1230
1231 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
1232 iow(db, oft, dev->dev_addr[i]);
1233
1234 /* Clear Hash Table */
1235 for (i = 0; i < 4; i++)
1236 hash_table[i] = 0x0;
1237
1238 /* broadcast address */
1239 hash_table[3] = 0x8000;
1240
1241 if (dev->flags & IFF_PROMISC)
1242 rcr |= RCR_PRMSC;
1243
1244 if (dev->flags & IFF_ALLMULTI)
1245 rcr |= RCR_ALL;
1246
1247 /* the multicast address in Hash Table : 64 bits */
1248 for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1249 hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f;
1250 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1251 }
1252
1253 /* Write the hash table to MAC MD table */
1254 for (i = 0, oft = DM9000_MAR; i < 4; i++) {
1255 iow(db, oft++, hash_table[i]);
1256 iow(db, oft++, hash_table[i] >> 8);
1257 }
1258
1259 iow(db, DM9000_RCR, rcr);
1260 spin_unlock_irqrestore(&db->lock, flags);
1261 }
1262
1263
1264 /*
1265 * Sleep, either by using msleep() or if we are suspending, then
1266 * use mdelay() to sleep.
1267 */
1268 static void dm9000_msleep(board_info_t *db, unsigned int ms)
1269 {
1270 if (db->in_suspend)
1271 mdelay(ms);
1272 else
1273 msleep(ms);
1274 }
1275
1276 /*
1277 * Read a word from phyxcer
1278 */
1279 static int
1280 dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
1281 {
1282 board_info_t *db = (board_info_t *) dev->priv;
1283 unsigned long flags;
1284 unsigned int reg_save;
1285 int ret;
1286
1287 mutex_lock(&db->addr_lock);
1288
1289 spin_lock_irqsave(&db->lock,flags);
1290
1291 /* Save previous register address */
1292 reg_save = readb(db->io_addr);
1293
1294 /* Fill the phyxcer register into REG_0C */
1295 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1296
1297 iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
1298
1299 writeb(reg_save, db->io_addr);
1300 spin_unlock_irqrestore(&db->lock,flags);
1301
1302 dm9000_msleep(db, 1); /* Wait read complete */
1303
1304 spin_lock_irqsave(&db->lock,flags);
1305 reg_save = readb(db->io_addr);
1306
1307 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
1308
1309 /* The read data keeps on REG_0D & REG_0E */
1310 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
1311
1312 /* restore the previous address */
1313 writeb(reg_save, db->io_addr);
1314 spin_unlock_irqrestore(&db->lock,flags);
1315
1316 mutex_unlock(&db->addr_lock);
1317
1318 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
1319 return ret;
1320 }
1321
1322 /*
1323 * Write a word to phyxcer
1324 */
1325 static void
1326 dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
1327 {
1328 board_info_t *db = (board_info_t *) dev->priv;
1329 unsigned long flags;
1330 unsigned long reg_save;
1331
1332 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
1333 mutex_lock(&db->addr_lock);
1334
1335 spin_lock_irqsave(&db->lock,flags);
1336
1337 /* Save previous register address */
1338 reg_save = readb(db->io_addr);
1339
1340 /* Fill the phyxcer register into REG_0C */
1341 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1342
1343 /* Fill the written data into REG_0D & REG_0E */
1344 iow(db, DM9000_EPDRL, value);
1345 iow(db, DM9000_EPDRH, value >> 8);
1346
1347 iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
1348
1349 writeb(reg_save, db->io_addr);
1350 spin_unlock_irqrestore(&db->lock, flags);
1351
1352 dm9000_msleep(db, 1); /* Wait write complete */
1353
1354 spin_lock_irqsave(&db->lock,flags);
1355 reg_save = readb(db->io_addr);
1356
1357 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
1358
1359 /* restore the previous address */
1360 writeb(reg_save, db->io_addr);
1361
1362 spin_unlock_irqrestore(&db->lock, flags);
1363 mutex_unlock(&db->addr_lock);
1364 }
1365
1366 static int
1367 dm9000_drv_suspend(struct platform_device *dev, pm_message_t state)
1368 {
1369 struct net_device *ndev = platform_get_drvdata(dev);
1370 board_info_t *db;
1371
1372 if (ndev) {
1373 db = (board_info_t *) ndev->priv;
1374 db->in_suspend = 1;
1375
1376 if (netif_running(ndev)) {
1377 netif_device_detach(ndev);
1378 dm9000_shutdown(ndev);
1379 }
1380 }
1381 return 0;
1382 }
1383
1384 static int
1385 dm9000_drv_resume(struct platform_device *dev)
1386 {
1387 struct net_device *ndev = platform_get_drvdata(dev);
1388 board_info_t *db = (board_info_t *) ndev->priv;
1389
1390 if (ndev) {
1391
1392 if (netif_running(ndev)) {
1393 dm9000_reset(db);
1394 dm9000_init_dm9000(ndev);
1395
1396 netif_device_attach(ndev);
1397 }
1398
1399 db->in_suspend = 0;
1400 }
1401 return 0;
1402 }
1403
1404 static int __devexit
1405 dm9000_drv_remove(struct platform_device *pdev)
1406 {
1407 struct net_device *ndev = platform_get_drvdata(pdev);
1408
1409 platform_set_drvdata(pdev, NULL);
1410
1411 unregister_netdev(ndev);
1412 dm9000_release_board(pdev, (board_info_t *) ndev->priv);
1413 free_netdev(ndev); /* free device structure */
1414
1415 dev_dbg(&pdev->dev, "released and freed device\n");
1416 return 0;
1417 }
1418
1419 static struct platform_driver dm9000_driver = {
1420 .driver = {
1421 .name = "dm9000",
1422 .owner = THIS_MODULE,
1423 },
1424 .probe = dm9000_probe,
1425 .remove = __devexit_p(dm9000_drv_remove),
1426 .suspend = dm9000_drv_suspend,
1427 .resume = dm9000_drv_resume,
1428 };
1429
1430 static int __init
1431 dm9000_init(void)
1432 {
1433 printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION);
1434
1435 return platform_driver_register(&dm9000_driver); /* search board and register */
1436 }
1437
1438 static void __exit
1439 dm9000_cleanup(void)
1440 {
1441 platform_driver_unregister(&dm9000_driver);
1442 }
1443
1444 module_init(dm9000_init);
1445 module_exit(dm9000_cleanup);
1446
1447 MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
1448 MODULE_DESCRIPTION("Davicom DM9000 network driver");
1449 MODULE_LICENSE("GPL");
1450 MODULE_ALIAS("platform:dm9000");