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net: dsa: b53: Properly account for VLAN filtering
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
31 #include <net/dsa.h>
32
33 #include "b53_regs.h"
34 #include "b53_priv.h"
35
36 struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40 };
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 };
77
78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80 /* BCM63xx MIB counters */
81 static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124 };
125
126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128 /* MIB counters */
129 static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165 };
166
167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
169 static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224 };
225
226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
228 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229 {
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245 }
246
247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
249 {
250 if (is5325(dev)) {
251 u32 entry = 0;
252
253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285 }
286
287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289 {
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
324 }
325
326 static void b53_set_forwarding(struct b53_device *dev, int enable)
327 {
328 u8 mgmt;
329
330 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
331
332 if (enable)
333 mgmt |= SM_SW_FWD_EN;
334 else
335 mgmt &= ~SM_SW_FWD_EN;
336
337 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
338
339 /* Include IMP port in dumb forwarding mode
340 */
341 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
342 mgmt |= B53_MII_DUMB_FWDG_EN;
343 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
344 }
345
346 static void b53_enable_vlan(struct b53_device *dev, bool enable,
347 bool enable_filtering)
348 {
349 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
350
351 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
353 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
354
355 if (is5325(dev) || is5365(dev)) {
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
358 } else if (is63xx(dev)) {
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
361 } else {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
364 }
365
366 mgmt &= ~SM_SW_FWD_MODE;
367
368 if (enable) {
369 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
370 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
371 vc4 &= ~VC4_ING_VID_CHECK_MASK;
372 if (enable_filtering) {
373 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
374 vc5 |= VC5_DROP_VTABLE_MISS;
375 } else {
376 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
377 vc5 &= ~VC5_DROP_VTABLE_MISS;
378 }
379
380 if (is5325(dev))
381 vc0 &= ~VC0_RESERVED_1;
382
383 if (is5325(dev) || is5365(dev))
384 vc1 |= VC1_RX_MCST_TAG_EN;
385
386 } else {
387 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
388 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
389 vc4 &= ~VC4_ING_VID_CHECK_MASK;
390 vc5 &= ~VC5_DROP_VTABLE_MISS;
391
392 if (is5325(dev) || is5365(dev))
393 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
394 else
395 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
396
397 if (is5325(dev) || is5365(dev))
398 vc1 &= ~VC1_RX_MCST_TAG_EN;
399 }
400
401 if (!is5325(dev) && !is5365(dev))
402 vc5 &= ~VC5_VID_FFF_EN;
403
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
405 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
406
407 if (is5325(dev) || is5365(dev)) {
408 /* enable the high 8 bit vid check on 5325 */
409 if (is5325(dev) && enable)
410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
411 VC3_HIGH_8BIT_EN);
412 else
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
414
415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
416 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
417 } else if (is63xx(dev)) {
418 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
421 } else {
422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
425 }
426
427 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
428
429 dev->vlan_enabled = enable;
430 dev->vlan_filtering_enabled = enable_filtering;
431 }
432
433 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
434 {
435 u32 port_mask = 0;
436 u16 max_size = JMS_MIN_SIZE;
437
438 if (is5325(dev) || is5365(dev))
439 return -EINVAL;
440
441 if (enable) {
442 port_mask = dev->enabled_ports;
443 max_size = JMS_MAX_SIZE;
444 if (allow_10_100)
445 port_mask |= JPM_10_100_JUMBO_EN;
446 }
447
448 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
449 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
450 }
451
452 static int b53_flush_arl(struct b53_device *dev, u8 mask)
453 {
454 unsigned int i;
455
456 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
457 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
458
459 for (i = 0; i < 10; i++) {
460 u8 fast_age_ctrl;
461
462 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
463 &fast_age_ctrl);
464
465 if (!(fast_age_ctrl & FAST_AGE_DONE))
466 goto out;
467
468 msleep(1);
469 }
470
471 return -ETIMEDOUT;
472 out:
473 /* Only age dynamic entries (default behavior) */
474 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
475 return 0;
476 }
477
478 static int b53_fast_age_port(struct b53_device *dev, int port)
479 {
480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
481
482 return b53_flush_arl(dev, FAST_AGE_PORT);
483 }
484
485 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
486 {
487 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
488
489 return b53_flush_arl(dev, FAST_AGE_VLAN);
490 }
491
492 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
493 {
494 struct b53_device *dev = ds->priv;
495 unsigned int i;
496 u16 pvlan;
497
498 /* Enable the IMP port to be in the same VLAN as the other ports
499 * on a per-port basis such that we only have Port i and IMP in
500 * the same VLAN.
501 */
502 b53_for_each_port(dev, i) {
503 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
504 pvlan |= BIT(cpu_port);
505 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
506 }
507 }
508 EXPORT_SYMBOL(b53_imp_vlan_setup);
509
510 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
511 {
512 struct b53_device *dev = ds->priv;
513 unsigned int cpu_port = ds->ports[port].cpu_dp->index;
514 u16 pvlan;
515
516 /* Clear the Rx and Tx disable bits and set to no spanning tree */
517 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
518
519 /* Set this port, and only this one to be in the default VLAN,
520 * if member of a bridge, restore its membership prior to
521 * bringing down this port.
522 */
523 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
524 pvlan &= ~0x1ff;
525 pvlan |= BIT(port);
526 pvlan |= dev->ports[port].vlan_ctl_mask;
527 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
528
529 b53_imp_vlan_setup(ds, cpu_port);
530
531 /* If EEE was enabled, restore it */
532 if (dev->ports[port].eee.eee_enabled)
533 b53_eee_enable_set(ds, port, true);
534
535 return 0;
536 }
537 EXPORT_SYMBOL(b53_enable_port);
538
539 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
540 {
541 struct b53_device *dev = ds->priv;
542 u8 reg;
543
544 /* Disable Tx/Rx for the port */
545 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
546 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
547 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
548 }
549 EXPORT_SYMBOL(b53_disable_port);
550
551 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
552 {
553 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
554 DSA_TAG_PROTO_NONE);
555 struct b53_device *dev = ds->priv;
556 u8 hdr_ctl, val;
557 u16 reg;
558
559 /* Resolve which bit controls the Broadcom tag */
560 switch (port) {
561 case 8:
562 val = BRCM_HDR_P8_EN;
563 break;
564 case 7:
565 val = BRCM_HDR_P7_EN;
566 break;
567 case 5:
568 val = BRCM_HDR_P5_EN;
569 break;
570 default:
571 val = 0;
572 break;
573 }
574
575 /* Enable Broadcom tags for IMP port */
576 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
577 if (tag_en)
578 hdr_ctl |= val;
579 else
580 hdr_ctl &= ~val;
581 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
582
583 /* Registers below are only accessible on newer devices */
584 if (!is58xx(dev))
585 return;
586
587 /* Enable reception Broadcom tag for CPU TX (switch RX) to
588 * allow us to tag outgoing frames
589 */
590 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
591 if (tag_en)
592 reg &= ~BIT(port);
593 else
594 reg |= BIT(port);
595 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
596
597 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
598 * allow delivering frames to the per-port net_devices
599 */
600 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
601 if (tag_en)
602 reg &= ~BIT(port);
603 else
604 reg |= BIT(port);
605 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
606 }
607 EXPORT_SYMBOL(b53_brcm_hdr_setup);
608
609 static void b53_enable_cpu_port(struct b53_device *dev, int port)
610 {
611 u8 port_ctrl;
612
613 /* BCM5325 CPU port is at 8 */
614 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
615 port = B53_CPU_PORT;
616
617 port_ctrl = PORT_CTRL_RX_BCST_EN |
618 PORT_CTRL_RX_MCST_EN |
619 PORT_CTRL_RX_UCST_EN;
620 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
621
622 b53_brcm_hdr_setup(dev->ds, port);
623 }
624
625 static void b53_enable_mib(struct b53_device *dev)
626 {
627 u8 gc;
628
629 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
630 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
631 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
632 }
633
634 static u16 b53_default_pvid(struct b53_device *dev)
635 {
636 if (is5325(dev) || is5365(dev))
637 return 1;
638 else
639 return 0;
640 }
641
642 int b53_configure_vlan(struct dsa_switch *ds)
643 {
644 struct b53_device *dev = ds->priv;
645 struct b53_vlan vl = { 0 };
646 int i, def_vid;
647
648 def_vid = b53_default_pvid(dev);
649
650 /* clear all vlan entries */
651 if (is5325(dev) || is5365(dev)) {
652 for (i = def_vid; i < dev->num_vlans; i++)
653 b53_set_vlan_entry(dev, i, &vl);
654 } else {
655 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
656 }
657
658 b53_enable_vlan(dev, false, dev->vlan_filtering_enabled);
659
660 b53_for_each_port(dev, i)
661 b53_write16(dev, B53_VLAN_PAGE,
662 B53_VLAN_PORT_DEF_TAG(i), def_vid);
663
664 if (!is5325(dev) && !is5365(dev))
665 b53_set_jumbo(dev, dev->enable_jumbo, false);
666
667 return 0;
668 }
669 EXPORT_SYMBOL(b53_configure_vlan);
670
671 static void b53_switch_reset_gpio(struct b53_device *dev)
672 {
673 int gpio = dev->reset_gpio;
674
675 if (gpio < 0)
676 return;
677
678 /* Reset sequence: RESET low(50ms)->high(20ms)
679 */
680 gpio_set_value(gpio, 0);
681 mdelay(50);
682
683 gpio_set_value(gpio, 1);
684 mdelay(20);
685
686 dev->current_page = 0xff;
687 }
688
689 static int b53_switch_reset(struct b53_device *dev)
690 {
691 unsigned int timeout = 1000;
692 u8 mgmt, reg;
693
694 b53_switch_reset_gpio(dev);
695
696 if (is539x(dev)) {
697 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
698 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
699 }
700
701 /* This is specific to 58xx devices here, do not use is58xx() which
702 * covers the larger Starfigther 2 family, including 7445/7278 which
703 * still use this driver as a library and need to perform the reset
704 * earlier.
705 */
706 if (dev->chip_id == BCM58XX_DEVICE_ID ||
707 dev->chip_id == BCM583XX_DEVICE_ID) {
708 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
709 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
710 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
711
712 do {
713 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
714 if (!(reg & SW_RST))
715 break;
716
717 usleep_range(1000, 2000);
718 } while (timeout-- > 0);
719
720 if (timeout == 0)
721 return -ETIMEDOUT;
722 }
723
724 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
725
726 if (!(mgmt & SM_SW_FWD_EN)) {
727 mgmt &= ~SM_SW_FWD_MODE;
728 mgmt |= SM_SW_FWD_EN;
729
730 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
731 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
732
733 if (!(mgmt & SM_SW_FWD_EN)) {
734 dev_err(dev->dev, "Failed to enable switch!\n");
735 return -EINVAL;
736 }
737 }
738
739 b53_enable_mib(dev);
740
741 return b53_flush_arl(dev, FAST_AGE_STATIC);
742 }
743
744 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
745 {
746 struct b53_device *priv = ds->priv;
747 u16 value = 0;
748 int ret;
749
750 if (priv->ops->phy_read16)
751 ret = priv->ops->phy_read16(priv, addr, reg, &value);
752 else
753 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
754 reg * 2, &value);
755
756 return ret ? ret : value;
757 }
758
759 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
760 {
761 struct b53_device *priv = ds->priv;
762
763 if (priv->ops->phy_write16)
764 return priv->ops->phy_write16(priv, addr, reg, val);
765
766 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
767 }
768
769 static int b53_reset_switch(struct b53_device *priv)
770 {
771 /* reset vlans */
772 priv->enable_jumbo = false;
773
774 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
775 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
776
777 return b53_switch_reset(priv);
778 }
779
780 static int b53_apply_config(struct b53_device *priv)
781 {
782 /* disable switching */
783 b53_set_forwarding(priv, 0);
784
785 b53_configure_vlan(priv->ds);
786
787 /* enable switching */
788 b53_set_forwarding(priv, 1);
789
790 return 0;
791 }
792
793 static void b53_reset_mib(struct b53_device *priv)
794 {
795 u8 gc;
796
797 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
798
799 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
800 msleep(1);
801 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
802 msleep(1);
803 }
804
805 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
806 {
807 if (is5365(dev))
808 return b53_mibs_65;
809 else if (is63xx(dev))
810 return b53_mibs_63xx;
811 else if (is58xx(dev))
812 return b53_mibs_58xx;
813 else
814 return b53_mibs;
815 }
816
817 static unsigned int b53_get_mib_size(struct b53_device *dev)
818 {
819 if (is5365(dev))
820 return B53_MIBS_65_SIZE;
821 else if (is63xx(dev))
822 return B53_MIBS_63XX_SIZE;
823 else if (is58xx(dev))
824 return B53_MIBS_58XX_SIZE;
825 else
826 return B53_MIBS_SIZE;
827 }
828
829 void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
830 {
831 struct b53_device *dev = ds->priv;
832 const struct b53_mib_desc *mibs = b53_get_mib(dev);
833 unsigned int mib_size = b53_get_mib_size(dev);
834 unsigned int i;
835
836 for (i = 0; i < mib_size; i++)
837 memcpy(data + i * ETH_GSTRING_LEN,
838 mibs[i].name, ETH_GSTRING_LEN);
839 }
840 EXPORT_SYMBOL(b53_get_strings);
841
842 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
843 {
844 struct b53_device *dev = ds->priv;
845 const struct b53_mib_desc *mibs = b53_get_mib(dev);
846 unsigned int mib_size = b53_get_mib_size(dev);
847 const struct b53_mib_desc *s;
848 unsigned int i;
849 u64 val = 0;
850
851 if (is5365(dev) && port == 5)
852 port = 8;
853
854 mutex_lock(&dev->stats_mutex);
855
856 for (i = 0; i < mib_size; i++) {
857 s = &mibs[i];
858
859 if (s->size == 8) {
860 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
861 } else {
862 u32 val32;
863
864 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
865 &val32);
866 val = val32;
867 }
868 data[i] = (u64)val;
869 }
870
871 mutex_unlock(&dev->stats_mutex);
872 }
873 EXPORT_SYMBOL(b53_get_ethtool_stats);
874
875 int b53_get_sset_count(struct dsa_switch *ds)
876 {
877 struct b53_device *dev = ds->priv;
878
879 return b53_get_mib_size(dev);
880 }
881 EXPORT_SYMBOL(b53_get_sset_count);
882
883 static int b53_setup(struct dsa_switch *ds)
884 {
885 struct b53_device *dev = ds->priv;
886 unsigned int port;
887 int ret;
888
889 ret = b53_reset_switch(dev);
890 if (ret) {
891 dev_err(ds->dev, "failed to reset switch\n");
892 return ret;
893 }
894
895 b53_reset_mib(dev);
896
897 ret = b53_apply_config(dev);
898 if (ret)
899 dev_err(ds->dev, "failed to apply configuration\n");
900
901 /* Configure IMP/CPU port, disable unused ports. Enabled
902 * ports will be configured with .port_enable
903 */
904 for (port = 0; port < dev->num_ports; port++) {
905 if (dsa_is_cpu_port(ds, port))
906 b53_enable_cpu_port(dev, port);
907 else if (dsa_is_unused_port(ds, port))
908 b53_disable_port(ds, port, NULL);
909 }
910
911 return ret;
912 }
913
914 static void b53_adjust_link(struct dsa_switch *ds, int port,
915 struct phy_device *phydev)
916 {
917 struct b53_device *dev = ds->priv;
918 struct ethtool_eee *p = &dev->ports[port].eee;
919 u8 rgmii_ctrl = 0, reg = 0, off;
920
921 if (!phy_is_pseudo_fixed_link(phydev))
922 return;
923
924 /* Override the port settings */
925 if (port == dev->cpu_port) {
926 off = B53_PORT_OVERRIDE_CTRL;
927 reg = PORT_OVERRIDE_EN;
928 } else {
929 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
930 reg = GMII_PO_EN;
931 }
932
933 /* Set the link UP */
934 if (phydev->link)
935 reg |= PORT_OVERRIDE_LINK;
936
937 if (phydev->duplex == DUPLEX_FULL)
938 reg |= PORT_OVERRIDE_FULL_DUPLEX;
939
940 switch (phydev->speed) {
941 case 2000:
942 reg |= PORT_OVERRIDE_SPEED_2000M;
943 /* fallthrough */
944 case SPEED_1000:
945 reg |= PORT_OVERRIDE_SPEED_1000M;
946 break;
947 case SPEED_100:
948 reg |= PORT_OVERRIDE_SPEED_100M;
949 break;
950 case SPEED_10:
951 reg |= PORT_OVERRIDE_SPEED_10M;
952 break;
953 default:
954 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
955 return;
956 }
957
958 /* Enable flow control on BCM5301x's CPU port */
959 if (is5301x(dev) && port == dev->cpu_port)
960 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
961
962 if (phydev->pause) {
963 if (phydev->asym_pause)
964 reg |= PORT_OVERRIDE_TX_FLOW;
965 reg |= PORT_OVERRIDE_RX_FLOW;
966 }
967
968 b53_write8(dev, B53_CTRL_PAGE, off, reg);
969
970 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
971 if (port == 8)
972 off = B53_RGMII_CTRL_IMP;
973 else
974 off = B53_RGMII_CTRL_P(port);
975
976 /* Configure the port RGMII clock delay by DLL disabled and
977 * tx_clk aligned timing (restoring to reset defaults)
978 */
979 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
980 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
981 RGMII_CTRL_TIMING_SEL);
982
983 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
984 * sure that we enable the port TX clock internal delay to
985 * account for this internal delay that is inserted, otherwise
986 * the switch won't be able to receive correctly.
987 *
988 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
989 * any delay neither on transmission nor reception, so the
990 * BCM53125 must also be configured accordingly to account for
991 * the lack of delay and introduce
992 *
993 * The BCM53125 switch has its RX clock and TX clock control
994 * swapped, hence the reason why we modify the TX clock path in
995 * the "RGMII" case
996 */
997 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
998 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
999 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1000 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1001 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1002 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1003
1004 dev_info(ds->dev, "Configured port %d for %s\n", port,
1005 phy_modes(phydev->interface));
1006 }
1007
1008 /* configure MII port if necessary */
1009 if (is5325(dev)) {
1010 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1011 &reg);
1012
1013 /* reverse mii needs to be enabled */
1014 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1015 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1016 reg | PORT_OVERRIDE_RV_MII_25);
1017 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1018 &reg);
1019
1020 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1021 dev_err(ds->dev,
1022 "Failed to enable reverse MII mode\n");
1023 return;
1024 }
1025 }
1026 } else if (is5301x(dev)) {
1027 if (port != dev->cpu_port) {
1028 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1029 u8 gmii_po;
1030
1031 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1032 gmii_po |= GMII_PO_LINK |
1033 GMII_PO_RX_FLOW |
1034 GMII_PO_TX_FLOW |
1035 GMII_PO_EN |
1036 GMII_PO_SPEED_2000M;
1037 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1038 }
1039 }
1040
1041 /* Re-negotiate EEE if it was enabled already */
1042 p->eee_enabled = b53_eee_init(ds, port, phydev);
1043 }
1044
1045 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1046 {
1047 struct b53_device *dev = ds->priv;
1048 struct net_device *bridge_dev;
1049 unsigned int i;
1050 u16 pvid, new_pvid;
1051
1052 /* Handle the case were multiple bridges span the same switch device
1053 * and one of them has a different setting than what is being requested
1054 * which would be breaking filtering semantics for any of the other
1055 * bridge devices.
1056 */
1057 b53_for_each_port(dev, i) {
1058 bridge_dev = dsa_to_port(ds, i)->bridge_dev;
1059 if (bridge_dev &&
1060 bridge_dev != dsa_to_port(ds, port)->bridge_dev &&
1061 br_vlan_enabled(bridge_dev) != vlan_filtering) {
1062 netdev_err(bridge_dev,
1063 "VLAN filtering is global to the switch!\n");
1064 return -EINVAL;
1065 }
1066 }
1067
1068 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1069 new_pvid = pvid;
1070 if (dev->vlan_filtering_enabled && !vlan_filtering) {
1071 /* Filtering is currently enabled, use the default PVID since
1072 * the bridge does not expect tagging anymore
1073 */
1074 dev->ports[port].pvid = pvid;
1075 new_pvid = b53_default_pvid(dev);
1076 } else if (!dev->vlan_filtering_enabled && vlan_filtering) {
1077 /* Filtering is currently disabled, restore the previous PVID */
1078 new_pvid = dev->ports[port].pvid;
1079 }
1080
1081 if (pvid != new_pvid)
1082 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1083 new_pvid);
1084
1085 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1086
1087 return 0;
1088 }
1089 EXPORT_SYMBOL(b53_vlan_filtering);
1090
1091 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1092 const struct switchdev_obj_port_vlan *vlan,
1093 struct switchdev_trans *trans)
1094 {
1095 struct b53_device *dev = ds->priv;
1096
1097 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1098 return -EOPNOTSUPP;
1099
1100 if (vlan->vid_end > dev->num_vlans)
1101 return -ERANGE;
1102
1103 b53_enable_vlan(dev, true, dev->vlan_filtering_enabled);
1104
1105 return 0;
1106 }
1107 EXPORT_SYMBOL(b53_vlan_prepare);
1108
1109 void b53_vlan_add(struct dsa_switch *ds, int port,
1110 const struct switchdev_obj_port_vlan *vlan,
1111 struct switchdev_trans *trans)
1112 {
1113 struct b53_device *dev = ds->priv;
1114 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1115 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1116 struct b53_vlan *vl;
1117 u16 vid;
1118
1119 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1120 vl = &dev->vlans[vid];
1121
1122 b53_get_vlan_entry(dev, vid, vl);
1123
1124 vl->members |= BIT(port);
1125 if (untagged && !dsa_is_cpu_port(ds, port))
1126 vl->untag |= BIT(port);
1127 else
1128 vl->untag &= ~BIT(port);
1129
1130 b53_set_vlan_entry(dev, vid, vl);
1131 b53_fast_age_vlan(dev, vid);
1132 }
1133
1134 if (pvid) {
1135 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1136 vlan->vid_end);
1137 b53_fast_age_vlan(dev, vid);
1138 }
1139 }
1140 EXPORT_SYMBOL(b53_vlan_add);
1141
1142 int b53_vlan_del(struct dsa_switch *ds, int port,
1143 const struct switchdev_obj_port_vlan *vlan)
1144 {
1145 struct b53_device *dev = ds->priv;
1146 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1147 struct b53_vlan *vl;
1148 u16 vid;
1149 u16 pvid;
1150
1151 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1152
1153 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1154 vl = &dev->vlans[vid];
1155
1156 b53_get_vlan_entry(dev, vid, vl);
1157
1158 vl->members &= ~BIT(port);
1159
1160 if (pvid == vid)
1161 pvid = b53_default_pvid(dev);
1162
1163 if (untagged && !dsa_is_cpu_port(ds, port))
1164 vl->untag &= ~(BIT(port));
1165
1166 b53_set_vlan_entry(dev, vid, vl);
1167 b53_fast_age_vlan(dev, vid);
1168 }
1169
1170 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1171 b53_fast_age_vlan(dev, pvid);
1172
1173 return 0;
1174 }
1175 EXPORT_SYMBOL(b53_vlan_del);
1176
1177 /* Address Resolution Logic routines */
1178 static int b53_arl_op_wait(struct b53_device *dev)
1179 {
1180 unsigned int timeout = 10;
1181 u8 reg;
1182
1183 do {
1184 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1185 if (!(reg & ARLTBL_START_DONE))
1186 return 0;
1187
1188 usleep_range(1000, 2000);
1189 } while (timeout--);
1190
1191 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1192
1193 return -ETIMEDOUT;
1194 }
1195
1196 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1197 {
1198 u8 reg;
1199
1200 if (op > ARLTBL_RW)
1201 return -EINVAL;
1202
1203 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1204 reg |= ARLTBL_START_DONE;
1205 if (op)
1206 reg |= ARLTBL_RW;
1207 else
1208 reg &= ~ARLTBL_RW;
1209 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1210
1211 return b53_arl_op_wait(dev);
1212 }
1213
1214 static int b53_arl_read(struct b53_device *dev, u64 mac,
1215 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1216 bool is_valid)
1217 {
1218 unsigned int i;
1219 int ret;
1220
1221 ret = b53_arl_op_wait(dev);
1222 if (ret)
1223 return ret;
1224
1225 /* Read the bins */
1226 for (i = 0; i < dev->num_arl_entries; i++) {
1227 u64 mac_vid;
1228 u32 fwd_entry;
1229
1230 b53_read64(dev, B53_ARLIO_PAGE,
1231 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1232 b53_read32(dev, B53_ARLIO_PAGE,
1233 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1234 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1235
1236 if (!(fwd_entry & ARLTBL_VALID))
1237 continue;
1238 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1239 continue;
1240 *idx = i;
1241 }
1242
1243 return -ENOENT;
1244 }
1245
1246 static int b53_arl_op(struct b53_device *dev, int op, int port,
1247 const unsigned char *addr, u16 vid, bool is_valid)
1248 {
1249 struct b53_arl_entry ent;
1250 u32 fwd_entry;
1251 u64 mac, mac_vid = 0;
1252 u8 idx = 0;
1253 int ret;
1254
1255 /* Convert the array into a 64-bit MAC */
1256 mac = ether_addr_to_u64(addr);
1257
1258 /* Perform a read for the given MAC and VID */
1259 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1260 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1261
1262 /* Issue a read operation for this MAC */
1263 ret = b53_arl_rw_op(dev, 1);
1264 if (ret)
1265 return ret;
1266
1267 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1268 /* If this is a read, just finish now */
1269 if (op)
1270 return ret;
1271
1272 /* We could not find a matching MAC, so reset to a new entry */
1273 if (ret) {
1274 fwd_entry = 0;
1275 idx = 1;
1276 }
1277
1278 memset(&ent, 0, sizeof(ent));
1279 ent.port = port;
1280 ent.is_valid = is_valid;
1281 ent.vid = vid;
1282 ent.is_static = true;
1283 memcpy(ent.mac, addr, ETH_ALEN);
1284 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1285
1286 b53_write64(dev, B53_ARLIO_PAGE,
1287 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1288 b53_write32(dev, B53_ARLIO_PAGE,
1289 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1290
1291 return b53_arl_rw_op(dev, 0);
1292 }
1293
1294 int b53_fdb_add(struct dsa_switch *ds, int port,
1295 const unsigned char *addr, u16 vid)
1296 {
1297 struct b53_device *priv = ds->priv;
1298
1299 /* 5325 and 5365 require some more massaging, but could
1300 * be supported eventually
1301 */
1302 if (is5325(priv) || is5365(priv))
1303 return -EOPNOTSUPP;
1304
1305 return b53_arl_op(priv, 0, port, addr, vid, true);
1306 }
1307 EXPORT_SYMBOL(b53_fdb_add);
1308
1309 int b53_fdb_del(struct dsa_switch *ds, int port,
1310 const unsigned char *addr, u16 vid)
1311 {
1312 struct b53_device *priv = ds->priv;
1313
1314 return b53_arl_op(priv, 0, port, addr, vid, false);
1315 }
1316 EXPORT_SYMBOL(b53_fdb_del);
1317
1318 static int b53_arl_search_wait(struct b53_device *dev)
1319 {
1320 unsigned int timeout = 1000;
1321 u8 reg;
1322
1323 do {
1324 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1325 if (!(reg & ARL_SRCH_STDN))
1326 return 0;
1327
1328 if (reg & ARL_SRCH_VLID)
1329 return 0;
1330
1331 usleep_range(1000, 2000);
1332 } while (timeout--);
1333
1334 return -ETIMEDOUT;
1335 }
1336
1337 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1338 struct b53_arl_entry *ent)
1339 {
1340 u64 mac_vid;
1341 u32 fwd_entry;
1342
1343 b53_read64(dev, B53_ARLIO_PAGE,
1344 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1345 b53_read32(dev, B53_ARLIO_PAGE,
1346 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1347 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1348 }
1349
1350 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1351 dsa_fdb_dump_cb_t *cb, void *data)
1352 {
1353 if (!ent->is_valid)
1354 return 0;
1355
1356 if (port != ent->port)
1357 return 0;
1358
1359 return cb(ent->mac, ent->vid, ent->is_static, data);
1360 }
1361
1362 int b53_fdb_dump(struct dsa_switch *ds, int port,
1363 dsa_fdb_dump_cb_t *cb, void *data)
1364 {
1365 struct b53_device *priv = ds->priv;
1366 struct b53_arl_entry results[2];
1367 unsigned int count = 0;
1368 int ret;
1369 u8 reg;
1370
1371 /* Start search operation */
1372 reg = ARL_SRCH_STDN;
1373 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1374
1375 do {
1376 ret = b53_arl_search_wait(priv);
1377 if (ret)
1378 return ret;
1379
1380 b53_arl_search_rd(priv, 0, &results[0]);
1381 ret = b53_fdb_copy(port, &results[0], cb, data);
1382 if (ret)
1383 return ret;
1384
1385 if (priv->num_arl_entries > 2) {
1386 b53_arl_search_rd(priv, 1, &results[1]);
1387 ret = b53_fdb_copy(port, &results[1], cb, data);
1388 if (ret)
1389 return ret;
1390
1391 if (!results[0].is_valid && !results[1].is_valid)
1392 break;
1393 }
1394
1395 } while (count++ < 1024);
1396
1397 return 0;
1398 }
1399 EXPORT_SYMBOL(b53_fdb_dump);
1400
1401 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1402 {
1403 struct b53_device *dev = ds->priv;
1404 s8 cpu_port = ds->ports[port].cpu_dp->index;
1405 u16 pvlan, reg;
1406 unsigned int i;
1407
1408 /* Make this port leave the all VLANs join since we will have proper
1409 * VLAN entries from now on
1410 */
1411 if (is58xx(dev)) {
1412 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1413 reg &= ~BIT(port);
1414 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1415 reg &= ~BIT(cpu_port);
1416 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1417 }
1418
1419 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1420
1421 b53_for_each_port(dev, i) {
1422 if (dsa_to_port(ds, i)->bridge_dev != br)
1423 continue;
1424
1425 /* Add this local port to the remote port VLAN control
1426 * membership and update the remote port bitmask
1427 */
1428 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1429 reg |= BIT(port);
1430 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1431 dev->ports[i].vlan_ctl_mask = reg;
1432
1433 pvlan |= BIT(i);
1434 }
1435
1436 /* Configure the local port VLAN control membership to include
1437 * remote ports and update the local port bitmask
1438 */
1439 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1440 dev->ports[port].vlan_ctl_mask = pvlan;
1441
1442 return 0;
1443 }
1444 EXPORT_SYMBOL(b53_br_join);
1445
1446 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1447 {
1448 struct b53_device *dev = ds->priv;
1449 struct b53_vlan *vl = &dev->vlans[0];
1450 s8 cpu_port = ds->ports[port].cpu_dp->index;
1451 unsigned int i;
1452 u16 pvlan, reg, pvid;
1453
1454 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1455
1456 b53_for_each_port(dev, i) {
1457 /* Don't touch the remaining ports */
1458 if (dsa_to_port(ds, i)->bridge_dev != br)
1459 continue;
1460
1461 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1462 reg &= ~BIT(port);
1463 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1464 dev->ports[port].vlan_ctl_mask = reg;
1465
1466 /* Prevent self removal to preserve isolation */
1467 if (port != i)
1468 pvlan &= ~BIT(i);
1469 }
1470
1471 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1472 dev->ports[port].vlan_ctl_mask = pvlan;
1473
1474 pvid = b53_default_pvid(dev);
1475
1476 /* Make this port join all VLANs without VLAN entries */
1477 if (is58xx(dev)) {
1478 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1479 reg |= BIT(port);
1480 if (!(reg & BIT(cpu_port)))
1481 reg |= BIT(cpu_port);
1482 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1483 } else {
1484 b53_get_vlan_entry(dev, pvid, vl);
1485 vl->members |= BIT(port) | BIT(cpu_port);
1486 vl->untag |= BIT(port) | BIT(cpu_port);
1487 b53_set_vlan_entry(dev, pvid, vl);
1488 }
1489 }
1490 EXPORT_SYMBOL(b53_br_leave);
1491
1492 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1493 {
1494 struct b53_device *dev = ds->priv;
1495 u8 hw_state;
1496 u8 reg;
1497
1498 switch (state) {
1499 case BR_STATE_DISABLED:
1500 hw_state = PORT_CTRL_DIS_STATE;
1501 break;
1502 case BR_STATE_LISTENING:
1503 hw_state = PORT_CTRL_LISTEN_STATE;
1504 break;
1505 case BR_STATE_LEARNING:
1506 hw_state = PORT_CTRL_LEARN_STATE;
1507 break;
1508 case BR_STATE_FORWARDING:
1509 hw_state = PORT_CTRL_FWD_STATE;
1510 break;
1511 case BR_STATE_BLOCKING:
1512 hw_state = PORT_CTRL_BLOCK_STATE;
1513 break;
1514 default:
1515 dev_err(ds->dev, "invalid STP state: %d\n", state);
1516 return;
1517 }
1518
1519 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1520 reg &= ~PORT_CTRL_STP_STATE_MASK;
1521 reg |= hw_state;
1522 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1523 }
1524 EXPORT_SYMBOL(b53_br_set_stp_state);
1525
1526 void b53_br_fast_age(struct dsa_switch *ds, int port)
1527 {
1528 struct b53_device *dev = ds->priv;
1529
1530 if (b53_fast_age_port(dev, port))
1531 dev_err(ds->dev, "fast ageing failed\n");
1532 }
1533 EXPORT_SYMBOL(b53_br_fast_age);
1534
1535 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1536 {
1537 /* Broadcom switches will accept enabling Broadcom tags on the
1538 * following ports: 5, 7 and 8, any other port is not supported
1539 */
1540 switch (port) {
1541 case B53_CPU_PORT_25:
1542 case 7:
1543 case B53_CPU_PORT:
1544 return true;
1545 }
1546
1547 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", port);
1548 return false;
1549 }
1550
1551 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds,
1552 int port)
1553 {
1554 struct b53_device *dev = ds->priv;
1555
1556 /* Older models (5325, 5365) support a different tag format that we do
1557 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1558 * mode to be turned on which means we need to specifically manage ARL
1559 * misses on multicast addresses (TBD).
1560 */
1561 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1562 !b53_can_enable_brcm_tags(ds, port))
1563 return DSA_TAG_PROTO_NONE;
1564
1565 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1566 * which requires us to use the prepended Broadcom tag type
1567 */
1568 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1569 return DSA_TAG_PROTO_BRCM_PREPEND;
1570
1571 return DSA_TAG_PROTO_BRCM;
1572 }
1573
1574 int b53_mirror_add(struct dsa_switch *ds, int port,
1575 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1576 {
1577 struct b53_device *dev = ds->priv;
1578 u16 reg, loc;
1579
1580 if (ingress)
1581 loc = B53_IG_MIR_CTL;
1582 else
1583 loc = B53_EG_MIR_CTL;
1584
1585 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1586 reg |= BIT(port);
1587 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1588
1589 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1590 reg &= ~CAP_PORT_MASK;
1591 reg |= mirror->to_local_port;
1592 reg |= MIRROR_EN;
1593 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1594
1595 return 0;
1596 }
1597 EXPORT_SYMBOL(b53_mirror_add);
1598
1599 void b53_mirror_del(struct dsa_switch *ds, int port,
1600 struct dsa_mall_mirror_tc_entry *mirror)
1601 {
1602 struct b53_device *dev = ds->priv;
1603 bool loc_disable = false, other_loc_disable = false;
1604 u16 reg, loc;
1605
1606 if (mirror->ingress)
1607 loc = B53_IG_MIR_CTL;
1608 else
1609 loc = B53_EG_MIR_CTL;
1610
1611 /* Update the desired ingress/egress register */
1612 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1613 reg &= ~BIT(port);
1614 if (!(reg & MIRROR_MASK))
1615 loc_disable = true;
1616 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1617
1618 /* Now look at the other one to know if we can disable mirroring
1619 * entirely
1620 */
1621 if (mirror->ingress)
1622 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1623 else
1624 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1625 if (!(reg & MIRROR_MASK))
1626 other_loc_disable = true;
1627
1628 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1629 /* Both no longer have ports, let's disable mirroring */
1630 if (loc_disable && other_loc_disable) {
1631 reg &= ~MIRROR_EN;
1632 reg &= ~mirror->to_local_port;
1633 }
1634 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1635 }
1636 EXPORT_SYMBOL(b53_mirror_del);
1637
1638 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1639 {
1640 struct b53_device *dev = ds->priv;
1641 u16 reg;
1642
1643 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1644 if (enable)
1645 reg |= BIT(port);
1646 else
1647 reg &= ~BIT(port);
1648 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1649 }
1650 EXPORT_SYMBOL(b53_eee_enable_set);
1651
1652
1653 /* Returns 0 if EEE was not enabled, or 1 otherwise
1654 */
1655 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1656 {
1657 int ret;
1658
1659 ret = phy_init_eee(phy, 0);
1660 if (ret)
1661 return 0;
1662
1663 b53_eee_enable_set(ds, port, true);
1664
1665 return 1;
1666 }
1667 EXPORT_SYMBOL(b53_eee_init);
1668
1669 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1670 {
1671 struct b53_device *dev = ds->priv;
1672 struct ethtool_eee *p = &dev->ports[port].eee;
1673 u16 reg;
1674
1675 if (is5325(dev) || is5365(dev))
1676 return -EOPNOTSUPP;
1677
1678 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1679 e->eee_enabled = p->eee_enabled;
1680 e->eee_active = !!(reg & BIT(port));
1681
1682 return 0;
1683 }
1684 EXPORT_SYMBOL(b53_get_mac_eee);
1685
1686 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1687 {
1688 struct b53_device *dev = ds->priv;
1689 struct ethtool_eee *p = &dev->ports[port].eee;
1690
1691 if (is5325(dev) || is5365(dev))
1692 return -EOPNOTSUPP;
1693
1694 p->eee_enabled = e->eee_enabled;
1695 b53_eee_enable_set(ds, port, e->eee_enabled);
1696
1697 return 0;
1698 }
1699 EXPORT_SYMBOL(b53_set_mac_eee);
1700
1701 static const struct dsa_switch_ops b53_switch_ops = {
1702 .get_tag_protocol = b53_get_tag_protocol,
1703 .setup = b53_setup,
1704 .get_strings = b53_get_strings,
1705 .get_ethtool_stats = b53_get_ethtool_stats,
1706 .get_sset_count = b53_get_sset_count,
1707 .phy_read = b53_phy_read16,
1708 .phy_write = b53_phy_write16,
1709 .adjust_link = b53_adjust_link,
1710 .port_enable = b53_enable_port,
1711 .port_disable = b53_disable_port,
1712 .get_mac_eee = b53_get_mac_eee,
1713 .set_mac_eee = b53_set_mac_eee,
1714 .port_bridge_join = b53_br_join,
1715 .port_bridge_leave = b53_br_leave,
1716 .port_stp_state_set = b53_br_set_stp_state,
1717 .port_fast_age = b53_br_fast_age,
1718 .port_vlan_filtering = b53_vlan_filtering,
1719 .port_vlan_prepare = b53_vlan_prepare,
1720 .port_vlan_add = b53_vlan_add,
1721 .port_vlan_del = b53_vlan_del,
1722 .port_fdb_dump = b53_fdb_dump,
1723 .port_fdb_add = b53_fdb_add,
1724 .port_fdb_del = b53_fdb_del,
1725 .port_mirror_add = b53_mirror_add,
1726 .port_mirror_del = b53_mirror_del,
1727 };
1728
1729 struct b53_chip_data {
1730 u32 chip_id;
1731 const char *dev_name;
1732 u16 vlans;
1733 u16 enabled_ports;
1734 u8 cpu_port;
1735 u8 vta_regs[3];
1736 u8 arl_entries;
1737 u8 duplex_reg;
1738 u8 jumbo_pm_reg;
1739 u8 jumbo_size_reg;
1740 };
1741
1742 #define B53_VTA_REGS \
1743 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1744 #define B53_VTA_REGS_9798 \
1745 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1746 #define B53_VTA_REGS_63XX \
1747 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1748
1749 static const struct b53_chip_data b53_switch_chips[] = {
1750 {
1751 .chip_id = BCM5325_DEVICE_ID,
1752 .dev_name = "BCM5325",
1753 .vlans = 16,
1754 .enabled_ports = 0x1f,
1755 .arl_entries = 2,
1756 .cpu_port = B53_CPU_PORT_25,
1757 .duplex_reg = B53_DUPLEX_STAT_FE,
1758 },
1759 {
1760 .chip_id = BCM5365_DEVICE_ID,
1761 .dev_name = "BCM5365",
1762 .vlans = 256,
1763 .enabled_ports = 0x1f,
1764 .arl_entries = 2,
1765 .cpu_port = B53_CPU_PORT_25,
1766 .duplex_reg = B53_DUPLEX_STAT_FE,
1767 },
1768 {
1769 .chip_id = BCM5389_DEVICE_ID,
1770 .dev_name = "BCM5389",
1771 .vlans = 4096,
1772 .enabled_ports = 0x1f,
1773 .arl_entries = 4,
1774 .cpu_port = B53_CPU_PORT,
1775 .vta_regs = B53_VTA_REGS,
1776 .duplex_reg = B53_DUPLEX_STAT_GE,
1777 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1778 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1779 },
1780 {
1781 .chip_id = BCM5395_DEVICE_ID,
1782 .dev_name = "BCM5395",
1783 .vlans = 4096,
1784 .enabled_ports = 0x1f,
1785 .arl_entries = 4,
1786 .cpu_port = B53_CPU_PORT,
1787 .vta_regs = B53_VTA_REGS,
1788 .duplex_reg = B53_DUPLEX_STAT_GE,
1789 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1790 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1791 },
1792 {
1793 .chip_id = BCM5397_DEVICE_ID,
1794 .dev_name = "BCM5397",
1795 .vlans = 4096,
1796 .enabled_ports = 0x1f,
1797 .arl_entries = 4,
1798 .cpu_port = B53_CPU_PORT,
1799 .vta_regs = B53_VTA_REGS_9798,
1800 .duplex_reg = B53_DUPLEX_STAT_GE,
1801 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1802 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1803 },
1804 {
1805 .chip_id = BCM5398_DEVICE_ID,
1806 .dev_name = "BCM5398",
1807 .vlans = 4096,
1808 .enabled_ports = 0x7f,
1809 .arl_entries = 4,
1810 .cpu_port = B53_CPU_PORT,
1811 .vta_regs = B53_VTA_REGS_9798,
1812 .duplex_reg = B53_DUPLEX_STAT_GE,
1813 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1814 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1815 },
1816 {
1817 .chip_id = BCM53115_DEVICE_ID,
1818 .dev_name = "BCM53115",
1819 .vlans = 4096,
1820 .enabled_ports = 0x1f,
1821 .arl_entries = 4,
1822 .vta_regs = B53_VTA_REGS,
1823 .cpu_port = B53_CPU_PORT,
1824 .duplex_reg = B53_DUPLEX_STAT_GE,
1825 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1826 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1827 },
1828 {
1829 .chip_id = BCM53125_DEVICE_ID,
1830 .dev_name = "BCM53125",
1831 .vlans = 4096,
1832 .enabled_ports = 0xff,
1833 .arl_entries = 4,
1834 .cpu_port = B53_CPU_PORT,
1835 .vta_regs = B53_VTA_REGS,
1836 .duplex_reg = B53_DUPLEX_STAT_GE,
1837 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1838 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1839 },
1840 {
1841 .chip_id = BCM53128_DEVICE_ID,
1842 .dev_name = "BCM53128",
1843 .vlans = 4096,
1844 .enabled_ports = 0x1ff,
1845 .arl_entries = 4,
1846 .cpu_port = B53_CPU_PORT,
1847 .vta_regs = B53_VTA_REGS,
1848 .duplex_reg = B53_DUPLEX_STAT_GE,
1849 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1850 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1851 },
1852 {
1853 .chip_id = BCM63XX_DEVICE_ID,
1854 .dev_name = "BCM63xx",
1855 .vlans = 4096,
1856 .enabled_ports = 0, /* pdata must provide them */
1857 .arl_entries = 4,
1858 .cpu_port = B53_CPU_PORT,
1859 .vta_regs = B53_VTA_REGS_63XX,
1860 .duplex_reg = B53_DUPLEX_STAT_63XX,
1861 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1862 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1863 },
1864 {
1865 .chip_id = BCM53010_DEVICE_ID,
1866 .dev_name = "BCM53010",
1867 .vlans = 4096,
1868 .enabled_ports = 0x1f,
1869 .arl_entries = 4,
1870 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1871 .vta_regs = B53_VTA_REGS,
1872 .duplex_reg = B53_DUPLEX_STAT_GE,
1873 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1874 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1875 },
1876 {
1877 .chip_id = BCM53011_DEVICE_ID,
1878 .dev_name = "BCM53011",
1879 .vlans = 4096,
1880 .enabled_ports = 0x1bf,
1881 .arl_entries = 4,
1882 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1883 .vta_regs = B53_VTA_REGS,
1884 .duplex_reg = B53_DUPLEX_STAT_GE,
1885 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1886 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1887 },
1888 {
1889 .chip_id = BCM53012_DEVICE_ID,
1890 .dev_name = "BCM53012",
1891 .vlans = 4096,
1892 .enabled_ports = 0x1bf,
1893 .arl_entries = 4,
1894 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1895 .vta_regs = B53_VTA_REGS,
1896 .duplex_reg = B53_DUPLEX_STAT_GE,
1897 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1898 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1899 },
1900 {
1901 .chip_id = BCM53018_DEVICE_ID,
1902 .dev_name = "BCM53018",
1903 .vlans = 4096,
1904 .enabled_ports = 0x1f,
1905 .arl_entries = 4,
1906 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1907 .vta_regs = B53_VTA_REGS,
1908 .duplex_reg = B53_DUPLEX_STAT_GE,
1909 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1910 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1911 },
1912 {
1913 .chip_id = BCM53019_DEVICE_ID,
1914 .dev_name = "BCM53019",
1915 .vlans = 4096,
1916 .enabled_ports = 0x1f,
1917 .arl_entries = 4,
1918 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1919 .vta_regs = B53_VTA_REGS,
1920 .duplex_reg = B53_DUPLEX_STAT_GE,
1921 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1922 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1923 },
1924 {
1925 .chip_id = BCM58XX_DEVICE_ID,
1926 .dev_name = "BCM585xx/586xx/88312",
1927 .vlans = 4096,
1928 .enabled_ports = 0x1ff,
1929 .arl_entries = 4,
1930 .cpu_port = B53_CPU_PORT,
1931 .vta_regs = B53_VTA_REGS,
1932 .duplex_reg = B53_DUPLEX_STAT_GE,
1933 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1934 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1935 },
1936 {
1937 .chip_id = BCM583XX_DEVICE_ID,
1938 .dev_name = "BCM583xx/11360",
1939 .vlans = 4096,
1940 .enabled_ports = 0x103,
1941 .arl_entries = 4,
1942 .cpu_port = B53_CPU_PORT,
1943 .vta_regs = B53_VTA_REGS,
1944 .duplex_reg = B53_DUPLEX_STAT_GE,
1945 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1946 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1947 },
1948 {
1949 .chip_id = BCM7445_DEVICE_ID,
1950 .dev_name = "BCM7445",
1951 .vlans = 4096,
1952 .enabled_ports = 0x1ff,
1953 .arl_entries = 4,
1954 .cpu_port = B53_CPU_PORT,
1955 .vta_regs = B53_VTA_REGS,
1956 .duplex_reg = B53_DUPLEX_STAT_GE,
1957 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1958 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1959 },
1960 {
1961 .chip_id = BCM7278_DEVICE_ID,
1962 .dev_name = "BCM7278",
1963 .vlans = 4096,
1964 .enabled_ports = 0x1ff,
1965 .arl_entries= 4,
1966 .cpu_port = B53_CPU_PORT,
1967 .vta_regs = B53_VTA_REGS,
1968 .duplex_reg = B53_DUPLEX_STAT_GE,
1969 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1970 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1971 },
1972 };
1973
1974 static int b53_switch_init(struct b53_device *dev)
1975 {
1976 unsigned int i;
1977 int ret;
1978
1979 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1980 const struct b53_chip_data *chip = &b53_switch_chips[i];
1981
1982 if (chip->chip_id == dev->chip_id) {
1983 if (!dev->enabled_ports)
1984 dev->enabled_ports = chip->enabled_ports;
1985 dev->name = chip->dev_name;
1986 dev->duplex_reg = chip->duplex_reg;
1987 dev->vta_regs[0] = chip->vta_regs[0];
1988 dev->vta_regs[1] = chip->vta_regs[1];
1989 dev->vta_regs[2] = chip->vta_regs[2];
1990 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1991 dev->cpu_port = chip->cpu_port;
1992 dev->num_vlans = chip->vlans;
1993 dev->num_arl_entries = chip->arl_entries;
1994 break;
1995 }
1996 }
1997
1998 /* check which BCM5325x version we have */
1999 if (is5325(dev)) {
2000 u8 vc4;
2001
2002 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2003
2004 /* check reserved bits */
2005 switch (vc4 & 3) {
2006 case 1:
2007 /* BCM5325E */
2008 break;
2009 case 3:
2010 /* BCM5325F - do not use port 4 */
2011 dev->enabled_ports &= ~BIT(4);
2012 break;
2013 default:
2014 /* On the BCM47XX SoCs this is the supported internal switch.*/
2015 #ifndef CONFIG_BCM47XX
2016 /* BCM5325M */
2017 return -EINVAL;
2018 #else
2019 break;
2020 #endif
2021 }
2022 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2023 u64 strap_value;
2024
2025 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2026 /* use second IMP port if GMII is enabled */
2027 if (strap_value & SV_GMII_CTRL_115)
2028 dev->cpu_port = 5;
2029 }
2030
2031 /* cpu port is always last */
2032 dev->num_ports = dev->cpu_port + 1;
2033 dev->enabled_ports |= BIT(dev->cpu_port);
2034
2035 dev->ports = devm_kzalloc(dev->dev,
2036 sizeof(struct b53_port) * dev->num_ports,
2037 GFP_KERNEL);
2038 if (!dev->ports)
2039 return -ENOMEM;
2040
2041 dev->vlans = devm_kzalloc(dev->dev,
2042 sizeof(struct b53_vlan) * dev->num_vlans,
2043 GFP_KERNEL);
2044 if (!dev->vlans)
2045 return -ENOMEM;
2046
2047 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2048 if (dev->reset_gpio >= 0) {
2049 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2050 GPIOF_OUT_INIT_HIGH, "robo_reset");
2051 if (ret)
2052 return ret;
2053 }
2054
2055 return 0;
2056 }
2057
2058 struct b53_device *b53_switch_alloc(struct device *base,
2059 const struct b53_io_ops *ops,
2060 void *priv)
2061 {
2062 struct dsa_switch *ds;
2063 struct b53_device *dev;
2064
2065 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2066 if (!ds)
2067 return NULL;
2068
2069 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2070 if (!dev)
2071 return NULL;
2072
2073 ds->priv = dev;
2074 dev->dev = base;
2075
2076 dev->ds = ds;
2077 dev->priv = priv;
2078 dev->ops = ops;
2079 ds->ops = &b53_switch_ops;
2080 mutex_init(&dev->reg_mutex);
2081 mutex_init(&dev->stats_mutex);
2082
2083 return dev;
2084 }
2085 EXPORT_SYMBOL(b53_switch_alloc);
2086
2087 int b53_switch_detect(struct b53_device *dev)
2088 {
2089 u32 id32;
2090 u16 tmp;
2091 u8 id8;
2092 int ret;
2093
2094 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2095 if (ret)
2096 return ret;
2097
2098 switch (id8) {
2099 case 0:
2100 /* BCM5325 and BCM5365 do not have this register so reads
2101 * return 0. But the read operation did succeed, so assume this
2102 * is one of them.
2103 *
2104 * Next check if we can write to the 5325's VTA register; for
2105 * 5365 it is read only.
2106 */
2107 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2108 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2109
2110 if (tmp == 0xf)
2111 dev->chip_id = BCM5325_DEVICE_ID;
2112 else
2113 dev->chip_id = BCM5365_DEVICE_ID;
2114 break;
2115 case BCM5389_DEVICE_ID:
2116 case BCM5395_DEVICE_ID:
2117 case BCM5397_DEVICE_ID:
2118 case BCM5398_DEVICE_ID:
2119 dev->chip_id = id8;
2120 break;
2121 default:
2122 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2123 if (ret)
2124 return ret;
2125
2126 switch (id32) {
2127 case BCM53115_DEVICE_ID:
2128 case BCM53125_DEVICE_ID:
2129 case BCM53128_DEVICE_ID:
2130 case BCM53010_DEVICE_ID:
2131 case BCM53011_DEVICE_ID:
2132 case BCM53012_DEVICE_ID:
2133 case BCM53018_DEVICE_ID:
2134 case BCM53019_DEVICE_ID:
2135 dev->chip_id = id32;
2136 break;
2137 default:
2138 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2139 id8, id32);
2140 return -ENODEV;
2141 }
2142 }
2143
2144 if (dev->chip_id == BCM5325_DEVICE_ID)
2145 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2146 &dev->core_rev);
2147 else
2148 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2149 &dev->core_rev);
2150 }
2151 EXPORT_SYMBOL(b53_switch_detect);
2152
2153 int b53_switch_register(struct b53_device *dev)
2154 {
2155 int ret;
2156
2157 if (dev->pdata) {
2158 dev->chip_id = dev->pdata->chip_id;
2159 dev->enabled_ports = dev->pdata->enabled_ports;
2160 }
2161
2162 if (!dev->chip_id && b53_switch_detect(dev))
2163 return -EINVAL;
2164
2165 ret = b53_switch_init(dev);
2166 if (ret)
2167 return ret;
2168
2169 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2170
2171 return dsa_register_switch(dev->ds);
2172 }
2173 EXPORT_SYMBOL(b53_switch_register);
2174
2175 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2176 MODULE_DESCRIPTION("B53 switch library");
2177 MODULE_LICENSE("Dual BSD/GPL");
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